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73s8010c smart card interface simplifying system integration? data sheet april 2009 rev. 1.5 ? 2009 teridian semiconductor corporation 1 description the teridian 73s8010c is a single smart card interface ic. it provides full electrical compliance with iso-7816-3 and emv 4.0 specifications. interfacing with the host is done through the two-wire i2c bus. data exchange with the card is managed from the system controller using the i/o line (and eventually the auxiliary i/o lines). an on-chip oscillator using an external crystal, or connection to a clock signal coming from the system controller can generate the card clock signal. the 73s8010c ic incorporates an iso-7816-3 activation/deactivation sequencer that controls the card signals. level shifters drive the card signals with the selected card voltage (3 v or 5 v), coming from an internal dc-dc converter. with its high-efficiency dc-dc converter, the teridian 73s8010c is a cost-effective solution for any smart card reader application to be powered from a single 2.7 v to 3.6 v power supply. hardware support for auxiliary i/o lines, c4 / c8 contacts, is provided. emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. the fault can be a vdd (digital power supply), a vcc (card power supply), a card over-current, or an over-heating fault. advantages ? single smart card interface ? the inductor-based dc-dc converter provides higher current and efficiency than the usual charge-pump capacitor-based converters ? ideal for battery-powered applications ? suitable for high current cards and sams: (100 ma max) ? power down mode: 2 ? a typical ? small format (5x5mm) 32-qfn package option features ? card interface: ? complies with iso-7816-3 and emv 4.0 ? a dc-dc converter provides 3v / 5v to the card from an external power supply input ? high-efficiency converter: > 80% @ v dd = 3.3 v, v cc = 5 v and i cc = 65 ma ? up to 100 ma supplied to the card ? iso-7816-3 activation / deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry ? protection include 2 voltage supervisors that detect voltage drops on card v cc and v dd power supplies ? the v dd voltage supervisor threshold value can be externally adjusted ? true over-current detection (150 ma max.) ? 1 card detection input ? auxiliary i/o lines, for c4 / c8 contact signals ? host interface: ? fast mode, 400 kbps i 2 c slave bus ? 8 possible devices in parallel ? one control register and one status register ? interrupt output to the host for fault detection ? crystal oscillator or host clock, up to 27 mhz ? power supply: ? v dd : 2.7 v to 3.6 v ? 6 kv esd protection on the card interface ? package: so28 or 32qfn applications ? set-top-boxes, dvd / hdd recorders: conditional access and pay-per-view slots ? point of sales and transaction terminals ? emv slots in cell phones and pdas downloaded from: http:///
73s8010c data sheet ds_8010c_024 2 rev. 1.5 functional diagram figure 1: 73s8010c block diagram pin number reference to so28 package [pin number] reference to 32qfn package downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 3 table of contents 1 ? pin descr iption ............................................................................................................... ..................... 5 ? 1.1 ? card inte rface ................................................................................................................ ............... 5 ? 1.2 ? miscellaneous inputs and outputs ................................................................................................ 5 ? 1.3 ? power supply and grou nd ....................................................................................................... ..... 5 ? 1.4 ? microcontroller interface ..................................................................................................... .......... 6 ? 2 ? host interface (i 2 c bus) ...................................................................................................................... 7 ? 2.1 ? host interfac e control ........................................................................................................ ........... 7 ? 2.2 ? host interfac e status ......................................................................................................... ........... 8 ? 2.3 ? i 2 c-bus timing .................................................................................................................. ............ 9 ? 3 ? oscillator ............................................................................................................................... ............. 10 ? 4 ? dc-dc converter C ca rd power supply ......................................................................................... 1 0 ? 5 ? voltage supe rvision ........................................................................................................... .............. 11 ? 6 ? power down ............................................................................................................................... ........ 11 ? 7 ? over-temperature monitor ................................................................................................................ 12 ? 8 ? activation sequence ........................................................................................................... .............. 12 ? 9 ? deactivation sequence ..................................................................................................................... 13 ? 10 ? interrupt ..................................................................................................................... ........................ 13 ? 11 ? warm reset .................................................................................................................... ................... 14 ? 12 ? i/o timing ............................................................................................................................... ............ 14 ? 13 ? typical applicat ion schematic ................................................................................................. ....... 15 ? 14 ? electrical speci fication ...................................................................................................... ............... 16 ? 14.1 ? absolute maxi mum ratings ...................................................................................................... .. 16 ? 14.2 ? recommended operati ng condit ions......................................................................................... 16 ? 14.3 ? dc characteristics: card interface ............................................................................................ . 17 ? 14.4 ? dc characteristics: digital signals ........................................................................................... .. 20 ? 14.5 ? dc characterist ics: supply .................................................................................................... ..... 20 ? 14.6 ? dc characteristics: i 2 c interface ................................................................................................ 21 ? 14.7 ? voltage / temperature fault detection circuits .......................................................................... 21 ? 15 ? mechanical drawings ........................................................................................................... ............ 22 ? 15.1 ? 32-pin qfn .................................................................................................................... ............. 22 ? 15.2 ? 28-pin so ..................................................................................................................... ............... 23 ? 16 ? package pin d esignati on ....................................................................................................... .......... 24 ? 16.1 ? 32-pin qfn .................................................................................................................... ............. 24 ? 16.2 ? 28-pin so ..................................................................................................................... ............... 25 ? 17 ? ordering info rmation .......................................................................................................... .............. 26 ? 18 ? related docu mentation ......................................................................................................... ........... 26 ? 19 ? contact info rmation ........................................................................................................... ............... 26 ? revision hi story .............................................................................................................. .......................... 27 ? downloaded from: http:///
73s8010c data sheet ds_8010c_024 4 rev. 1.5 figures figure 1: 73s8010c block di agram .............................................................................................. ............... 2 ? figure 2: i 2 c bus write protocol .......................................................................................................... ......... 8 ? figure 3: i 2 c bus read pr otocol ........................................................................................................... ........ 9 ? figure 4: i 2 c bus timing diagram .......................................................................................................... ...... 9 ? figure 5: power down mode operation ...................................................................................................... 12 ? figure 6: activa tion sequence ................................................................................................. ................... 12 ? figure 7: deactiva tion sequence ............................................................................................... ................. 13 ? figure 8: fault functions, int operation ................................................................................................. 13 ? figure 9: warm re set operation ................................................................................................ ................. 14 ? figure 10: i/o timing ......................................................................................................... ......................... 14 ? figure 11: 73s8010c C typical applicat ion schematic ........................................................................... ... 15 ? figure 12: dc C dc converter efficiency (v cc = 5 v) ................................................................................ 18 ? figure 13: dc C dc converter efficiency (v cc = 3 v) ................................................................................ 18 ? figure 14: 32-pin qf n package drawing ......................................................................................... .......... 22 ? figure 15: 28-pin so package drawing .......................................................................................... ........... 23 ? tables table 1: device ad dress selections ............................................................................................ ................. 7 ? table 2: host c ontrol register ................................................................................................ ...................... 7 ? table 3: host st atus register ................................................................................................. ...................... 8 ? table 4: choice of vcc capacitor .............................................................................................. ................. 10 ? downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 5 1 pin description 1.1 card interface name pin (so) pin (qfn) description i/o 11 9 card i/o: data signal to/from ca rd. includes a pull-up resistor to v cc. aux1 13 11 aux1: auxiliary data signal to /from card. includes a pull-up resistor to v cc. aux2 12 10 aux2: auxiliary data signal to /from card. includes a pull-up resistor to v cc. rst 16 14 card reset: provides reset (rst) signal to card. clk 15 13 card clock: provides clock (clk) signal to card. the rate of this clock is determined by the crystal oscillator frequency and clksel bits in the control register. pres 10 7 card presence switch: active high indicates card is present. includes a pull-down resistor. vcc 17 15 card power supply: logically contro lled by sequencer, output of dc-dc converter. requires an external filter capacitor to the card gnd. gnd 14 12 card ground. 1.2 miscellaneous inputs and outputs name pin (so) pin (qfn) description xtalin 24 23 crystal oscillator input: can either be connected to a crystal or driven as a source for the card clock. xtalout 25 24 crystal oscillator output: connected to crystal. left open if xtalin is being used as an external clock input. vddf_adj 18 17 v dd threshold adjustment input: this pin can be used to overwrite a higher v ddf value (that controls deactivation of the card). must be left open if unused. nc 7, 9 4, 6, 8, 16, 25, 32 non-connected pin. 1.3 power supply and ground name pin (so) pin (qfn) description vdd 6, 21 3, 20 system controller interface supply voltage: supply voltage for internal circuitry and dc-dc converter power supply source. gnd 4 1 dc-dc converter ground. gnd 14 12 smart card i/o ground. gnd 22 21 digital ground. lin 5 2 external inductor: connect external inductor from pin 5 to v dd . keep the inductor close to pin 5. downloaded from: http:///
73s8010c data sheet ds_8010c_024 6 rev. 1.5 1.4 microcontroller interface name pin (so) pin (qfn) description int 23 22 interrupt output (negative assertion): interrupt output signal to the processor. a 20 k ? pull up to v dd is provided internally. pwrdn 8 5 power down control input: active high. when power down (pd) mode is activated, all internal analog func tions are disabled to place the 73s8010c in its lowest power consumption mode. must be tied to ground when the power down function is not used. sad0 sad1 sad2 1 2 3 29 30 31 serial device address bits: digital i nputs for address selection that allow the connection of up to 8 devices in parallel. address selections as follows: sad2 sad1 sad0 i 2 c address (7 bits) 0 0 0 0x40 0 0 1 0x42 0 1 0 0x44 0 1 1 0x46 1 0 0 0x48 1 0 1 0x4a 1 1 0 0x4c 1 1 1 0x4e pins sad0 and sad1 are internally pulled-down and sad2 is internally pulled-up. the default address when left unconnected is 48h. scl 19 18 i 2 c clock signal input. sda 20 19 i 2 c bi-directional serial data signal. i/ouc 26 26 system controller data i/o to/from the card. includes internal pull-up resistor to v dd. aux1uc 27 27 system controller auxiliary data i/o to/from the card. includes internal pull- up resistor to v dd. aux2uc 28 28 system controller auxiliary data i/o to/from the card. includes internal pull- up resistor to v dd. downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 7 2 host interface (i 2 c bus) a fast-mode 400 khz i 2 c bus slave interface is used for controlli ng the device and reading the status of the device via the data pin sda and clock pin scl. the bus has 3 address select pins, sad0, sad1, and sad2. this allows up to 8 devices to be connected in parallel. table 1: device address selections sad2 sad1 sad0 i 2 c address (7 bits) 0 0 0 0x40 0 0 1 0x42 0 1 0 0x44 0 1 1 0x46 1 0 0 0x48 1 0 1 0x4a 1 1 0 0x4c 1 1 1 0x4e bit 0 of the i 2 c address is the r/w bit. refer to figure 2 and figure 3 for usage. 2.1 host interface control table 2 describes the host interface cont rol register bits (power-on reset = 0x00). table 2: host control register name bit description start/stop 0 when set, initiates an activation and a cold reset procedure; when reset, initiates a deactivation sequence. warm reset 1 when set, initiates a warm reset procedure; automatically reset by hardware when the card starts answering or when the card is declared mute. 5 v and 3 v 2 when set, v cc = 3 v; when reset, v cc = 5 v. clock stop 3 when set, card clock is stopped. bit 4 determines the card clock stop level. clock stop level 4 when set, card clock stops high; when reset card clock stops low. clksel1 5 bits 5 and 6 determine the clock rate to the card according to the following table. clkdiv1 clkdiv2 clock rate 0 0 xtalin/8 0 1 xtalin/4 1 1 xtalin/2 1 0 xtalin clksel2 6 i/o enable 7 when set, data is transferred between i/o (aux1, aux2) and i/ouc (aux1uc, aux2uc); when reset, i/o (aux1, au x2) and i/ouc (aux1uc, aux2uc) are high impedance. i 2 c-bus write to the control register the i 2 c-bus write command to the control register follows the format shown in figure 2. after the start condition, the master sends a slave address. this add ress is seven bits long followed by an eighth bit, which is an opcode bit (r/w) C a zero indicates the master will write data to the control register. after the r/w bit, the zero ack bit is sent to the master by the device. the master now starts sending the 8 bits of data to the control register during the data bits time. after the data bits, the zero downloaded from: http:///
73s8010c data sheet ds_8010c_024 8 rev. 1.5 ack bit is sent to the master by the device. the master should send the stop condition after receiving the ack bit. figure 2: i 2 c bus write protocol 2.2 host interface status table 3 describes the host interface status register bits (power-on reset = 0x04). table 3: host status register name bit description pres 0 set when the card is present; re set when the card is not present. presl 1 set when the pres pin changes state (rising/falling edge); reset when the status register is read. generates an interrupt when set i/o 2 set when i/o is high; reset when i/o is low. supl 3 set when a voltage fault is detected; rese t when the status register is read. generates an interrupt when set. prot 4 set when an over-current or over-heating f ault has occurred during a card session; reset when the status register is re ad. generates an interrupt when set. mute 5 set during atr when the card has not answered during the iso 7816-3 time window (40000 card clock cycles); reset when the next session begins or this register is read. early 6 set during atr when the card has answered before 400 card clock cycles; reset when the next session begins or this register is read. active 7 set when the card is active (v cc is on); reset when the card is inactive. i 2 c-bus read from the status register: the i 2 c-bus read command from the status register follows the format shown in figure 3 . after the start condition, the master sends a slave address. this add ress is seven bits long followed by an eighth bit, which is the opcode bit (r/ w ). a one indicates the master will read data from the status register. after the r/ w bit, the zero ack bit is sent to the ma ster by the device. the device now starts sending the 8-bit status register data to the control re gister during the data bits time. after the data bits, the one ack bit is sent to the device by t he master. the master should send the stop condition after receiving the ack bit. downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 9 figure 3: i 2 c bus read protocol 2.3 i 2 c-bus timing symbol parameter conditions min. typ. max. unit fsclk clock frequency 400 khz tlow clock low 1.3 ? s thi clock high 0.6 ? s thdsta hold time start condition 0.6 ? s tsudat data set up time 100 ns thddat data hold time 5 900 ns tsusto set up time stop condition 0.6 ? s tbuf bus free time between a stop and start condition 1.3 ? s figure 4: i 2 c bus timing diagram scl sda thdsta tsudat thddat tsusto tbuf tlow thi downloaded from: http:///
73s8010c data sheet ds_8010c_024 10 rev. 1.5 3 oscillator the teridian 73s8010c device has an on-chip oscillator that can generate the smart card clock using an external crystal, connected betwe en the xtalin and xtalout pins, to set the oscillator frequency. when the card clock signal is available from anothe r source, it can be connected to the pin xtalin, and the pin xtalout should be left unconnected. 4 dc-dc converter C card power supply an internal dc-dc converter provides the card power su pply. this converter is able to provide either a 3 v or 5 v card voltage from the power supply applied on the v dd pin. the digital iso-7816-3 sequencer controls the converter. bit 2 of the c ontrol register selects the card voltage. the circuit is an inductive step-up converter/regulator. the external compone nts required are 2 filter capacitors on the power-supply input v dd (100 nf + 10 ? f, next to the lin pin), an inductor, and an output filter capacitor on the card power supply v cc . the circuit performs regulation by activating the step-up operation when v cc is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage and the input supply v dd is less than the set point for v cc . when v dd is greater than the set point for v cc (v dd = 3.6 v, v cc = 3 v) the circuit operates as a linear regulato r. depending on the inductor values, the voltage converter can provide current on v cc as high as 100 ma. the circuit provides over-c urrent protection and limits i cc to 150 ma. when an over-current condition is sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host controller a fault on the interrupt output int . choice of the inductor the nominal inductor value is 10 ? h, rated for 400 ma. the inductor is connected between pin lin (pin 5 in the so package, pin 2 in the qfn package) and the v dd voltage. the value of the inductor can be optimized to meet a particular configuration (i cc_max ). the inductor should be located on the pcb as close as possible to the lin pin of the ic. choice of the v cc capacitor depending on the applications, the requirements in terms of both v cc minimum voltage and transient currents that the interface must be able to provide to the card vary. table 4 shows the recommended capacitors for each v cc power supply configuration and applicable specification. table 4: choice of vcc capacitor specification requirement application specification min v cc voltage allowed during transient current max transient current charge capacitor type capacitor value emv 4.0 4.6v 30na.s x5r/x7r w/ esr < 100 m ? 3.3 ? f iso-7816-3 4.5v 20na.s 1 ? f downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 11 5 voltage supervision two voltage supervisors constantly check the level of the v dd and v cc voltages. a card deactivation sequence is forced when a fault occurs for any of these voltage supervisors. the digital circuitry is powered by the power supply applied on the vdd pin. v dd also defines the voltage range to interface with the system controller. the v dd voltage supervisor is also used to initialize the iso-7816-3 sequencer at power-on, and to deactivate the card at power-off or when a fault occurs. the voltage threshold of the v dd voltage supervisor is internally set by default to 2.3 v nominal. however, it may be desirable in some applications, to modify this threshold value. the pin vddf_adj (pin 18 in the so package, pin 17 in the qfn package) is used to connect an external resistor r ext1 to ground to raise the v dd fault voltage to another value, v ddf (refer to figure 11 ). the resistor value is defined as follows: r ext = 180 k ? / (v ddf - 2.33) an alternative (more accurate) method of adjusting the v dd fault voltage is to use a resistive network of r3 from the pin to supply and r4 from the pin to ground (see figure 11 ). in order to set the new threshold voltage, the equivalent resistance must be determined. this resistance value will be designated kx. kx is defined as r4 /(r4+r5). kx is calculated as: kx = (2.649 / v th ) - 0.6042 where v th is the desired new threshold voltage. to determine the values of r4 and r5, use the following formulas. r5 = 72000 / kx r4 = r5*(kx / (1 C kx)) taking the example above, where a v dd fault threshold voltage of 2.7 v is desired, solving for kx gives: ? kx = (2.649 / 2.7) - 0.6042 = 0.377. solving for r5 gives: ? r5 = 72000 / 0.377 = 191 k ? . solving for r4 gives: ? r4 = 191000 *(0.377 / (1 C 0.377)) = 115.6 k ? . using standard 1% resistor values gives r5 = 191 k ?? and r4 = 115 k ???? these values give an equivalent resistance of kx = 0.376, a 0.3% error. if the 2.3 v default threshold is used, t he vddf_adj pin must be left unconnected. 6 power down a power down function is provided via the pwrdn pin (active high). when activated, the power down (pd) mode disables all the internal analog functions, including the card analog interface, the oscillators and the dc-dc converter, to put the 73s8010c in its lo west power consumption mode. pd mode is only allowed in the deactivated condition (out of a card se ssion, when the start/stop bit is set to 0 from the i 2 c host controller). the host controller invokes the power down state when it is desirable to save power. the signal pres remains functional in pd mode such that a card insertion sets int high. the micro-controller must then set pwrdn low and wait for the inte rnal stabilization time prior to st arting any card session (prior to setting the start/stop bit to 1). resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators + reset of the circuitry) after pwrdn is set low. no card activation should be invoked during this 10 ms time period. if a card is present, int can be used as an indication that the circuit has completed its recovery from power down state. int will go high at the end of the stabilization period. should the start/stop be set to 1 during pwrdn = 1, or within the 10 ms internal stabilization / reset time, it will not be taken into account and the card interface will remain inactive. since start/stop is taken into account on its edges, it should be toggled low and high again after the 10 ms to activate a card. figure 5 illustrates the sequencing of the pd and normal modes. pwrdn must be connected to gnd if the power down function is not used. downloaded from: http:///
73s8010c data sheet ds_8010c_024 12 rev. 1.5 figure 5: power down mode operation 7 over-temperature monitor a built-in detector monitors die temperature. when an over-temperature condition occurs (most likely resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is initiated, and a fault condition is reported to the system controller (bit 4 of the status register is set and generates an interrupt). 8 activation sequence after power on reset, the int signal is low until v dd is stable. when v dd has been stable for approximately 10 ms and the int signal is high, the system controller may read the status register to see if the card is present. if all the status bits are sati sfactory, the system controller can initiate the activation sequence by writing a 1 to the start/sto p bit (bit 0 of the control register). the following steps and figure 6 show the activation sequence and the timing of the card control signals when the system controller initiates the star t/stop bit (bit 0) of the control register: 1. voltage v cc to the card should be valid by the end of t 1 . if v cc is not valid for any reason, then the session is aborted. 2. turn i/o to reception mode at the end of t 1 . 3. clk is applied to the card at the end of t 2 . 4. rst (to the card) is set high at the end of t 3 . figure 6: activation sequence pres int pwrdn internal rc osc start/stop bit off follows pres regardless of pwrdn pwrdn during a card session has no effect after setting pwrdn = 0, the controller must wait at least 10ms before setting start/stop = 1 emv / iso deactivation time ~= 100 us ~10ms pwrdn has effect when the cardi s deactivated t 1 = 0.510 ms (timing by 1.5 mhz internal oscillator), i/o in reception mode t 2 0.5 s, clk starts t 3 ? 42000 card clock cycles, rst set high downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 13 9 deactivation sequence deactivation is initiated either by the system controlle r resetting the start/stop bit, or automatically in the event of hardware faults. hardware faul ts are over-current, over-temperature, v dd fault, v cc fault, and card extraction during the session. the following steps and figure 7 show the deactivation sequence and t he timing of the card control signals when the system contro ller clears the start/stop bit: 1. rst goes low at the end of t 1 . 2. clk goes low at the end of t 2 . 3. i/o goes low at the end of t 3 . out of reception mode. 4. shut down v cc at the end of time t 4 . figure 7: deactivation sequence 10 interrupt the interrupt is an active low interr upt. it is set low if either a v cc fault or a v dd fault is detected. it is also set low if one of the following status bit conditions is detected: ? early atr ? mute atr ? card insert or card extract ? protection status from over-current or over-heating if the interrupt is set low by the detection of these status bits, then the interrupt is set high when these status bits are read. (read status done) figure 8: fault functions, in t operation t 1 0.5 s t 3 0.5 s t 2 7.5 s t 4 0.5 s int any fault status bits read status done downloaded from: http:///
73s8010c data sheet ds_8010c_024 14 rev. 1.5 a power-on-reset (por) event will reset all of the control and status registers to their default states. a v dd fault event does not reset these registers, but it will signal an interrupt condition and by the action of the timer th at creates interval t 1 , will not clear the interrupt until v dd is valid for at least the t 1 time. the v dd fault can be considered valid for v dd as low as 1.5 to 1.8 volts. at the lower range of the v dd fault, por will be asserted. 11 warm reset the 73s8010c automatically asserts a warm reset to the card when instructed through bit 1 of the i 2 c control register (warm reset bit). the warm reset length is automatically defined as 42,000 card clock cycles. the bit warm reset is automatically reset when the card starts answering or when the card is declared mute. figure 9: warm reset operation 12 i/o timing the states of the i/o, aux1, and aux2 pins are lo w after power on reset and they are high when the activation sequencer turns on the i/o reception state. see section 8 activation sequence for more details on when the i/o reception is enabled. the states of i/ouc, aux1uc, and aux2uc are high after power on reset. when the control i/o enable bit (bit 7 of the control register) is set, the firs t i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line. when the input i/o line rising edge is detected then both i/o lines return to their neutral state. the delay between the i/o signals is shown in figure 10 . figure 10: i/o timing warm reset (bit 1) rst t 1 t 2 t 3 io t 1 > 1.5 s, warm reset starts t 2 = 42000 card clock cycles, end of warm reset t 3 = resets warm reset bit 1 when detected atr or mute delay from i/o to i/ouc: t io_hl = 100 ns t io_lh = 25 ns delay from i/ouc to i/o: t i/ouc_hl = 100 ns t i/ouc_lh = 25 ns downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 15 c2 22pf c3 22pf sda_f rom_uc scl_f rom_uc c6 100nf sad2 aux1uc_to.f rom_uc aux2uc_to/f rom_uc external_clock_f rom uc vdd r120k c1 iso7816=1uf, emv=3.3uf l1 10uh r4 rext1 sad1 sad0 r2 2k r3 2k int_interrupt_to_uc vdd see note 1 seenote 6 - or - see note 5 so28 card detection switch is normally closed. clk track should be routed far from rst, i/o, c4 and c8 . see note 3 notes: 1) vdd supply should be = 2.7v to 3.6v dc. 2) hardwire to define address of device 3) required if external clock from up is used. 4) required if crystal is used. y1, c2 and c3 must be removed if external clock is use d. 5) pin can not float. must be driven or connected to gnd if power down function is not used. 6) rext1 and rext2 are external resistors to ground and vdd to modify the vdd fault voltage. can be left open 7) keep l1 cl ose to pi n 5 see note 4 see note 5 low esr (<1 0 0mohms) c1 should be placed near the sc connecter contact iouc_to/f rom_uc see note 7 pwrdn_f rom_uc y1 crystal note 2 smart card connector vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 73s8010c sad0 1 sad1 2 sad2 3 gnd 4 gnd 5 vpc 6 nc 7 aux2 12 nc 8 nc 9 pres 10 i/o 11 aux1 13 gnd 14 clk 15 rst 16 vcc 17 vdd_adj 18 scl 19 sda 20 vdd 21 gnd 22 int_ 23 aux2uc 28 aux1uc 27 xta l o u t 25 xta l i n 24 i/ouc 26 r5 rext2 c4 100nf c510uf 13 typical application schematic figure 11: 73s8010c C typical application schematic downloaded from: http:///
73s8010c data sheet ds_8010c_024 16 rev. 1.5 14 electrical specification 14.1 absolute maximum ratings operation outside these rating limits may cause permanent damage to the device. parameter rating supply voltage v dd -0.5 to 4.0 vdc input voltage for digital inputs -0.3 to (v dd +0.5) vdc storage temperature -60 c to 150 c pin voltage (except lin and card interface) -0.3 to (v dd +0.5) vdc pin voltage (lin) -0.3 to 6.0 vdc pin voltage (card interface) -0.3 to (v cc + 0.5) vdc esd tolerance C card interface pins +/- 6 kv esd tolerance C other pins +/- 2 kv esd testing on card pins uses the hbm condition, 3 pulses, each polarity referenced to ground. 14.2 recommended operating conditions parameter rating supply voltage v dd 2.7 to 3.6 vdc ambient operating temperature -40 c to +85 c input voltage for digital inputs 0 v to v dd + 0.3 v downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 17 14.3 dc characteristics: card interface symbol parameter condition min. typ. max. unit card power supply (v cc ) dc-dc converter general conditions, -40 ? c < t < 85 ? c, 2.7 v < v dd < 3.6 v v cc card supply voltage including ripple and noise inactive mode -0.1 0.1 v inactive mode i cc = 1 ma -0.1 0.4 v active mode i cc < 65 ma; 5 v 4.75 5.25 v active mode i cc < 65 ma; 3 v 2.8 3.2 v active mode single pulse of 100 ma for 2 ? s; 5 v, fixed load = 25 ma 4.6 5.25 v active mode single pulse of 100 ma for 2 ? s; 3 v, fixed load = 25 ma 2.76 3.2 v active mode current pulses of 40 nas with peak |i cc | < 200 ma, t < 400 ns; 5 v 4.6 5.25 v active mode current pulses of 40 nas with peak |i cc | < 200 ma, t < 400 ns; 3 v 2.76 3.2 v i ccmax maximum supply current to the card static load current, v cc > 4.6 or 2.7 v as selected, l=10 ? h 100 ma i ccf i cc fault current short circuit, v cc to ground 100 125 180 ma v sr v cc slew rate - rise rate on activate c f on v cc = 1 f 0.05 0.15 0.25 v/ ? s v sf v cc slew rate - fall rate on deactivate c f on v cc = 1 f 0.1 0.3 0.5 v/ ? s c f external filter capacitor (v cc to gnd) 0.47 1 3.3 ? f l inductor (lin to v dd ) 10 ? h limax imax in inductor v cc = 5 v, i cc = 65 ma, v dd = 2.7 v 400 ma ? efficiency v cc = 5 v, i cc = 65 ma, v dd = 3.3 v 87 % downloaded from: http:///
73s8010c data sheet ds_8010c_024 18 rev. 1.5 1011b01 converter efficiency (vcc 5v) 50 55 60 65 70 75 80 85 90 95 100 0 2 04 06 08 01 0 0 icc [ma] efficiency [%] 2.7v 3.0v 3.3v 3.6v figure 12: dc C dc converter efficiency (v cc = 5 v) output current on vcc at 5 v. input voltage on v dd at 2.7, 3.0, 3.3 and 3.6 volts. 1011b01 converter efficiency (vcc 3v) 50 55 60 65 70 75 80 85 90 95 100 0 20 40 60 80 100 icc [ma] efficiency [%] 2.7v 3.0v 3.3v (linear) 3.6v (linear) figure 13: dc C dc converter efficiency (v cc = 3 v) output current on v cc at 3 v. input voltage on v dd at 2.7, 3.0, 3.3 and 3.6 volts. converter efficiency (v cc 5 v) downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 19 symbol parameter condition min. typ. max. unit interface requirements C data signals: i/o, aux1, aux2, and host interfaces: i/ouc, aux1uc, aux2uc. i shortl , i shorth , and v inact requirements do not pertain to i/ouc, aux1uc, and aux2uc. i il requirements only pertain to i//ouc, aux1uc, and aux2uc. v oh output level, high (i/o, aux1, aux2) i oh = 0 0.9 v cc v cc + 0.1 v i oh = -40 ? a 0.75 v cc v cc + 0.1 v v oh output level, high (i/ouc, aux1uc, aux2uc) i oh = 0 0.9 v dd v dd + 0.1 v i oh = -40 ? a 0.75 v dd v dd + 0.1 v v ol output level, low i ol =1 ma 0.3 v v ih input level, high (i/o, aux1, aux2) 1.8 v cc + 0.30 v v ih input level, high (i/ouc, aux1uc, aux2uc) 1.8 v dd + 0.30 v v il input level, low -0.3 0.8 v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1 ma 0.3 v i leak input leakage v ih = v cc 10 ? a i il input current, low v il = 0, cs = 1 0.65 ma v il = 0, cs = 0 5 a i shortl short circuit output current for output low, shorted to v cc through 33 ? 15 ma i shorth short circuit output current for output high, shorted to ground through 33 ? 15 ma t r , t f output rise time, fall times for i/o, aux1, aux2, c l = 80 pf, 10% to 90% for i/ouc, aux1uc, aux2uc, cl=50 pf, 10% to 90% 100 ns t ir , t if input rise, fall times 1 ? s r pu internal pull-up resistor output stable for >200 ns 8 11 14 k ? fd max maximum data rate 1 mhz t fdio delay, i/o to i/ouc, i/ouc to i/o 20 ns c in input capacitance 10 pf downloaded from: http:///
73s8010c data sheet ds_8010c_024 20 rev. 1.5 symbol parameter condition min. typ. max. unit reset and clock for card interface, rst, clk v oh output level, high i oh = -200 ? a 0.9 v cc v cc v v ol output level, low i ol = 200 ? a 0 0.3 v v inact output voltage when outside of a session i ol = 0 0.1 v i ol = 1 ma 0.3 v i rst_lim output current limit, rst 30 ma i clk_lim output current limit, clk 70 ma t r , t f output rise time, fall time c l = 35 pf for clk, 10% to 90% 8 ns c l = 200 pf for rst, 10% to 90% 100 ns ? duty cycle for clk, except for f=f xtal c l =35 pf, f clk ?? 20 mhz 45 55 % 14.4 dc characteristics: digital signals symbol parameter condition min. typ. max. unit digital i/o except for osc i/o v il input low voltage -0.3 0.8 v v ih input high voltage 1.8 v dd + 0.3 v v ol output low voltage i ol = 2 ma 0.45 v v oh output high voltage i oh = -1 ma v dd - 0.45 v r out pull-up resistor, int 20 k ? |i il1 | input leakage current gnd < v in < v dd -5 5 a oscillator (xtalin) i/o parameters v ilxtal input low voltage - xtalin -0.3 0.3 v dd v v ihxtal input high voltage - xtalin 0.7 v dd v dd +0.3 v i ilxtal input current - xtalin gnd < v in < v dd -30 30 a f max max freq. osc or external clock 27 mhz ? in external input duty cycle limit t r/f < 10% f in , 45% < ? clk < 55% 48 52 % 14.5 dc characteristics: supply symbol parameter condition min. typ. max. unit i dd supply current on v dd linear mode, icc=0 i/o, aux1, aux2=high 4.9 ma step up mode, icc=0 i/o, aux1, aux2=high 4.7 ma i dd_pd supply current on v dd in power down mode pwrdn=1, start/stop bit = 0 all digital inputs driven with a true logical 0 or 1 0.11 2.5 ? a downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 21 14.6 dc characteristics: i 2 c interface symbol parameter condition min. typ. max. unit sda, scl v il input low voltage -0.3 0.3* v dd v v ih input high voltage 0.7*v dd v dd + 0.3 v v ol output low voltage i ol = 3 ma 0.40 v c in pin capacitance 10 pf i in output high voltage i oh = -1 ma v dd - 0.45 v t f output fall time c l = 0 to 400 pf 20 + 0.1*c l 250 ns t sp pulse width of spikes that are suppressed transition from valid logic level to opposite level 50 ns 14.7 voltage / temperature fault detection circuits symbol parameter condition min. typ. max. unit v ddf v dd fault C v dd voltage supervisor threshold no external resistor on vddf_adj pin 2.15 2.4 v v ccf v cc fault C v cc voltage supervisor threshold v cc = 5 v 4.20 4.6 v v cc = 3 v 2.5 2.7 v t f die over temperature fault 115 145 ? c downloaded from: http:///
73s8010c data sheet ds_8010c_024 22 rev. 1.5 15 mechanical drawings 15.1 32-pin qfn figure 14: 32-pin qfn package drawing 0.85 nom. / 0.9max. 0.00 / 0.005 0.20 ref. seating plane side view 0.2 min. 0.35 / 0.45 1.5 / 1.875 3.0 / 3.75 0.18 / 0.3 bottom view 1 2 3 0.25 0.5 0.5 0.25 3.0 / 3.75 1.5 / 1.875 0.35 / 0.45 chamfered 0.30 2.5 5 2.5 5 top view 1 2 3 downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 23 15.2 28-pin so figure 15: 28-pin so package drawing downloaded from: http:///
73s8010c data sheet ds_8010c_024 24 rev. 1.5 16 package pin designation use handling procedures necessary for a static sensitive component. 16.1 32-pin qfn figure 13: 73s8010c 32-pin qfn pin out (top view) 67 8 9 5 4 3 2 1 17 18 19 20 2423 22 21 1011 12 13 14 15 16 32 31 3029 28 27 26 25 gnd lin vdd nc prdwn pres i/o xtalout xtalin int gnd vdd sda scl vddf_adj nc aux2 aux1 gnd clk rst vcc nc teridian 73s8010c nc nc sad2 sad1 sad0 aux2uc aux1uc i/ouc nc downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 25 16.2 28-pin so figure 15: 73s8010c 28-pin so pin out (top view) 73s8010c 1 1817 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 19 20 2827 26 25 24 23 22 21 sad0 sad1 sad2 gnd vdd nc pres i/o aux2 aux1 gnd aux2uc aux1uc i/ouc xtalin xtalout int vdd sda scl vcc rst clk nc lin pwrdn vddf_adj gnd downloaded from: http:///
73s8010c data sheet ds_8010c_024 26 rev. 1.5 17 ordering information part description order number packaging mark 73s8010c-so 28-pin lead-free so 73s8010c-il/f 73s8010c-il 73s8010c-so 28-pin lead-free so tape / reel 73s8010c-ilr/f 73s8010c-il 73s8010c-qfn 32-pin lead-fr ee qfn 73s8010c-im/f 73s8010c 73s8010c-qfn 32-pin lead-free qfn tape / reel 73s8010c-imr/f 73s8010c 18 related documentation the following 73s8010c documents are available from teridian semiconductor corporation: 73s8010c data sheet (this document) 73s8010c 28so demo board users guide 73s8010c qfn demo board users guide 19 contact information for more information about teridian semiconductor products or to check the availability of the 73s8010c, contact us at: 6440 oak canyon road suite 100 irvine, ca 92618-5201 telephone: (714) 508-8800 fax: (714) 508-8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com. downloaded from: http:///
ds_8010c_024 73s8010c data sheet rev. 1.5 27 revision history revision date description 1.0 6/13/2005 first publication. 1.2 9/21/2005 changed sdata hold time. 1.3 12/5/2007 added iso and env logo, remove leaded package options, replace 32qfn punched with sawn, update 28so dimension. 1.4 1/17/2008 changed dimension of botto m exposed pad on 32qfn mechanical package figure. 1.5 4/3/2009 removed all references to vpc as vpc must be tied to vdd. ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. all other trademarks are the proper ty of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, other than expressly contained in the companys warranty detailed in the teridian semiconductor corporation standard terms and conditions. the company assumes no responsi bility for any errors which may appear in this document, reserves the right to change devices or sp ecifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon rd., suite 100, irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http://www.teridian.com downloaded from: http:///

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