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ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 1 ? copyright 2008?2010 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. powerpc is a trademark of ibm corp. and is used under license. all other trademarks are the property of their respective owners. virtex-4qv fpga electrical characteristics space-grade, radiation-tolerant virtex?-4qv fpgas are available in the -10 speed gr ade and qualified for military (t j =?55 c to +125 c) operational temperatures. virtex-4qv fpga dc and ac characteristics are specified for military temperatures on ly. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -10 speed grade military device are the same as for a -10 speed grade industrial device). all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. this virtex-4qv fpga data sheet is part of an overall set of documentation on the virtex-4 family of fpgas available on the xilinx website: ? ds653 , space-grade virtex-4qv family overview ? u g070 , virtex-4 fpga user guide ? u g071 , virtex-4 fpga configuration guide ? ug073 , xtremedsp for virtex-4 fpgas ? ug496 , virtex-4qv fpga ceramic packaging and pinout specifications ? u g072 , virtex-4 fpga pcb designer?s guide virtex-4qv fpga dc characteristics space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 product specification r ta bl e 1 : absolute maximum ratings symbol description units v ccint internal supply voltage relative to gnd ?0.5 to 1.32 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 3.0 v v cco output drivers supply voltage relative to gnd ?0.5 to 3.75 v v batt key memory battery backup supply ?0.5 to 4.05 v v ref input reference voltage ?0.3 to 3.75 v v in i/o input voltage relative to gnd (all user and dedicated i/os) ?0.75 to 4.05 v i/o input voltage relative to gnd (3) (restricted to maximum of 100 user i/os) (4) ?0.85 to 4.3 v 2.5v or below i/o input voltage relative to gnd (user and dedicated i/os) ?0.75 to v cco + 0.5 v v ts voltage applied to 3-state 3.3v output (3) (all user and dedicated i/os) ?0.75 to 4.05 v voltage applied to 3-state 3.3v output (3) (restricted to maximu m of 100 user i/os) (4) ?0.85 to 4.3 v 2.5v or below i/o input voltage relative to gnd (user and dedicated i/os) ?0.75 to v cco + 0.5 v t stg storage temperature (ambient) ?65 to 150 c t sol maximum soldering temperature (2) +220 c t j maximum junction temperature (2) +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. for soldering guidelines and thermal considerations, see the virtex-4qv fpga ceramic packaging and pinout specifications on the xilinx website. 3. for 3.3v i/o operation, refer to the virtex-4 fpga user guide , chapter 6, 3.3v i/o design guidelines, table 6-38. 4. for more flexibility in specific designs, a maximum of 100 user i/os can be stressed beyond the normal spec for no more than 20% of a data period. there are no bank restrictions.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 2 r ta bl e 2 : recommended operating conditions symbol description min max units v ccint internal supply voltage relative to gnd 1.14 1.26 v v ccaux auxiliary supply voltage relative to gnd 2.375 2.625 v v cco (1,2,3,4,5)) supply voltage relative to gnd 1.14 3.45 v v in 3.3v supply voltage relative to gnd gnd ? 0.20 3.45 v 2.5v and below supply voltage relative to gnd gnd ? 0.20 v cco +0.2 v v batt (2) battery voltage relative to gnd 1.0 3.6 v notes: 1. configuration data is retained even if v cco drops to 0v. 2. v batt is required only when using bitstream encryption. if battery is not used, connect v batt to either ground or v ccaux . 3. for 3.3v i/o operation, refer to the virtex-4 fpga user guide . 4. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. 5. the configuration output supply voltage v cc_config is also known as v cco_0 . ta bl e 3 : dc characteristics over recommended operating conditions symbol description min typ max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.9 v v dri data retention v ccaux voltage (below which configuration data might be lost) 2.0 v i ref v ref current per pin 10 a i l input or output leakage current per pin (sample-tested) 10 a c in input capacitance (sample-tested) 10 pf i rpu (1) pad pull-up (when selected) @ v in =0v, v cco =3.3v 5 200 a pad pull-up (when selected) @ v in =0v, v cco =3.0v 5 125 a pad pull-up (when selected) @ v in =0v, v cco =2.5v 5 120 a pad pull-up (when selected) @ v in =0v, v cco = 1.8v 5 60 a pad pull-up (when selected) @ v in =0v, v cco = 1.5v 5 40 a i rpd (1) pad pull-down (when selected) @ v in =v cco 5100a i batt (1) battery supply current 75 na p cpu power dissipation of powerpc? 405 processor block 0.45 mw/ mhz n temperature diode ideality factor 1.02 n r series resistance 2 notes: 1. typical values are specified at nominal voltage, 25c.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 3 r power-on power supply requirements xilinx? fpgas require a certai n amount of supply current during power-on to ensure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. the power supplies can be turned on in any sequence, though the specifications shown in ta b l e 5 are for the recommended power-on sequence of v ccint , v ccaux , v cco . xilinx does not specify th e current for other power-on sequences. ta b l e 5 shows the maximum current required by virtex-4 devices for proper power-on and configuration. once initialized and configur ed, use the xpower tool to estimate current drain on these supplies. ta bl e 4 : quiescent supply current symbol description device typ (1) max units i ccintq quiescent v ccint supply current XQR4VSX55 488 note (4) ma xqr4vfx60 365 note (4) ma xqr4vfx140 796 note (4) ma xqr4vlx200 880 note (4) ma i ccoq quiescent v cco supply current XQR4VSX55 3.00 note (4) ma xqr4vfx60 3.00 note (4) ma xqr4vfx140 5.00 note (4) ma xqr4vlx200 5.00 note (4) ma i ccauxq quiescent v ccaux supply current XQR4VSX55 137 note (4) ma xqr4vfx60 120 note (4) ma xqr4vfx140 215 note (4) ma xqr4vlx200 225 note (4) ma notes: 1. typical values are specified at nominal voltage, 25c. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. if dci or differential signaling is used, more accurate quiescent current estimates can be obtained by using the power estima tor or xpower tool. 4. use the xpower? estimator (xpe) tool to calculate maximum static power for specific process, voltage, and temperature conditi ons. ta bl e 5 : maximum power-on current for virtex-4qv devices device i ccint i ccaux i cco units typ (1) max (2) typ (1) max (2) typ (1) max (2) XQR4VSX55 520 5355 225 930 150 450 ma xqr4vfx60 410 4680 220 1050 150 435 ma xqr4vfx140 860 9540 450 1313 250 563 ma xqr4vlx200 1020 8820 500 1313 250 600 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. maximum values are specified under worst-case process, voltage, and military temperature conditions. ta bl e 6 : power supply ramp time symbol description ramp time units v ccint internal supply voltage relative to gnd 0.20 to 50.0 ms v cco output drivers supply voltage relative to gnd 0.20 to 50.0 ms v ccaux auxiliary supply voltage relative to gnd 0.20 to 50.0 ms
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 4 r selectio dc input and output levels values for v il and v ih are recommended input voltages. unless otherwise noted, values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 7 : select i/o dc input and output levels iostandard attribute v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl ?0.2 0.8 2.0 3.45 0.4 2.4 note(3) note(3) lvcmos33 ?0.2 0.8 2.0 3.45 0.4 v cco ? 0.4 note(3) note(6) lvcmos25 ?0.3 0.7 1.7 v cco +0.3 0.4 v cco ? 0.4 note(3) note(3) lvcmos18 ?0.3 35% v cco 65% v cco v cco +0.3 0.4 v cco ? 0.45 note(4) note(4) lvcmos15 ?0.3 35% v cco 65% v cco v cco +0.3 0.4 v cco ? 0.45 note(4) note(6) pci33_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco 1.5 ?0.5 pci66_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco 1.5 ?0.5 pci-x (5) ?0.2 35% v cco 50% v cco v cco 10% v cco 90% v cco 1.5 ?0.5 gtlp ?0.3 v ref ?0.1 v ref +0.1 ? 0.6 ? 36 ? gtl ?0.3 v ref ?0.05 v ref + 0.05 ? 0.4 ? 32 ? hstl i (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 8 ?8 hstl ii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 16 ?16 hstl iii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 24 ?8 hstl iv (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 48 ?8 diff hstl ii (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 0.4 v cco ?0.4 ? ? sstl2 i ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.61 v tt + 0.61 8.1 ?8.1 sstl2 ii ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.81 v tt + 0.81 16.2 ?16.2 diff sstl2 ii ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 0.5 v cco ?0.5 ? ? sstl18 i ?0.3 v ref ?0.125 v ref + 0.125 v cco +0.3 v tt ?0.47 v tt + 0.47 6.7 ?6.7 sstl18 ii ?0.3 v ref ?0.125 v ref +0.125 v cco +0.3 v tt ?0.60 v tt + 0.60 13.4 ?13.4 diff sstl18 ii ?0.3 50% v cco ?0.125 50% v cco + 0.125 v cco +0.3 0.4 v cco ?0.4 ? ? notes: 1. tested according to relevant specifications. 2. applies to both 1.5v and 1.8v hstl. 3. using drive strengths of 2, 4, 6, 8, 12, 16, or 24 ma. 4. using drive strengths of 2, 4, 6, 8, 12, or 16 ma. 5. for more information on pci33_3, pci66_3, and pcix, refer to the virtex-4 fpga user guide, selectio resources, chapter 6 . 6. lvcmos15 4 ma, lvcmos33 6 ma, lvcmos33 8 ma have reduced drive strength (i oh ) by 20%.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 5 r ldt dc specifications (ldt_25) lvds dc specifications (lvds_25) extended lvds dc specif ications (lvdsext_25) ta bl e 8 : ldt dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v od differential output voltage (1,2) r t = 100 across q and q signals 495 600 750 mv v od change in v od magnitude ?15 15 mv v ocm output common mode voltage r t = 100 across q and q signals 495 600 715 mv v ocm change in v ocm magnitude ?15 15 mv v id input differential voltage 200 600 1000 mv v id change in v id magnitude ?15 15 mv v icm input common mode voltage 440 600 780 mv v icm change in v icm magnitude ?15 15 mv notes: 1. recommended input maximum voltage not to exceed v cc0 +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 9 : lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 across q and q signals 1.602 v v ol output low voltage for q and q r t = 100 across q and q signals 0.898 v v odiff differential output voltage (1,2) (q ? q ), q = high (q ?q), q = high r t = 100 across q and q signals 247 350 550 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.100 1.250 1.375 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high 100 350 600 mv v icm input common-mode voltage 0.3 1.2 2.2 v notes: 1. recommended input maximum voltage not to exceed v cc0 +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 1 0 : extended lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.785 v v ol output low voltage for q and q r t = 100 across q and q signals 0.715 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 across q and q signals 380 ? 820 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.000 1.250 1.375 v v idiff differential input voltage (1,2) (q ? q ), q = high (q ?q), q = high common-mode input voltage = 1.25v 100 ? 1000 mv v icm input common-mode voltage differentia l input voltage = 350 mv 0.3 1.2 2.2 v notes: 1. recommended input maximum voltage not to exceed v cc +0.2v. 2. recommended input minimum voltage not to go below ?0.5v.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 6 r lvpecl dc specifi cations (lvpecl_25) these values are valid when driving a 100 differential load only, for example, a 100 resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. ta bl e 1 1 summarizes the dc output specif ications of lvpecl. for more information on using lvpecl , see the virtex-4 fpga user guide : chapter 6, selectio resources . interface performan ce characteristics ta bl e 1 1 : lvpecl dc specifications symbol dc parameter min typ max units v oh output high voltage v cc ? 1.025 1.545 v cc ?0.88 v v ol output low voltage v cc ? 1.81 0.795 v cc ?1.62 v v icm input common-mode voltage 0.6 2.2 v v idiff differential input voltage (1,2) 0.100 1.5 v notes: 1. recommended input maximum voltage not to exceed v cc0 +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 1 2 : interface performances description speed grade -10 networking applications sfi-4.1 (sdr lvds interface) (5) 500 mhz spi-4.2 (ddr lvds interface) 800 mb/s memory interfaces ddr (1) 426 mb/s ddr2 (2) 510 mb/s qdr ii sram (3) 514 mb/s rldram ii (4) 524 mb/s notes: 1. performance defined using design implementation described in application note xapp709 : ddr sdram controller using virtex-4 fpga devices . 2. performance defined using design implementation described in application note xapp702 : ddr2 controller using virtex-4 devices . 3. performance defined using design implementation described in application note xapp703 : qdr ii sram interface for virtex-4 devices . 4. performance defined using design implementation described in application note xapp710 : synthesizable cio ddr rldram ii controller for virtex-4 fpgas . 5. 644 mhz not supported for operating temperatures above 100c.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 7 r switching characteristics switching characteristics are specified on a per-speed- grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under- reporting might still occur. preliminary these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. ta bl e 1 3 correlates the current status of each virtex-4qv device with a corresponding speed specification version 1.67 designation. because individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. all specifications are always representative of worst-case supply voltage and junction temperature conditions. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotate to the simulation net list. unless otherwise noted, values apply to all virtex-4qv fpgas. ta b l e 1 3 : virtex-4qv device speed grade designations device speed grade designations advance preliminary production XQR4VSX55 -10 xq4rvfx60 -10 xqr4vfx140 -10 xqr4vlx200 -10
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 8 r powerpc processor switching characteristics consult u g018 , powerpc 405 processor block reference guide for further information. ta bl e 1 4 : powerpc 405 processor clocks absolute ac characteristics description speed grade units -10 min max characteristics when apu not used cpmc405clock frequency (1,4) 0350mhz cpmdcrclk (3) 0350mhz cpmfcmclk (3) ??mhz jtagc405tck frequency (2) 0175mhz plbclk (3) 0350mhz bramdsocmclk (3) 0350mhz bramisocmclk (3) 0350mhz characteristics when apu used cpmc405clock frequency (1,4) 0233mhz cpmdcrclk (3) 0233mhz cpmfcmclk (3) 0233mhz jtagc405tck frequency (2) 0 116.5 mhz plbclk (3) 0233mhz bramdsocmclk (3) 0233mhz bramisocmclk (3) 0233mhz notes: 1. worst-case dcm output clock jitter is included in these specifications. 2. the theoretical maximum frequency of this clock is one-half t he cpmc405clock. however, the achievable maximum is system depen dent, and will be much less. 3. the theoretical maximum frequency of these clocks is equal to the cpmc405clock. integer cloc k ratios are required for the cpmc405clock and bramdsocmclk , cpmc405clock and bramisocmclk , cpmc405clock and cpmdcrclk, cpmc405clock and cpmfcmclk, and cpmc405clock and plbclk. the integer ratios can be different for each interface. however, the achievable maximum is system dependent. 4. maximum operating frequency of cpmc405clock is specified with the input pin tiec405disoperandfwd connected to a logic 1.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 9 r ta bl e 1 5 : processor block switching characteristics description symbol speed grade units -10 setup and hold relative to clock (cpmc405clock) clock and power management control inputs t ppcdck_corecki t ppcckd_corecki 0.74 0.23 ns min reset control inputs t ppcdck_rstchip t ppcckd_rstchip 0.74 0.23 ns min debug control inputs t ppcdck_exbushak t ppcckd_exbushak 0.74 0.23 ns min trace control inputs t ppcdck_trcdis t ppcckd_trcdis 0.74 0.23 ns min external interrupt controller control inputs t ppcdck_cinpirq t ppcckd_cinpirq 1.40 0.23 ns min clock to out clock and power management control outputs t ppccko_coreslp 1.74 ns max reset control outputs t ppccko_rstchip 1.83 ns max debug control outputs t ppccko_dbgldapu 1.70 ns max trace control outputs t ppccko_trccycle 1.83 ns max clock cpmc405clock minimum pulse width, high t cpwh 1.43 ns min cpmc405clock minimum pulse width, low t cpwl 1.43 ns min ta bl e 1 6 : processor block plb switching characteristics description symbol speed grade units -10 setup and hold relati ve to clock (plbclk) processor local bus (icu/dcu) control inputs t ppcdck_icubusy t ppcckd_icubusy 0.76 0.23 ns min processor local bus (icu/dcu) data inputs t ppcdck_icurddb t ppcckd_icurddb 1.15 0.23 ns min clock to out processor local bus (icu/dcu) control outputs t ppccko_dcuabort 2.05 ns max processor local bus (icu/dcu) address bus outputs t ppccko_icuabus 2.13 ns max processor local bus (i cu/dcu) data bus outputs t ppccko_dcuwrdbus 2.57 ns max ta bl e 1 7 : processor block jtag switching characteristics description symbol speed grade units -10 setup and hold relative to clock (jtagc405tck) jtag control inputs t ppcdck_jtgtdi t ppcckd_jtgtdi 1.48 0.23 ns min jtag reset input t ppcdck_jtgtrstn t ppcckd_jtgtrstn 0.74 0.23 ns min clock to out jtag control outputs t ppccko_jtgtdo 2.14 ns max
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 10 r ta bl e 1 8 : powerpc 405 data-side on-chip memory switching characteristics description symbol speed grade units -10 setup and hold relative to clock (bramdsocmclk) data-side on-chip memory data bus inputs t ppcdck_dsocmrddb t ppcckd_dsocmrddb 0.74 0.23 ns min clock to out data-side on-chip memory control outputs t ppccko_brambwr 2.65 ns max data-side on-chip memory address bus outputs t ppccko_bramabus 2.65 ns max data-side on-chip memory data bus outputs t ppccko_ibramwrdbus01 2.06 ns max ta bl e 1 9 : powerpc 405 instruction-side on-chip memory switching characteristics description symbol speed grade units -10 setup and hold relative to clock (bramisocmclk) instruction-side on-chip memory data bus inputs t ppcdck_isocmrddb t ppcckd_isocmrddb 0.94 0.23 ns min clock to out instruction-side on-chip memory control outputs t ppccko_ibramen 3.88 ns max instruction-side on-chip memory address bus outputs t ppccko_ibramrdabus 2.13 ns max instruction-side on-chip memory data bus outputs t ppccko _ ibramwrdbus 2.14 ns max ta bl e 2 0 : processor block dcr bus switching characteristics description symbol speed grade units -10 setup and hold relative to clock (cpmdcrclock) device control register bus control inputs t ppcdck_exdcrack t ppcckd_exdcrack 0.15 0.19 ns min device control register bus data inputs t ppcdck_exdcrdbusi t ppcckd_exdcrdbusi 1.02 0.27 ns min clock to out device control register bus control outputs t ppccko_exdcrrd 1.54 ns max device control register bus address bus outputs t ppccko_exdcrabus 1.66 ns max device control register bus data bus outputs t ppccko_exdcrdbuso 1.67 ns max ta bl e 2 1 : processor block apu interface switching characteristics description symbol speed grade units -10 setup and hold relative to clock (cpmdfcmclock) apu bus control inputs t ppcdck_dcdcren t ppcckd_dcdcren 0.42 0.23 ns min apu bus data inputs t ppcdck_result t ppcckd_result 0.78 0.23 ns min clock to out apu bus control outputs t ppccko_apufcmdec 2.00 ns max apu bus data outputs t ppccko_radata 2.00 ns max
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 11 r iob pad input/output/3-state switching characteristics ta bl e 2 2 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on the capability of the selectio? input buffer technology. t ioop is described as the delay fr om the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of the selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. table 24, page 16 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (for example, a high-impedance state). ta bl e 2 2 : iob switching characteristics (1,2) iostandard attribute (1) speed grade units -10 t iopi t ioop t iotp lvds_25 1.28 1.85 1.85 ns rsds_25 1.28 1.85 1.85 ns lvdsext_25 1.30 1.91 1.91 ns ldt_25 1.28 1.82 1.82 ns blvds_25 1.28 2.34 2.34 ns ulvds_25 1.28 1.83 1.83 ns pci33_3 (pci, 33 mhz, 3.3v) 0.97 3.02 3.02 ns pci66_3 (pci, 66 mhz, 3.3v) 0.97 2.72 2.72 ns pci-x 0.97 2.25 2.25 ns gtl 1.63 2.03 2.03 ns gtlp 1.68 2.03 2.03 ns hstl_i 1.64 2.35 2.35 ns hstl_ii 1.64 2.13 2.13 ns hstl_iii 1.64 2.22 2.22 ns hstl_iv 1.64 2.03 2.03 ns hstl_i _18 1.60 2.21 2.21 ns hstl_ii _18 1.60 2.16 2.16 ns hstl_iii _18 1.60 2.09 2.09 ns hstl_iv_18 1.60 2.06 2.06 ns sstl2_i 1.68 2.43 2.43 ns sstl2_ii 1.68 2.16 2.16 ns lvttl, slow, 2 ma 0.97 7.03 7.03 ns lvttl, slow, 4 ma 0.97 5.04 5.04 ns lvttl, slow, 6 ma 0.97 4.91 4.91 ns lvttl, slow, 8 ma 0.97 4.91 4.91 ns lvttl, slow, 12 ma 0.97 3.96 3.96 ns lvttl, slow, 16 ma 0.97 3.46 3.46 ns lvttl, slow, 24 ma 0.97 3.12 3.12 ns lvttl, fast, 2 ma 0.97 4.86 4.86 ns lvttl, fast, 4 ma 0.97 3.46 3.46 ns lvttl, fast, 6 ma 0.97 3.00 3.00 ns
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 12 r lvttl, fast, 8 ma 0.97 2.79 2.79 ns lvttl, fast, 12 ma 0.97 2.47 2.47 ns lvttl, fast, 16 ma 0.97 2.47 2.47 ns lvttl, fast, 24 ma 0.97 2.20 2.20 ns lvcmos33, slow, 2 ma 0.97 8.73 8.73 ns lvcmos33, slow, 4 ma 0.97 6.09 6.09 ns lvcmos33, slow, 6 ma 0.97 5.00 5.00 ns lvcmos33, slow, 8 ma 0.97 3.95 3.95 ns lvcmos33, slow, 12 ma 0.97 3.42 3.42 ns lvcmos33, slow, 16 ma 0.97 2.49 2.49 ns lvcmos33, slow, 24 ma 0.97 2.49 2.49 ns lvcmos33, fast, 2 ma 0.97 7.44 7.44 ns lvcmos33, fast, 4 ma 0.97 4.33 4.33 ns lvcmos33, fast, 6 ma 0.97 3.55 3.55 ns lvcmos33, fast, 8 ma 0.97 2.46 2.46 ns lvcmos33, fast, 12 ma 0.97 2.27 2.27 ns lvcmos33, fast, 16 ma 0.97 2.08 2.08 ns lvcmos33, fast, 24 ma 0.97 2.08 2.08 ns lvcmos25, slow, 2 ma 0.88 5.89 5.89 ns lvcmos25, slow, 4 ma 0.88 5.02 5.02 ns lvcmos25, slow, 6 ma 0.88 4.31 4.31 ns lvcmos25, slow, 8 ma 0.88 4.31 4.31 ns lvcmos25, slow, 12 ma 0.88 3.50 3.50 ns lvcmos25, slow, 16 ma 0.88 3.31 3.31 ns lvcmos25, slow, 24 ma 0.88 2.77 2.77 ns lvcmos25, fast, 2 ma 0.88 3.89 3.89 ns lvcmos25, fast, 4 ma 0.88 3.19 3.19 ns lvcmos25, fast, 6 ma 0.88 2.81 2.81 ns lvcmos25, fast, 8 ma 0.88 2.52 2.52 ns lvcmos25, fast, 12 ma 0.88 2.43 2.43 ns lvcmos25, fast, 16 ma 0.88 2.21 2.21 ns lvcmos25, fast, 24 ma 0.88 2.13 2.13 ns lvcmos18, slow, 2 ma 1.25 5.89 5.89 ns lvcmos18, slow, 4 ma 1.25 4.35 4.35 ns lvcmos18, slow, 6 ma 1.25 4.00 4.00 ns lvcmos18, slow, 8 ma 1.25 3.76 3.76 ns lvcmos18, slow, 12 ma 1.25 3.74 3.74 ns lvcmos18, slow, 16 ma 1.25 3.55 3.55 ns lvcmos18, fast, 2 ma 1.25 3.89 3.89 ns lvcmos18, fast, 4 ma 1.25 3.02 3.02 ns lvcmos18, fast, 6 ma 1.25 2.72 2.72 ns ta bl e 2 2 : iob switching characteristics (1,2) (cont?d) iostandard attribute (1) speed grade units -10 t iopi t ioop t iotp
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 13 r lvcmos18, fast, 8 ma 1.25 2.52 2.52 ns lvcmos18, fast, 12 ma 1.25 2.36 2.36 ns lvcmos18, fast, 16 ma 1.25 2.27 2.27 ns lvcmos15, slow, 2 ma 1.34 6.61 6.61 ns lvcmos15, slow, 4 ma 1.34 4.88 4.88 ns lvcmos15, slow, 6 ma 1.34 4.26 4.26 ns lvcmos15, slow, 8 ma 1.34 4.26 4.26 ns lvcmos15, slow, 12 ma 1.34 3.77 3.77 ns lvcmos15, slow, 16 ma 1.34 3.53 3.53 ns lvcmos15, fast, 2 ma 1.34 4.17 4.17 ns lvcmos15, fast, 4 ma 1.34 3.32 3.32 ns lvcmos15, fast, 6 ma 1.34 2.94 2.94 ns lvcmos15, fast, 8 ma 1.34 2.71 2.71 ns lvcmos15, fast, 12 ma 1.34 2.50 2.50 ns lvcmos15, fast, 16 ma 1.34 2.43 2.43 ns lvdci_33 0.97 3.13 3.13 ns lvdci_25 0.88 3.02 3.02 ns lvdci_18 1.25 2.95 2.95 ns lvdci_15 1.34 2.93 2.93 ns lvdci_dv2_25 0.88 2.27 2.27 ns lvdci_dv2_18 1.25 2.28 2.28 ns lvdci_dv2_15 1.34 2.58 2.58 ns gtl_dci 1.51 2.03 2.03 ns gtlp_dci 1.23 2.03 2.03 ns hstl_i_dci 1.64 2.35 2.35 ns hstl_ii_dci 1.64 2.13 2.13 ns hstl_iii_dci 1.64 2.22 2.22 ns hstl_iv_dci 1.64 2.03 2.03 ns hstl_i_dci_18 1.60 2.21 2.21 ns hstl_ii_dci_18 1.60 2.16 2.16 ns hstl_iii_dci_18 1.60 2.09 2.09 ns hstl_iv_dci_18 1.60 2.06 2.06 ns sstl2_i_dci 1.68 2.46 2.46 ns sstl2_ii_dci 1.68 2.45 2.45 ns lvpecl_25 1.77 1.74 1.74 ns sstl18_i 1.68 2.54 2.54 ns sstl18_ii 1.68 2.24 2.24 ns sstl18_i_dci 1.68 2.32 2.32 ns sstl18_ii_dci 1.68 2.18 2.18 ns notes: 1. the i/o standard is selected in the xilinx ise? software tool using the iostandard attribute. 2. all i/o timing specifications are measured with v cco at -5% from nominal. ta bl e 2 2 : iob switching characteristics (1,2) (cont?d) iostandard attribute (1) speed grade units -10 t iopi t ioop t iotp
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 14 r ta bl e 2 3 : t ioop and t iotp offset for 125c operation iostandard attribute speed grade units -10 i grade v grade delta lv d s 1.85 2.23 0.38 ns rsds 1.85 2.23 0.38 ns lvdsext 1.91 2.25 0.34 ns ldt 1.82 2.23 0.41 ns pci33_3 3.02 3.26 0.24 ns pci66_3 2.72 3.26 0.54 ns pcix 2.25 2.49 0.24 ns gtl 2.03 2.27 0.24 ns gtlp 2.03 2.25 0.22 ns hstl_i 2.35 2.54 0.19 ns hstl_ii 2.13 2.47 0.34 ns hstl_iii 2.22 2.55 0.33 ns hstl_iv 2.03 2.43 0.40 ns hstl_i_18 2.21 2.43 0.22 ns hstl_ii_18 2.16 2.39 0.23 ns hstl_iii_18 2.09 2.40 0.31 ns hstl_iv_18 2.06 2.38 0.32 ns sstl2_i 2.43 2.46 0.03 ns sstl2_ii 2.16 2.27 0.11 ns lvttl_s2 7.03 9.95 2.92 ns lvttl_s4 5.04 7.84 2.80 ns lvttl_s6 4.91 6.67 1.76 ns lvttl_s8 4.91 6.40 1.49 ns lvttl_s12 3.96 4.87 0.91 ns lvttl_s16 3.46 4.42 0.96 ns lvttl_s24 3.12 3.24 0.12 ns lvttl_f2 4.86 8.44 3.58 ns lvttl_f4 3.46 6.41 2.95 ns lvttl_f6 3.00 4.76 1.76 ns lvttl_f8 2.79 3.97 1.18 ns lvttl_f12 2.47 2.92 0.45 ns lvttl_f16 2.47 2.93 0.46 ns lvttl_f24 2.20 2.87 0.67 ns lvcmos33_s2 8.73 11.43 2.70 ns lvcmos33_s4 6.09 8.56 2.47 ns lvcmos33_s6 5.00 7.27 2.27 ns lvcmos33_s8 3.95 6.35 2.40 ns lvcmos33_s12 3.42 4.74 1.32 ns
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 15 r lvcmos33_s16 2.49 4.56 2.07 ns lvcmos33_s24 2.49 3.06 0.57 ns lvcmos33_f2 7.44 10.18 2.74 ns lvcmos33_f4 4.33 6.18 1.85 ns lvcmos33_f6 3.55 5.53 1.98 ns lvcmos33_f8 2.46 4.47 2.01 ns lvcmos33_f12 2.27 3.22 0.95 ns lvcmos33_f16 2.08 2.74 0.66 ns lvcmos33_f24 2.08 2.61 0.53 ns lvcmos25_s2 5.89 8.57 2.68 ns lvcmos25_s4 5.02 6.44 1.42 ns lvcmos25_s6 4.31 6.00 1.69 ns lvcmos25_s8 4.31 5.24 0.93 ns lvcmos25_s12 3.50 4.30 0.80 ns lvcmos25_s16 3.31 3.95 0.64 ns lvcmos25_s24 2.77 2.64 -0.13 ns lvcmos25_f2 3.89 7.97 4.08 ns lvcmos25_f4 3.19 4.99 1.80 ns lvcmos25_f6 2.81 3.92 1.11 ns lvcmos25_f8 2.52 3.29 0.77 ns lvcmos25_f12 2.43 2.43 0.00 ns lvcmos25_f16 2.21 2.39 0.18 ns lvcmos25_f24 2.13 2.39 0.26 ns lvcmos18_s2 5.89 8.68 2.79 ns lvcmos18_s4 4.35 7.31 2.96 ns lvcmos18_s6 4.00 5.66 1.66 ns lvcmos18_s8 3.76 5.11 1.35 ns lvcmos18_s12 3.74 4.59 0.85 ns lvcmos18_s16 3.55 3.89 0.34 ns lvcmos18_f2 3.89 8.34 4.45 ns lvcmos18_f4 3.02 5.99 2.97 ns lvcmos18_f6 2.72 4.35 1.63 ns lvcmos18_f8 2.52 3.66 1.14 ns lvcmos18_f12 2.36 2.80 0.44 ns lvcmos18_f16 2.27 2.70 0.43 ns lvcmos15_s2 6.61 9.21 2.60 ns lvcmos15_s4 4.88 7.75 2.87 ns lvcmos15_s6 4.26 6.14 1.88 ns ta bl e 2 3 : t ioop and t iotp offset for 125c operation (cont?d) iostandard attribute speed grade units -10 i grade v grade delta
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 16 r ethernet mac switching characteristics consult ug074 , virtex-4 embedded tri-mode ethernet mac user guide for further information. lvcmos15_s8 4.26 6.18 1.92 ns lvcmos15_s12 3.77 4.77 1.00 ns lvcmos15_s16 3.53 4.07 0.54 ns lvcmos15_f2 4.17 8.32 4.15 ns lvcmos15_f4 3.32 6.53 3.21 ns lvcmos15_f6 2.94 4.69 1.75 ns lvcmos15_f8 2.71 3.90 1.19 ns lvcmos15_f12 2.50 2.92 0.42 ns lvcmos15_f16 2.43 2.84 0.41 ns sstl18_i 2.54 2.44 -0.10 ns sstl18_ii 2.24 2.42 0.18 ns ta bl e 2 4 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -10 t iotphz t input to pad high-impedance 1.12 ns ta bl e 2 5 : maximum ethernet mac performance description speed grade units -10 ethernet mac maximum performance 10/100/1000 mb/s ta bl e 2 3 : t ioop and t iotp offset for 125c operation (cont?d) iostandard attribute speed grade units -10 i grade v grade delta
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 17 r input/output logic switching characteristics ta bl e 2 6 : ilogic switching characteristics symbol description speed grade units -10 setup/hold t ice1ck / t ickce1 ce1 pin setup/hold with respect to clk 0.79/?0.23 ns t iceck / t ickce dlyce pin setup/hold with re spect to clkdiv 0.23/0.16 ns t irstck / t ickrst dlyrst pin setup/hold with respect to clkdiv ?0.02/0.54 ns t iincck / t ickinc dlyinc pin setup/hold with respect to clkdiv 0.01/0.51 ns t isrck / t icksr sr/rev pin setup/hold with respect to clk 1.59/?0.56 ns t idock / t iockd d pin setup/hold with respect to clk without delay 0.34/?0.10 ns t idockd / t iockdd d pin setup/hold with respect to clk (iobdelay_type = default) 8.84/?5.99 ns d pin setup/hold with respect to clk (iobdelay_type = fixed, iobdelay_value = 0) 1.09/?0.63 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.24 ns t idid d pin to o pin propagation delay (iobdelay_type = default) 7.96 ns d pin to o pin propagation delay (iobdelay_type = fixed, iobdelay_value = 0) 0.99 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.71 ns t idlod d pin to q1 pin using flip-flop as a latch (iobdelay_type = default) 9.21 ns d pin to q1 pin using flip-flop as a latch (iobdelay_type = fixed, iobdelay_value = 0) 1.45 ns t ickq clk to q outputs 0.72 ns t ice1q ce1 pin to q1 using flip-flop as a latch, propagation delay 1.27 ns t rq sr/rev pin to oq/tq out 2.44 ns t gsrq global set/reset to q outputs 2.03 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.70 ns, min
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 18 r ta bl e 2 7 : ologic switching characteristics symbol description speed grade units -10 setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk 0.75/?0.22 ns t ooceck /t ockoce oce pin setup/hold with respect to clk 0.77/?0.33 ns t osrck /t ocksr sr/rev pin setup/hold with respect to clk 1.42/?0.55 ns t otck /t ockt t1/t2 pins setup/hold with respect to clk 0.75/?0.22 ns t otceck /t ocktce tce pin setup/hold with respect to clk 0.77/?0.33 ns combinatorial t odq d1 to oq out 0.76 ns t otq t1 to tq out 0.76 ns sequential delays t iosron rev pin to tq out 1.64 ns t ockq clk to oq/tq out 0.59 ns t rq sr/rev pin to oq/tq out 1.64 ns t gsrq global set/reset to q outputs 2.03 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.70 ns min
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 19 r input serializer/deserializer switching characteristics ta bl e 2 8 : iserdes switching characteristics symbol description speed grade units -10 setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.40/?0.13 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.69/?0.25 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) 0.16/?0.02 ns t iscck_dlyce / t isckc_dlyce dlyce pin setup/hold with re spect to clkdiv 0.23/0.16 ns t iscck_dlyinc / t isckc_dlyinc dlyinc pin setup/hold with respect to clkdiv 0.01/0.51 ns t iscck_dlyrst / t isckc_dlyrst dlyrst pin setup/hold with respect to clkdiv ?0.02/0.54 ns t iscck_rev rev pin setup with respect to clk 1.23 ns t iscck_sr sr pin setup with respect to clkdiv 0.92 ns setup/hold for data lines t isdck_d / t isckd_d d pin setup/hold with respect to clk (iobdelay = ibuf or none) 0.34/?0.11 ns d pin setup/hold with respect to clk (iobdelay = ifd or both, iobdelay_type = default) 8.84/?6.51 ns d pin setup/hold with respect to clk (1) (iobdelay = ifd or both, iobdelay_type = fixed, iobdelay_value = 0) 1.08/?0.68 ns t isdck_ddr / t isckd_ddr d pin setup/hold with respect to clk at ddr mode (iobdelay = ibuf or none) 0.34/?0.11 ns d pin setup/hold with respect to clk at ddr mode (iobdelay = ifd or both, iobdelay_type = default) 8.84/?6.51 ns d pin setup/hold with respect to clk at ddr mode (1) (iobdelay = ifd or both, iobdelay_type = fixed, iobdelay_value = 0) 1.08/?0.68 ns sequential delays t iscko_q clkdiv to out at q pin 0.85 ns propagation delays t isdo_do_iobdelay_ifd d input to do output pin (iobdelay = ifd) 0.24 ns t isdo_do_iobdelay_none d input to do output pi n (iobdelay = none) 0.24 ns t isdo_do_iobdelay_both d input to do output pin (iobdelay = both, iobdelay_type = default) 7.96 ns d input to do output pin (1) (iobdelay = both, iobdelay_type = fixed, iobdelay_value = 0) 0.99 ns t isdo_do_iobdelay_ibuf d input to do output pin (iobdelay = ibuf, iobdelay_type = default) 7.96 ns d input to do output pin (1) (iobdelay = ibuf, iobdelay_type = fixed, iobdelay_value = 0) 0.99 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce / t isckc_ce in trce report.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 20 r input delay switching characteristics output serializer/deserializ er switching characteristics ta bl e 2 9 : input delay switching characteristics symbol description speed grade units -10 t idelayresolution idelay chain delay resolution 75 ps t idelaytotal_err cumulative delay at a given tap (3) [(tap ? 1) x 75 + 34] 0.07[(tap ? 1) x 75 + 34] ps t idelayctrlco_rdy reset to ready for idelayctrl (maximum) 3.00 s f idelayctrl_ref refclk frequency 200 mhz idelayctrl_ref_precision (2) refclk precision 10 mhz t idelayctrl_rpw minimum reset pulse width 50.0 ns t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern 0note (1) pattern dependent period jitter in delay chain for random data pattern (prbs 23) 10 2 note (1) notes: 1. units in ps peak-to-peak per tap. 2. see the ?refclk - reference clock? section (specific to idelayctrl) in the virtex-4 fpga user guide: chapter 7, ? selectio logic resources .? 3. this value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps. ta bl e 3 0 : oserdes switching characteristics symbol description speed grade units -10 setup/hold t osdck_d / t osckd_d d input setup/hold with respect to clkdiv 0.50/?0.03 ns t osdck_t / t osckd_t (1) t input setup/hold with re spect to clk 0.62/?0.16 ns t osdck_t2 / t osckd_t2 (1) t input setup/hold with res pect to clkdiv 0.50/?0.03 ns t oscck_oce / t osckc_oce oce input setup/hold with respect to clk 0.64/0.03 ns t oscck_s sr (reset) input setup with respect to clkdiv 0.96 ns t oscck_tce / t osckc_tce tce input setup/hold with respect to clk 0.64/0.03 ns sequential delays t oscko_oq clock to out from clk to oq 0.59 ns t oscko_tq clock to out from clk to tq 0.59 ns combinatorial t osdo_ttq t input to tq out 0.76 ns t osco_oq asynchronous reset to oq 1.64 ns t osco_tq asynchronous reset to tq 1.64 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t / t osckd_t in trce report.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 21 r clb switching characteristics ta bl e 3 1 : clb switching characteristics symbol description speed grade units -10 combinatorial delays t ilo 4-input function: f/g inputs to x/y outputs 0.20 ns, max t if5 5-input function: f/g inputs to f5 output 0.46 ns, max t if5x 5-input function: f/g inputs to x output 0.57 ns, max t if6y fxina or fxinb inputs to ymux output 0.39 ns, max t inafx fxina input to fx output via muxfx 0.27 ns, max t inbfx fxinb input to fx output via muxfx 0.26 ns, max t bxx bx input to xmux output 0.76 ns, max t byy by input to ymux output 0.56 ns, max t bxcy bx input to c out output ? getting into carry chain (2) 0.78 ns, max t bycy by input to c out output ? getting into carry chain (2) 0.63 ns, max t byp c in input to c out output ? carry chain delay (2) 0.09 ns, max t opcyf f input to c out output ? getting out from carry chain (2) 0.58 ns, max t opcyg g input to c out output ? getting out from carry chain (2) 0.57 ns, max sequential delays t cko ff clock clk to xq/yq outputs 0.36 ns, max t cklo latch clock clk to xq/yq outputs 0.48 ns, max setup and hold times of clb flip-flops before/after clock clk t dick / t ckdi bx/by inputs 0.47/?0.09 ns, min t ceck / t ckce ce input 0.75/?0.16 ns, min t fxck / t ckfx fxina/fxinb inputs 0.54/?0.14 ns, min t srck / t cksr sr/by inputs (synchronous) 1.35/?0.73 ns, min t cinck / t ckcin c in data inputs (di) ? getting out from carry chain (2) 0.67/?0.23 ns, min set/reset t rpw minimum pulse width, sr/by inputs 0.70 ns, min t rq delay from sr/by inputs to xq/yq outputs (asynchronous) 1.35 ns, max f tog toggle frequency (mhz) (for export control) 1028 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. these items are of interest for carry chain applications.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 22 r clb distributed ram switching characteristics (slicem only) ) clb shift register switching characteristics (slicem only) ) ta bl e 3 2 : clb distributed ram swit ching characteristics symbol description speed grade units -10 sequential delays t shcko clock clk to x outputs (we active) 2.08 ns, max t shckof5 clock clk to f5 output (we active) 1.98 ns, max setup and hold times before/after clock clk t ds / t dh bx/by data inputs (d i) 1.80/?0.88 ns, min t as / t ah f/g address inputs 1.13/?0.29 ns, min t ws / t wh we input (sr) 1.42/?0.47 ns, min clock clk t wph minimum pulse width, high 0.69 ns, min t wpl minimum pulse width, low 0.70 ns, min t wc minimum clock period to meet address write cycle time 0.98 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. t shcko also represents the clk to xmux output. refer to trce report for the clk to xmux path. ta bl e 3 3 : clb shift register switching characteristics symbol description speed grade units -10 sequential delays t reg clock clk to x/y outputs 2.57 ns, max t regxb clock clk to xb output via mc15 lut output 2.04 ns, max t regyb clock clk to yb output via mc15 lut output 2.17 ns, max t cksh clock clk to shiftout 1.99 ns, max t regf5 clock clk to f5 output 2.47 ns, max setup and hold times before/after clock clk t ws / t wh we input (sr) 1.12/?0.62 ns, min t ds / t dh bx/by data inputs (d i) 1.75/?1.11 ns, min clock clk t wph minimum pulse width, high 0.69 ns, min t wpl minimum pulse width, low 0.70 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 23 r block ram and fifo switching characteristics ta bl e 3 4 : block ram switching characteristics symbol description speed grade units -10 sequential delays t rcko_dora clock clk to dout output (without output register) (2) 2.10 ns, max t rcko_doa clock clk to dout output (with output register) (3) 0.92 ns, min setup and hold tim es before clock clk t rcck_addr / t rckc_addr addr inputs 0.43/0.33 ns, min t rdck_di / t rckd_di din inputs (4) 0.23/0.33 ns, min t rcck_en / t rckc_en en input (5) 0.52/0.33 ns, min t rcck_regce / t rckc_regce ce input of output register 0.32/0.33 ns, min t rcck_ssr / t rckc_ssr rst input 0.32/0.33 ns, min t rcck_we / t rckc_we wen input 0.75/0.33 ns, min maximum frequency f max write first and no change mode 400.00 mhz f max read first mode 400.00 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. t rcko_dora includes t rcko_dowa , t rcko_dopar , and t rcko_dopaw as well as the b port equivalent timing parameters. 3. t rcko_doa includes t rcko_dopa as well as the b port equivalent timing parameters. 4. t rcko_di includes both a and b inputs as well as the parity inputs of a and b. 5. xilinx block rams do not have asynchronous inputs on an enabled port address. during the time that a port is enabled, its add resses must be stable during the specified set-up time. do not create an asynchronous input on an enabled port address. ta bl e 3 5 : fifo switching characteristics symbol description speed grade units -10 sequential delays t fcko_do clock clk to do output (2) 0.92 ns, max t fcko_flags clock clk to fifo flags outputs (3) 1.19 ns, max t fcko_pointers clock clk to fifo pointer outputs (4) 1.48 ns, max setup and hold tim es before clock clk t fdck_di / t fckd_di di input (5) 0.23/0.33 ns, min t fcck_en / t fckc_en enable inputs (6) 0.84/0.33 ns, min reset delays t fco_flags reset rst to flags (7) 1.68 ns, max maximum frequency f max fifo in all modes 400.00 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case, ? but if a ?0? is listed, there is no positive hold time. 2. t fcko_do includes parity output (t fcko_dop ). 3. t fcko_flags includes these parameters: t fcko_aempty , t fcko_afull , t fcko_empty , t fcko_full , t fcko_rderr , t fcko_wrerr. 4. t fcko_pointers includes both t fcko_rdcount and t fcko_wrcount. 5. t fdck_di includes parity inputs (t fdck_dip ). 6. t fcck_en includes both write and read enable. 7. t fco_flags includes these flags: aempty, afull, empt y, full, rderr, wrerr, rdcount and wrcount.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 24 r xtremedsp switching characteristics ta bl e 3 6 : xtremedsp? switchi ng characteristics symbol description speed grade units -10 setup and hold of ce pins t dspcck_ce /t dspckc_ce setup/hold of all ce inputs of the dsp48 slice 0.49/0.12 ns t dspcck_rst /t dspckc_rst setup/hold of all rst inputs of the dsp48 slice 0.40/0.12 ns setup and hold times of data t dspdck_{aa, bb, cc} / t dspckd_{aa, bb, cc} setup/hold of {a, b, c} input to {a, b, c} register 0.32/0.29 ns t dspdck_{am, bm} / t dspckd_{am, bm} setup/hold of {a, b} input to m register 2.28/0.00 ns sequential delays t dspcko_pp clock to out from p register to p output 0.79 ns t dspcko_pm clock to out from m register to p output 2.98 ns combinatorial t dspdo_{ap, bp}l from {a, b} input to p output (legacy_mode = mult18x18) 4.41 ns maximum frequency f max from {a, b} register to p register (legacy_mode = mult18x18) 253.94 mhz fully pipelined 400.00 mhz
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 25 r configuration switching characteristics ta bl e 3 7 : configuration switching characteristics symbol description speed grade units -10 power-up timing characteristics t pl program latency 0.5 s/fram e, max t por power-on-reset t pl +10 ms, max t icck cclk (output) delay 500 ns, min t program program pulse width 400 ns, min master/slave serial mode programming switching t dcc / t ccd din setup/hold, slave mode 1.0/1.0 ns, min t dsck / t sckd din setup/hold, master mode 1.0/1.0 ns, min t cco dout 8.0 ns, max t cch high time 2.0 ns, min t ccl low time 2.0 ns, min f cc_serial maximum frequency, master mode with respect to nominal cclk. 80 mhz, max f mcctol frequency tolerance, master mode with respect to nominal cclk. 50 % f max_slave slave mode external cclk 80 mhz selectmap mode programming switching t smdcc /t smccd selectmap setup/hold 3.0/0.0 ns, min t smcscc /t smcccs cs_b setup/hold 2.0/0.5 ns, min t smccw /t smwcc rdwr_b setup/hold 8.0/1.0 ns, min t smckby busy propagation delay 8.0 ns, max f cc_selectmap maximum frequency, master mode with respect to nominal cclk. 80 mhz, max f mcctol frequency tolerance, master mode with respect to nominal cclk. 50 % boundary-scan port timing specifications t taptck tms and tdi setup time before tck 1.5 ns, min t tcktap tms and tdi hold time after tck 2.0 ns, min t tcktdo tck falling edge to tdo output valid 8.0 ns, max f tck maximum configuration tck clock frequency 66 mhz, max f tckb maximum boundary-scan tck clock frequency 50 mhz, max
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 26 r master/slave selectmap parameters figure 1 is a generic timing diagram for data loading using selectmap. for other data loading diagrams, refer to the virtex-4 fpga user guide . dynamic reconfiguration port (drp) for dcm clkin_freq_dll_hf_ms_max maximum frequency for dclk 400 mhz, max d_dcmadv_daddr_dclk_setup/ d_dcmadv_daddr_dclk_hold daddr setup/hold 0.72/0.00 ns, max d_dcmadv_di_dclk_setup/ d_dcmadv_di_dclk_hold di setup/hold 0.72/0.00 ns, max d_dcmadv_den_dclk_setup/ d_dcmadv_den_dclk_hold den setup/hold time 0.58/0.00 ns, max d_dcmadv_dwe_dclk_setup/ d_dcmadv_dwe_dclk_hold dwe setup/hold time 0.58/0.00 ns, max d_dcmadv_dclk_do clk to out of do (1) 0ns, max d_dcmadv_dclk_drdy clk to out of drdy 0.92 ns, max notes: 1. do holds until next drp operation. ta bl e 3 7 : configuration switching characteristics (cont?d) symbol description speed grade units -10 x-ref target - figure 1 figure 1: selectmap mode data loading sequence (generic) d s 6 8 0_01_0 3 260 8 cclk no write write no write write data[0:7] c s _b rdwr_b bu s y t s mc s cc t s mdcc t s mccd t s mccc s t s mwcc t s mckby t s mccw
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 27 r clock buffers and networks dcm and pmcd switching characteristics dcm in maximum range (mr) mode is not supported for operation beyond industrial temperature range. ta bl e 3 8 : global clock switching characte ristics (incl uding bufgctrl) symbol description speed grade units -10 t bccck_ce / t bcckc_ce (1) ce pins setup/hold 0.35/0.00 ns t bccck_s / t bcckc_s (1) s pins setup/hold 0.35/0.00 ns t bccko_o bufgctrl delay 0.90 ns maximum frequency f max global clock tree 400 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux_virtex4 primitive that assures glitch-free operation. the other global clock setup and h old times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis whe n switching between clocks. ta bl e 3 9 : operating frequency ranges for dcm in maximum speed (ms) mode symbol description speed grade units -10 outputs clocks (low frequency mode) clkout_freq_1x_lf_ms_min clk0, clk90, clk180, clk270 32 mhz clkout_freq_1x_lf_ms_max 150 mhz clkout_freq_2x_lf_ms_min clk2x, clk2x180 64 mhz clkout_freq_2x_lf_ms_max 300 mhz clkout_freq_dv_lf_ms_min clkdv 2mhz clkout_freq_dv_lf_ms_max 100 mhz clkout_freq_fx_lf_ms_min clkfx, clkfx180 32 mhz clkout_freq_fx_lf_ms_max 210 mhz input clocks (low frequency mode) clkin_freq_dll_lf_ms_min clkin (using dll outputs) (1,3,4,5) 32 mhz clkin_freq_dll_lf_ms_max 150 mhz clkin_freq_fx_lf_ms_min clkin (using dfs outputs only) (2,3,4) 1mhz clkin_freq_fx_lf_ms_max 210 mhz psclk_freq_lf_ms_min psclk 1khz psclk_freq_lf_ms_max 400 mhz outputs clocks (hig h frequency mode) clkout_freq_1x_hf_ms_min clk0, clk90, clk180, clk270 150 mhz clkout_freq_1x_hf_ms_max 400 mhz clkout_freq_2x_hf_ms_min clk2x, clk2x180 300 mhz clkout_freq_2x_hf_ms_max 400 mhz clkout_freq_dv_hf_ms_min clkdv 9.4 mhz clkout_freq_dv_hf_ms_max 267 mhz clkout_freq_fx_hf_ms_min clkfx, clkfx180 210 mhz clkout_freq_fx_hf_ms_max 300 mhz
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 28 r input clocks (high frequency mode) clkin_freq_dll_hf_ms_min clkin (using dll outputs) (1,3,4) 150 mhz clkin_freq_dll_hf_ms_max 400 mhz clkin_freq_fx_hf_ms_min clkin (using dfs outputs only) (2,3,4) 50 mhz clkin_freq_fx_hf_ms_max 300 mhz psclk_freq_hf_ms_min psclk 1khz psclk_freq_hf_ms_max 400 mhz notes: 1. dll outputs are used in these instances to describe the output s: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. when using the dcms clkin_divide_by_2 attribute these values should be doubled. 4. when using a clkin frequency > 400 mhz and the dcms clkin_divide_by_ 2 attribute, the clkin duty cycle must be within 5% (45/5 5 to 55/45). 5. the dcm must be reset if the clock input clock stops for more than 100 ms. ta bl e 4 0 : input clock duty cycle input tolerance symbol description frequency range value units clkin_psclk_pulse_range_1 psclk only < 1 mhz 25 ? 75 % clkin_psclk_pulse_range_1_50 psclk and clkin 1 ? 50 mhz 25 ? 75 % clkin_psclk_pulse_range_50_100 50 ? 100 mhz 30 ? 70 % clkin_psclk_pulse_range_100_200 100 ? 200 mhz 40 ? 60 % clkin_psclk_pulse_range_200_400 200 ? 400 mhz 45 ? 55 % ta bl e 4 1 : input clock tolerances symbol description speed grade units -10 input clock cycle-cycle ji tter (low frequency mode) clkin_cyc_jitt_dll_lf clkin (using dll outputs) (1) 300 ps clkin_cyc_jitt_fx_lf clkin (using dfs outputs) (2) 300 ps input clock cycle-cycle jitter (high frequency mode) clkin_cyc_jitt_dll_hf clkin (using dll outputs) (1) 150 ps clkin_cyc_jitt_fx_hf clkin (using dfs outputs) (2) 150 ps input clock period jitter (low frequency mode) clkin_per_jitt_dll_lf clkin (using dll outputs) (1) 1.0 ns clkin_per_jitt_fx_lf clkin (using dfs outputs) (2) 1.0 ns input clock period jitter (high frequency mode) clkin_per_jitt_dll_hf clkin (using dll outputs) (1) 1.0 ns clkin_per_jitt_fx_hf clkin (using dfs outputs) (2) 1.0 ns feedback clock path delay variation clkfb_delay_var_ext clkfb off-chip feedback 1.0 ns notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. if both dll and dfs outputs are used, follow the more restrictive specifications. ta bl e 3 9 : operating frequency ranges for dcm in maximum speed (ms) mode (cont?d) symbol description speed grade units -10
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 29 r output clock jitter ta bl e 4 2 : output clock jitter description symbol speed grade units -10 clock synthesis period jitter clk0 clkout_per_jitt_0 100 ps clk90 clkout_per_jitt_90 150 ps clk180 clkout_per_jitt_180 150 ps clk270 clkout_per_jitt_270 150 ps clk2x, clk2x180 clkout_per_jitt_2x 200 ps clkdv (integer division) clkout_per_jitt_dv1 150 ps clkdv (non-integer division) clkout_per_jitt_dv2 300 ps clkfx, clkfx180 clkout_per_jitt_fx note 1 ps notes: 1. values for this parameter are available at www.xilinx.com .
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 30 r output clock phase alignment ta bl e 4 3 : output clock phase alignment description symbol speed grade units -10 phase offset between clkin and clkfb clkin / clkfb clkin_clkfb_phase 120 ps phase offset between any dcm outputs all clk outputs clkout_phase 200 ps duty cycle precision dll outputs (1) clkout_duty_cycle_dll (3,4) 150 ps dfs outputs (2) clkout_duty_cycle_fx (4) 250 ps notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. clkout_duty_cycle_dll applies to the 1x clock outputs (clk0, clk90, clk 180, and clk270) only if duty_cycle_correction=true. 4. the measured value includes the duty cycle distortion of the global clock tree. ta bl e 4 4 : miscellaneous timing parameters symbol description speed grade units -10 time required to achieve lock t_lock_dll_240 dll output ? frequency range > 240 mhz (1) 20 s t_lock_dll_120_240 dll output ? frequency range 120 ? 240 mhz (1) 63 s t_lock_dll_60_120 dll output ? frequency range 60 ? 120 mhz (1) 225 s t_lock_dll_50_60 dll output ? frequency range 50 ? 60 mhz (1) 325 s t_lock_dll_40_50 dll output ? frequency range 40 ? 50 mhz (1) 500 s t_lock_dll_30_40 dll output ? frequency range 30 ? 40 mhz (1) 900 s t_lock_dll_24_30 dll output ? frequency range 24 ? 30 mhz (1) 1250 s t_lock_dll_30 dll output ? frequency range < 30 mhz (1) 1250 s t_lock_fx_min dfs outputs (2) 10 ms t_lock_fx_max 10 ms t_lock_dll_fine_shift multiplication factor for dll lock time with fine shift 2 ? fine phase shifting fine_shift_range_ms absolute shifting range in maximum speed mode 7 ns delay lines dcm_tap_ms_min tap delay resolution (min) in maximum speed mode 5 ps dcm_tap_ms_max tap delay resolution (max) in maximum speed mode 40 ps
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 31 r input signal requirements dcm_reset (3) minimum duration that rst must be held asserted 200 ms maximum duration that rst can be held asserted (4) 10 sec dcm_input_clock_stop maximum duration that clkin and clkfb can be stopped (5,6) 100 ms notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. clkin must be present and stable during the dcm_reset. 4. this only applies to production step 1 lx and sx devices. for these devices, use the design solutions described in answer rec ord 21127 for support of longer reset durations. production step 2 lx and sx devices and all production fx devices do not have this requireme nt. 5. for production step 1 lx and sx devices, use the design solutions described in answer record 21127 for support of longer dura tions of stopped clocks. for production step 2 lx and sx devices and all production fx devices, the ise software automatically inserts a small macro to support longer durations of stopped clocks. 6. for all stepping levels, once the input clock is toggling again and stable after being stopped, dcm must be reset. ta bl e 4 5 : frequency synthesis attribute min max clkfx_multiply 2 32 clkfx_divide 1 32 ta bl e 4 6 : dcm switching characteristics symbol description speed grade units -10 t dmcck_psen / t dmckc_psen psen setup/hold 1.07/0.00 ns t dmcck_psincdec / t dmckc_psincdec psincdec setup/hold 1.07/0.00 ns t dmcko_psdone clock to out of psdone 0.69 ns ta bl e 4 7 : pmcd switching characteristic symbol description speed grade units -10 t pmccck_rel / t pmcckc_rel rel setup/hold for all outputs 0.60/0.00 ns t pmcco_clk{a1,b,c,d} rst assertion to clock ou tput deassertion 4.50 ns t pmccko_clk{a1,b,c,d} max clock propagation delay of pmcd for all outputs 5.20 ns pmcd_clk_skew max phase between all outputs assuming all inputs 150 ps clkin_freq_pmcd_clka_max max input/output frequency 400 mhz clkin_psclk_pulse_range max duty-cycle input tolerance (same as dcm) note (1) pmcd_rel_high_pulse_min min pulse width for rel 1.25 ns pmcd_rst_high_pulse_min min pulse width for rst 1.25 ns notes: 1. refer to table 40, page 28 parameter: clkin_psclk_pulse_range. ta bl e 4 4 : miscellaneous timing parameters (cont?d) symbol description speed grade units -10
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 32 r system-synchronous switching characteristics virtex-4qv fpga pin-to-pin output parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 4 8 . values are expressed in nanoseconds unless otherwise noted. ta bl e 4 8 : global clock input-to-output delay for lv cmos25, 12 ma, fast slew rate, with dcm symbol description device speed grade units -10 lvcmos25 global clock input-to-output delay usin g output flip-flop, 12ma, fast slew rate, with dcm. (3) t ickofdcm global clock and off with dcm XQR4VSX55 4.14 ns xqr4vfx60 3.96 ns xqr4vfx140 4.59 ns xqr4vlx200 4.46 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already included in the timing calculation. 3. clock to out has +320 ps offset for operation above 100 c. ta bl e 4 9 : global clock input-to-output delay for lvcm os25, 12 ma, fast slew rate, without dcm symbol description device speed grade units -10 lvcmos25 global clock input-to-o utput delay using outp ut flip-flop, 12ma, fast slew rate, without dcm. (2) t ickof global clock and off without dcm XQR4VSX55 9.54 ns xqr4vfx60 9.11 ns xqr4vfx140 10.02 ns xqr4vlx200 10.14 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. clock to out has +250 ps offset for operation above 100 c
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 33 r virtex-4qv fpga pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 5 0 . values are expressed in nanoseconds unless otherwise noted. ta bl e 5 0 : global clock setup and hold for lvcmos25 standard, with dcm symbol description device speed grade units -10 input setup-and-hold time relative to global clock input signal for lvcmos25 standard. (1,4) t psdcm /t phdcm no delay global clock and iff with dcm (2) XQR4VSX55 1.73/?0.13 ns xqr4vfx60 1.53/0.12 ns xqr4vfx140 1. 52/0.82 ns xqr4vlx200 1. 76/0.41 ns notes: 1. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 2. these measurements include: clk0 dcm jitter iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. 4. hold time has +200 ps offset for operation above 100 c. ta bl e 5 1 : global clock setup and hold for lvcmos25 standard, with dcm in source-synchronous mode symbol description device speed grade units -10 example data input setup-and- hold times relative to a forwarded clock input pin, using dcm and global clock buffer. (1,3,4) t psdcm_0 /t phdcm_0 no delay global clock and iff with dcm in source-synchronous mode (2) XQR4VSX55 ?0.09/1.52 ns xqr4vfx60 ?0.25/1.77 ns xqr4vfx140 ?0.32/2.56 ns xqr4vlx200 0. 00/2.06 ns notes: 1. the timing values were measured using the fine-phase adjustment feature of the dcm. these measurements include clk0 dcm jitte r. package skew is not included in these measurements. 2. iff = input flip-flop 3. for situations where clock and data inputs conform to differen t standards, adjust the setup and hold values accordingly using the values shown in "iob switching characte ristics(1,2)," page 11 . 4. setup time has +100 ps offset for operation above 100 c. ta bl e 5 2 : global clock setup and hold for lvcmos25 standard, without dcm symbol description device speed grade units -10 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psfd /t phfd full delay global clock and iff without dcm (2) XQR4VSX55 3.02/0.98 ns xqr4vfx60 3.58/0.62 ns xqr4vfx140 3. 51/1.71 ns xqr4vlx200 4. 32/0.82 ns notes: 1. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 2. iff = input flip-flop or latch 3. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed best-case, but if a ?0? is listed, there is no positive hold time.
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 34 r chipsync source-synchronous tec hnology switching characteristics the parameters in this section provide the necessary va lues for calculating timing budgets for virtex-4qv fpga source-synchronous transmitter and receiver data-valid windows. ta bl e 5 3 : duty cycle distortion and clock-tree skew symbol description device speed grade units -10 t dcd_clk global clock tree duty cycle distortion (1) all 150 ps t ckskew global clock tree skew (2) XQR4VSX55 190 ps xqr4vfx60 190 ps xqr4vfx140 350 ps xqr4vlx200 350 ps t dcd_bufio i/o clock tree duty cycle distortion all 100 ps i/o clock tree skew across one clock region all 50 ps t bufioskew i/o clock tree skew across multiple clock regions all 50 ps t dcd_bufr regional clock tree duty cycle distortion all 250 ps t bufio_max_freq i/o clock tree max frequency all 500 mhz t bufr_max_freq regional clock tree max frequency all 250 mhz notes: 1. these parameters represent the worst-case duty cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to the application. ta bl e 5 4 : sample window symbol description device speed grade units -10 t samp sampling error at receiver pins (1) all 550 ps t samp_bufio sampling error at receiver pins using bufio (2) all 450 ps notes: 1. this parameter indicates the total sampling error of virtex-4 fpga ddr input registers across voltage, temperature, and proce ss. the characterization methodology uses the dcm to capture the ddr input registers? edges of operation. these measurements include: - clk0 dcm jitter - dcm accuracy (phase offset) - dcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of virtex-4 fpga ddr input registers across voltage, temperature, and proce ss. the characterization methodology uses the bufio clock network and idelay to capture the ddr input registers? edges of operation. th ese measurements do not include package or clock tree skew. ta bl e 5 5 : chipsync? technology pin-to-pin setup/hold and clock to out symbol description speed grade units -10 data input setup and hold times relative to a forwarded clock input pin using bufio t pscs /t phcs setup/hold of i/o clock across multiple clock regions ?0.44/1.17 ns pin-to-pin clock to out using bufio t ickofcs clock-to-out of i/o clock across multiple clock regions 5.02 ns
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 35 r production stepping the virtex-4 fpga stepping identification system denotes the capability improvement of pr oduction released devices. by definition, devices from one stepping are functional supersets of previous devices. bitstreams compiled for a device with an earlier stepping are guaranteed to operate correctly in subsequent device steppings. new device steppings can be shipped in place of earlier device steppings. existing production designs are guaranteed on new device steppings. to take advantage of the capabilities of a newer device stepping, customers are able to order a new stepping version and compile a new bitstream. production devices are marked with a stepping version, with the exception of some step 1 devices. designs should be compiled with a config steppi ng parameter set to a specific stepping version. this parameter is set in the ucf file: config stepping = ?#?; where # = the stepping version ta b l e 5 6 shows the jtag id code by step. current production virtex-4 fpga devices ta bl e 5 7 summarizes the current production device stepping. ta b l e 5 6 : jtag id code by step device id code stepping XQR4VSX55 4 2 xq4rvfx60 8 1 xqr4vfx140 4 1 xqr4vlx200 2 or 5 0 or 3 ta bl e 5 7 : current production devices device stepping step 2 example ordering code xqr4vfx60-cf1144v device steppings shipped when ordered per example ordering code step 1 or 2 only (see ta b l e 5 6 ) capability improvements ? t config requirement is removed ? dcm_reset requirement is removed ? dcm_input_clock_stop requirement is removed by a macro (automatically inserted by ise software) config stepping parameter (must be set in ucf file) ?1? minimum software required ise 7.1i sp4 minimum speed specification required 1.58
space-grade virtex-4qv fpgas: dc and switching characteristics ds680 (v2.0) april 12, 2010 www.xilinx.com product specification 36 r revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. critical applications disclaimer xilinx products (including hardware, software and/or ip cores) are no t designed or intended to be fail- safe, or for use in any application requiring fail-s afe performance, such as in life-support or safety devices or systems, class iii medical devices, nuclea r facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury or severe property or environmental damage (individually and collectivel y, ?critical applications?). furthermore, xilinx products are not designed or intended for use in an y applications that affect control of a vehicle or aircraft, unless there is a fail-saf e or redundancy feature (which do es not include use of software in the xilinx device to implement the redundancy) and a warning signal upon failure to the operator. customer agrees, prior to using or distributing any systems that incorporate xilinx products, to thoroughly test the same for safety purposes. to the maximum extent permitted by applicable law, customer assumes the sole risk and liability of any use of xilinx products in critical applications. date version revisions 03/28/08 1.0 initial xilinx release. 12/16/08 1.1 changed occurrences of ?hardened? to ?tolerant?. 04/12/10 2.0 changed document classification from prelim inary product specification to product specification. changed product title to ?space-grade virtex-4qv fpgas? and changed product name to ?virtex-4qv fpga? throughout document. in the first paragraph of "virtex-4qv fpga electrical characteristics," added ?radiation-tolerant? to the description of the virtex-4qv fpga. in ta b l e 1 2 , removed table notes referring to obsolete application notes. added values for xqr4vfx140 device to ta bl e 1 3 , ta b l e 4 8 , ta b l e 4 9 , ta b l e 5 0 , ta bl e 5 1 , ta b l e 5 2 , ta b l e 5 3 , and ta b l e 5 6 . added critical applications disclaimer.

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