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| 1. product pro?le 1.1 general description logic level n-channel enhancement mode field-effect transistor (fet) in a plastic package using trenchmos? technology. 1.2 features 1.3 applications 1.4 quick reference data 2. pinning information PMV117EN m trenchmos? enhanced logic level fet n logic level threshold n very fast switching n subminiature surface-mounted package n battery management n low power dc-to-dc converter n high-speed switch n v ds 30 v n i d 2.5 a n r dson 117 m w (v gs =10v) n p tot 0.83 w table 1: pinning pin description simpli?ed outline symbol 1 gate (g) sot23 2 source (s) 3 drain (d) 12 3 s d g mbb076 1 of 3 sales@zpsemi.com www.zpsemi.com
3. ordering information 4. limiting values table 2: ordering information type number package name description version PMV117EN to-236ab plastic surface mounted package; 3 leads sot23 table 3: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage (dc) 25 c t j 150 c - 30 v v dgr drain-gate voltage (dc) 25 c t j 150 c; r gs =20k w -30v v gs gate-source voltage (dc) - 20 v i d drain current (dc) t sp =25 c; v gs =10v; figure 2 and 3 - 2.5 a t sp = 100 c; v gs =10v; figure 2 - 1.6 a i dm peak drain current t sp =25 c; pulsed; t p 10 m s; figure 3 -10a p tot total power dissipation t sp =25 c; figure 1 - 0.83 w t stg storage temperature - 65 +150 c t j junction temperature - 65 +150 c source-drain diode i s source (diode forward) current (dc) t sp =25 c - 0.8 a i sm peak source (diode forward) current t sp =25 c; pulsed; t p 10 m s - 3.3 a PMV117EN m trenchmos? enhanced logic level fet 2 of 3 sales@zpsemi.com www.zpsemi.com 5. characteristics table 4: characteristics t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit static characteristics v (br)dss drain-source breakdown voltage i d =10 m a; v gs =0v t j =25 c 3037- v t j = - 55 c27--v v gs(th) gate-source threshold voltage i d = 1 ma; v ds =v gs ; figure 9 and 10 t j =25 c 1.5 2 - v t j = 150 c 1.1 - - v t j = - 55 c - - 2.7 v i dss drain-source leakage current v ds =24v; v gs =0v t j =25 c - 0.01 0.5 m a t j = 150 c --10 m a i gss gate-source leakage current v gs = 20 v; v ds = 0 v - 10 100 na r dson drain-source on-state resistance v gs =10v; i d = 500 ma; figure 6 and 8 t j =25 c - 74 117 m w v gs = 4.5 v; i d = 500 ma; figure 6 and 8 - t j =25 c - 117 190 m w t j = 150 c 188 300 m w dynamic characteristics q g(tot) total gate charge i d = 0.5 a; v dd =15v; v gs =10v; figure 11 - 4.6 - nc q gs gate-source charge - 0.6 - nc q gd gate-drain (miller) charge - 1.35 - nc c iss input capacitance v gs =0v; v ds = 10 v; f = 1 mhz; figure 13 - 147 - pf c oss output capacitance - 65 - pf c rss reverse transfer capacitance - 41 - pf t d(on) turn-on delay time v dd =15v; r l =15 w ; v gs =10v - 4 - ns t r rise time - 7.5 - ns t d(off) turn-off delay time - 18 - ns t f fall time -13-ns source-drain diode v sd source-drain (diode forward) voltage i s = 0.83 a; v gs =0v; figure 12 - 0.7 1.2 v t rr reverse recovery time i s = 1 a; di s /dt = - 100 a/ m s; v gs =0v; v ds =25v -69-ns PMV117EN m trenchmos? enhanced logic level fet 3 of 3 sales@zpsemi.com www.zpsemi.com |
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