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this is information on a product in full production. may 2014 docid025777 rev 1 1/39 ST2100 broadband powerline communi cation soc optimized for audio/video streaming an d consumer applications datasheet - production data features ? configurable hw engine for multiple homeplug ? phy and real-time mac layers processing supporting: ? homeplug av and 1.0 standards ? homeplug green phy? standard ? integrated analog front-end ? arm926ej-s? 32-bit risc cpu up to 333 mhz ? 8/16 bit ddr mobile at 166 mhz and ddr2 at 333 mhz memory controller ? serial memory interface ? 8/16-bits nor flash/nand flash and sram memories controllers ? multichannel dma controller ? ethernet 10/100 mac with mii interface ? usb 2.0 ? pci express and s-ata ? color lcd (clcd) controller ? jpeg codec accelerator ? cryptographic coprocessor ? up to 40 gpios ? enhanced i 2 s (digital audio interface) ? i 2 c master/slave mode ? master/slave ssi ? two independent uarts ? fast irda ? ? real-time clock ? configurable serial port (sport) interface for external dsp and audio codec (adc and dac) in i 2 s mode ? transport stream interface (video ts) ? vectored interrupt controller (vic) ? jtag (ieee1149. 1) interface ? three cpu instruction sets applications the streamplug ST2100 is configurable for a wide range of powerline applications such as: ? smart gateway ? powerline communication bridging, including wireless ? smart grid ? electromobility ? in house audio/video distribution ? video surveillance ? home automation ? ?network area storage? (nas) ? display panels control tfbga 12 x 12 x 1.2 mm table 1. device summary order code operating temp. range package packing ST2100 -40 to +85 c tfbga 12 x 12 x 1.2 mm, pitch 0.5 mm tray, tape and reel www.st.com
contents ST2100 2/39 docid025777 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 architecture description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 system bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 expi subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6 high-speed connectivity subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 low-speed connectivity subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8 application subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9 clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 shared i/o pins (mfios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 clocking parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 master clock (mclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 pcie/sata clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 power-up and reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 internal 2.5 v linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
docid025777 rev 1 3/39 ST2100 contents 39 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables ST2100 4/39 docid025777 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. system bus connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. key to system bus connectivity matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 table 4. master clock rtc, reset and 3.3 v comparator pin descriptions . . . . . . . . . . . . . . . . . . 14 table 5. power supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. debug pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. boot source descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. boot source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. smi pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. usb pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. pcie / sata pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. internal afe pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13. ac crossing pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 14. external pli pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 15. ddr pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 16. mfio pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. memory map description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. expi clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 19. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 20. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 21. power consumption using 2.5 v internal ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 22. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 23. thermal recommended ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 24. internal 2.5 v voltage regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 25. tfbga 12 x 12 x 1.2 mm, 324 + 49 balls, 4r23 x 23, pitch 0.5 mm, ball 0.3 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 26. tfgba package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 27. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
docid025777 rev 1 5/39 ST2100 list of figures 39 list of figures figure 1. streamplug ST2100 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. mifo 0-87 muxing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3. mfio 88-103 muxing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4. mclk crystal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5. rtc crystal connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 6. power-up and reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 7. package outline for tfbga 12 x 12 x 1.2 mm, 324 + 49 balls, 4r23 x 23, pitch 0.5 mm, ball 0.3 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
description ST2100 6/39 docid025777 rev 1 1 description the streamplug ST2100 device is the stmicroelectronics ? ?broad band powerline communication? (bb plc) solution, based on the powerful arm926ej-s? processor (up to 333 mhz), widely used in applications where high computation performance is required, such as consumer (?home area network? or han), industrial and smart grid applications. in addition, the streamplug ST2100 has a memory management unit (mmu) that allows virtual memory management - making the system compliant with the linux ? operating system. it also offers 16 kbyte of data cache, 32 kbyte of instruction cache, jtag and etm? (embedded trace macrocell? ) for debug operations. a large set of peripherals allows a wide flexibilit y of the usage of the system in most of the possible plc broadband applications (indoor and outdoor).
docid025777 rev 1 7/39 ST2100 main features 39 2 main features ? configurable hardware engin e for multiple homeplug ph y and real-time mac layers ? homeplug? av and 1.0 standards ? homeplug green phy standard ? integrated analog front-end ? programmable gain amplifier: gain range -12 db to 48 db ? adc and dac ? 2.5 v voltage regulator ? zero crossing (zc) comparator ? arm926ej-s? 32-bit risc cpu up to 333 mhz ? 16 kbyte if instruction cache, 16 kbyte of data cache ? 32 kbyte of instruction tc m and 16 kbyte of data tcm ? three instruction sets: 32-bit for high performance, 16-bit (thumb ? ) for efficient code density, bytecode java? mode (jazelle ?) for direct execution of java code ? amba? bus interface with f max 166 mhz ? 48 kbyte on-chip boot rom ? 8 kbyte on-chip sram ? 8/16 bit ddr mobile at 166 mhz and ddr2 at 333 mhz memory controller ? serial memory interface ? 8/16-bits nor flash/nand flas h and sram memory controller ? boot capability from nand flash, serial/parallel nor flash, and uart ? multichannel dma controller (8 fifos and 16 dedicated channels) ? ethernet 10/100 mac with mii interface (ieee 802.3), revmii, ieee 802.1-as and 802.1-qav for audio video (av) traffic ? usb 2.0 (high-full-low speed) port with an integrated phy able to work as a host or device ? pci express gen1 (pci express standard version 1.1), single lane x1 dual mode (both ?root complex? and ?endpoint? mode s supported), the phy is a standard 8-bit/16-bit pipe phy interface. this peripher al supports also the serial ata compliant with the sata/150. ? color lcd controller (up to 1024 x 768 resolution at 24 bpp true color, stn/tft display panels) ? jpeg codec accelera tor (1 clock/pixel) ? cryptographic coprocessor (dma based programmable engine) with support for: ? advanced encryption standard (aes) ci pher (128, 192, 256 bit keys) in ecb, cbc, ctr modes ? data encryption standard (des) and triple des (tdes) cipher in ecb and cbc modes ? sha-1, hmac-sha-1, sha-256, hmac -sha-256, md5, hmac-md5 digests ? up to 40 gpios (multiplexed with peripheral i/os), all the i/ os have interrupt capability, 24 application specific gpios: four i/os support pwm and four i/os support double pwm features.
main features ST2100 8/39 docid025777 rev 1 ? enhanced i 2 s for 4-channel ?digital audio interface? (dai) ? master/slave ssp (m otorola spi, texas instrument s, national semiconductor protocols) up to 5 mbits/s in slave mo de and up to 20 mbits/s in master mode ? i 2 c master/slave mode ? two independent uarts supporting hardware (hw) flow control ? fast irda (sir/mir/fir) ? three pairs of 16-bit general purpose ti mers with programmable 8-bit prescaler ? real-time clock (rtc) ? configurable serial port (sport) interfac e for external dsp and audio codec (adc and dac in i 2 s mode) ? transport stream interface (video ts also called ?synchronous peripheral bus?) for external mpeg- 2/h.264 encod er and decoder. ts port also implements image sensor interface (ccd camera) ? watchdog timer ? clock synthesizer (4 outputs) ? vectored interrupt controller (vic) ? jtag (ieee1149.1) interface ? etm9 interface ? multichannel crypt ographic coprocesso r. des/tdes and aes security for the powerline link ? pgc (ir) interface ? supply voltages: 1.2 v core, 1.8 v / 2.5 v ddr, 2.5 v afe and plls, 1.5 v rtc and 3.3 v i/os ? available in a tfbga373 package (12 x 12 x 1.2 mm, pitch 0.5 mm).
docid025777 rev 1 9/39 ST2100 architecture description 39 3 architecture description figure 1 is the architecture overview of the streamplug ST2100. the internal architecture is based on several shared subsystems interconnected through a multilayer system bus. the bus structure allows differ ent subsystem data flows to be executed in parallel improving the core platform efficiency. high performance master agents are directly interconnected with the memory controller reducing the memory access latency. figure 1. streamplug ST2100 functional block diagram ([slvxev\vwhp +ljkvshhgvxev\vwhp %dvlfvxev\vwhp 0hpru\vxev\vwhp &38vxev\vwhp $50(-6 008 -7$* (70 7&0 .e\whvlqvwu .e\whvgdwd *37 wlphu sdlu 9,& $+% v\vwhpexv $3% eulgjh 036'5$0 phpru\ frqw uroohu '0$& %227 520 &/&' .e\whv lqvwufdfkh 86%vxev\vwhp 08; .e\whv gdwdfdfkh 60, $3% eulgjh 57& :'* *37 *37 57& 5&* $ssolfdwlrqvxev\vwhp 3/& 0r'hp & 76 63257 $3% eulgjh '$, 3*& $6b*3,2 /rzvshhgvxev\vwhp 5$0 -3*& )60& ),u'$ $3% eulgjh 63, ,& 8$57 8$57 &$1 &$1 (7+ 5hy0,, 8+& 3+< 8'& 3+< 08; 8'& 3&,h 6$7$ $0
architecture description ST2100 10/39 docid025777 rev 1 3.1 cpu subsystem ? arm926ej-s? running at 333 mhz with: ? mmu ? 16 kbyte of instruction cache ? 16 kbyte of data cache ? 32 kbyte of instruction ?tightly coupled memory? (tcm) ? 16 kbyte of data ?tightly coupled memory? (tcm) ? amba bus interface ?jtag ? etm9 (embedded trace macrocell) for debug, medium size version ? interrupt controller managing sources which are prioritized and vectorized 3.2 system bus the system bus structure allows different sub system data flows to be executed in parallel improving the core platform efficiency. high performance master agents are directly interconnected with the memory controller reducing the memory access latency. the overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round- robin arbitration mechanism. table 2 shows the system bus scheme and table 3 is the key to its contents. table 2. system bus connectivity cpu pcie/sata dma 1 dma 2 eth. ts/sport uhc/udc plc modem crypto clcd targets (slave ports) mp sdram x x x x x x x x x x low speed x x x application x x x basic x x high speed x x expi x x table 3. key to system bus connectivity matrix format definition grey box no connection exists between target and initiator x a connection exists between target and initiator
docid025777 rev 1 11/39 ST2100 architecture description 39 3.3 memory subsystem the multiport memory controller within the me mory subsystem manages ddr mobile up to 166 mhz and ddr2 up to 333 mhz external memory. internally, it handles 5 ports supporting all the chip master ports. the multiport memory controller block has a programmable arbitration scheme and the transactions happen on a different layer from the main bus. it also offers a local fifo to increase the throughput and reduce the latency. 3.4 expi subsystem ? pci express gen1 (pci express standard version 1.1) single lane x1 dual mode ? root complex mode is supported. ? endpoint mode is supported. ? serial ata compliant with sata/150 specifications ? phy is standard 8-bit/16 -bit pipe phy interface 3.5 basic subsystem ? 8 fifos and 16 high performance dma channels with two ahb interfaces to parallelize the activity when two channels are working at the same time. ? 48 kbytes of rom (f or boot procedure) ? ?serial memory interface? (smi) supporting external serial flash. ? color lcd controller (clcd) up to 1024 x 768 resolution at 24 bpp (true color) supporting stn/tft display panels ? three pair of 16 bit general purpose timers with programmable prescaler ? watchdog timer ? rtc with separate power supply allowing battery connection ? up to 104 ?multi-function? i/os (mfios) multiplexed with peripheral i/os: ? allows a large number of po ssible application scenarios ? up to 40 gpios with interrupt capability ? system controller, reset and clock generation, and miscellaneous registers array allowing a full configur ability of the system.
architecture description ST2100 12/39 docid025777 rev 1 3.6 high-speed conn ectivity subsystem ? ethernet 10/100 mac with mii interface (ieee 802.3), with external phy ? revmii (supporting 25 and 50 mhz clock frequencies) ? ieee 802.1-as and 802.1 -qav for audio vi deo (av) traffic ? usb 2.0 (high-full-low speed) port with integrated phy able to work as a host or device. the phy is embedded. ? one usb host controller compatible with usb 2.0 high-speed specification managing a single port. the peripheral has a dedicated channel to the multiport memory controller and a dedicated slave port for cpu programming (ohci and ehci). ? one usb device compatible with usb 2.0 high-speed specifications. a dedicated channel connects the peripher al with the multiport memory controller and registers and an internal fifo are accessible from the cpu through the main ahb bus. a usb plug detector block is also ava ilable to detect the presence of the vbus voltage. 3.7 low-speed conne ctivity subsystem ? two independent uarts supporting hardware flow control up to 460.8 kbits/s ? fast irda controller with a speed rate from 9.6 kbits/s to 4 mbits/s (sir/mir/fir) ? one synchronous ?serial port interface? (spi) controller capable of operating as a master or a slave (motorola - texas in struments - national semiconductor) with a speed (data) rate up to 20 mbits/s ? one i 2 c (also known as a digital audio interface) controller capable of operating in master and slave mode and covering all the possible data rates (high, fast and low) ? jpeg codec accelerato r (1 clock per pixel) ? 8 kbytes of static ram ? ?flexible static memory cont roller? (fsmc) supporting: ? asynchronous parallel nand and nor flash memories ? synchronous and asynchronous sram ? two independent ?controller area network? (can) interfaces compliant with can protocol version 2.0 parts a and b (up to 1 mbit/s).
docid025777 rev 1 13/39 ST2100 architecture description 39 3.8 application subsystem ? configurable hardware engin e for multiple homeplug ph y and real-time mac layers processing supporting: ? homeplug av and 1.0 standards ? homeplug green phy standard ? integrated analog front-end: ? programmable gain amplifier: gain range -12 db to 48 db ? adc and dac ? 2.5 v, 150 ma voltage regulator ? zero crossing (zc) comparator ? cryptographic coprocessor channels (c3), dma based programmable engine, with support for: ? advanced encryption standard (aes) cipher ( 128-, 192-, 256 - bit keys) in ecb, cbc, ctr modes ? data encryption standard (des) and triple des cipher in ecb and cbc modes ? sha-1, hmac-sha-1, sha-256, hmac -sha-256, md5, hmac-md5 digests algorithms ? configurable serial port (sport) interfac e for external dsp and audio codec (adc and dac in i 2 s mode) ? transport stream (ts) interface ? pulse generator and capture (pgc) (ir) for remote controls ? 4-channel i 2 s [?digital audio interface? (dai)] ? 24 application specific gpios: ? up to 4 gpios supporting pwm ? up to 4 gpios supporting double pwm. 3.9 clock and reset system ? the system clocks are generated by: ? two fully programmable plls. one is used to generate a clock for cpu and amba ahb bus and the other is used in case the ddr clock has to be different (asynchronous) with respect to the cpu clock. ? one ?high precision? clock synthesi zer with 4 outputs providing different frequencies for the various ips ? fully programmable control of the clock and reset signals for all the slave blocks allowing sophisticated power management.
pin descriptions ST2100 14/39 docid025777 rev 1 4 pin descriptions from table 4 to table 15 on page 21 and table 16 in section 5 on page 29 describe the streamplug ST2100 pinouts. 4.1 dedicated pins table 4. master clock rtc, reset a nd 3.3 v comparator pin descriptions group signal name ball direction function pin type master clock rcg_mclk_a ab18 in 24 mhz (typical) cr ystal in oscillator 2.5 v capable rcg_mclk_zo ab19 out 24 mhz (typical) crystal out oscillator 2.5 v capable rtc rtc_tst g23 in por test signal keep it at gnd rtc_zo h22 out 32 khz crystal out put oscillator 1.5 v capable rtc_a h23 in 32 khz crystal input oscillator 1.5 v capable rtc_sgn j23 in por signal keep it floating reset mreset y13 in main reset ttl schmitt trigger input buffer 3.3 v tolerant with pu 3.3 v comp. comp_3v3_ anarext a21 power external resistor for 3.3 v i/os compensation analog, 3.3 v capable comp_3v3_ gndbgcomp a22 power return for external resistor for 3.3 v i/os compensation table 5. power suppl y pin descriptions group signal name ball value digital ground gnd a1, a23, d5, d20, j11, j 13, k10,k11, k12, k13, k14,k22, l10, l11, l12, l13, l14, l21, m1, m4, m10, m11, m12, m13, m14, m20, n10, n11, n12, n13, n14, p10, p11, p12, p13, p14, r11, r13, r22, ac1, ac23, ab23 0 v dvss_usb ab17 gnd_adc v21 gnd_dac t23 gnd_rcg_clk_synth aa19
docid025777 rev 1 15/39 ST2100 pin descriptions 39 analog ground gnde_rtc j22 0 v vssa_usb ac16 vssa_usb ac13 vssac_usb aa15 gndas_adc w21 gnda_adc w22 gnda1_dac v20 gnda2_dac t22 gndas_dac u20 dac_mass_quiet u22 gnde_dac w20 gnde_rcg_mclk ac19 agndsub_rcg_mclk y17 agnd_rcg_mclk aa17 agnd_pll1 y15 agnd_pll2 w17 gnda_rcg_clk_synth y20 gnde_reg ab22 gnde_pga ab21 pcie_p1_vssr k23 pcie_p1_vssr m23 pcie_p1_vsst n23 pcie_vss_pll p21 pcie_p1_vsst r23 i/o vdde_3v3 e5, e6, e7, e17, e18, e19, f5, f19, g5, g19, u5, u19, v5, v19, w5, w6, w7, w18, w19 3.3 v core vdd_1v2 j9, j10, j12, j14, j15, k9, k15, l9, l15, m9, m15, n9, n15, p9, p15, r9, r10, r12, r14, r15, aa21 1.2 v usb phy vdd_1v2_usb ab15 1.2 v vdd_2v5_usb aa16 2.5 v vdd_3v3_usb ab16 3.3 v table 5. power supply pin descriptions (continued) group signal name ball value
pin descriptions ST2100 16/39 docid025777 rev 1 analog ground gnde_rtc j22 0 v vssa_usb ac16 vssa_usb ac13 vssac_usb aa15 gndas_adc w21 gnda_adc w22 gnda1_dac v20 gnda2_dac t22 gndas_dac u20 dac_mass_quiet u22 gnde_dac w20 gnde_rcg_mclk ac19 agndsub_rcg_mclk y17 agnd_rcg_mclk aa17 agnd_pll1 y15 agnd_pll2 w17 gnda_rcg_clk_synth y20 gnde_reg ab22 gnde_pga ab21 pcie_p1_vssr k23 pcie_p1_vssr m23 pcie_p1_vsst n23 pcie_vss_pll p21 pcie_p1_vsst r23 i/o vdde_3v3 e5, e6, e7, e17, e18, e19, f5, f19, g5, g19, u5, u19, v5, v19, w5, w6, w7, w18, w19 3.3 v core vdd_1v2 j9, j10, j12, j14, j15, k9, k15, l9, l15, m9, m15, n9, n15, p9, p15, r9, r10, r12, r14, r15, aa21 1.2 v usb phy vdd_1v2_usb ab15 1.2 v vdd_2v5_usb aa16 2.5 v vdd_3v3_usb ab16 3.3 v table 5. power supply pin descriptions (continued) group signal name ball value
docid025777 rev 1 17/39 ST2100 pin descriptions 39 pcie phy pcie_vdd_pll m21 1.2 v pcie_p1_vddr m22 1.2 v pcie_p1_vddt1 n21 1.2 v pcie_p1_vddt2 n22 2.5 v pcie_vdd2_pll r21 2.5 v osci (master clock) vdd_1v2_rcg_mclk aa18 1.2 v vdde_2v5_rcg_mclk ac18 2.5 v pll 1 avdd_2v5_pll1 y16 2.5 v pll 2 avdd_2v5_pll2 y14 2.5 v synth vdd_1v2_rcg_clk_synth y19 1.2 v vcca_2v5_rcg_clk_synth y18 2.5 v ddr vdde_ddr a5, a11, a14, a20, c2 3, d6, d11, d14 1.8 v / 2.5 v afe_adc vdd_1v2_adc w23 1.2 v vccaiso_2v5_adc y21 2.5 v vcca_2v5_adc y23 2.5 v afe_dac vdd_1v2_dac t21 1.2 v vcca1_2v5_dac u21 2.5 v vcca2_2v5_dac t20 2.5 v afe_pga vdd_2v5_pga ab20 2.5 v vdde_3v3_pga ac20 3.3 v osci rtc vdd_1v5_rtc g22 1.5 v internal 2.5 v regulator vdde_2v5_reg (reg out) y22 2.5 v vdde_3v3_reg (reg in) aa22 3.3 v reserved reserved aa23, b23, d21, d22, d23, e20, e21, e22, e23, f20, f21, f22, f23, g20, g21, h20, h21, j20, j21, k20, k21, l20 keep it floating reserved reserved b22 connect to gnd table 5. power supply pin descriptions (continued) group signal name ball value
pin descriptions ST2100 18/39 docid025777 rev 1 table 6. debug pin descriptions signal name ball direction function pin type reserved b4 in reserved connect to gnd ttl input buffer, 3.3 v tolerant with pd jtag_tms c5 in test mode select ttl input buffer, 3.3 v tolerant with pu jtag_tck d4 in test clock ttl input buffer, 3.3 v tolerant with pu jtag_ntrst e4 in test reset input ttl input buffer, 3.3 v tolerant with pu jtag_tdi f4 in test data input ttl input buffer, 3.3 v tolerant with pu jtag_tdo g4 out test data output ttl output buffer, 3.3 v capable, 4 ma etm_traceclk y7 out etm clock (the other etm signals are available on mfios) ttl output buffer, 3.3 v capable, 4 ma table 7. boot source descriptions signal name ball direction function pin type soc_cfg_boot0 c2 in boot mode configuration ttl input buffer, 3.3 v tolerant with pd soc_cfg_boot1 b2 in boot mode configuration ttl input buffer, 3.3 v tolerant with pd soc_cfg_boot2 c3 in boot mode configuration ttl input buffer, 3.3 v tolerant with pd soc_cfg_boot3 b3 in boot mode configuration ttl input buffer, 3.3 v tolerant with pd
docid025777 rev 1 19/39 ST2100 pin descriptions 39 table 8. boot source selection boot source soc_cfg_boot3 soc_cfg _boot2 soc_cfg_boot1 soc_cfg_boot0 smi (3 - byte addressing) 0 0 0 0 smi (2 - byte addressing) 0 0 0 1 fsmc/nand 8-bit0010 fsmc/nand 16-bit 0 0 1 1 uart1 (g20) 0 1 0 0 uart2(g21) 0 1 0 1 fsmc/nor 8-bit 0 1 1 0 fsmc/nor 16-bit 0 1 1 1 reserved 1 x (1) x (1) x (1) 1. an ?x? may be a ?1? or a ?0?. table 9. smi pin descriptions signal name ball direction function pin type smi_din a2 in serial flash input data ttl input buffer, 3.3 v tolerant with configurable pu/pd and hyst smi_dout a3 out serial flash output data ttl output buffer, 3.3 v capable, 4 ma smi_clk a4 i/o serial flash clock ttl output buffer, 3.3 v capable, 4 ma smi_ncs0 b1 out serial flash chip select ttl output buffer, 3.3 v capable, 4 ma smi_ncs1 c1 out serial flash chip select ttl output buffer, 3.3 v capable, 4 ma smi_ncs2 d1 out serial flash chip select ttl output buffer, 3.3 v capable, 4 ma table 10. usb pin descriptions signal name ball direction function pin type usb_vbus aa14 i/o usb device vbus detect or usb host vbus control bidirectional ttl pad, 3.3 v tolerant input with pd for device mode; output for host mode usb_overcur ab13 in usb host overcurrent ttl input buffer 3.3 v tolerant with pu (for host mode only) usb_txrtune ab14 out reference resistor analog usb_dp ac14 i/o usb host or device d+ bidirectional analog buffer 5 v tolerant usb_dm ac15 usb host or device d- bidirectional analog buffer 5 v tolerant reserved ac17 out do not connect test output analog
pin descriptions ST2100 20/39 docid025777 rev 1 table 11. pcie / sata pin descriptions signal name ball direction function pin type pcie_p1_rxn l22 in high frequency negative rx input signal analog pcie_p1_rxp l23 in high frequency positive rx input signal analog pcie_xtal2 n20 out feedback of th e crystal oscillator oscillator pcie_xtal1 p20 in input of the crystal oscillator oscillator pcie_p1_txp p22 out high frequency positive tx output signal analog pcie_p1_txn p23 out high frequency negative tx output signal analog pcie_refres r20 input reference resistor for the impedance compensation analog table 12. internal afe pin descriptions signal name ball direction function pin type dac_idac u23 out hf dac differential positive current ?out? analog dac_rext v22 out external precision resistor analog dac_idacb v23 out hf dac differenti al negative current ?out? analog pga_in_n ac21 in pga negative input analog pga_in_p ac22 in pga positive input analog table 13. ac crossing pin descriptions signal name ball direction function pin type ac_crossing c4 in mains digital input, zero crossing ttl input buffer, 3.3 v tolerant, with configurable pu/pd and hyst zc_in aa20 in mains analog zero crossing analog table 14. external pli pin description signal name ball direction function pin type extpli_txon c22 out line driver enable ttl output buffer, 3.3 v capable, 4 ma
docid025777 rev 1 21/39 ST2100 pin descriptions 39 table 15. ddr pin descriptions signal name ball direction function pin type ddr_addr_0 d7 out address lines compatible with ddri (sstl2) and ddrii (sstl18) ddr_addr_1 c7 ddr_addr_2 b7 ddr_addr_3 a8 ddr_addr_4 b8 ddr_addr_5 c8 ddr_addr_6 d8 ddr_addr_7 a9 ddr_addr_8 b9 ddr_addr_9 c9 ddr_addr_10 d9 ddr_addr_11 a10 ddr_addr_12 b10 ddr_addr_13 c10 ddr_addr_14 d10 ddr_ba_0 c11 out bank select ddr_ba_1 d12 ddr_ba_2 c12 ddr_ras b14 out row address strobe ddr_cas b13 out column address strobe ddr_we b11 out write enable ddr_clken b12 out clock enable ddr_clk_p a12 out differential clock differential compatible with ddri (sstl2) and ddrii (sstl18) ddr_clk_n a13
pin descriptions ST2100 22/39 docid025777 rev 1 ddr_cs_0 c13 out chip select compatible with ddri (sstl2) and ddrii (sstl18) ddr_cs_1 c14 ddr_odt_1 a6 i/o on-die termination enable lines ddr_odt_0 a7 ddr_data_0 d15 i/o data lines (lower byte) ddr_data_1 c15 ddr_data_2 d16 ddr_data_3 c16 ddr_data_4 c18 ddr_data_5 d18 ddr_data_6 c17 ddr_data_7 d17 ddr_dqs_0 a15 out lower data strobe differential compatible with ddri (sstl2) and ddrii (sstl18) ddr_ndqs_0 a16 ddr_dm_0 b15 out lower data mask compatible with ddri (sstl2) and ddrii (sstl18) ddr_gate_0 a17 i/o lower gate open ddr_data_8 c21 i/o data lines (upper byte) ddr_data_9 b21 ddr_data_10 c20 ddr_data_11 b20 ddr_data_12 d19 ddr_data_13 c19 ddr_data_14 b19 ddr_data_15 b18 ddr_dqs_1 a18 out upper data strobe differential compatible with ddri (sstl2) and ddrii (sstl18) ddr_ndqs_1 a19 ddr_dm_1 b16 out upper data mask compatible with ddri (sstl2) and ddrii (sstl18) ddr_gate_1 b17 i/o upper gate open vref_ddr d13 in reference voltage analog 1.8 v ddr2_en b5 in configuration ttl input buffer, 3.3 v tolerant, with pu comp_1v8_anarext b6 power external resistor for 1.8 v i/os compensation analog 1.8 v capable comp_1v8_gndbgcomp c6 power return for external resistor for 1.8 v i/os compensation power table 15. ddr pin descr iptions (continued) signal name ball direction function pin type
docid025777 rev 1 23/39 ST2100 pin descriptions 39 4.2 shared i/o pins (mfios) the 104 mfios can be configured in different modes. this allows the streamplug ST2100 to be tailored for various applications. for the mfio from 88 to 103, the signal specified in table 16 is also conditioned by an internal selection mux that can choose among the specified signal and an internal basic subsystem general purpose io (bs_gpio), as specified in the streamplug ST2100 manual and shown in figure 2 and figure 3 . figure 2. mifo 0-87 muxing scheme figure 3. mfio 88-103 muxing scheme $0 ,3 ,3 ,3q ,36ho 0),2 $0 ,3 ,3 ,3q ,36ho 0),2 0),2$)6ho %6b*3,2
pin descriptions ST2100 24/39 docid025777 rev 1 table 16. mfio pin descriptions ball no. signal name muxing selection 01 2345 ab9 mfio0 eth_phy_int fsmc_bln0 fsmc_pcsel0 etm_tracepkta_0 aa8 mfio1 eth_clk fsmc_bln1 fsmc_pcsel1 etm_tracepkta_1 ab6 mfio2 mii_txer fsmc_pcoen fsmc_pcoen etm_tracepkta_2 aa7 mfio3 mii_txen fs mc_pcwen fsmc_pcwen etm_tracepkta_3 aa9 mfio4 mii_txd_3 fsmc_ebar0 fs mc_pcintrq_1 etm_tracepktb_0 ab7 mfio5 mii_txd_2 fsmc_ebar1 fs mc_pcintrq_2 etm_tracepktb_1 aa6 mfio6 mii_txd_1 fsmc_ebar2 fs mc_pcad16(cle) etm_tracepktb_2 ab8 mfio7 mii_txd_0 fsmc_ebar3 fs mc_pcad17(ale) etm_tracepktb_3 ab5 mfio8 mii_txclk fsmc_pcda0 etm_trace_synca ac8 mfio9 mii_rxer fsmc_pcda1 etm_pipestata_0 ac5 mfio10 mii_rxdv fsmc_pcda2 etm_pipestata_1 ac7 mfio11 mii_rxd_3 fsmc_pcda3 etm_pipestata_2 ab4 mfio12 mii_rxd_2 fsmc_pcda4 etm_trace_syncb ac6 mfio13 mii_rxd_1 fsmc_pcda5 etm_pipestatb_0 aa5 mfio14 mii_rxd_0 fsmc_pcda6 etm_pipestatb_1 ac4 mfio15 mii_rxclk fsmc_pcda7 etm_pipestatb_2 aa4 mfio16 mii_mdio fsmc_pcad0 as_gpio8 ac3 mfio17 mii_mdc fsmc_pcad1 as_gpio9 ab3 mfio18 mii_crs fsmc_pcad2 as_gpio10 ac2 mfio19 mii_col fsmc_pcad3 as_gpio11 y3 mfio20 uart2_cts fsmc_pcad4 as_gpio12 ab2 mfio21 uart2_rts fsmc_pcad5 as_gpio13
ST2100 pin descriptions docid025777 rev 1 25/39 y4mfio 22 uart2_rxd fsmc_pcad6 as_gpio14 aa3 mfio23 uart2_txd fsmc_pcad7 as_gpio15 y5 mfio24 uart1_cts fsmc_pcda8 aa1 mfio25 uart1_rts fsmc_pcda9 y6 mfio26 uart1_rxd fsmc_pcda10 ab1 mfio27 uart1_txd fsmc_pcda11 w4 mfio28 as_gpio4 fsmc_pcda12 y1 mfio29 as_gpio5 fsmc_pcda13 v3 mfio30 as_gpio6 fsmc_pcda14 v2 mfio31 as_gpio7 fsmc_pcda15 w3 mfio32 as_gpio0 fsmc_pcad8 y2 mfio33 as_gpio1 fsmc_pcad9 u3 mfio34 as_gpio2 fsmc_pcad10 w2 mfio35 as_gpio3 fsmc_pcad11 v4 mfio36 as_gpio8 fsmc_pcad12 aa2 mfio37 as_gpio9 fsmc_pcad13 u2 mfio38 as_gpio10 fsmc_pcad14 w1 mfio39 as_gpio11 fsmc_pcad15 u4 mfio40 as_gpio12 fsmc_pcad16 v1 mfio41 as_gpio13 fsmc_pcad17 t3 mfio42 as_gpio14 pgc_ir _tx firda_rx fsmc_pcad18 t1 mfio43 as_gpio15 pgc_ir _rx firda_tx fsmc_pcad19 r4 mfio44 sport_drsec2 rxquiet fsmc_pcad20 table 16. mfio pin descriptions (continued) ball no. signal name muxing selection 01 2345
pin descriptions ST2100 26/39 docid025777 rev 1 u1 mfio45 sport_drsec1 ts_data7 xgain fsmc_pcad21 r3 mfio46 sport_drsec0 ts_data6 tx_en2 fsmc_pcad22 r2 mfio47 sport_dtsec2 ts_data5 dai_sdo tx_en1 fsmc_pcad23 p4 mfio48 sport_dtsec1 ts_data4 dai_sdi as_gpio16 fsmc_wtn r1 mfio49 sport_dtsec0 ts_data 3 dai_lrclk as_gpio17 fsmc_clk p3 mfio50 sport_drpri ts_data2 dai_sclk as_gpio18 fsmc_lbar t2 mfio51 sport_rfs ts_data1 d ai_mclk as_gpio1 9 fsmc_pcsel0 t4 mfio52 sport_dtpri ts_data0 as_gpio20 fsmc_pcsel1 p1 mfio53 sport_tfs ts_dvalid as_gpio21 fsmc_pcsel2 p2 mfio54 sportnclk ts_sync as_gpio22 fsmc_pcsel3 n1 mfio55 sport_tsclk ts_clk as_gpio23 fsmc_pcwaitn n4 mfio56 eth_phy_int n2 mfio57 eth_clk n3 mfio58 clcd_pwr mii_txer m2 mfio59 clcd_le mii_txen m3 mfio60 clcd_lp mii_txd_3 l2 mfio61 clcd_fp mii_txd_2 l3 mfio62 clcd_cp mii_txd_1 l1 mfio63 clcd_ac mii_txd_0 l4 mfio64 clcd_d0 mii_txclk k1 mfio65 clcd_d1 mii_rxer k3 mfio66 clcd_d2 mii_rxdv k2 mfio67 clcd_d3 mii_rxd_3 table 16. mfio pin descriptions (continued) ball no. signal name muxing selection 01 2345
ST2100 pin descriptions docid025777 rev 1 27/39 k4 mfio68 clcd_d4 mii_rxd_2 j1 mfio69 clcd_d5 mii_rxd_1 j3 mfio70 clcd_d6 mii_rxd_0 h1 mfio71 clcd_d7 mii_rxclk j4 mfio72 clcd_d8 as_gpio16 mii_mdio g1 mfio73 clcd_d9 as_gpio17 mii_mdc j2 mfio74 clcd_d10 as_gpio18 mii_crs g2 mfio75 clcd_d11 as_gpio19 mii_col g3 mfio76 clcd_d12 as_gpio20 can1_rx f3 mfio77 clcd_d13 as_gpio21 can1_tx h2 mfio78 clcd_d14 as_gpio22 can2_rx f1 mfio79 clcd_d15 as_gpio23 can2_tx h4 mfio80 clcd_d16 uart1_cts f2 mfio81 clcd_d17 uart1_rts h3 mfio82 i2c_scl clcd_d18 uart1_rxd e1 mfio83 i2c_sda clcd_d19 uart1_txd d3 mfio84 spi_ssp_ss clcd_d20 uart2_cts e2 mfio85 spi_ssp_sclk clcd_d21 uart2_rts e3 mfio86 spi_ssp_miso clcd_d22 uart2_rxd d2 mfio87 spi_ssp_mosi clcd_d23 uart2_txd aa10 mfio88 can1_rx etm_pipestatb_2 y10 mfio89 can1_tx etm_pipestatb_1 aa11 mfio90 can2_rx etm_pipestatb_0 table 16. mfio pin descriptions (continued) ball no. signal name muxing selection 01 2345
pin descriptions ST2100 28/39 docid025777 rev 1 4.3 required external components ? comp_1v8_anarext: place an external 121 k ? 1% resistor between the ball b6 and ball c6 ? usb_txrtune: connect an external 43.2 ? 1% pull-down resistor to the ball ab14 ? comp_3v3_anarext: place an external 121 k ? 1% resistor between the ball a21 and ball a22 ? pcie_refres: place an external 487 ? 1% resistor between the ball r20 and ball m21 (if using pcie interface) ? dac_rext: place an external 7.87 k ? 1% resistor between the ball v22 and ball u22 ? dac_idac, dac_idacb: place an external 1% accuracy l oad resistor between the ball v23 and ball u23 to ground. y11 mfio91 can2_tx etm_trace_syncb y9 mfio92 fsmc_pcintrq_ 4 etm_pipestata_2 y12 mfio93 fsmc_pcintrq_ 3 etm_pipestata_1 aa12 mfio94 fsmc_pcintrq_ 2 etm_pipestata_0 ab12 mfio95 fsmc_pcintrq_ 1 etm_trace_synca aa13 mfio96 gpt1_cptr2 etm_tracepktb_3 ac12 mfio97 gpt1_cptr1 etm_tracepktb_2 ab11 mfio98 gpt1_clk2 etm_tracepktb_1 ab10 mfio99 gpt1_clk1 etm_tracepktb_0 ac11 mfio100 gpt2_cpt r2 etm_tracepkta_3 y8 mfio101 gpt2_cpt r1 etm_tracepkta_2 ac10 mfio102 gpt2_clk2 etm_tracepkta_1 ac9 mfio103 gpt2_clk1 etm_tracepkta_0 table 16. mfio pin descriptions (continued) ball no. signal name muxing selection 01 2345
docid025777 rev 1 29/39 ST2100 memory map 39 5 memory map the memory map is shown in table 17 . table 17. memory map description start address end address peripheral description 0x00000000 0x3fffffff external sdram ddr2 0x40000000 0xbfffffff pcie data 0xc0000000 0xc07fffff s-ata 0xc0800000 0xcfffffff - reserved 0xd0000000 0xd007ffff uart1 0xd0080000 0xd00fffff uart2 0xd0100000 0xd017ffff spi 0xd0180000 0xd01fffff i 2 c 0xd0200000 0xd027ffff aes 0xd0280000 0xd02fffff can1 0xd0300000 0xd03fffff can2 0xd0400000 0xd07fffff - reserved 0xd0800000 0xd0ffffff jpgc 0xd1000000 0xd17fffff firda 0xd2800000 0xd2ffffff 8 k sram 0xd3000000 0xd37fffff fsmc controller 0xd3800000 0xd3ffffff fsmc - nand memory 0xd4000000 0xd7ffffff fsmc - sram memory 0xd8000000 0xd807ffff pgc_ir 0xd8080000 0xd80fffff dai_i2s 0xd8100000 0xd817ffff as_gpio base address 0xd8180000 0xd87fffff - reserved 0xd8800000 0xd8ffffff plc modem 0xd9000000 0xd97fffff ts 0xd9800000 0xd9ffffff sport 0xda000000 0xda7fffff des_tdes 0xda800000 0xdaffffff c3 0xdb000000 0xe07fffff - reserved 0xe0800000 0xe0ffffff eth ethernet mii - mac 0xe1000000 0xe10fffff usb 2.0 device controller fifo 0xe1100000 0xe11fffff usb 2.0 device co ntroller configuration registers
memory map ST2100 30/39 docid025777 rev 1 0xe1200000 0xe12fffff usb 2.0 device controller configuration plug detect 0xe1300000 0xe17fffff - reserved 0xe1800000 0xe18fffff usb 2.0 host controller ehci 0xe1900000 0xe19fffff usb 2.0 host controller ohci 0xe1a00000 0xefffffff - reserved 0xf0000000 0xf00fffff gpt0 timer 0 or cpu timer 0xf0100000 0xf0ffffff - reserved 0xf1000000 0xf107ffff pcie dbi port 0xf1080000 0xf10fffff pcie miphy uport 0xf1100000 0xf11fffff vic vec tor interrupt controller 0xf1200000 0xf7ffffff - reserved 0xf8000000 0xfbffffff smi memory 0xfc000000 0xfc1fffff smi configuration registers 0xfc200000 0xfc3fffff clcd 0xfc400000 0xfc5fffff dmac 0xfc600000 0xfc7fffff external s dram cfg configuration registers 0xfc800000 0xfc87ffff gpt1 timer 1 0xfc880000 0xfc8fffff wdg watchdog 0xfc900000 0xfc97ffff rtc 0xfc980000 0xfc9fffff gpio1 0xfca00000 0xfca7ffff sys_ ctrl system controller 0xfca80000 0xfcafffff misc miscellaneous registers 0xfcb00000 0xfcb7ffff gpt2 timer 2 0xfcb80000 0xfcbfffff gpio2 0xfcc00000 0xfeffffff - reserved 0xff000000 0xff00ffff 48k_boot_rom 0xff00c000 0xffffffff - reserved table 17. memory map description (continued) start address end address peripheral description
docid025777 rev 1 31/39 ST2100 clocking parameters 39 6 clocking parameters this section details clock rela ted electrical specifications. 6.1 master clock (mclk) the external circuit for gene rating the clock from a crys tal oscillator is shown in figure 4 . figure 4. mclk crystal connections 1. c l1 and c l2 are the load capacitors. the value of the capacitors depends on the type of the selected crystal. to calculate the value of the load capacitance, use equation 1 . for this example, an aker c2e-24.000-12-3030 -x 24 mhz oscillator has been used. load capacitance c l : equation 1 c l = (c l1 c l2 / c l1 + c l2 ) + c s where c l1 and c l2 are the load capacitors and c s is the circuit's stray capacitance. in our application this implies: equation 2 c l1 = c l2 = c ext equation 3 c ext = (c l - c s ) 2 example for the aker ? c2e-24.000-12-3030-x crystal: c l = 12 pf; with c s = 3 pf, c ext = c l1 = c l2 = 18 pf. note: the esr of the used quartz must be < 50 ? ? . 0+] 9 '' 9 0&/.b;2 0&/.b ;, & / & / $0
clocking parameters ST2100 32/39 docid025777 rev 1 6.2 real-time clock (rtc) the external circuit for generating the real-tim e clock from a crystal oscillator is shown in figure 5 . figure 5. rtc crystal connection 1. c l1 and c l2 are the load capacitors. the value of the capacitors depends on the type of the selected crystal. for example, using a fox electronics ? , p/n nc26lf-327 32.768 khz oscillator, the value of the capacitors is 15 pf. the oscillator may not start if a crystal (f ox p/n fx325bs) is used. if the shunt capacitance (co) of the crystal is ~7.0 pf, then the maximum esr of the crystal must be less than 50 ? . 6.3 pcie/sata clock for sata operation, the pcie_xtal1/pcie_ xtal2 clock inputs can be implemented by a 30 mhz crystal oscillator as shown in table 18 . for pcie operation, a suitable clock driver such as idt idt_9fg104 can be used. .+] *1' 57&b;2 57& b;, & / & / $0 table 18. expi clock characteristics symbol parameter min. typical max. unit f osc pcie_xtal1/pcie_xtal2 clock input frequency for sata configuration 30 mhz pcie_xtal1/pcie_xtal2 clock input frequency for pcie configuration 100
docid025777 rev 1 33/39 ST2100 electrical characteristics 39 7 electrical characteristics this section provides electrical specif ications for the streamplug ST2100 device. 7.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high/low static voltages. however it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. the absolute maximum ratings shown in table 19 are the maximum stress that can be applied to a device without causing permanent damage. however, extended exposure to minimum/maximum ratings may affe ct long term device reliability. 7.2 power consumption in table 20 and table 21 power consumption data are based on bench measurements with devices using the linux os, the cpu and ddr2 running at 333 mhz and all on-chip peripherals and internal modules enabled while the streamplug ST2100 is transferring a file from the usb flash memory to the powerline. table 19. absolute maximum rating symbol parameter min. max. unit v dd 1.2 supply voltage for the core -0.3 1.32 v v dd 3.3 supply voltage for the i/os -0.3 3.63 v v dd 2.5 supply voltage for the ddr/afe -0.3 2.75 v v dd 1.5 supply voltage for the real-time clock -0.3 2.75 v t stg storage temperature -55 150 c t j junction temperature -40 125 c table 20. power consumption symbol parameter typical unit pd (core supply) power consumption of 1.2 v supply voltage for the core 460 mw pd (io supply) power consumption of 3.3 v supply voltage for the i/os 270 mw pd (afe supply) power consumption of 2.5 v supply voltage 260 mw pd (ddr supply) power consumption of 1.8 v supply voltage for the ddr interface 170 mw pd (rtc supply) power consumption of 1.5 v supply voltage for the rtc 9 w
electrical characteristics ST2100 34/39 docid025777 rev 1 7.3 dc electrical characteristics the recommended operating conditions are listed in table 22 and table 23 . thermal simulations should be done to verify if additional cooling is required. these simulations should take into account power consumption, pcb dissipation, air flow and/or heatsinks. the streamplug device can perfo rm correctly above the specified ambient temperature range if the maximum junction temperature remains below 125 c. table 21. power consumption using 2.5 v internal ldo symbol parameter typical unit p d (core supply) power consumption of 1.2 v supply voltage for the core 460 mw p d (io supply) power consumption of 3.3 v supply voltage for the i/os 630 mw p d (ddr supply) power consumption of 1.8 v supply voltage for the ddr interface 170 mw p d (rtc supply) power consumption of 1.5 v supply voltage for the rtc 9 w table 22. recommended operating conditions symbol parameter min. typical max. unit v dd 1.2 supply voltage for the core 1.08 1.2 1.32 v v dd 3.3 supply voltage for the i/os 2.97 3.3 3.63 v v dd 2.5 supply voltage for the analog peripherals 2.25 2.5 2.75 v v dd 1.8/2.5 supply voltage for the ddr -10% 2.5 v / 1.8 v +10% v v dd 1.5 supply voltage for the rtc 1.3 1.5 2.0 v v dd 3.3 reg supply voltage for 2.5 v linear regulator 2,97 3.3 3.63 v table 23. thermal recommended ratings symbol parameter min. max. unit t stg storage temperature range -55 150 c t j junction temperature -40 125 t a ambient temperature -40 85
docid025777 rev 1 35/39 ST2100 electrical characteristics 39 7.4 power-up an d reset sequence the master rese t (mreset) must be released after the v dd 2.5 power supply is stable for a time interval of 2 ms, which is the start-up time of the main oscillator, as illustrated in figure 6 . figure 6. power-up and reset sequence 7.5 internal 2.5 v linear regulator the internal linear regulator specified in table 24 provides a regulated 2.5 v power supply for on-chip afe, osci, pll, usb phy, pcie phy and synth functional blocks. the 2.5 v regulator cannot be used to supply external devices. 05(6(7 9 '' 9 9 '' 9 9 9 '' 9 9 '' 9 'hod\wlph pviurp vwdeoh 9 '' 9 pd[ $0 table 24. internal 2.5 v voltage regulator specifications symbol parameter min. typical max. unit v dd 3.3 reg supply voltage for 2.5 v linear regulator 2.97 3.3 3.36 v v dd 2.5 reg output voltage of 2.5 v linear regulator 2.25 2.5 2.75 v i load 2.5 reg output current of 2.5 v linear regulator - - 150 ma
package information ST2100 36/39 docid025777 rev 1 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 7. package outline for tfbga 12 x 12 x 1.2 mm, 324 + 49 balls, 4r23 x 23, pitch 0.5 mm, ball 0.3 mm 1. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heatslug. a distinguishing f eature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. 7)%*$
docid025777 rev 1 37/39 ST2100 package information 39 table 25 lists the mechanical data for the package shown in figure 7 . the tfbga (?thin profile fine pi tch ball grid array?) package uses a grid of solder balls as its connectors. the tfbga package is noted for its compact size, high lead count and low inductance, which allows lo wer voltages to be used. table 26 lists thermal characteristics for the tfgba package. table 25. tfbga 12 x 12 x 1.2 mm, 324 + 49 balls, 4r23 x 23, pitch 0.5 mm, ball 0.3 mm package mechanical data symbol dimensions (mm) note min. typical max. a1.20 (1) 1. the total profile height (dim. a) is measured fr om the seating plane to the top of the component. the maximum total package height is ca lculated by the following methodology: a1 typ. + a2 typ. + a3 typ. + ? (a1 2 + a2 2 + a3 2 tolerance values). thin profile: 1.00 < a . 1.20 mm / fine pitch: e < 1.00 mm pitch. a1 0.15 a2 0.20 a4 0.585 b 0.25 0.30 0.35 (2) 2. the typical ball diameter before mounting is 0.30 mm. d 11.85 12.00 12.15 d1 11.00 e 11.85 12.00 12.15 e1 11.00 e0.50 z0.50 ddd 0.08 eee 0.15 (3) 3. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindrical tolerance z one ?eee? perpendicular to datum ?c? and located on true position with respect to datums ?a ? and ?b? as defined by ?e?. the axis perpendicular to datum ?c? of each ball must lie within this tolerance zone. fff 0.05 (4) 4. the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance z one ?fff? perpendicular to datum ?c? and located on true position as defined by ?e?. the axis perpendicular to datum ?c? of each ball must lie within this tolerance zone. each tolerance zone ?fff? in the array is cont ained entirely in the respective zone ?eee? above. the axis of each ball must lie simu ltaneously in both tolerance zones. table 26. tfgba package thermal characteristics symbol parameter value unit ? ja (1) 1. measured on a jesd51 2s2p test board. thermal resistance junction to ambient 33 c/w
revision history ST2100 38/39 docid025777 rev 1 9 revision history table 27. document revision history date revision changes 23-may-2014 1 initial release.
docid025777 rev 1 39/39 ST2100 39 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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