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rev. 1.4 12/15 copyright ? 2015 by silicon laboratories SI5335 SI5335 w eb -c ustomizable , a ny -f requency , a ny -o utput q uad c lock g enerator /b uffer features applications description the SI5335 is a highly flexible clock generator capable of synthesizing four completely non-integer-related frequencies up to 350 mhz. the device has four banks of outputs with each bank supporting one differential pair or two single-ended outputs. using silicon laboratories' patented multisynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of configuration, enabling the replacement of multiple clock ics and crystal oscillators with a single device. the SI5335 supports up to three independent, pin-selectable device configurations, enabling one device to replace three separate clock generators or buffer ics. to ease system design, up to five user-assignable and pin-selectable control pins are provided, supporting pcie-compliant spread spectrum control, master and/or individual output enables, frequency plan selection, and device reset. two selectable pll loop bandwidths support jitter attenuation in applications, such as pcie and dsl. through its flexible clockbuilder? ( www.silabs.com/clockbuilder ) web configuration utility, factory-customized, pin-controlled devices are available in two weeks without minimum order quantity restrictions. measuring pcie clock jitter is quick and easy with the silicon labs pcie clock jitter tool. download it for free at www.silabs.com/pcie-learningcenter . ? low power multisynth? technology enables independent, any-frequency synthesis of four frequencies ? configurable as a clock generator or clock buffer device ? three independent, user-assignable, pin- selectable device configurations ? highly-configurable output drivers with up to four differential outputs, eight single-ended clock outputs, or a combination of both ? low phase jitter of 0.7 ps rms ? flexible input reference: ?? external crystal: 25 or 27 mhz ?? cmos input: 10 to 200 mhz ?? sstl/hstl input: 10 to 350 mhz ?? differential input: 10 to 350 mhz ? independently configurable outputs support any frequency or format: ?? lvpecl/lvds/cml: 1 to 350 mhz ?? hcsl: 1 to 250 mhz ?? cmos: 1 to 200 mhz ?? sstl/hstl: 1 to 350 mhz ? independent output voltage per driver: 1.5, 1.8, 2.5, or 3.3 v ? single supply core with excellent psrr: 1.8, 2.5, 3.3 v ? up to five user-assignable pin functions simplify system design: ssenb (spread spectrum control), reset, master oeb or oeb per pin, and frequency plan select (fs1, fs0) ? loss of signal alarm ? pcie gen 1/2/3/4 common clock compliant ? pcie gen 3 srns compliant ? two selectable loop bandwidth settings: 1.6 mhz or 475 khz ? easy to customize with web-based utility ? small size: 4 x 4 mm, 24-qfn ? low power (core): ?? 45 ma (pll mode) ?? 12 ma (buffer mode) ? wide temperature range: ?40 to +85 c ? ethernet switch/router ? pci express gen 1/2/3/4 ? pcie jitter attenuation ? dsl jitter attenuation ? broadcast video/audio timing ? processor and fpga clocking ? msan/dslam/pon ? fibre channel, san ? telecom line cards ? 1 gbe and 10 gbe ordering information: see page 41. pin assignments xa/clkin clk2b clk2a vddo2 vddo1 clk1b clk1a vdd vdd p1 clk3a clk3b los p2 vddo0 clk0b clk0a rsvd_gnd vddo3 gnd gnd pad 5 4 3 2 1 6 13 10 9 8 7 p3 gnd p5 p6 top view 11 12 15 14 16 17 18 19 20 21 22 23 24 xb/clkinb
SI5335 2 rev. 1.4 functional block diagram clk0a vddo1 vddo2 vddo3 vddo0 multisynth0 clk0b clk1a clk1b clk2a clk2b clk3a clk3b xa / clkin osc clkin los multisynth1 multisynth2 multisynth3 xb / clkinb pll pll bypass control p1 p2 p3 p5 p6 programmable pin function options: oeb0/1/2/3 oeb_all ssenb fs[1:0] reset pll bypass pll bypass pll bypass oeb0 oeb1 oeb2 oeb3
SI5335 rev. 1.4 3 t able of c ontents section page 1. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. typical pcie system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2. multisynth technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3. clockbuilder web-customization utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4. input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5. input and output frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6. multi-function control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7. output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8. frequency select/device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9. loss-of-signal alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10. output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5. spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. jitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7. power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8. loop bandwidth considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9. applications of the SI5335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1. free-running clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2. synchronous frequency translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3. configurable universal buffer and level translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12. package outline: 24-lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13. recommended pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.1. SI5335 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15. device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SI5335 4 rev. 1.4 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit ambient temperature t a ?40 25 85 c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.98 v output buffer supply voltage v ddon 1.4 ? 3.63 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. table 2. dc characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit core supply current (clock generator mode) i ddcg 100 mhz on all outputs, 25 mhz refclk, clock generator mode ?4560ma core supply current (buffer mode) i ddb 50 mhz refclk ? 12 ? ma output buffer supply current i ddox lvpecl, 350 mhz ? ? 30 ma cml, 350 mhz ? 12 ? ma lvds, 350 mhz ? ? 8 ma hcsl, 250 mhz 2pf load ??20ma sstl, 350 mhz ? ? 19 ma cmos, 50 mhz 15 pf load 1 ?6 9ma cmos, 200 mhz 1,2 3.3 v vdd0 ?1318ma cmos, 200 mhz 1,2 2.5 v ?1014ma cmos, 200 mhz 1,2 1.8 v ?710ma hstl, 350 mhz ? ? 19 ma notes: 1. single cmos driver active. 2. measured into a 5? 50 ? trace with 2 pf load.
SI5335 rev. 1.4 5 table 3. performance characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit pll acquisition time t acq 1.6 mhz loop bandwidth ? ? 25 ms pll tracking range f track 475 khz or 1.6 mhz loop bandwidth 5000 20000 ? ppm pll loop bandwidth f bw1 high bandwidth option ? 1.6 ? mhz f bw2 low bandwidth option ? 475 ? khz multisynth frequency synthesis resolution f res output frequency < fvco/8 0 0 1 ppb clkin loss of signal detect time t los ?2.6 5 s clkin loss of signal release time t losrls 0.01 0.2 1 s por to output clock valid t rdy ?? 2 ms input-to-output propagation delay t prop buffer mode (pll bypass) ?2.5 4 ns reset minimum pulse width t reset ??200 ns output-output skew 1 t dskew f out > 5mhz ? ? 100 ps spread spectrum pp frequency deviation 2 ss dev f out = 100 mhz ? ?0.45 ?0.5 % spread spectrum modulation rate 3 ss dev f out = 100 mhz 30 31.5 33 khz notes: 1. outputs at integer-related frequencie s and using the same driver format. 2. default value is 0.5% down spread. 3. default value is 31.5 khz for pci compliance.
SI5335 6 rev. 1.4 table 4. input and output clock characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit input clock (ac coupled differenti al input clocks on pins 1 and 2) 1 frequency f in lvds, lvpecl, hcsl, cml 10 2 ?350 mhz differential voltage swing v pp 350 mhz input 0.4 ? 2.4 v pp rise/fall time 3 t r /t f 20%?80% ? ? 1.0 ns duty cycle 3 dc (pll mode) <1ns t r /t f 40 ? 60 % dc (pll bypass mode) <1ns t r /t f 45 ? 55 % input impedance 1 r in 10 ? ? k ? input capacitance c in ?3.5?pf input clock (ac-coupled singl e-ended input clock on pin 1) frequency f in cmos, hstl, sstl 10 2 ?200mhz cmos input voltage swing v i 200 mhz 0.8 ? 1.2 vpp cmos rise/fall time t r /t f 10%?90% ? ? 4 ns cmos rise/fall time t r /t f 20%?80% ? ? 2.3 ns hstl/sstl input voltage v i(hstl/ sstl) 200 mhz 0.4 ? 1.2 v pp hstl/sstl rise/fall time t r /t f 10%?90% ? ? 1.4 ns notes: 1. use an external 100 ? resistor to provide load termination for a differential clock. see "3.4.2. differential input clocks" on page 19. 2. minimum input frequency in clock buffer mode (pll bypass) is 5 mhz. operation to 1 mhz is also supported in buffer mode, but loss-of-signal (los) status is not functional. 3. applies to differential inputs. for best jitter performance, keep the midpoint peak-to-peak differential input slew rate on pins 1 and 2 faster than 0.3 v/ns. 4. cml output format requires ac-coupling of th e differential outputs to a differential 100 ? load at the receiver. see "3.10.6. cml outputs" on page 31. 5. includes effect of internal series 22 ? resistor.
SI5335 rev. 1.4 7 duty cycle dc (pll mode) <1ns t r /t f 40 ? 60 % dc (pll bypass mode) <1ns t r /t f 45 ? 55 % input capacitance c in ?3.5?pf output clocks (differential) frequency f out lvpecl, lvds, cml 1 ? 350 mhz hcsl 1 ? 250 mhz lvpecl output voltage v oc common mode ? v ddo ? 1.45 v ?v v sepp peak-to-peak single- ended swing 0.55 0.8 0.96 v pp lvds output voltage (2.5/3.3 v) v oc common mode 1.125 1.2 1.275 v v sepp peak-to-peak single- ended swing 0.25 0.35 0.45 v pp lvds output voltage (1.8 v) v oc common mode 0.8 0.875 0.95 v v sepp peak-to-peak single- ended swing 0.25 0.35 0.45 v pp hcsl output voltage v oc common mode 0.35 0.375 0.400 v v sepp peak-to-peak single- ended swing 0.575 0.725 0.85 v pp cml output voltage v oc common mode ? see note 4 ?v v sepp peak-to-peak single- ended swing 0.67 0.860 1.07 v pp rise/fall time t r /t f 20% to 80% lvpecl, lvds, hcsl, cml ??450ps table 4. input and output clock characteristics (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. use an external 100 ? resistor to provide load termination for a differential clock. see "3.4.2. differential input clocks" on page 19. 2. minimum input frequency in clock buffer mode (pll bypass) is 5 mhz. operation to 1 mhz is also supported in buffer mode, but loss-of-signal (los) status is not functional. 3. applies to differential inputs. for best jitter performance, keep the midpoint peak-to-peak differential input slew rate on pins 1 and 2 faster than 0.3 v/ns. 4. cml output format requires ac-coupling of th e differential outputs to a differential 100 ? load at the receiver. see "3.10.6. cml outputs" on page 31. 5. includes effect of internal series 22 ? resistor.
SI5335 8 rev. 1.4 duty cycle dc lvpecl, lvds, hcsl, cml 45 ? 55 % output clocks (single-ended) frequency f out cmos 1 ? 200 mhz sstl, hstl 1 ? 350 mhz cmos 20%?80% rise/fall time t r /t f 2pf load ? 0.45 0.85 ns cmos 20%?80% rise/fall time t r /t f 15 pf load ? ? 2.0 ns cmos output voltage 5 v oh 4 ma load vddo ? 0.3 ? v v ol 4ma load ? 0.3 v cmos output resistance 5 ?50? ? hstl, sstl 20%?80% rise/fall time t r /t f see figure 16. ? 0.35 ? ns hstl output voltage v oh vddo = 1.4 to 1.6 v 0.5xvddo+0.3 ? ? v v ol ? ? 0.5xvddo ?0.3 v sstl output voltage v oh sstl-3 vddox = 2.97 to 3.63 v 0.45xvddo+0.41 ? ? v v ol ? ? 0.45xvddo?0.41 v v oh sstl-2 vddox = 2.25 to 2.75 v 0.5xvddo+0.41 ? ? v v ol ? ? 0.5xvddo?0.41 v v oh sstl-18 vddox = 1.71 to 1.98 v 0.5xvddo+0.34 ? v v ol ? ? 0.5xvddo?0.34 v hstl, sstl output resistance ?50? ? duty cycle dc 45 ? 55 % table 4. input and output clock characteristics (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. use an external 100 ? resistor to provide load termination for a differential clock. see "3.4.2. differential input clocks" on page 19. 2. minimum input frequency in clock buffer mode (pll bypass) is 5 mhz. operation to 1 mhz is also supported in buffer mode, but loss-of-signal (los) status is not functional. 3. applies to differential inputs. for best jitter performance, keep the midpoint peak-to-peak differential input slew rate on pins 1 and 2 faster than 0.3 v/ns. 4. cml output format requires ac-coupling of th e differential outputs to a differential 100 ? load at the receiver. see "3.10.6. cml outputs" on page 31. 5. includes effect of internal series 22 ? resistor.
SI5335 rev. 1.4 9 table 5. control pins* (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol condition min typ max unit input control pins (p1, p2, p3, p5*, p6*) input voltage low v il pins p1, p2, p3 ?0.1 ? 0.3 x v dd v pins p5 and p6 ? ? 0.3 v input voltage high v ih pins p1, p2, p3 0.7 x v dd ?3.73 v pins p5* and p6* 0.85 ? 1.2 v input capacitance c in ?? 4 pf input resistance r in ?20?k ? output control pins (los, pin 8) output voltage low v ol i sink =3ma 0 ? 0.4 v rise/fall time 20?80% t r /t f c l < 10 pf, pull up ? 1k ? ? ? 10 ns *note: for more information, see "3.6.1. p5 and p6 input control" on page 24. table 6. crystal specifications for 25 mhz parameter symbol min typ max unit crystal frequency f xtal ?25?mhz load capacitance (on-chip differential) c l ?18?pf crystal output capacitance c o ?? 5 pf equivalent series resistance r esr ??100 ? crystal max drive level d l 100 ? ? w table 7. crystal specifications for 27 mhz parameter symbol min typ max unit crystal frequency f xtal ?27?mhz load capacitance (on-chip differential) c l ?18?pf crystal output capacitance c o ?? 5 pf equivalent series resistance r esr ??75 ? crystal max drive level d l 100 ? ? w
SI5335 10 rev. 1.4 table 8. jitter specifications, clock generator mode (loop bandwidth = 1.6 mhz) 1,2,3 (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test c ondition min typ max unit gbe random jitter (12khz?20mhz) 4 j gbe clkin = 25 mhz all clkn at 125 mhz 5 ? 0.7 1 ps rms gbe random jitter (1.875?20 mhz) r jgbe clkin = 25 mhz all clkn at 125 mhz 5 ? 0.38 0.79 ps rms oc-12 random jitter (12 khz?5 mhz) j oc12 clkin = 19.44 mhz all clkn at 155.52 mhz 5 ? 0.7 1 ps rms pci express 1.1 common clocked (with spread spectrum) total jitter 6 ? 20.1 33.6 ps pk-pk pci express 2.1 common clocked (no spread spec- trum) rms jitter 6 , 10 khz to 1.5 mhz ? 0.15 1.47 ps rms rms jitter 6 , 1.5 mhz to 50 mhz ? 0.58 0.75 ps rms pci express 3.0 common clocked (no spread spectrum) rms jitter 6 ? 0.15 0.45 ps rms pcie gen 3 separate reference no spread, srns pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz ? 0.11 0.32 ps rms pcie gen 4, common clock pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz ? 0.15 0.45 ps rms period jitter j per n = 10,000 cycles 7 ? 10 30 ps pk-pk notes: 1. all jitter measurements apply for lvds/ hcsl/lvpecl/cml output format with a low noise differential input clock and are made with an agilent 90804 oscilloscope. all rj measurements use rj/dj separation. 2. all jitter data in this table is based upon all output formats being differential. when single-ended outputs are used, there is the potential that the output jitter may increase due to the nature of single-ended outpu ts. if your configuration implements any single-ended output and any output is requ ired to have jitter less than 2 p s rms, contact silicon labs for support to validate your configurat ion and ensure the best jitter performa nce. in many configurations, cmos outputs have little to no effect upon jitter. 3. for best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 v/ns and the differential clock input slew rates greater than 0.3 v/ns. 4. d j for pci and gbe is < 5 ps pp 5. output multisynth in integer mode. 6. all output clocks 100 mhz hcsl format. jitter is from the pcie ji tter filter combinat ion that produces the highest jitter. see an562 for details. jitter is mesured with the intel clock jitter tool, ver.1.6.4. 7. for any output frequency > 10 mhz. 8. measured in accordance with jedec standard 65. 9. rj is multiplied by 14; estimate the pp jitter from rj over 2 12 rising edges. 10. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5. 11. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI5335 rev. 1.4 11 cycle-cycle jitter j cc n = 10,000 cycles output multisynth operated in integer or fractional mode 7 ? 9 29 ps pk 8 random jitter (12khz?20mhz) r j output and feedback multisynth in integer or fractional mode 7 ? 0.7 1.5 ps rms deterministic jitter d j output multisynth operated in fractional mode 7 ?315ps pk-pk output multisynth operated in integer mode 7 ?210ps pk-pk total jitter (12khz?20mhz) t j =d j +14xr j (see note 9 ) output multisynth operated in fractional mode 7 ? 13 36 ps pk-pk output multisynth operated in integer mode 7 ? 12 20 ps pk-pk table 8. jitter specifications, clock generator mode (loop bandwidth = 1.6 mhz) 1,2,3 (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test c ondition min typ max unit notes: 1. all jitter measurements apply for lvds/ hcsl/lvpecl/cml output format with a low noise differential input clock and are made with an agilent 90804 oscilloscope. all rj measurements use rj/dj separation. 2. all jitter data in this table is based upon all output formats being differential. when single-ended outputs are used, there is the potential that the output jitter may increase due to the nature of single-ended outpu ts. if your configuration implements any single-ended output and any output is requ ired to have jitter less than 2 p s rms, contact silicon labs for support to validate your configurat ion and ensure the best jitter performa nce. in many configurations, cmos outputs have little to no effect upon jitter. 3. for best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 v/ns and the differential clock input slew rates greater than 0.3 v/ns. 4. d j for pci and gbe is < 5 ps pp 5. output multisynth in integer mode. 6. all output clocks 100 mhz hcsl format. jitter is from the pcie ji tter filter combinat ion that produces the highest jitter. see an562 for details. jitter is mesured with the intel clock jitter tool, ver.1.6.4. 7. for any output frequency > 10 mhz. 8. measured in accordance with jedec standard 65. 9. rj is multiplied by 14; estimate the pp jitter from rj over 2 12 rising edges. 10. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5. 11. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI5335 12 rev. 1.4 table 9. jitter specifications, clock generator mode (loop bandwidth = 475 khz) 1,2 (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit dsl random jitter (10 khz?400 khz) r jdsl1 clkin = 70.656 mhz all clkn at 70.656 mhz 4 ? 0.8 2 ps rms dsl random jitter (100 khz?10 mhz) r jdsl2 clkin = 70.656 mhz all clkn at 70.656 mhz 4 ? 0.9 2 ps rms dsl random jitter (10 hz?30 mhz) r jdsl3 clkin = 70.656 mhz all clkn at 70.656 mhz 4 ? 1.95 2.2 ps rms pci express 1.1 common clocked (with spread spectrum) total jitter 5 ? 20 34 ps pk-pk pci express 2.1 common clocked (no spread spectrum) rms jitter 5 , 10 khz to 1.5 mhz ? 0.3 0.5 ps rms rms jitter 5 , 1.5 mhz to 50 mhz ? 0.5 1.0 ps rms pci express 3.0 common clocked (no spread spectrum) rms jitter 5 ? 0.15 0.45 ps rms pcie gen 3 separate reference no spread, srns pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz ? 0.11 0.32 ps rms pcie gen 4, common clock pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz ? 0.15 0.45 ps rms period jitter j per n = 10,000 cycles 6 ? 10 30 ps pk-pk notes: 1. all jitter measurements apply for lvds/ hcsl/lvpecl/cml output format with a low noise differential input clock and are made with an agilent 90804 oscilloscope. all rj measurements use rj/dj separation. 2. all jitter data in this table is based upon all output formats being differential. when single-ended outputs are used, there is the potential that the output jitter may increase due to the nature of single-ended outpu ts. if your configuration implements any single-ended output and any output is requ ired to have jitter less than 2 p s rms, contact silicon labs for support to validate your configurat ion and ensure the best jitter performa nce. in many configurations, cmos outputs have little to no effect upon jitter. 3. d j for pci and gbe is < 5 ps pp 4. output multisynth in integer mode. 5. all output clocks 100 mhz hcsl format. jitter is from the pcie ji tter filter combinat ion that produces the highest jitter. see an562 for details. jitter is mesured with the intel clock jitter tool, ver.1.6.4. 6. for any output frequency > 5mhz. 7. measured in accordance with jedec standard 65. 8. rj is multiplied by 14; estimate the pp jitter from rj over 2 12 rising edges. 9. gen 4 specifications based on the pci-express base specification 4.0 rev. 0.5. 10. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI5335 rev. 1.4 13 cycle-cycle jitter j cc n = 10,000 cycles output multisynth operated in integer or fractional mode 6 ?929ps pk 7 random jitter (12khz?20mhz) r j output and feedback multisynth in integer or fractional mode 6 ? 1 2.5 ps rms deterministic jitter d j output multisynth operated in fractional mode 6 ? 3 15 ps pk-pk output multisynth operated in integer mode 6 ? 2 10 ps pk-pk total jitter (12khz?20mhz) t j =d j +14xr j (see note 8 ) output multisynth operated in fractional mode 6 ? 13 36 ps pk-pk output multisynth operated in integer mode 6 ? 15 30 ps pk-pk table 9. jitter specifications, clock generator mode (loop bandwidth = 475 khz) 1,2 (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. all jitter measurements apply for lvds/ hcsl/lvpecl/cml output format with a low noise differential input clock and are made with an agilent 90804 oscilloscope. all rj measurements use rj/dj separation. 2. all jitter data in this table is based upon all output formats being differential. when single-ended outputs are used, there is the potential that the output jitter may increase due to the nature of single-ended outpu ts. if your configuration implements any single-ended output and any output is requ ired to have jitter less than 2 p s rms, contact silicon labs for support to validate your configurat ion and ensure the best jitter performa nce. in many configurations, cmos outputs have little to no effect upon jitter. 3. d j for pci and gbe is < 5 ps pp 4. output multisynth in integer mode. 5. all output clocks 100 mhz hcsl format. jitter is from the pcie ji tter filter combinat ion that produces the highest jitter. see an562 for details. jitter is mesured with the intel clock jitter tool, ver.1.6.4. 6. for any output frequency > 5mhz. 7. measured in accordance with jedec standard 65. 8. rj is multiplied by 14; estimate the pp jitter from rj over 2 12 rising edges. 9. gen 4 specifications based on the pci-express base specification 4.0 rev. 0.5. 10. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI5335 14 rev. 1.4 table 10. itter specifications, clock buffer mode (pll bypass)* (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit additive phase jitter (12khz?20mhz) t rphase 0.7 v pk-pk differential input clock at 350 mhz with 70 ps rise/fall time ? 0.165 ? ps rms additive phase jitter (50khz?80mhz) t rphasewb 0.7 v pk-pk differential input clock at 350 mhz with 70 ps rise/fall time ? 0.225 ? ps rms *note: all outputs are in clock buffer mode (pll bypass). table 11. typical phase noise performance offset frequency loop bandwidth 25 mhz xtal to 156.25 mhz 27 mhz ref in to 148.3517 mhz 19.44 mhz ref in to 155.52 mhz 100 mhz ref in to 100 mhz units 100 hz 1.6 mhz ?90 ?87 ?110 ?115 dbc/hz 475 khz n/a* ?91 ?91 ?113 dbc/hz 1 khz 1.6 mhz ?120 ?117 ?116 ?122 dbc/hz 475 khz n/a* ?112 ?111 ?122 dbc/hz 10 khz 1.6 mhz ?126 ?123 ?123 ?128 dbc/hz 475 khz n/a* ?124 ?122 ?127 dbc/hz 100 khz 1.6 mhz ?132 ?130 ?128 ?136 dbc/hz 475 khz n/a* ?122 ?121 ?124 dbc/hz 1 mhz 1.6 mhz ?132 ?132 ?128 ?136 dbc/hz 475 khz n/a* ?133 ?131 ?135 dbc/hz 10 mhz 1.6 mhz ?145 ?145 ?145 ?152 dbc/hz 475 khz n/a* ?152 ?153 ?152 dbc/hz *note: xtal input mode does not support the 475 khz loop bandwidth setting. table 12. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 37 c/w thermal resistance junction to case ? jc still air 25 c/w
SI5335 rev. 1.4 15 table 13. absolute maximum ratings 1 parameter symbol test condition value unit dc supply voltage v dd ?0.5 to 3.8 v input voltage v in pins: xa/clkin, xb/clkinb, p5, p6 ?0.5 to 1.3 v pins: p1, p2, p3 ?0.5 to 3.8 v storage temperature range t stg ?55 to 150 c esd tolerance hbm (100 pf, 1.5 k ? ) 2.5 kv esd tolerance cdm 550 v esd tolerance mm 175 v latch-up tolerance jesd78 compliant junction temperature t j 150 c peak soldering reflow temperature 2 260 c notes: 1. permanent device damage may occur if the absolute maxi mum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. refer to jedec j-std-020 standard for more information.
SI5335 16 rev. 1.4 2. typical pcie system diagram figure 1. pci express switching application example figure 1 shows the SI5335 in a pci express applicatio n using the common clock topology. the SI5335 provides reference clocks to the three fpgas, each of which requ ires a different clock signaling format (lvds, lvpecl), i/o voltage (1.8, 2.5, 3.3 v), or frequency (25, 100, 125 mh z). in addition, the SI5335 provides a pcie compliant, 100 mhz hcsl reference cloc k to the pcie switch. main board pcie core fpga a pcie core fpga b pcie link pcie core fpga c pcie switch backplane pcie link pcie link peripheral board peripheral board 125mhz lvds 100mhz hcsl 25mhz lvpecl 25mhz lvpecl SI5335 clock generator
SI5335 rev. 1.4 17 3. functional description figure 2. SI5335 functional block diagram 3.1. overview the SI5335 is a high-performance, low-jitter clock genera tor or buffer capable of synthesizing four independent user-programmable clock frequencies up to 350 mhz. the device supports free-run operation using an external 25 or 27 mhz crystal, or it can lock to an external clock for generating synchronous clocks. the output drivers support four differential clocks or eight single-ended clocks or a combination of both. the output drivers are configurable to support common signal formats, such as lvpecl, lvds, hcsl, cml, cmos , hstl, and sstl. separate output supply pins allow supply voltages of 3.3, 2.5, 1.8, and 1.5 v to support the multi-format output driver. the core voltage supply accepts 3.3, 2.5, or 1.8 v and is indep endent from the output supplies. using its two-stage synthesis architecture and patented high-resolution multisynth technology, the SI5335 can generate four independent frequencies from a single input frequency. in addition to clock generation, the inputs can bypass the synthesis stage enabling the SI5335 to be used as a high-performance clock buffer. spread spectrum* is available on each of the clock outputs for emi-sensit ive applications, such as pci express. the device includes an interrupt pin that monitors for both loss of pll lock (lol) and loss of input signal (los) conditions while configured in clock generator mode. in clock generator mode, the lo s pin is asserted whenever lol or los is true. in clock buffer mode (i.e., when the pll is bypassed), the los pin is asserted whenever the input clock is lost. the lol condition does not apply in clock buffer mode. *note: see " document change list" on page 46 for more information. clk0a vddo1 vddo2 vddo3 vddo0 multisynth0 clk0b clk1a clk1b clk2a clk2b clk3a clk3b xa / clkin osc clkin los multisynth1 multisynth2 multisynth3 xb / clkinb pll pll bypass control p1 p2 p3 p5 p6 programmable pin function options: oeb0/1/2/3 oeb_all ssenb fs[1:0] reset pll bypass pll bypass pll bypass oeb0 oeb1 oeb2 oeb3
SI5335 18 rev. 1.4 3.2. multisynth technology next-generation timing architectures require a wide ra nge of frequencies which are often non-integer related. traditional clock architectures address this by using a co mbination of single pll ics, 4-pll ics and discrete xos, often at the expense of bom comple xity and power. the SI5335 uses pa tented multisynth technology to dramatically simplify timing architectu res by integrating the fre quency synthesis capability of 4 phase-locked loops (plls) in a single device, greatly minimizing size and powe r requirements versus traditional solutions. based on a fractional-n pll, the heart of the architecture is a lo w phase noise, high-frequency vco. the vco supplies a high frequency output clock to the multisynth block on each of the four independent output paths. each multisynth operates as a high -speed fractional divider with s ilicon laboratories' pr oprietary phase error correction to divide down the vco clock to the required output frequency with very low jitter. the first stage of the multisynth architecture is a fracti onal-n divider which switches seamlessly between the two closest integer divider values to pr oduce the exact output clock frequency with 0 ppm error. to eliminate phase error generated by this process, multisynth calculates the relative phase difference between the clock produced by the fractional-n divider and the desired output clock an d dynamically adjusts the phase to match the ideal clock waveform. this novel approach makes it possible to generat e any output clock frequency without sacrificing jitter performance. based on this architecture, the output of each multisynth can produce any frequency from 1 to 350 mhz. figure 3. silicon labs' multisynth technology 3.3. clockbuilder we b-customization utility clockbuilder is a web-ba sed utility available at www.silabs.com/clockbuilder that allows hardware designers to tailor the SI5335?s flexible clock architecture to meet an y application-specific requirements and order custom clock samples. through a simple point-and-click interface, users can specify any combination of input frequency and output frequencies and generate a custom part number for each application-specific configuration. there are no minimum order quantity restrictions. clockbuilder enables mass customization of clock generators. this allo ws a broader range of applications to take advantage of using application-specific pin controlled clocks, simplifying design wh ile eliminating the firmware development required by traditional i 2 c-programmable clock generators. based on silicon labs? patented multis ynth technology, the device pll output frequency is constant and all clock output frequencies are synthesized by the four multisynth fractional dividers. all pll parameters, including divider settings, vco frequency, loop bandwidth, charge pump curr ent, and phase margin are internally set by the device during the configuration process. this ensures optimized jitte r performance an d loop stability while simplifying design. fractional-n divider phase adjust phase error calculator divider select (div1, div2) f vco f out multisynth
SI5335 rev. 1.4 19 3.4. input configuration the SI5335 input can be driven from either an external cr ystal or a reference clock. reference selection is made when the device configuration is specified using the clockbuilder ? web-based utility available at www.silabs.com/ clockbuilder . 3.4.1. crystal input if the crystal input option is used, the SI5335 operates as a free-running clock generator. in this mode of operation the device requires a low-cost 25 or 27 mhz fundamenta l mode crystal connected across xa and xb as shown in figure 4. given the SI5335?s fr equency flexibility, the same 25 or 27 mhz crystal can be reused to generate any combination of output frequencies. custom frequency crys tals are not required. the SI5335 integrates the crystal load capacitors on-chip to reduce external component coun t. the crystal should be placed very close to the device to minimize stray capacitance. to en sure stable oscillation, the recommende d crystal specifications provided in tables 6 and 7 must be followed. see an360 for additional details regarding crystal recommendations. figure 4. connecting an xtal to the SI5335 3.4.2. differential input clocks the multi-format differential clock inpu ts of the SI5335 will interface with t oday?s most common di fferential signals, such as lvds, lvpecl, cml, and hcsl. the di fferential inputs are in ternally self-biased and must be ac-coupled externally with a 0.1 f capacitor . the receiver will accept a signal wi th a voltage swing between 400 mv and 2.4 v pp differential. each half of the diff erential signal must not exceed 1.2 v pp at the input to the SI5335 or else the 1.3 v dc voltage limit may be exceeded. 3.4.2.1. lvds inputs when interfacing the SI5335 device to an lvds signal, a 100 ? termination is required at the input along with the required dc blocking capacitors as shown in figure 5. figure 5. lvds input signal 3.4.2.2. lvpecl input clocks recommended configurations for interfacing an lvpecl i nput signal to the SI5335 are shown in figure 6. typical values for the bias resistors (rb) range between 120 ? and 200 ? depending on the lvpecl driver. the 100 ? resistor provides line termination. because the receiver is internally self-biased, no additional external bias is required. another solution is to te rminate the lvpecl driver wit h a thevenin configurati on as shown in figure 6b. ? the xb/clkinb xa/clkin xtal SI5335 lvds keep termination close to input pin of the SI5335 100 50 50 0.1 uf 0.1 uf SI5335 must be ac coupled pin 1 pin 2
SI5335 20 rev. 1.4 values for r 1 and r 2 are calculated to provide a 50 ? termination to v dd -2v. given this, the recommended resistor values are r 1 =127 ?? and r 2 =82.5 ? for v dd = 3.3 v, and r 1 = 250 ?? and ? r 2 =62.5 ?? for v dd =2.5v. figure 6. recommended options for inte rfacing to an lvpecl input signal since the differential receiver of the SI5335 is internally self biased, an lvpecl sign al may not be dc-coupled to the device. figure 7 shows so me common lvpecl connections that should not be used becaus e of the dc levels they present at the receiver?s input. figure 7. common lvpecl connections that may be destructive to the SI5335 input lvpecl input signal with source biasing option lvpecl keep termination close to input pin of the SI5335 3.3 v, 2.5 v 100 rb rb 0.1 uf 0.1 uf SI5335 50 50 must be ac coupled pin 1 pin 2 lvpecl input signal with load biasing option keep termination close to input pin of the SI5335 r 1 50 50 v dd r 2 v dd r 1 r 2 lvpecl = 3.3 v, 2.5 v v dd 0.1 uf 0.1 uf SI5335 must be ac coupled v t = v dd ? 2 v r 1 // r 2 = 50 ohm pin 1 pin 2 lvpecl r 1 50 50 v dd r 2 v dd r 1 r 2 rb rb ac coupled with thevenin re-biasing not recommended lvpecl dc coupled with thevenin termination r 1 v dd r 2 v dd r 1 r 2 50 50
SI5335 rev. 1.4 21 3.4.2.3. cml input clocks cml signals may be applied to the differential inputs of the SI5335. since the SI5335 differential inputs are internally self-biased, a cml signal may not be dc-coupled to the device. the recommended configurations for interfacing a cml in put signal to the SI5335 are shown in figure 8. the 100 ? resistor provides line termination, an d, since the receiver is internally-bia sed, no additional external biasing components are required. figure 8. cml input signal 3.4.2.4. hcsl input clocks a typical hcsl driver has an open source output, which re quires an external series resistor and a resistor to ground. the values of these resistors depend on the driver but are typically equal to 33 ? (rs) and 50 ? (rt). note that the hcsl driver in the SI5335 requires neither rs nor rt resistors. other than two ac-coupling capacitors, no additional external components are necessary wh en interfacing an hcsl signal to the SI5335. figure 9. hcsl input signal to SI5335 cml keep termination close to input pin of the SI5335 100 0.1 uf 0.1 uf SI5335 50 50 must be ac coupled pin 1 pin 2 hcsl 3.3v, 2.5v, 1.8v 0.1 uf 0.1 uf 50 50 rs rs rt rt SI5335 must be ac coupled pin 1 pin 2
SI5335 22 rev. 1.4 3.4.3. single-ended cmos input clocks for synchronous timing applications, the SI5335 can lock to a 10 to 200 mhz cmos reference clock. a typical interface circuit is shown in figure 10. a series termination resistor may be required if the cmos driver impedance does not match the trace impedance. figure 10. interfacing cmos reference clocks to the SI5335 3.4.4. single-ended sstl and hstl input clocks hstl and sstl single-ended inputs can be input to the diff erential inputs, pins 1 and 2, of the SI5335 with the circuit shown in figure 11. some drivers may require a series 25 ? resistor. if the sstl/hstl input is being driven by another SI5335 device, the 25 ? series resistor is not required as this is integrated on-chip. the maximum recommended input frequency in this case is 350 mhz. figure 11. single-ended sstl/hstl input clocks to the SI5335 keep r se and r sh close to the receiver 0.1 uf SI5335 50 0.1 uf cmos input signal r se r sh r se = 402 ? r sh = 357 ? 2.5 v cmos r se = 499 ? r sh = 274 ? 3.3 v cmos r se = 249 ? r sh = 464 ? 1.8 v cmos pin 1 pin 2 keep termination close to input pin of the SI5335 0.1 uf SI5335 50 0.1 uf 50 0.4 to 1.2 v pk-pk differential input v tt 0.1 uf v tt v dd r 1 r 2 r 2 = 2 k r 1 = 2.43 k sstl_3 r 2 = 2 k r 1 = 2.43 k sstl_2, sstl_18, hstl pin 1 pin 2
SI5335 rev. 1.4 23 3.4.5. applying a single-ended clock to the differential input clock pins it is possible to interface any single-ended clock signal to the differential input pins (xa/clkin, xb/clkinb). the recommended interface for a signal that requires a 50 ? load is shown in figure 12. on these inputs, it is important that the signal level be less than 1.2 v pp se and greater than 0.4 v pp se. the maximum recommended input frequency in this case is 350 mhz. figure 12. single-ended input signal with 50 ? termination 3.5. input and output frequency configuration the SI5335 utilizes a single pll-based ar chitecture, four independent multisyn th fractional output dividers, and a multisynth fractional feedback divider such that a single device provides the cl ock generation capability of 4 independent plls. unlike competitive multi-pll solution s, the SI5335 can generate four unique non-integer related output frequencies with 0 ppm frequency error for an y combination of output frequencies. in addition, any combination of output frequencies can be generated from a single reference frequency without having to change the crystal or reference clock frequency between frequency configurations. the SI5335 frequency configuration is set when the device configuration is specifie d using the clockbuilder web- based utility available at www.silabs.com/clockbuilder . any combination of output frequencies ranging from 1 to 350 mhz can be configured on each of the device outp uts. up to three unique device configurations can be specified in a single device, enabling the SI5335 to replace 3 different clock generators or clock buffers. 3.6. multi-function control inputs the SI5335 supports five user-defined input pins (pins 3, 5, 6, 12, 19) that are customizable to support the functions listed below. the pinout of each device is customized using the clockbuilder utility. this enables the device to be custom tailored to a specif ic application. each of the different functions is described in further detail below. table 14. multi-function control inputs pin function description assignable pin name oeb_all output enable all. all outputs enabled when low. p1, p2, p3, p5*, p6* oeb0 output enable bank 0. clk0a/0b enabled when low. p1, p2, p3, p5*, p6* oeb1 output enable bank 1. clk1a/1b enabled when low. p1, p2, p3, p5*, p6* oeb2 output enable bank 2. clk2a/2b enabled when low. p1, p2, p3, p5*, p6* oeb3 output enable bank 3. clk3a/3b enabled when low. p1, p2, p3, p5*, p6* keep termination close to input pin of the SI5335 50 0.1 uf SI5335 50 0.1 uf 0.4 to 1.2v pk-pk pin 1 pin 2
SI5335 24 rev. 1.4 3.6.1. p5 and p6 input control control input signals to p5 and p6 cannot exceed 1.2 v. when these inputs are driven from cmos sources, a resistive attenuator is required for pins 5 and 6, as shown in figure 13. figure 13. p5, p6 control pin termination 3.7. output enable each of the device?s four banks of clock outputs can be individually disabled using oeb0, oeb1, oeb2 and oeb3, respectively. alternatively, all clock outputs can be di sabled using the master output enable oeb_all. when a SI5335 clock output bank is disabled, the output disable st ate is determined by the configuration specified in the clockbuilder web utility. when one or more banks of cl ock outputs are enabled or disabled, clock start and stop transitions are handled glitchlessly. 3.8. frequency select/device reset the device frequency plan is customized using the clockbu ilder web utility. the SI5335 optionally supports up to three unique, pin-selectable configurations per device, e nabling one device to replace up to three separate clock ics. to select a particular frequency plan, set the fs pins as outlined below: for custom SI5335 devices configured to support two fr equency plans, the fs1 pin should be set as follows: fs0 frequency select. selects active device frequency plan from factory-configured profiles. see ?3.8. frequency select/device reset? for more information. p1 fs1 frequency select. selects active device frequency plan from factory-configured profiles. see ?3.8. frequency select/device reset? for more information. p1 (for 2-plan devices) p2 (for 3-plan devices) reset reset. asserting this pin (driving high) is required to change fs1,fs0 pin setting. reset is no t required if fs1,fs0 pins are unassigned. p1, p2, p3 ssenb spread spectrum enable. enables pci-compliant spread spectrum clocking on all 100 mhz clock outputs when low. p1, p2, p3, p5*, p6* *note: see ?3.6.1. p5 and p6 input control? for re commended termination circuits for these pins. fs1 profile table 14. multi-function control inputs (continued) keep r se and r sh close to pin 5 and pin 6 50 cmos input signal r se r sh SI5335 pin 5, pin 6 r se = 1 k ? 1.96 k ? 3.09 k ? r sh = 1.58 k ? 1.58 k ? 1.58 k ? 1.8 v cmos 2.5 v cmos 3.3 v cmos
SI5335 rev. 1.4 25 for custom SI5335 devices configured to support three frequency plans, the fs1 and fs0 pins should be set as follows: i f a change is made to the fs pin settings, the device re set pin (reset) must be held high for the minimum pulse width specified in table 3 on page 5 to change the devi ce configuration. the out put clocks will be momentarily squelched until the device begins operation with the new frequency plan. if the reset pin is not selected in clo ckbuilder as one of the five programmable pins, a power-on reset must be applied for an fs pin change to take effect. 3.9. loss-of-signal alarm the SI5335 supports a loss of signal (los) output indica tor for monitoring the condition of the crystal/clock reference input. the los condition occurs when there is no input clock to the device or the pll has lost lock (in clock generator mode). when an input clock is removed, the los pin will assert and the output clocks may drift up to 5% (in clock generator m ode). when the in put clock with an appropr iate frequency is rea pplied, the los pin will deassert. in clock buffer mode, los is driven high when the input clock is lost. 01 12 fs1 fs0 profile 00reserved 011 102 113 los output state description 0 input clock present and pll is locked 1 input clock not present and pll is not locked
SI5335 26 rev. 1.4 3.10. output stage the output stage consists of programmable output drivers as shown in figure 14. figure 14. output stage the SI5335 devices provide four outputs that can be differ ential or single-ended. when configured as single- ended, the driver generates two signals that can be config ured as in-phase or complementary. each of the outputs has its own output supply pin, allowing the device to be used in mixed supply applications without the need for external level translators. the cml output driver generates a similar output swing as the lvpecl driver but consumes half the current. cml outputs must be ac-coupled. 3.10.1. cmos/lvttl outputs the cmos output driver has a controlled impedance of about 50 ? , which includes an internal series resistor of approximately 22 ? . for this reason, an external rs series resistor is not recommended when driving 50 ? traces. if the trace impedance is higher than 50 ? , a series resistor, rs, should be used. a typical configuration is shown in figure 15. a cmos output driver can be configured wit h clockbuilder as a single- or dual-output driver. dual otuput configurations support in-phase or complementar y outputs. the output supports 3.3, 2.5, and 1.8 v cmos signal levels when the appropriate voltage is supplied to the external vddo pin and the device is configured accordingly. figure 15. interfacing to a cmos receiver clk0a vddo1 vddo2 vddo3 vddo0 clk0b clk1a clk1b clk2a clk2b clk3a clk3b output stage from synthesis stage or input stage SI5335 50 3.3, 2.5, or 1.8 v lvttl/ cmos v ddox clkxa clkxb 50 cmos
SI5335 rev. 1.4 27 3.10.2. sstl and hstl outputs the SI5335 supports both sstl and hstl outputs, whic h can be single-ended or differential. the recommended termination scheme for sstl is shown in figure 16. the v tt supply can be generated using a simple voltage divider as shown below (note that rt = 50 ? ). figure 16. interfacing the SI5335 to an sstl or hstl receiver 3.10.3. lvpecl outputs the lvpecl driver is configurable in both 3.3 v or 2.5 v standard lvpecl modes. the output driver can be ac- coupled or dc-coupled to the receiver. 3.10.3.1. dc-coupled lvpecl outputs the standard lvpecl driver su pports two commonly used dc-c oupled configurations. bo th of these are shown in figure 17a and figure 17b. lvpecl drivers were designed to be terminated with 50 ? to vdd?2 v, which is illustrated in figure 17a. v tt can be supplied with a simple voltage divider as shown. an alternative method of terminating lvpecl is shown in figure 17b, which is the thevenin e quivalent to the termination in figure 17a. it provides a 50 ? load terminated to v dd ?2.0 v. for 3.3 v lvpecl, use r 1 =127 ?? and r 2 =82.5 ? ; for 2.5 v lvpecl, use r 1 =250 ?? and r 2 =62.5 ??? the only disadvantage to this type of termination is that the thevenin circuit cons umes additional power from the v ddo supply. SI5335 sstl (3.3, 2.5, or 1.8 v) hstl (1.5 v) rt rt v tt sstl_3 sstl_2 sstl_18 hstl v ddox clkxa clkxb sstl or hstl r 1 = 2 k ? r 2 = 2 k ? sstl_2, sstl_18, hstl r 1 = 2.43 k ? r 2 = 2 k ? sstl_3 50 50 v tt v ddo v tt r 1 r 2 0.1 f
SI5335 28 rev. 1.4 figure 17. interfacing the SI5335 to an lvpecl receiver using dc coupling b. dc-coupled with thevenin termination keep termination close to the receiver r 1 v ddo r 2 v ddo r 1 r 2 lvpecl SI5335 3.3 v, 2.5 v 50 50 3.3 v lvpecl 2.5 v lvpecl 3.3 v lvpecl r 1 = 127 ? r 2 = 82.5 ? 2.5 v lvpecl r 1 = 250 ? r 2 = 62.5 ? v t = v ddo ? 2.0 v r 1 // r 2 = 50 ? v ddox clkxa clkxb a. dc-coupled termination of 50 ? to v ddo ? 2.0 v lvpecl SI5335 3.3 v, 2.5 v 3.3 v lvpecl 2.5 v lvpecl 50 50 keep termination close to the receiver 50 50 v tt = v ddo ? 2.0 v ddox clkxa clkxb
SI5335 rev. 1.4 29 3.10.3.2. ac coupled lvpecl outputs ac coupling is necessary when a receiver and a driver have compatible voltage swings but different common- mode voltages. ac coupling works well for dc-balanced si gnals, such as for 50% duty cycle clocks. figure 18 describes two methods for ac coupling the standard lvpecl driver. the thevenin termination shown in figure 18a is a convenient and co mmon approach when a v bb (v dd ? 1.3 v) supply is not available; however, it does consume additional power. the termination method shown in figure 18b consumes less power. a v bb supply can be generated from a simple voltage divider circuit as shown in figure 18b. figure 18. interfacing to an l vpecl receiver using ac coupling lvpecl 3.3 v, 2.5 v b. ac coupled with 100 ? termination 3.3 v lvpecl 2.5 v lvpecl 0.1 f 0.1 f 50 50 keep termination close to the receiver 50 50 v bb v ddox clkxa clkxb v ddo ? 1.3 v rb rb rb = 130 ? (2.5 v lvpecl) rb = 200 ? (3.3 v lvpecl) v ddo r 1 r 2 0.1 f SI5335 v bb keep termination close to the receiver r 1 v ddo r 2 v ddo r 1 r 2 lvpecl SI5335 3.3 v, 2.5 v a. ac-coupled with thevenin termination 50 50 3.3 v lvpecl 2.5 v lvpecl 3.3 v lvpecl r 1 = 82.5 ? r 2 = 127 ? 2.5 v lvpecl v ddo ? 1.3 v r 1 // r 2 = 50 ? rb rb v ddox clkxa clkxb 0.1 f 0.1 f rb = 130 ? (2.5 v lvpecl) rb = 200 ? (3.3 v lvpecl) r 1 = 62.5 ? r 2 = 250 ?
SI5335 30 rev. 1.4 3.10.4. lvds outputs the lvds output option provides a very simple and power-efficient interface that requires no external biasing when connected to an lvds receiver. an ac-coupled lvds driver is often useful as a cml driver. the lvds driver may be dc-coupled or ac-coupled to the receiver in 3.3 v or 2.5 v output mode. 3.10.4.1. ac-coupled lvds outputs the SI5335 lvds output can drive an ac-coupled load. th e ac coupling capacitors may be placed at either the driver or receiver end, as long as they are placed prior to the 100 ? termination resistor. keep the 100 ? termination resistor as close to the receiver as possi ble, as shown in figure 19. when a 1.8 v output supply voltage is used, the lvds output of the SI5335 pro duces a common-mode voltage of ~0.875 v, which does not support the lvds standard. in this case, it is best to ac-couple the output to the load. figure 19. interfacing to an lvds receiver SI5335 3.3 v or 2.5 v 50 50 v ddo x clkxa clkxb lvds lvds 100 ? keep termination close to the receiver ac-coupled lvds output 3.3 v, 2.5 v, or 1.8 v 50 50 v ddo x clkxa clkxb lvds 100 ? keep termination close to the receiver 0.1 f 0.1 f dc-coupled lvds output SI5335
SI5335 rev. 1.4 31 3.10.5. hcsl outputs host clock signal level (hcsl) outputs are commonly used in pci express applications. a typical hcsl driver has an open source output that requires an external series resistor and a resistor to ground. the SI5335 hcsl driver has integrated these resistors to simplify the interface to an hcsl receiver. no external components are necessary when connecting the SI5335 hcsl driver to an hcsl receiver. figure 20. interfacing the SI5335 to an hcsl receiver 3.10.6. cml outputs current mode logic (cml) is transmitted differentially and terminated to 50 ? to vcc as shown in figure 20. a cml receiver can be driven with either an lvpecl, cml, or lvds output. to drive a cml receiver , an si53 35 output configured in lvpecl or cml mode generates a single-ended output swing of 550 mv to 960 mv. however, to reduce power cons umption by approximatel y 15 ma per output driv er pair (compared to an lvpecl-configured output), the SI5335's cml output mode can be selected wit hout affecting the output voltage swing. for even lower power consumption, depending on the input signal swin g required, cml receivers can be driven with an SI5335 output configured in lvds mode. cml output format is not available when the SI5335 is in pll bypass (clock buffer) mode. figure 21. terminating an lvpecl or an lvds output to a cml receiver SI5335 3.3, 2.5, or 1.8 v 50 50 v ddox clkxa clkxb hcsl hcsl rs rs rt rt cml receiver vcc 50 50 50 50 lvpecl cml receiver vcc 50 50 50 50 cml or lvds 670 mv to 1070 mvp-p (cml) 250 mv to 450 mvp-p (lvds) 550 mv to 960 mvp-p SI5335 SI5335 driving a cml receiver using the lvpecl output driving a cml receiver using the cml or lvds output rb rb rb = 130 ? (2.5 v lvpecl) rb = 200 ? (3.3 v lvpecl) 0.1 f 0.1 f 0.1 f 0.1 f
SI5335 32 rev. 1.4 4. power consumption in clock generator mode, the SI5335 power consumption is a function of the following: ? supply voltage ? frequency of output clocks ? number of output clocks ? format of output clocks because of internal voltage regulation, the current from the core v dd is independent of the v dd voltage and hence the plot shown in figure 5 can be used to estimate the v dd core (pins 7 and 24) current. the current from the output supply voltages can be estimated from the values provided in table 2, ?dc characteristics,? on page 4. to get the most accurate value for v dd currents, the si5338 -evb with clockbuilder desktop software should be used. to do this, go to the ?power? tab of clockbuilder de sktop and press ?measure?. in this manner, a specific configuration can be implemented on the evb and the actual current for each supply voltage measured. when doing this it is critical that th e output drivers have the proper load impedance for the selected format. when testing for output driver current with hstl and sstl, it is required to have load circuitry as shown in "3.10.2. sstl and hstl outputs" on page 27. the si5338 evb has la yout pads that can be us ed for this purpose. when testing for output driver cu rrent with lvpecl the same la yout pads can be used to implement the lvpecl bias resistor of 130 ? (2.5 v vddx) or 200 ? (3.3 v vddx). see the schematic in the si5338-evb data sheet and an408 for additional information. figure 22. core vdd supply average current vs output frequency 30 35 40 45 50 55 60 65 70 75 80 0 50 100 150 200 250 300 350 400 typical vdd core current (ma) output frequency (mhz) 4 active outputs, fractional output ms 4 active outputs, integer output ms 3 active outputs, fractional output ms 3 active outputs, integer output ms 2 active outputs, fractional output ms 2 active outputs, integer output ms 1 active output, fractional output ms 1 active output, integer output ms
SI5335 rev. 1.4 33 5. spread spectrum to help reduce electromagnetic interf erence (emi), the SI5335 supports spread spectrum modulation in clock generator mode only. the output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system emi. spread spectrum modu lation is generated digita lly in the output multisynth dividers, which means that the spread spectrum paramete rs are virtually independent of process, voltage, and temperature variations. if the ssenb function is assig ned to a pin in clockbuilder and assert ed (driven low), pcie-compliant spread spectrum is applied to all 100 mhz output clocks with a default spreading rate of 31.5 khz and 0.5% down spread. if no 100 mhz output clocks are defined but the ssenb is assigned and asserted, none of the output clocks will have spread spectrum clocking applied. some custom spread-spectrum clocking profiles are available. if the SI5335's default pcie spread spectrum profile is not suit able for your application, submit your custom spread spectrum requirements fo r review by visiting the silicon labs technical support web page at https:// www.silabs.com/support/pages/contacttechnicalsupport.aspx , or contact your local silicon labs sales representative for more information. figure 23. spread spectrum clocking impact on output power spectrum carrier frequency reduced amplitude and emi clock with ssc off clock with ssc on (downspread) f
SI5335 34 rev. 1.4 6. jitter performance the SI5335 provides consistently low jitter for any combi nation of output frequencies. the device leverages a low phase noise single pll architecture and silicon labora tories? patented multisynth fractional output divider technology to deliver period jitter of 10 ps pk-pk (typ). the SI5335 provides superior performance to conventional multi-pll solutions which may suffer from degraded jitter performance depending on frequency plan and the number of active plls. 7. power supply considerations the SI5335 has 2 core supply voltage pins (v dd ) and 4 clock output bank supply voltage pins (v ddo0 ?v ddo3 ), enabling the device to be used in mixed supply applicatio ns. the SI5335 does not typically require ferrite beads for power supply filtering. the device has extensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter. figure 24 shows that the addi tive jitter created when a significant amount of noise is applied to the device po wer supply is very low. figure 24. peak-to-peak additive jitter from 100 mv sine wave on supply 0 1 2 3 4 5 6 7 8 9 10 0.0001 0.001 0.01 0.1 1 modulation frequency (mhz) additive jitter (ps pk-pk) vddo vdd
SI5335 rev. 1.4 35 8. loop bandwidth considerations for synchronous reference clock applications, two user-s electable loop bandwidth settings (1.6 mhz and 475 khz) are available to allow designers to optimize their timing system to support jitter atte nuation of the reference clock. in general, the 1.6 mhz setting provides the lowest outp ut jitter and should be selected for most applications. the 1.6 mhz option provides faster pll tracki ng of the input clock but less jitter a ttenuation of the input clock than the 475 khz loop bandwidth option. the 1.6 mhz loop bandwidth option must be selected for all applications which use a crystal reference input on the xa/xb pins (pins 1 and 2) and for all applications whic h provide a low jitter input clock reference to the SI5335. the 475 khz setting reduces the clock generator's loop bandwidth, which has the benefit of attenuating some of jitter that would normally pass through the 1.6 mhz setti ng. as the pll loop bandwidth decreases, the intrinsic jitter of the device increases and is reflected in higher jitter ge neration specifications, but to tal output jitter is the best measure of system performance. total output jitter includes both the generated jitter as well as the transferred jitter. this lower loop bandwidth option can be useful in some applications, such as pcie, dsl or other systems which may utilize backplane distributed refere nce clocks. in these systems, the input clock may hav e appreciable low frequency jitter (e.g., < 1.6 mhz). the so urce of the reference clock jitter can arise from suboptimal pcb trace layouts, impedance mismatches and co nnectors. input clock jitter may also be generated from an ic which has poor power supply rejection performa nce, resulting in switching power su pply noise and jitter coupling onto the clock input of the SI5335. in these applications, designe rs may opt to use the 475 khz loop bandwidth to help attenuate the input clock jitter. proper selection of pll loop bandwidth involves a number of application-specific considerations. refer to ?a n513: jitter attenuation?choosing the right phase-locked loop bandwidth? for more information. please also refer to ?an624: SI5335 solves timing cha llenges in pci express, computing, communications and fpga-based systems?.
SI5335 36 rev. 1.4 9. applications of the SI5335 because of its flexible architecture, the SI5335 can be c onfigured to serve several functions in the timing path. the following sections describe some common applications. 9.1. free-running clock generator using the internal oscillator (osc) and an inexpensive exte rnal crystal (xtal), the SI5335 can be configured as a free-running clock gene rator for replacing high-end and long-lead-time crystal oscilla tors found on many printed circuit boards (pcbs). replacing several crystal oscillators with a single ic solution helps consolidate the bill of materials (bom), reduces the number of suppliers, and reduces the number of long-lead-time components on the pcb. in addition, since crystal oscillato rs tend to be the least reliable aspect of many systems, the overall failure-in- time (fit) rate improves with th e elimination of each oscillator. up to four independent clock frequencies can be genera ted at any rate within its supported frequency range and with any of supported output types. fi gure 25 shows the SI5335 configured as a free-running clock generator. figure 25. SI5335 as a free-running clock generator 9.2. synchronous frequency translation in other cases, it is useful to genera te an output frequency that is synchro nous (or phase-locked) to another clock frequency. the SI5335 is the ideal ch oice for generating up to four clocks with different frequencies with a fixed phase relationship to an input reference. because of its highly precise frequency synthesis, the SI5335 can generate all four output frequencies with 0 ppm error to the input reference. the SI5335 is an ideal choice for applications that have traditionally required multiple stages of frequency synthesis to achieve complex frequency translations. examples are in broadcast video (e.g., 14 8.5 mhz to 148.3516483 mhz), wan/lan applications (e.g. 155.52 mhz to 156.25 mhz), and forward error corr ection (fec) applications (e.g., 156.25 mhz to 161.1328125 mhz). figure 26 shows the SI5335 configured as a synchronous clock generator. frequencies may be entered into the clo ckbuilder web utility with up to seven decimal points to ensur e that the exac t frequencies can be achieved. figure 26. SI5335 as a synchronous clock generator or frequency translator ms0 osc SI5335 f 0 f 1 f 2 f 3 xtal ms1 ms2 ms3 pll ref ms0 SI5335 f 0 f 1 f 2 f 3 ms1 ms2 ms3 pll clkin
SI5335 rev. 1.4 37 9.3. configurable universal buffer and level translator using the clockbuilder web utility, the sy nthesis stage can be entirely bypasse d allowing the SI5335 to act as a configurable clock buffer with level translation. because of its highly selectable config uration, virtually any output format and i/o voltage combination is possible. the configur able output drivers allow four differential outputs, eight single-ended outputs, or a combination of both. figure 27 shows the SI5335 configured as a flexible clock buffer supporting mixed i/o supplies. figure 27. SI5335 as a configurable clock buffer with level translation SI5335 clkin 3.3 v lvds 2.5 v cmos 1.8 v lvpecl 3.3 v hcsl
SI5335 38 rev. 1.4 10. pin descriptions note: center pad must be tied to gnd for normal operation. table 15. SI5335 pin descriptions pin # pin name i/o signal type description 1,2 xa/clkin, xb/clkinb imulti xa/clkin, xb/clkinb. these pins are used as the main differential or single-ended clock input or as the xtal input. see "3.4. input configuration" on page 19 and figures 10, 11, and 12 for connection details. clock inputs to these pins must be ac-coupled. keep the traces from pins 1,2 to the crystal as short as possible and keep other signals and radiat- ing sources away from the crystal. the single-ended input voltage swing must be limited to 1.2 vpp. 3p3 imulti multi-function input. 3.3 v tolerant. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb0, oeb1, oeb2, oeb3, ssenb, or reset) is user-selectable at time of config uration using the clockbuilder web configuration utility. 4 gnd gnd gnd ground. must be connected to system gr ound for proper device operation. 5,6 p5, p6 i multi multi-function input. these pins function as multi-func tion input pins. the pin functions (oeb_all, oeb0, oeb1, oeb2, oeb3, or ssenb) are user- selectable at time of configuration using the clockbuilder configu- ration utility. a resistor voltage divider is re quired when driven by a signal greater than 1.2 v. see "3.6.1. p5 and p6 input control" on page 24 for details. 7 vdd vdd supply core supply voltage. this is the core supply voltage, which can operate from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. xa/clkin clk2b clk2a vddo2 vddo1 clk1b clk1a vdd vdd p1 clk3a clk3b los p2 vddo0 clk0b clk0a rsvd_gnd vddo3 gnd gnd pad 5 4 3 2 1 6 13 10 9 8 7 p3 gnd p5 p6 top view 11 12 15 14 16 17 18 19 20 21 22 23 24 xb/clkinb
SI5335 rev. 1.4 39 8 los o open drain loss of signal. a typical pullup resistor of 1?4 k ? is used on this pin. this pin can be pulled up to a supply voltage as high as 3.6 v regardless of the other supply voltages on pins 7, 11, 15, 16, 20, and 24. the los condition allows the pull up resist or to pull the output up to the supply voltage. see "3.9. loss-of-signal alarm" on page 25. this pin functions as an input clock loss-of-signal and pll lock status pin in clock generator mode: 0 = input clock present and pll locked. 1 = input clock not present or pll not locked. in clock buffer mode, los is asserted when the input clock is not present. 9 clk3b o multi output clock b for channel 3. may be a single-ended output or half of a differential output with clk3a being the other differential half. if unused, leave this pin floating. 10 clk3a o multi output clock a for channel 3. may be a single-ended output or half of a differential output with clk3b being the other differential half. if unused, leave this pin floating. 11 vddo3 vdd supply output clock supply voltage. supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk3a,b. a 0.1 f capacitor must be located very close to this pin. if clk3 is not used, this pin must be tied to vdd (pin 7, 24). 12 p1 i multi multi-function input. 3.3 v tolerant. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb0, oeb1, oeb2, o eb3, ssenb, fs0, fs1, or reset) is user-selectable at time of configuration using the clock- builder web configuration utility 13 clk2b o multi output clock b for channel 2. may be a single-ended output or half of a differential output with clk2a being the other differential half. if unused, leave this pin floating. 14 clk2a o multi output clock a for channel 2. may be a single-ended output or half of a differential output with clk2b being the other differential half. if unused, leave this pin floating. 15 vddo2 vdd supply output clock supply voltage. supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk2a,b. a 0.1 f capacitor must be located ve ry close to this pin. if clk2 is not used, this pin must be tied to vdd (pin 7, 24). 16 vddo1 vdd supply output clock supply voltage. supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk1a,b. a 0.1 f capacitor must be located ve ry close to this pin. if clk1 is not used, this pin must be tied to vdd (pin 7, 24). table 15. SI5335 pin descriptions (continued) pin # pin name i/o signal type description
SI5335 40 rev. 1.4 17 clk1b o multi output clock b for channel 1. may be a single-ended output or half of a differential output with clk1a being the other differential half. if unused, leave this pin floating. 18 clk1a o multi output clock a for channel 1. may be a single-ended output or half of a differential output with clk1b being the other differential half. if unused, leave this pin floating. 19 p2 i multi multi-function input. 3.3 v tolerant. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb0, oeb1, oeb2, o eb3, ssenb, fs1, or reset) is user-selectable at time of co nfiguration using the clockbuilder web configuration utility. 20 vddo0 vdd supply output clock supply voltage. supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk0a,b. a 0.1 f capacitor must be located ve ry close to this pin. if clk0 is not used, this pin must be tied to vdd (pin 7, 24). 21 clk0b o multi output clock b for channel 0. may be a single-ended output or half of a differential output with clk0a being the other differential half. if unused, leave this pin floating. 22 clk0a o multi output clock a for channel 0. may be a single-ended output or half of a differential output with clk0b being the other differential half. if unused, leave this pin floating. 23 rsvd_gnd gnd gnd ground. must be connected to system gr ound. minimize the ground path impedance for optimal performance of this device. 24 vdd vdd supply core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be lo cated very close to this pin. gnd pad gnd gnd gnd ground pad. this is the large pad in the cent er of the package. the device will not function unless the ground p ad is properly connected to a ground plane on the pcb. see table 17, ?pcb land pattern,? on page 43 for ground via requirements. table 15. SI5335 pin descriptions (continued) pin # pin name i/o signal type description
SI5335 rev. 1.4 41 11. ordering information SI5335x bxxxxx gmr b = product revision b xxxxx = nvm code. custom nvm configuration code. a unique 5-digit ordering code will be assigned by the clockbuilder web utility . operating temp range: -40 to +85 c package: 4 x 4 mm qfn, rohs6, pb-free r = tape & reel (ordering option) non tape & reel shipment media is trays frequency/configuration: SI5335a - 1 mhz to 350 mhz output with xtal input SI5335b - 1 mhz to 200 mhz output with xtal input SI5335c - 1 mhz to 350 mhz output with differential/single-ended input clock SI5335d - 1 mhz to 200 mhz output with differential/single-ended input clock si5338 evb evaluation boards SI5335 evaluation board the si5338-evb with clockbuilder desktop software includes the ability to evaluate si 5335 output frequency and format configurations. the evb does not currently include the ability to control the programmable function pins (p1, p2, p3, p5, and p6).
SI5335 42 rev. 1.4 12. package outline: 24-lead qfn figure 28. 24-lead quad flat no-lead (qfn) table 16. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 4.00 bsc. d2 2.35 2.50 2.65 e 0.50 bsc. e 4.00 bsc. e2 2.35 2.50 2.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the je dec/ipc j-std-020 specif ication for small body components. 5. terminal base alloy: cu 6. terminal plating/grid array material: au/nipd. 7. visit www.silabs.com/support/quality/ pages/rohsinfo rmation.aspx for more information.
SI5335 rev. 1.4 43 13. recommended pcb land pattern table 17. pcb land pattern dimension min nom max p1 2.50 2.55 2.60 p2 2.50 2.55 2.60 x1 0.20 0.25 0.30 y1 0.75 0.80 0.85 c1 3.90 c2 3.90 e0.50 notes general: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. connect the center ground pad to a ground plane with no less than five vias. these 5 vias should have a length of no more than 20 mils to the ground plane. via drill size should be no smaller than 10 mils. a longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing. solder mask design: 5. all metal pads are to be non-solder mask defined (nsmd). cl earance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 6. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. a 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly: 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components.
SI5335 44 rev. 1.4 14. top marking 14.1. SI5335 top marking 14.2. top marking explanation line characters description line 1 SI5335 base part number. line 2 xxxxxx x = frequency and configuration code. see "11. ordering information" on page 41 for more information. xxxxx = nvm code assigned by clockbuilder web utility. see "11. ordering information" on page 41. line 3 rttttt r = product revision. ttttt = manufacturing trace code. line 4 circle with 0.5 mm diameter; left-justified pin 1 indicator. yyww yy = year. ww = work week. characters correspond to the year and work week of package assem- bly. yyww rttttt xxxxxx SI5335
SI5335 rev. 1.4 45 15. device errata please visit www.silabs.com to access the device errata document.
SI5335 46 rev. 1.4 d ocument c hange l ist revision 0.4 to revision 0.9 ? updated table 2, ?dc characteristics,? on page 4. ?? added core power supply specification in buffer mode. ? updated table 3, ?performance characteristics,? on page 5. ?? added t reset specification. ? updated table 4, ?input and output clock characteristics,? on page 6. ?? corrected v i on pin 1 to 1.3 v (max). ?? updated cml output voltage specification to 0.86 vpp. ? updated table 6, ?crystal specifications for 25 mhz,? on page 9. ?? corrected cl to 18 pf (typical). ? updated table 7, ?crystal specifications for 27 mhz,? on page 9. ?? corrected cl to 18 pf (typical). ? updated "3.4. input configuration" on page 19. ?? revised text in section 3.4.2. ? updated "3.6.1. p5 and p6 input control" on page 24. ?? added figure 13 to replace table 15. ? updated figure 21 on page 31. ? updated table 14 on page 23. ?? corrected assignable pin name column entries. ? updated "3.10. output stage" on page 26. ?? revised throughout and included termination circuit diagrams and text. ? removed references to p4 as a programmable pin option throughout document. pin 4 is now a ground pin. revision 0.9 to revision 1.0 ? updated table 9 on page 12. ?? dsl random jitter from 2.1 ps rms (typ) to 1.95 ps rms (typ) and from "?" (max) to 2.2 ps rms (max). ? corrected text in ?9.2. synchronous frequency translation? to match the capabilities of the clockbuilder web utility. revision 1.0 to revision 1.1 ? updated table 8 on page 10 and table 9 on page 12. ?? updated typical specifications for total jitter for pci express 1.1 common clocked topology. ?? updated typical specificatio ns for rms jitter for pci express 2.1 common clocked topology. ? updated table 10 on page 14. ?? updated typical additive jitter (12 khz?20mhz) from 0.150 to 0.165 ps rms. ? added " document change list" on page 46. revision 1.1 to revision 1.2 ? removed down spread spectrum errata that has been corrected in revision b. ? updated ordering information to refer to revision b silicon. ? updated top marking expl anation in section 14.2. revision 1.2 to revision 1.3 ? added link to errata document. revision 1.3 to revision 1.4 ? updated features on page 1. ? updated description on page 1. ? updated specs in table 8. ? updated specs in table 9.
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