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| 8 bit microcontroller tlcs-870/c1 series tmp89fh46l
? 2009 toshiba corporation all rights reserved revision history date revision 2008/2/14 1 first release 2008/9/3 2 contents revised 2009/7/23 3 contents revised table of contents tmp89fh46l 1.1 features ...................................................................................................................................... 1 1.2 pin assignment .......................................................................................................................... 3 1.3 block diagram ........................................................................................................................... 4 1.4 pin names and functions .......................................................................................................... 5 2. cpu core 2.1 configuration ............................................................................................................................. 9 2.2 memory space ............................................................................................................................ 9 2.2.1 code area ............................................................................................................................................................................. 9 2.2.1.1 ram 2.2.1.2 bootrom 2.2.1.3 flash 2.2.2 data area ............................................................................................................................................................................ 13 2.2.2.1 sfr 2.2.2.2 ram 2.2.2.3 bootrom 2.2.2.4 flash 2.3 system clock controller ........................................................................................................... 16 2.3.1 configuration ..................................................................................................................................................................... 16 2.3.2 control ............................................................................................................................................................................... 16 2.3.3 functions ............................................................................................................................................................................18 2.3.3.1 clock generator 2.3.3.2 clock gear 2.3.3.3 timing generator 2.3.4 warm-up counter ............................................................................................................................................................... 21 2.3.4.1 warm-up counter operation when the oscillation is enabled by the hardware 2.3.4.2 warm-up counter operation when the oscillation is enabled by the software 2.3.5 operation mode control circuit .......................................................................................................................................... 23 2.3.5.1 single-clock mode 2.3.5.2 dual-clock mode 2.3.5.3 stop mode 2.3.5.4 transition of operation modes 2.3.6 operation mode control .................................................................................................................................................... 28 2.3.6.1 stop mode 2.3.6.2 idle1/2 and sleep1 modes 2.3.6.3 idle0 and sleep0 modes 2.3.6.4 slow mode 2.4 reset control circuit ............................................................................................................... 39 2.4.1 configuration ..................................................................................................................................................................... 39 2.4.2 control ............................................................................................................................................................................... 39 2.4.3 functions ............................................................................................................................................................................41 2.4.4 reset signal generating factors ........................................................................................................................................ 43 2.4.4.1 power-on reset 2.4.4.2 external reset input (reset pin input) 2.4.4.3 voltage detection reset 2.4.4.4 watchdog timer reset 2.4.4.5 system clock reset 2.4.4.6 trimming data reset 2.4.4.7 flash standby reset 2.4.4.8 internal factor reset detection status register 2.4.4.9 how to use the external reset input pin as a port 2.5 revision history ...................................................................................................................... 47 i 3. interrupt control circuit 3.1 configuration ........................................................................................................................... 51 3.2 interrupt latches (il25 to il3) ................................................................................................52 3.3 interrupt enable register (eir) ............................................................................................... 53 3.3.1 interrupt master enable flag (imf) .................................................................................................................................... 53 3.3.2 individual interrupt enable flags (ef25 to ef4) ................................................................................................................ 53 3.4 maskable interrupt priority change function ......................................................................... 56 3.5 interrupt sequence ................................................................................................................... 58 3.5.1 initial setting ......................................................................................................................................................................58 3.5.2 interrupt acceptance processing ......................................................................................................................................... 58 3.5.3 saving/restoring general-purpose registers ........................................................................................................................ 59 3.5.3.1 using push and pop instructions 3.5.3.2 using data transfer instructions 3.5.3.3 using a register bank to save/restore general-purpose registers 3.5.4 interrupt return ................................................................................................................................................................... 61 3.6 software interrupt (intsw) ....................................................................................................62 3.6.1 address error detection ...................................................................................................................................................... 62 3.6.2 debugging .......................................................................................................................................................................... 62 3.7 undefined instruction interrupt (intundef) ....................................................................... 62 4. external interrupt control circuit 4.1 configuration ........................................................................................................................... 63 4.2 control ..................................................................................................................................... 63 4.3 function ................................................................................................................................... 67 4.3.1 low power consumption function ..................................................................................................................................... 68 4.3.2 external interrupt 0 ............................................................................................................................................................ 68 4.3.3 external interrupts 1/2/3 .................................................................................................................................................... 69 4.3.3.1 interrupt request signal generating condition detection function 4.3.3.2 a noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.3.3 noise cancel time selection function 4.3.4 external interrupt 4 ............................................................................................................................................................ 70 4.3.4.1 interrupt request signal generating condition detection function 4.3.4.2 a noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.4.3 noise cancel time selection function 4.3.5 external interrupt 5 ............................................................................................................................................................ 72 5. watchdog timer (wdt) 5.1 configuration ........................................................................................................................... 73 5.2 control ..................................................................................................................................... 74 5.3 functions ..................................................................................................................................76 5.3.1 setting of enabling/disabling the watchdog timer operation ............................................................................................. 76 5.3.2 setting the clear time of the 8-bit up counter .....................................................................................................................76 5.3.3 setting the overflow time of the 8-bit up counter .............................................................................................................. 77 5.3.4 setting an overflow detection signal of the 8-bit up counter ............................................................................................. 77 5.3.5 writing the watchdog timer control codes ......................................................................................................................... 78 5.3.6 reading the 8-bit up counter .............................................................................................................................................. 78 5.3.7 reading the watchdog timer status .................................................................................................................................... 78 6. power-on reset circuit 6.1 configuration ........................................................................................................................... 81 ii 6.2 function ................................................................................................................................... 81 7. voltage detection circuit 7.1 configuration ........................................................................................................................... 83 7.2 control ..................................................................................................................................... 84 7.3 function ................................................................................................................................... 85 7.3.1 enabling/disabling the voltage detection operation ........................................................................................................... 85 7.3.2 selecting the voltage detection operation mode ................................................................................................................ 85 7.3.3 selecting the detection voltage level ................................................................................................................................. 86 7.3.4 voltage detection flag and voltage detection status flag ................................................................................................... 86 7.4 register settings ...................................................................................................................... 88 7.4.1 setting procedure when the operation mode is set to generate intvltd interrupt request signals ................................ 88 7.4.2 setting procedure when the operation mode is set to generate voltage detection reset signals ......................................... 88 7.5 revision history ...................................................................................................................... 90 8. i/o ports 8.1 i/o port control registers ....................................................................................................... 93 8.2 list of i/o port settings ........................................................................................................... 94 8.3 i/o port registers .................................................................................................................... 97 8.3.1 port p0 (p03 to p00) .......................................................................................................................................................... 97 8.3.2 port p1 (p13 to p10) ........................................................................................................................................................ 101 8.3.3 port p2 (p27 to p20) ........................................................................................................................................................ 105 8.3.4 port p4 (p47 to p40) ........................................................................................................................................................ 109 8.3.5 port p7 (p77 to p70) ........................................................................................................................................................ 112 8.3.6 port p8 (p83 to p80) ........................................................................................................................................................ 114 8.3.7 port p9 (p91 to p90) ........................................................................................................................................................ 116 8.3.8 port pb (pb7 to pb4) ...................................................................................................................................................... 119 8.4 serial interface selecting function ........................................................................................ 122 8.5 revision history .................................................................................................................... 125 9. special function registers 9.1 sfr1 (0x0000 to 0x003f) ..................................................................................................... 127 9.2 sfr2 (0x0f00 to 0x0fff) .....................................................................................................128 9.3 sfr3 (0x0e40 to 0x0eff) .................................................................................................... 130 10. low power consumption function for peripherals 10.1 control ................................................................................................................................. 134 11. divider output ( dvo ) 11.1 configuration .......................................................................................................................137 11.2 control ................................................................................................................................. 138 11.3 function ............................................................................................................................... 139 iii 12. time base timer (tbt) 12.1 time base timer ................................................................................................................. 141 12.1.1 configuration ................................................................................................................................................................. 141 12.1.2 control ........................................................................................................................................................................... 141 12.1.3 functions ........................................................................................................................................................................142 13. 16-bit timer counter (tca) 13.1 configuration ....................................................................................................................... 146 13.2 control ................................................................................................................................. 147 13.3 low power consumption function ..................................................................................... 152 13.4 timer function .................................................................................................................... 153 13.4.1 timer mode .................................................................................................................................................................... 153 13.4.1.1 setting 13.4.1.2 operation 13.4.1.3 auto capture 13.4.1.4 register buffer configuration 13.4.2 external trigger timer mode ........................................................................................................................................... 157 13.4.2.1 setting 13.4.2.2 operation 13.4.2.3 auto capture 13.4.2.4 register buffer configuration 13.4.3 event counter mode ....................................................................................................................................................... 159 13.4.3.1 setting 13.4.3.2 operation 13.4.3.3 auto capture 13.4.3.4 register buffer configuration 13.4.4 window mode ................................................................................................................................................................ 161 13.4.4.1 setting 13.4.4.2 operation 13.4.4.3 auto capture 13.4.4.4 register buffer configuration 13.4.5 pulse width measurement mode .................................................................................................................................... 163 13.4.5.1 setting 13.4.5.2 operation 13.4.5.3 capture process 13.4.6 programmable pulse generate (ppg) mode ................................................................................................................... 166 13.4.6.1 setting 13.4.6.2 operation 13.4.6.3 register buffer configuration 13.5 noise canceller ....................................................................................................................169 13.5.1 setting ............................................................................................................................................................................ 169 13.6 revision history .................................................................................................................. 170 14. 8-bit timer counter (tc0) 14.1 configuration ....................................................................................................................... 172 14.2 control ................................................................................................................................. 173 14.2.1 timer counter 00 ............................................................................................................................................................173 14.2.2 timer counter 01 ............................................................................................................................................................175 14.2.3 common to timer counters 00 and 01 ............................................................................................................................177 14.2.4 operation modes and usable source clocks ................................................................................................................... 179 14.3 low power consumption function ..................................................................................... 180 14.4 functions ..............................................................................................................................181 14.4.1 8-bit timer mode .............................................................................................................................................................181 14.4.1.1 setting 14.4.1.2 operation 14.4.1.3 double buffer iv 14.4.2 8-bit event counter mode ............................................................................................................................................... 184 14.4.2.1 setting 14.4.2.2 operation 14.4.2.3 double buffer 14.4.3 8-bit pulse width modulation (pwm) output mode ....................................................................................................... 186 14.4.3.1 setting 14.4.3.2 operations 14.4.3.3 double buffer 14.4.4 8-bit programmable pulse generate (ppg) output mode ............................................................................................... 191 14.4.4.1 setting 14.4.4.2 operation 14.4.4.3 double buffer 14.4.5 16-bit timer mode ...........................................................................................................................................................195 14.4.5.1 setting 14.4.5.2 operations 14.4.5.3 double buffer 14.4.6 16-bit event counter mode ............................................................................................................................................. 199 14.4.6.1 setting 14.4.6.2 operations 14.4.6.3 double buffer 14.4.7 12-bit pulse width modulation (pwm) output mode ..................................................................................................... 201 14.4.7.1 setting 14.4.7.2 operations 14.4.7.3 double buffer 14.4.8 16-bit programmable pulse generate (ppg) output mode ............................................................................................. 207 14.4.8.1 setting 14.4.8.2 operations 14.4.8.3 double buffer 14.5 revision history .................................................................................................................. 211 15. real time clock (rtc) 15.1 configuration ....................................................................................................................... 213 15.2 control ................................................................................................................................. 213 15.3 function ............................................................................................................................... 214 15.3.1 low power consumption function ............................................................................................................................... 214 15.3.2 enabling/disabling the real time clock operation .......................................................................................................... 214 15.3.3 selecting the interrupt generation interval ..................................................................................................................... 214 15.4 real time clock operation ................................................................................................. 215 15.4.1 enabling the real time clock operation .......................................................................................................................... 215 15.4.2 disabling the real time clock operation ......................................................................................................................... 215 16. asynchronous serial interface (uart) 16.1 configuration ....................................................................................................................... 218 16.2 control ................................................................................................................................. 219 16.3 low power consumption function ..................................................................................... 223 16.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed ....... 224 16.5 activation of stop, idle0 or sleep0 mode ................................................................... 225 16.5.1 transition of register status ............................................................................................................................................225 16.5.2 transition of txd pin status ......................................................................................................................................... 225 16.6 transfer data format ........................................................................................................... 226 16.7 infrared data format transfer mode .................................................................................. 226 16.8 transfer baud rate .............................................................................................................. 227 16.8.1 transfer baud rate calculation method ...........................................................................................................................228 16.8.1.1 bit width adjustment using uart0cr2 16.11.1 data transmit operation ................................................................................................................................................ 234 16.11.2 data receive operation ................................................................................................................................................. 234 16.12 status flag ......................................................................................................................... 235 16.12.1 parity error ................................................................................................................................................................... 235 16.12.2 framing error .............................................................................................................................................................. 236 16.12.3 overrun error ............................................................................................................................................................... 237 16.12.4 receive data buffer full ............................................................................................................................................. 240 16.12.5 transmit busy flag ...................................................................................................................................................... 241 16.12.6 transmit buffer full .................................................................................................................................................... 241 16.13 receiving process .............................................................................................................. 242 16.14 ac properties .....................................................................................................................244 16.14.1 irda properties ............................................................................................................................................................ 244 17. synchronous serial interface (sio) 17.1 configuration ....................................................................................................................... 246 17.2 control ................................................................................................................................. 247 17.3 low power consumption function ..................................................................................... 250 17.4 functions ..............................................................................................................................251 17.4.1 transfer format .............................................................................................................................................................. 251 17.4.2 serial clock .................................................................................................................................................................... 251 17.4.3 transfer edge selection .................................................................................................................................................. 251 17.5 transfer modes .................................................................................................................... 253 17.5.1 8-bit transmit mode ........................................................................................................................................................ 253 17.5.1.1 setting 17.5.1.2 starting the transmit operation 17.5.1.3 transmit buffer and shift operation 17.5.1.4 operation on completion of transmission 17.5.1.5 stopping the transmit operation 17.5.2 8-bit receive mode ........................................................................................................................................................258 17.5.2.1 setting 17.5.2.2 starting the receive operation 17.5.2.3 operation on completion of reception 17.5.2.4 stopping the receive operation 17.5.3 8-bit transmit/receive mode ........................................................................................................................................... 262 17.5.3.1 setting 17.5.3.2 starting the transmit/receive operation 17.5.3.3 transmit buffer and shift operation 17.5.3.4 operation on completion of transmission/reception 17.5.3.5 stopping the transmit/receive operation 17.6 ac characteristics ............................................................................................................... 267 18. serial bus interface (sbi) 18.1 communication format ....................................................................................................... 270 18.1.1 i2c bus ........................................................................................................................................................................... 270 18.1.2 free data format ............................................................................................................................................................. 271 18.2 configuration ....................................................................................................................... 272 18.3 control ................................................................................................................................. 273 18.4 functions ..............................................................................................................................276 18.4.1 low power consumption function ............................................................................................................................... 276 18.4.2 selecting the slave address match detection and the general call detection .......................................................276 18.4.3 selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode ...... 276 18.4.3.1 number of clocks for data transfer 18.4.3.2 output of an acknowledge signal 18.4.4 serial clock .................................................................................................................................................................... 278 18.4.4.1 clock source 18.4.4.2 clock synchronization 18.4.5 master/slave selection .................................................................................................................................................... 280 vi 18.4.6 transmitter/receiver selection ........................................................................................................................................280 18.4.7 start/stop condition generation ...................................................................................................................................... 280 18.4.8 interrupt service request and release .............................................................................................................................. 281 18.4.9 setting of serial bus interface mode ............................................................................................................................... 282 18.4.10 software reset .............................................................................................................................................................. 282 18.4.11 arbitration lost detection monitor ................................................................................................................................282 18.4.12 slave address match detection monitor ....................................................................................................................... 284 18.4.13 general call detection monitor .......................................................................................................................... 284 18.4.14 last received bit monitor ............................................................................................................................................. 285 18.4.15 slave address and address recognition mode specification ......................................................................................... 285 18.5 data transfer of i2c bus ..................................................................................................... 286 18.5.1 device initialization ....................................................................................................................................................... 286 18.5.2 start condition and slave address generation ................................................................................................................. 286 18.5.3 1-word data transfer ....................................................................................................................................................... 287 18.5.3.1 when sbi0sr2 21.3.1 byte program ................................................................................................................................................................. 324 21.3.2 sector erase (4-kbyte partial erase) ................................................................................................................................ 325 21.3.3 chip erase (all erase) ......................................................................................................................................................325 21.3.4 product id entry .............................................................................................................................................................325 21.3.5 product id exit ............................................................................................................................................................... 326 21.3.6 security program ............................................................................................................................................................326 21.4 toggle bit (d6) ....................................................................................................................326 21.5 access to the flash memory area ....................................................................................... 327 21.5.1 flash memory control in serial prom mode ................................................................................................................ 327 21.5.1.1 how to transfer and write a control program to the ram area in ram loader mode of the serial prom mode 21.5.2 flash memory control in mcu mode ............................................................................................................................ 330 21.5.2.1 how to write to the flash memory by transferring a control program to the ram area 21.5.2.2 how to write to the flash memory by using a support program (api) of bootrom 21.5.2.3 how to set the security program by using a support program (api) of bootrom 21.5.2.4 how to read data from flash memory 21.6 api (application programming interface) .......................................................................... 338 21.6.1 . btwrite ........................................................................................................................................................................ 339 21.6.2 . bterasesec ................................................................................................................................................................... 339 21.6.3 . bterasechip ................................................................................................................................................................. 339 21.6.4 . btgetsp ....................................................................................................................................................................... 339 21.6.5 . btsetsp ........................................................................................................................................................................ 339 21.6.6 . btcalcuart ............................................................................................................................................................... 340 21.7 revision history .................................................................................................................. 342 22. serial prom mode 22.1 outline ................................................................................................................................. 343 22.2 security ................................................................................................................................ 343 22.3 serial prom mode setting ................................................................................................. 344 22.3.1 serial prom mode control pins .................................................................................................................................... 344 22.4 example connection for on-board writing ........................................................................ 346 22.5 activating the serial prom mode ......................................................................................347 22.6 interface specifications ....................................................................................................... 348 22.6.1 sio communication ....................................................................................................................................................... 348 22.6.2 uart communication ................................................................................................................................................... 348 22.7 memory mapping ................................................................................................................ 349 22.8 operation commands .......................................................................................................... 349 22.8.1 flash memory erase command (0xf0) ...........................................................................................................................352 22.8.1.1 specifying the erase area 22.8.2 flash memory write command (operation command: 0x30) ......................................................................................... 355 22.8.3 flash memory read command (operation command: 0x40) .......................................................................................... 357 22.8.4 ram loader command (operation command: 0x60) ..................................................................................................... 359 22.8.5 flash memory sum output command (operation command: 0x90) ............................................................................. 361 22.8.6 product id code output command (operation command: 0xc0) ................................................................................... 362 22.8.7 flash memory status output command (0xc3) .............................................................................................................. 364 22.8.7.1 flash memory status code 22.8.8 mask rom emulation setting command (0xd0) .......................................................................................................... 367 22.8.9 flash memory security setting command (0xfa) ..........................................................................................................368 22.9 error code ........................................................................................................................... 369 22.10 checksum (sum) .............................................................................................................. 370 22.10.1 calculation method ...................................................................................................................................................... 370 22.10.2 calculation data ........................................................................................................................................................... 370 22.11 intel hex format (binary) ................................................................................................. 371 22.12 security .............................................................................................................................. 372 22.12.1 passwords .....................................................................................................................................................................372 22.12.1.1 how a password can be specified 22.12.1.2 password structure 22.12.1.3 password setting, cancellation and authentication 22.12.1.4 password values and setting range 22.12.2 security program ..........................................................................................................................................................376 22.12.2.1 how the security program functions viii 22.12.2.2 enabling or disabling the security program 22.12.3 option codes ................................................................................................................................................................ 377 22.12.4 recommended settings ................................................................................................................................................ 379 22.13 flowchart ........................................................................................................................... 380 22.14 ac characteristics (uart) .............................................................................................. 381 22.14.1 reset timing ................................................................................................................................................................. 382 22.14.2 flash memory erase command (0xf0) .........................................................................................................................382 22.14.3 flash memory write command (0x30) ......................................................................................................................... 383 22.14.4 flash memory read command (0x40) .......................................................................................................................... 383 22.14.5 ram loader command (0x60) ..................................................................................................................................... 384 22.14.6 flash memory sum output command (0x90) ............................................................................................................. 384 22.14.7 product id code output command (0xc0) ................................................................................................................... 384 22.14.8 flash memory status output command (0xc3) ............................................................................................................ 385 22.14.9 mask rom emulation setting command (0xd0) ........................................................................................................ 385 22.14.10 flash memory security setting command (0xfa) ......................................................................................................385 22.15 revision history ................................................................................................................ 386 23. on-chip debug function (ocd) 23.1 features ................................................................................................................................ 387 23.2 control pins ......................................................................................................................... 387 23.3 how to connect the on-chip debug emulator to a target system .................................... 389 23.4 security ................................................................................................................................ 389 24. input/output circuit 24.1 control pins ......................................................................................................................... 391 25. electrical characteristics 25.1 absolute maximum ratings ............................................................................................... 393 25.2 operating conditions ........................................................................................................... 394 25.2.1 mcu mode (flash programming or erasing) ................................................................................................................ 394 25.2.2 mcu mode (except flash programming or erasing) .................................................................................................... 395 25.2.3 serial prom mode ........................................................................................................................................................ 396 25.3 dc characteristics .............................................................................................................. 397 25.4 ad conversion characteristics .......................................................................................... 400 25.5 power-on reset circuit characteristics ............................................................................... 401 25.6 voltage detecting circuit characteristics ........................................................................... 402 25.7 ac characteristics ............................................................................................................... 403 25.7.1 mcu mode (flash programming or erasing) ................................................................................................................ 403 25.7.2 mcu mode (except flash programming or erasing) .................................................................................................... 403 25.7.3 serial prom mode ........................................................................................................................................................ 404 25.8 flash characteristics ........................................................................................................... 404 25.8.1 write characteristics ...................................................................................................................................................... 404 25.9 oscillating condition ........................................................................................................... 405 25.10 handling precaution .......................................................................................................... 405 25.11 revision history ................................................................................................................ 406 26. package dimensions ix x cmos 8-bit microcontroller tmp89fh46l the tmp89fh46l is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of flash memory. product no. rom (flash) ram package emulation chip TMP89FH46LDUG 16384 bytes 2048 bytes lqfp48-p-0707-0.50d * tmp89c900xbg note : * ; under development 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c1 series - instruction execution time : 238 ns (at 4.2 mhz) 122 s (at 32.768 khz) - 133 types & 732 basic instructions 2. 25 interrupt sources (external : 6 internal : 19 , except reset) 3. input / output ports (42 pins) note : two of above pins can not be used for the i/o port, because they should be connected with the high frequency osc input. - large current output: 8 pins (typ. 6ma) 4. watchdog timer - interrupt or reset can be selected by the program. 5. power-on reset circuit 6. voltage detection circuit 7. divider output function 8. time base timer 9. 16-bit timer counter (tca) : 2 ch - timer, external trigger, event counter, window, pulse width measurement, ppg output modes 10. 8-bit timer counter (tc0) : 4 ch - timer, event counter, pwm, ppg output modes - usable as a 16-bit timer, 12-bit pwm output and 16-bit ppg output by the cascade connection of two channels. 11. real time clock 12. uart : 1ch 13. uart/sio : 1ch note : one sio channel can be used at the same time. 14. i 2 c/sio : 1ch 15. key-on wake-up : 8 ch 16. 10-bit successive approximation type ad converter - analog input : 8ch 17. on-chip debug function - break/event this product uses the super flash? technology under the licence of silicon storage technology, inc. super flash? is registered trademark of silicon storage technology, inc. tmp89fh46l page 1 ra000 - trace - ram monitor - flash memory writing 18. clock operation mode control circuit : 2 circuit single clock mode / dual clock mode 19. low power consumption operation (8 mode) - stop mode: oscillation stops. (battery/capacitor back-up.) - slow1 mode: low power consumption operation using low-frequency clock.(high-frequency clock stop.) - slow2 mode: low power consumption operation using low-frequency clock.(high-frequency clock oscillate.) - idle0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using high frequency clock. released when the reference time set to tbt has elapsed. - idle1 mode: the cpu stops, and peripherals operate using high frequency clock. release by interruputs(cpu restarts). - idle2 mode: cpu stops and peripherals operate using high and low frequency clock. release by interruputs. (cpu restarts). - sleep0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using low frequency clock. released when the reference time set to tbt has elapsed. - sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interruput.(cpu restarts). 20. wide operation voltage: 2.7 v to 3.6 v at 4.2mhz /32.768 khz 2.2 v to 3.6 v at 2 mhz /32.768 khz tmp89fh46l 1.1 features page 2 ra000 1.2 pin assignment p91 (rxd1/txd1) p90 (txd1/rxd1) p77 (int4) p76 (int3) p75 (int2) p74 ( dvo) p47 (ain7/kwi7) p46 (ain6/kwi6) p45 (ain5/kwi5) p44 (ain4/kwi4) p43 (ain3/kwi3) p42 (ain2/kwi2) ( pwm02/ ppg02/tc02) p80 p41 (ain1/kwi1) ( pwm03/ ppg03/tc03) p81 p40 (ain0/kwi0) p82 varef p83 avdd ( pwm00/ ppg00/tc00) p70 avss ( pwm01/ ppg01/tc01) p71 p27 ( ppga0/tca0) p72 p26 ( ppga1/tca1) p73 p25 (sclk0) (so0/rxd0/txd0) pb4 p24 (scl0/si0) (si0/txd0/rxd0) pb5 p23 (sda0/so0) (sclk0) pb6 p22 (sclk0) pb7 p21 (rxd0/txd0/si0/ocdio) vss (xin) p00 (xout) p01 mode vdd (xtin) p02 (xtout) p03 ( reset) p10 ( stop/ int5) p11 ( int0) p12 (int1) p13 (ocdck/so0/rxd0/txd0) p20 figure 1-1 pin assignment tmp89fh46l page 3 ra000 1.3 block diagram figure 1-2 block diagram tmp89fh46l 1.3 block diagram page 4 ra000 1.4 pin names and functions the tmp89fh46l has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin func- tions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions (1/3) pin name input/output functions p03 xtout io o port03 low frequency osc output p02 xtin io i port02 low frequency osc input p01 xout io o port01 high frequency osc output p00 xin io i port00 high frequency osc input p13 int1 io i port13 external interrupt 1 input p12 int0 io i port12 external interrupt 0 input p11 int5 stop io i i port11 external interrupt 5 input stop mode release input p10 reset io i port10 reset signal input p27 io port27 p26 io port26 p25 sclk0 io io port25 serial clock input/output 0 p24 scl0 si0 io io i port24 i2c bus clock input/output 0 serial data input 0 p23 sda0 so0 io io o port23 i2c bus data input/output 0 serial data output 0 p22 sclk0 io io port22 serial clock input/output 0 p21 rxd0 txd0 si0 ocdio io i o i io port21 uart data input 0 uart data output 0 serial data input 0 ocd data input/output p20 txd0 rxd0 so0 ocdck io o i o i port20 uart data output 0 uart data input 0 serial data output 0 ocd clock input tmp89fh46l page 5 ra000 table 1-2 pin names and functions (2/3) pin name input/output functions p47 ain7 kwi7 io i i port47 analog input 7 key-on wake-up input 7 p46 ain6 kwi6 io i i port46 analog input 6 key-on wake-up input 6 p45 ain5 kwi5 io i i port45 analog input 5 key-on wake-up input 5 p44 ain4 kwi4 io i i port44 analog input 4 key-on wake-up input 4 p43 ain3 kwi3 io i i port43 analog input 3 key-on wake-up input 3 p42 ain2 kwi2 io i i port42 analog input 2 key-on wake-up input 2 p41 ain1 kwi1 io i i port41 analog input 1 key-on wake-up input 1 p40 ain0 kwi0 io i i port40 analog input 0 key-on wake-up input 0 p77 int4 io i port77 external interrupt 4 input p76 int3 io i port76 external interrupt 3 input p75 int2 io i port75 external interrupt 2 input p74 dvo io o port74 divider output p73 tca1 ppga1 io i o port73 tca1 input ppga1 output p72 tca0 ppga0 io i o port72 tca0 input ppga0 output p71 tc01 ppg01 pwm01 io i o o port71 tc01 input ppg01 output pwm01 output tmp89fh46l 1.4 pin names and functions page 6 ra000 table 1-2 pin names and functions (3/3) pin name input/output functions p70 tc00 ppg00 pwm00 io i o o port70 tc00 input ppg00 output pwm00 output p83 io port83 p82 io port82 p81 tc03 ppg03 pwm03 io i o o port81 tc03 input ppg03 output pwm03 output p80 tc02 ppg02 pwm02 io i o o port80 tc02 input ppg02 output pwm02 output p91 rxd1 txd1 io i o port91 uart data input 1 uart data output 1 p90 txd1 rxd1 io o i port90 uart data output 1 uart data input 1 pb7 io portb7 pb6 sclk0 io io portb6 serial clock input/output 0 pb5 rxd0 txd0 si0 io i o i portb5 uart data input 0 uart data output 0 serial data input 0 pb4 txd0 rxd0 so0 io o i o portb4 uart data output 0 uart data input 0 serial data output 0 mode i test pin for out-going test (fix to low level). varef i analog reference voltage input pin for a/d conversion. avdd i analog power supply pin. avss i analog gnd pin vdd i vdd pin vss i gnd pin tmp89fh46l page 7 ra000 tmp89fh46l 1.4 pin names and functions page 8 ra000 2. cpu core 2.1 configuration the cpu core consists of a cpu, a system clock controller and a reset circuit. this chapter describes the cpu core address space, the system clock controller and the reset circuit. 2.2 memory space the 870/c1 cpu memory space consists of a code area to be accessed as instruction operation codes and operands and a data area to be accessed as sources and destinations of transfer and calculation instructions. both the code and data areas have independent 64-kbyte address spaces. 2.2.1 code area the code area stores operation codes, operands, vector tables for vector call instructions and interrupt vector tables. the ram, the bootrom and the flash are mapped in the code area. 0x0000 swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. 0x003f 0x0040 ram (2048 bytes) ram (2048 bytes) 0x083f swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. 0x1000 bootrom (2048 bytes) bootrom (2048 bytes) 0x17ff 0x1800 0xbfff 0xc000 flash (16384 bytes) flash (16384 bytes) flash (16384 bytes) flash (16384 bytes) 0xffa0 vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) 0xffbf 0xffcc interrupt vector table (52 bytes) interrupt vector table (52 bytes) interrupt vector table (52 bytes) interrupt vector table (52 bytes) 0xffff immediately after re- set release when the ram is mapped in the code area when the boot- rom is mapped in the code area when the ram and the bootrom are mapped in the code area figure 2-1 memory map in the code area note: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. tmp89fh46l page 9 rb000 2.2.1.1 ram the ram is mapped in the data area immediately after reset release. by setting syscr3 system control status register 4 syssr4 (0x0fdf) 7 6 5 4 3 2 1 0 bit symbol - - - - - rvctrs rareas (rstdis) read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 rareas status of mapping of the ram in the code area 0 : 1 : the enabled syscr3 register. this means that a register setting value does not take effect until "0xd5" is written to the register flscr2. the value of the shift register can be checked by reading the register flscrm. flash memory control register 2 flscr2 7 6 5 4 3 2 1 0 (0x0fd1) bit symbol cr1en read/write w after reset * * * * * * * * cr1en flscr1 register enable/disable control 0xd5 others enable a change in the flscr1 setting reserved 2.2.1.3 flash the flash is mapped to 0xc000 to 0xffff in the code area after reset release. tmp89fh46l 2. cpu core 2.2 memory space page 12 rb000 2.2.2 data area the data area stores the data to be accessed as sources and destinations of transfer and calculation instructions. the sfr, the ram, the bootrom and the flash are mapped in the data area. 0x0000 sfr1 (64 bytes) sfr1 (64 bytes) 0x003f 0x0040 ram (2048 bytes) ram (2048 bytes) 0x083f 0xff is read 0xff is read 0x0e40 sfr3 (192 bytes) sfr3 (192 bytes) 0x0eff 0x0f00 sfr2 (256 bytes) sfr2 (256 bytes) 0x0fff 0x1000 bootrom (2048 bytes) 0x17ff 0x1800 0xff is read 0xff is read 0xbfff 0xc000 flash (16384 bytes) flash (16384 bytes) 0xffff immediately after re- set release when the boot- rom is mapped in the data area figure 2-2 memory map in the data area note: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. 2.2.2.1 sfr the sfr is mapped to 0x0000 to 0x003f (sfr1), 0x0f00 to 0x0fff (sfr2) and 0x0e40 to 0x0eff (sfr3) in the data area after reset release. note:don't access the reserved sfr. 2.2.2.2 ram the ram is mapped to 0x0040 to 0x083f in the data area after reset release. note: the contents of the ram become unstable when the power is turned on and immediately after a reset is released. to execute the program by using the ram, transfer the program to be executed in the initialization routine. tmp89fh46l page 13 rb000 example: ram initialization program ld hl, ram_top_address ; head of address of the ram to be initialized ld a, 0x00 ; initialization data ld bc, byte_of_clear_bytes ; number of bytes of ram to be initialized -1 clr_ram: ld (hl), a ; initialization of the ram inc hl ; initialization address increment dec bc ; have all the rams been initialized? j f, clr_ram 2.2.2.3 bootrom the bootrom is not mapped in the code area or the data area after reset release. setting flscr1 2.2.2.4 flash the flash is mapped to 0xc000 to 0xffff in the data area after reset release. tmp89fh46l page 15 rb000 2.3 system clock controller 2.3.1 configuration the system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up counter and an operation mode control circuit. figure 2-3 system clock controller 2.3.2 control the system clock controller is controlled by system control register 1 (syscr1), system control register 2 (syscr2), the warm-up counter control register (wuccr), the warm-up counter data register (wucdr) and the clock gear control register (cgcr). system control register 1 syscr1 (0x0fdc) 7 6 5 4 3 2 1 0 bit symbol stop relm outen dv9ck - - - - read/write r/w r/w r/w r/w r r r r after reset 0 0 0 0 1 0 0 0 stop activates the stop mode 0 : 1 : operate the cpu and the peripheral circuits stop the cpu and the peripheral circuits (activate the stop mode) relm selects the stop mode release method 0 : edge-sensitive release mode (release the stop mode at the rising edge of the stop mode release signal) 1 : level-sensitive release mode (release the stop mode at the "h" level of the stop mode release signal) outen selects the port output state in the stop mode 0 : 1 : high impedance output hold dv9ck selects the input clock to stage 9 of the divider 0 : 1 : fcgck/2 9 fs/4 note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: bits 2, 1 and 0 of syscr1 are read as "0". bit 3 is read as "1". note 3: if the stop mode is activated with syscr1 note 4: the p11 pin is also used as the stop pin. when the stop mode is activated, the pin reverts to high impedance state and is put in input mode, regardless of the state of syscr1 warm-up counter data register wucdr (0x0fce) 7 6 5 4 3 2 1 0 bit symbol wucdr read/write r/w after reset 0 1 1 0 0 1 1 0 wucdr warm-up time setting note 1: don't start the warm-up counter operation with wucdr set at "0x00". clock gear control register cgcr (0x0fcf) 7 6 5 4 3 2 1 0 bit symbol - - - - - - fcgcksel read/write r r r r r r r/w after reset 0 0 0 0 0 0 0 0 fcgcksel clock gear setting 00 : 01 : 10 : 11 : fcgck = fc / 4 fcgck = fc / 2 fcgck = fc reserved note 1: fcgck: gear clock [hz], fc: high-frequency clock [hz] note 2: don't change cgcr the hardware control is executed by reset release and the operation mode control circuit when the operation is switched to the stop mode as described in "2.3.5 operation mode control circuit". note: no hardware function is available for external direct monitoring of the basic clock. the oscillation fre- quency can be adjusted by programming the system to output pulses at a certain frequency to a port (for example, a clock output) with interrupts disabled and the watchdog timer disabled and monitoring the output. an adjustment program must be created in advance for a system that requires adjustment of the oscillation frequency. to prevent the dead lock of the cpu core due to the software-controlled enabling/disabling of the oscil- lation, an internal factor reset is generated depending on the combination of values of the clock selected as the main system clock, syscr2 table 2-2 gear clock (fcgck) cgcr these circuits divide fcgck. the divided clocks are supplied to the timer counter, the time base timer and other peripheral circuits. when both syscr1 when the power is turned on and the supply voltage exceeds the power-on reset release voltage, the warm-up counter reset signal is released. at this time, the cpu and the peripheral circuits are held in the reset state. a reset signal initializes wuccr 2.3.4.2 warm-up counter operation when the oscillation is enabled by the software the warm-up counter serves to secure the time after the oscillation is enabled by the software before the oscillation becomes stable, at a mode change from normal1 to normal2 or from slow1 to slow2. select the input clock to the frequency division circuit at wuccr in the single-clock mode, the low-frequency clock generation circuit pins p02 (xtin) and p03 (xtout) can be used as the i/o ports. (1) normal1 mode in this mode, the cpu core and the peripheral circuits operate using the gear clock (fcgck). the normal1 mode becomes active after reset release. (2) idle1 mode in this mode, the cpu and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck). the idle1 mode is activated by setting syscr2 the main system clock (fm) is generated from the gear clock (fcgck) in the normal2 or idle2 mode, and generated from the clock that is a quarter of the low-frequency clock (fs) in the slow1/2 or sleep0/1 mode. therefore, the machine cycle time is 1/fcgck [s] in the normal2 or idle2 mode and is 4/fs [s] in the slow1/2 or sleep0/1 mode. p02 (xtin) and p03 (xtout) are used as the low-frequency clock oscillation circuit pins. (these pins cannot be used as i/o ports in the dual-clock mode.) the operation of the tlcs-870/c1 series becomes the single-clock mode after reset release. to operate it in the dual-clock mode, allow the low-frequency clock to oscillate at the beginning of the program. (1) normal2 mode in this mode, the cpu core operates using the gear clock (fcgck), and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). (2) slow2 mode in this mode, the cpu core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). in the slow mode, some peripheral circuits become the same as the states when a reset is released. for operations of the peripheral circuits in the slow mode, refer to the section of each peripheral circuit. set syscr2 (5) sleep1 mode in this mode, the high-frequency clock oscillation circuit stops operation, the cpu and the watchdog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). in the sleep1 mode, some peripheral circuits become the same as the states when a reset is released. for operations of the peripheral circuits in the sleep1 mode, refer to the section of each peripheral circuit. the sleep1 mode can be activated and released in the same way as for the idle1 mode. the operation returns to the slow1 mode after this mode is released. in the slow1 or sleep1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (6) sleep0 mode in this mode, the high-frequency clock oscillation circuit stops operation, the time base timer operates using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral circuits stop. in the sleep0 mode, the peripheral circuits stop in the states when the sleep0 mode is activated or become the same as the states when a reset is released. for operations of the peripheral circuits in the sleep0 mode, refer to the section of each peripheral circuit. the sleep0 mode can be activated and released in the same way as for the idle0 mode. the operation returns to the slow1 mode after this mode is released. in the sleep0 mode, the cpu stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer. 2.3.5.3 stop mode in this mode, all the operations in the system, including the oscillation circuits, are stopped and the internal states in effect before the system was stopped are held with low power consumption. in the stop mode, the peripheral circuits stop in the states when the stop mode is activated or become the same as the states when a reset is released. for operations of the peripheral circuits in the stop mode, refer to the section of each peripheral circuit. the stop mode is activated by setting syscr1 2.3.5.4 transition of operation modes note 1: the normal1 and normal2 modes are generically called the normal mode; the slow1 and slow2 modes are called the slow mode; the idle0, idle1 and idle2 modes are called the idle mode; and the sleep0 and sleep1 are called the sleep mode. note 2: the mode is released by the falling edge of the source clock selected at tbtcr table 2-3 operation modes and conditions operation mode oscillation circuit cpu core watchdog timer time base timer ad converter other periph- eral circuits machine cy- cle time high-fre- quency low-fre- quency single clock reset oscillation stop reset reset reset reset reset 1 / fcgck [s] normal1 operate operate operate operate operate idle1 stop stop idle0 stop stop stop stop stop ? dual clock normal2 oscillation oscillation operate with the high fre- quency operate with the high / low frequency operate operate operate 1 / fcgck [s] idle2 stop stop slow2 operate with the low fre- quency operate with the low fre- quency stop 4/ fs [s] slow1 stop operate with the low fre- quency operate with the low fre- quency sleep1 stop stop sleep0 stop stop stop stop ? 2.3.6 operation mode control 2.3.6.1 stop mode the stop mode is controlled by system control register 1 (syscr1) and the stop mode release signals. (1) start the stop mode the stop mode is started by setting syscr1 note: during the stop period (from the start of the stop mode to the end of the warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after the stop mode is released. before starting the stop mode, therefore, disable interrupts. also, before enabling interrupts after stop mode is released, clear unnecessary interrupt latches. 1. release by the stop pin release the stop mode by using the stop pin. the stop mode release by the stop pin includes the level-sensitive release mode and the edge-sensitive release mode, either of which can be selected at syscr1 note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr the stop mode is released by inputting the prescribed level to the key-on wakeup pin. the level to release the stop mode can be selected from "h" and "l". for release by the key-on wakeup, refer to section "key-on wakeup". note: if the key-on wakeup pin input becomes the opposite level to the release level after the warm-up starts, the stop mode is not restarted. 3. release by the voltage detection circuits the stop mode is released by the supply voltage detection by the voltage detection circuits. if the voltage detection operation mode of the voltage detection circuits is set to "generates a voltage detection reset signal", the stop mode is released and a reset is applied as soon as the supply voltage becomes lower than the detection voltage. when the supply voltage becomes equal to or higher than the detection voltage of the voltage detection circuits, the reset is released and the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. for details, refer to the section of the voltage detection circuits. note: if the supply voltage becomes equal to or higher than the detection voltage within 1 ma- chine cycle after syscr1 note: when the operation returns to the normal2 mode, fc is input to the frequency division circuit of the warm-up counter. 2.3.6.2 idle1/2 and sleep1 modes the idle1/2 and sleep1 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following states are maintained during these modes. 1. the cpu and the watchdog timer stop their operations. the peripheral circuits continue to operate. 2. the data memory, the registers, the program status word and the port output latches are all held in the status in effect before idle1/2 or sleep1 mode was started. 3. the program counter holds the address of the instruction 2 ahead of the instruction which starts the idle1/2 or sleep1 mode. figure 2-10 idle1/2 and sleep 1 modes tmp89fh46l 2. cpu core 2.3 system clock controller page 32 rb000 cpu and wdt stop interrupt processing reset yes no no no no imf = "1" reset input yes yes (interrupt release mode) (normal release mode) interrupt request starting idle1/2 mode or sleep1 mode by an instruction execution of the instruction which follows the idle1/2 mode or sleep1 mode start instruction (1) start the idle1/2 and sleep1 modes after the interrupt master enable flag (imf) is set to "0", set the individual interrupt enable flag (ef) to "1", which releases idle1/2 and sleep1 modes. to start the idle1/2 or sleep1 mode, set syscr2 figure 2-11 idle0 and sleep0 modes ? start the idle0 and sleep0 modes stop (disable) the peripherals such as a timer counter. to start the idle0 or sleep0 mode, set syscr2 (1) normal release mode (imf, ef5, tbtcr figure 2-12 switching of the main system clock (fm) (switching from fcgck to fs/4) example 1: switching from the normal2 mode to the slow1 mode (when fc is used as the basic clock for the high- frequency clock) set (syscr2).4 ; syscr2 vintwuc: dw pintwuc ; intwuc vector table (2) switching from the slow1 mode to the normal1 mode set syscr2 set (eirl). 4 ; enables intwuc interrupts set (syscr2) .6 ; syscr2 2.4 reset control circuit the reset circuit controls the external and internal factor resets and initializes the system. 2.4.1 configuration the reset control circuit consists of the following reset signal generation circuits: 1. external reset input (external factor) 2. power-on reset (internal factor) 3. voltage detection reset 1 (internal factor) 4. voltage detection reset 2 (internal factor) 5. watchdog timer reset (internal factor) 6. system clock reset (internal factor) 7. trimming data reset (internal factor) 8. flash standby reset (internal factor) figure 2-14 reset control circuit 2.4.2 control the reset control circuit is controlled by system control register 3 (syscr3), system control register 4 (syscr4), system control status register (syssr4) and the internal factor reset detection status register (irstsr). system control register 3 syscr3 (0x0fde) 7 6 5 4 3 2 1 0 bit symbol - - - - - (rvctr) (rarea) rstdis read/write r r r r r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 rstdis external reset input enable register 0 : 1 : enables the external reset input. disables the external reset input. note 1: the enabled syscr3 note 3: after syscr3 internal factor reset detection status register irstsr (0x0fcc) 7 6 5 4 3 2 1 0 bit symbol fclr flsrf trmds trmrf lvd2rf lvd1rf sysrf wdtrf read/write w r r r r r r r after reset 0 0 0 0 0 0 0 0 fclr flag initialization control 0 : 1 : - clears the internal factor reset flag to "0". flsrf flash standby reset detection flag 0 : 1 : - detects the flash standby reset. trmds trimming data status 0 : 1 : - detect state of abnormal trimming data trmrf trimming data reset detection flag 0 : 1 : - detects the trimming data reset. lvd2rf voltage detection reset 2 detection flag 0 : 1 : - detects the voltage detection 2 reset. lvd1rf voltage detection reset 1 detection flag 0 : 1 : - detects the voltage detection 1 reset. sysrf system clock reset detection flag 0 : 1 : - detects the system clock reset. wdtrf watchdog timer reset detection flag 0 : 1 : - detects the watchdog timer reset. note 1: internal reset factor flag (irstsr table 2-5 initialization of built-in hardware by reset operation and its status after release built-in hardware during reset during the warm-up opera- tion that follows reset re- lease immediately after the warm-up operation that fol- lows reset release program counter (pc) mcu mode: 0xfffe serial prom mode: 0x1ffe mcu mode: 0xfffe serial prom mode: 0x1ffe mcu mode: 0xfffe serial prom mode: 0x1ffe stack pointer (sp) 0x00ff 0x00ff 0x00ff ram indeterminate indeterminate indeterminate general-purpose registers (w, a, b, c, d, e, h, l, ix and iy) indeterminate indeterminate indeterminate register bank selector (rbs) 0 0 0 jump status flag (jf) indeterminate indeterminate indeterminate zero flag (zf) indeterminate indeterminate indeterminate carry flag (cf) indeterminate indeterminate indeterminate half carry flag (hf) indeterminate indeterminate indeterminate sign flag (sf) indeterminate indeterminate indeterminate overflow flag (vf) indeterminate indeterminate indeterminate interrupt master enable flag (imf) 0 0 0 individual interrupt enable flag (ef) 0 0 0 interrupt latch (il) 0 0 0 high-frequency clock oscillation circuit oscillation enabled oscillation enabled oscillation enabled low-frequency clock oscillation circuit oscillation disabled oscillation disabled oscillation disabled warm-up counter reset start stop timing generator prescaler and divider 0 0 0 watchdog timer disabled disabled enabled voltage detection circuit disabled or enabled disabled or enabled disabled or enabled i/o port pin status hiz hiz hiz special function register refer to the sfr map. refer to the sfr map. refer to the sfr map. note:the voltage detection circuits are disabled by an external reset input or power-on reset only. tmp89fh46l 2. cpu core 2.4 reset control circuit page 42 rb000 2.4.4 reset signal generating factors reset signals are generated by each factor as follows: 2.4.4.1 power-on reset the power-on reset is an internal reset that occurs when power is turned on. during power-up, a power-on reset signal is generated while the supply voltage is below the power-on reset release voltage. when the supply voltage rises above the power-on reset release voltage, the power-on reset signal is released. during power-down, a power-on reset signal is generated when the supply voltage falls below the power- on reset detection voltage. refer to "power-on reset circuit". 2.4.4.2 external reset input ( reset pin input) this is an external reset that is generated by the reset pin input. port p10 is also used as the reset pin, and it is configured as the reset pin at power-up. ? during power-up - when the supply voltage rises rapidly when the power supply rise time (t vdd ) is shorter than 5 [ms] with enough margin, the reset can be released by a power-on reset or an external reset ( reset pin input). the power-on reset logic and external reset ( reset pin input) logic are ored. this means that the tmp89fh46l is reset when either or both of these reset sources are asserted. therefore, the reset time is determined by the reset source with a longer reset period. if the reset pin level changes from low to high before the supply voltage rises above the power-on-reset release voltage (v proff ) (or if the reset pin level is high from the be- ginning), the reset time depends on the power-on reset. if the reset pin level changes from low to high after the supply voltage rises above v proff , the reset time depends on the external reset. in the former case, a warm-up period begins when the power-on reset signal is released. in the latter case, a warm-up period begins when the reset pin level becomes high. upon completion of the warm-up period, the cpu and peripheral circuits start operating (figure 2-15). - when the supply voltage rises slowly when the power supply rise time (t vdd ) is longer than 5 [ms], the reset must be released by using the reset pin. in this case, hold the reset pin low until the supply voltage rises to the operating voltage range and oscillation is stabilized. when this state is achieved, wait at least 5 [s] and then pull the reset pin high. changing the reset pin level to high starts a warm-up period. upon completion of the warm-up period, the cpu and peripheral circuits start operating (figure 2-15). tmp89fh46l page 43 rb000 figure 2-15 external reset input (during power-up) tmp89fh46l 2. cpu core 2.4 reset control circuit page 44 rb000 operating voltage range v proff t vdd reset pin warm-up period (t pwup ) when the supply voltage rises rapidly (when the reset time depends on external reset) cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset operating voltage range v proff 5 s or more t vdd reset pin warm-up period (t pwup ) when the supply voltage rises slowly cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset operating voltage range v proff t vdd reset pin warm-up period (t pwup ) when the supply voltage rises rapidly (when the reset time depends on power-on reset) cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset ? when the supply voltage is within the operating voltage range when the supply voltage is within the operating voltage range and stable oscillation is achieved, holding the reset pin low for 5 [ s] or longer generates a reset. then, changing the reset pin level to high starts a warm-up period. upon completion of the warm-up period, the cpu and peripheral circuits start operating (figure 2-16). figure 2-16 external reset input (when the power supply is stable) 2.4.4.3 voltage detection reset the voltage detection reset is an internal factor reset that occurs when it is detected that the supply voltage has reached a predetermined detection voltage. refer to "voltage detection circuit". 2.4.4.4 watchdog timer reset the watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer is detected. refer to "watchdog timer". 2.4.4.5 system clock reset the system clock reset is an internal factor reset that occurs when it is detected that the oscillation enable register is set to a combination that puts the cpu into deadlock. refer to "clock control circuit". 2.4.4.6 trimming data reset the trimming data reset is an internal factor reset that occurs when the trimming data latched in the internal circuit is broken down during operation due to noise or other factors. the trimming data is a data bit provided for adjustment of the ladder resistor that generates the comparison voltage for the power-on reset and the voltage detection circuits. this bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows reset release (tpwup) and latched into the internal circuit. if the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation that follows reset release is abnormal, irstsr when irstsr 2.5 revision history rev description ra002 "table 2-3 operation modes and conditions" added ad converter condition. "(2) release the stop mode" added new example program and note to level-sensitive release mode. ra003 "table 2-3 operation modes and conditions" revised character code error. "table 2-3 operation modes and conditions" added ad converter condition. "(2) release the stop mode" added new example program. ra004 "2.3.6 operation mode control" revised register name from vdcr2 tmp89fh46l 2. cpu core 2.5 revision history page 48 rb000 3. interrupt control circuit the tmp89fh46l has a total of 25 interrupt sources excluding reset. interrupts can be nested with priorities. three of the internal interrupt sources are non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il), which hold interrupt requests, and have independent vector addresses. when a request for an interrupt is generated, its interrupt latch is set to "1", which requests the cpu to accept the interrupt. acceptance of interrupts is enabled or disabled by software using the interrupt master enable flag (imf) and individual enable flag (ef) for each interrupt source. if multiple maskable interrupts are generated simul- taneously, the interrupts are accepted in order of descending priority. the priorities are determined by the interrupt priority change control register (ilprs1-ilprs6) as levels and determined by the hardware as the basic priorities. however, there are no prioritized interrupt sources among non-maskable interrupts. interrupt sources enable condition interrupt latch vector address (mcu mode) basic priori- ty rvctr=0 enabled rvctr=1 enabled internal/ex- ternal (reset) non-maskable - 0xfffe - 1 internal intswi non-maskable - 0xfffc 0x01fc 2 internal intundef non-maskable - 0xfffc 0x01fc 2 internal intwdt non-maskable ill |