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S6J3200 series 32 - bit microcontroller traveo ? family cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 05682 rev.*a revised april 22, 2016 the traveo mcu family S6J3200 features 32 - bit risc microcontrollers with an arm ? cortex ? - r5 core and operates up to 240mhz. this microcontroller comes with highly - efficient 2d/3d graphic engines with advanced feature - sets for memory savings, safety and high image quality to help manufacturers take advantage of the lower overall system costs while meeting the increasingly high levels of performance and quality that industrial, consu mer and automotive applications demand. in addition, this microcontroller offers support for cypress hyperbus tm memory interface, a breakthrough that dramatically improves read performance while reducing the number of pins. this microcontroller comes with ethernet avb, can - fd, a high - speed communication protocol compatible with the conventional can, and she (secure hardware extension) as security function. features ? system ? 32bit arm cortex - r5f cpu core at up to 240mhz ? general purpose i/o port up to 120 ? 12 - bit a/d converter up to 50 channels ? external interrupt up to 16 channels ? base timer up to 24 channels ? 32 - bit free - run timer up to 12 channels ? built - in cr oscillators ? real - time clock ? input capture unit up to 24 channels ? output compare unit up to 24 channels ? dma controller 16 channels ? stepper motor controller (smc): 6 units ? jtag debug interface ? graphics and display ? 2d graphic engine ? 3d graphic engine (optional) ? timing generator - tcon ? ttl/rsds ? fpd - link C lvds (optional) ? video capture (optional) ? communication: ethernet avb mac (optional) ? can - fd up to 4 channels ? multi - function serial interface up to 12 channels, select able protocol: uart, csio, lin and i2c ? medialb : up to 1 channel (optio nal) ? memory ? cypress hyperbus? memory interface ? dual quad double data rate spi flash interface ? multimedia ? i2s input/output: up to 2 units ? pcm to pwm output unit ? sound mixer (optional): 1 unit x 10 inputs (optional) ? stereo audio dac (optional) ? security and safety ? secure hardware extension - she ? safety features, such as mpu, tpu, ecc and others ? crc generator: 1 channel ? watchdog timer with window function ? low voltage detector ? clock supervisor for all source clocks
document number: 002 - 05682 rev.*a page 2 of 179 S6J3200 series table of contents features ................................ ................................ ................................ ................................ ................................ ................... 1 1. overview ................................ ................................ ................................ ................................ ................................ ............ 4 1.1 document definition ................................ ................................ ................................ ................................ ...................... 4 2. function list ................................ ................................ ................................ ................................ ................................ ..... 5 2.1 function list ................................ ................................ ................................ ................................ ................................ .. 5 2.2 optional function ................................ ................................ ................................ ................................ .......................... 8 2.2.1 basic option ................................ ................................ ................................ ................................ ................................ ... 8 2.2.2 id ................................ ................................ ................................ ................................ ................................ ................. 10 2.2.3 restriction ................................ ................................ ................................ ................................ ................................ .... 11 3. product description ................................ ................................ ................................ ................................ ........................ 13 3.1 overview ................................ ................................ ................................ ................................ ................................ ..... 13 3.2 product desc ription ................................ ................................ ................................ ................................ ..................... 13 3.2.1 ethernet ................................ ................................ ................................ ................................ ................................ ....... 18 4. package and pin assignment ................................ ................................ ................................ ................................ ........ 19 4.1 pin assignment ................................ ................................ ................................ ................................ ........................... 19 4.1.1 teqf p - 216 pin assignment ................................ ................................ ................................ ................................ ........ 20 4.1.2 teqpf - 208 pin assignment ................................ ................................ ................................ ................................ ........ 27 4.1.3 teqpf - 256 pin assignment ................................ ................................ ................................ ................................ ........ 34 4.2 package dimensions ................................ ................................ ................................ ................................ ................... 35 4.2.1 teqfp216 ................................ ................................ ................................ ................................ ................................ ... 36 4.2.2 teqfp208 ................................ ................................ ................................ ................................ ................................ ... 37 5. i/o circuit type ................................ ................................ ................................ ................................ ................................ 39 5.1 i/o circuit type ................................ ................................ ................................ ................................ ........................... 39 5.2 note ................................ ................................ ................................ ................................ ................................ ............. 46 6. port description ................................ ................................ ................................ ................................ .............................. 47 6.1 port description list ................................ ................................ ................................ ................................ .................... 47 6.2 remark ................................ ................................ ................................ ................................ ................................ ........ 64 7. precautions and handling devices ................................ ................................ ................................ ............................... 65 7.1 handling precautions ................................ ................................ ................................ ................................ .................. 65 7.1.1 precautions for product design ................................ ................................ ................................ ................................ .... 65 7.1.2 precautions for package mounting ................................ ................................ ................................ .............................. 66 7.1.3 precautions for use environment ................................ ................................ ................................ ................................ . 67 7.2 handling devices ................................ ................................ ................................ ................................ ........................ 68 8. electric characteristics ................................ ................................ ................................ ................................ .................. 70 8.1 absolute maximum rating ................................ ................................ ................................ ................................ ........... 70 8.2 operation assurance condition ................................ ................................ ................................ ................................ ... 74 8.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 79 8.3.1 port function characteristics ................................ ................................ ................................ ................................ ....... 79 8.3.2 power supply current ................................ ................................ ................................ ................................ .................. 86 8. 4 ac characteristics ................................ ................................ ................................ ................................ ....................... 91 8.4.1 source clock timing ................................ ................................ ................................ ................................ .................... 91 8.4.2 sub clock timing ................................ ................................ ................................ ................................ ......................... 92 8.4.3 internal clock timing ................................ ................................ ................................ ................................ ................... 93 8.4.4 reset input ................................ ................................ ................................ ................................ ................................ ... 98 8.4. 5 power - on conditions ................................ ................................ ................................ ................................ ................... 98 8.4.6 multi - function serial ................................ ................................ ................................ ................................ .................... 99 8.4.7 timer input ................................ ................................ ................................ ................................ ................................ . 114 8.4.8 trigger input ................................ ................................ ................................ ................................ ............................... 115
document number: 002 - 05682 rev.*a page 3 of 179 S6J3200 series 8.4.9 nmi input ................................ ................................ ................................ ................................ ................................ ... 116 8.4.10 low - v oltage detection ................................ ................................ ................................ ................................ ............... 117 8.4.11 high current output slew rate ................................ ................................ ................................ ................................ .. 123 8.4.12 display controller ................................ ................................ ................................ ................................ ....................... 124 8.4.13 video capture ................................ ................................ ................................ ................................ ............................ 127 8.4.14 fpd - link (lvds) ................................ ................................ ................................ ................................ ....................... 128 8.4.15 ddr - hsspi ................................ ................................ ................................ ................................ ............................... 131 8.4.16 hyperbus ................................ ................................ ................................ ................................ ................................ ... 135 8.4.17 ethernet avb ................................ ................................ ................................ ................................ ............................. 139 8.4.18 medialb ................................ ................................ ................................ ................................ ................................ ..... 142 8.4.19 port noise filter ................................ ................................ ................................ ................................ ......................... 144 8. 5 a/d converter ................................ ................................ ................................ ................................ ............................ 145 8.5.1 electrical characteristics ................................ ................................ ................................ ................................ ............ 145 8.5.2 notes on a/d converters ................................ ................................ ................................ ................................ ........... 146 8.5.3 glossary ................................ ................................ ................................ ................................ ................................ ..... 146 8.5.4 calibration condition ................................ ................................ ................................ ................................ .................. 146 8.6 audio dac ................................ ................................ ................................ ................................ ................................ . 149 8.6.1 electrical characteristics ................................ ................................ ................................ ................................ ............ 149 8.7 flash memory ................................ ................................ ................................ ................................ ............................ 152 8.7.1 electrical characteristics ................................ ................................ ................................ ................................ ............ 152 8.7.2 notes ................................ ................................ ................................ ................................ ................................ .......... 152 9. abbreviation ................................ ................................ ................................ ................................ ................................ .. 153 10. ordering information ................................ ................................ ................................ ................................ .................... 155 11. major changes ................................ ................................ ................................ ................................ .............................. 156 11.1 suppl ementary information ................................ ................................ ................................ ................................ ....... 156 document history ................................ ................................ ................................ ................................ ............................... 178 sales, solutions, and legal information ................................ ................................ ................................ ........................... 179
document number: 002 - 05682 rev.*a page 4 of 179 S6J3200 series 1. o verview 1.1 documen t definition t he related documents of S6J3200 are the followings. table 1 - 1 document type definition primary user document code datasheet t he function and its characteristics are specified quantitatively. investigator and hardware engineer 002 - 05682 revision (previous: ds708 - 00003 - revision ) S6J3200 hardware manual t he function and its operation of S6J3200 series are described. software engineer mn708 - 00005 - revision traveo tm platform hardware manual the function and its operation of cpu core platform are described. software engineer mn708 - 00006 - revision supplementary information for datasheet supplementary information for document such as difference with previous revision. datasheet user. in this documen t supplementary information for hardware manual supplementary information for document such as difference with previous revision. hardware manual user. mn708 - 00005 - revision - e - si a pplication note t he reference software, sample application, the reference board design and so on are explained. software and hardware engineer under consideration notes: ? r efer all documents for the system development. ? "primary user" is a most likely engineer for whom the document is the most useful. ? t he description of the dat asheet and the S6J3200 hardware manual should precede the duplicated description of traveo platform hardware manual. ? traveo platform hardware manual is expected to be used as dictionary of platform specification. ? document code usually includes its revision . ? revise information from the previous revision can be seen the supplementary information.
document number: 002 - 05682 rev.*a page 5 of 179 S6J3200 series 2. function list 2.1 function list the table shows the functions which are implemented in S6J3200 series. table 2 - 1 function description remark cpu core arm cortex r5f fpu available (double precision and single precision) ppu available mpu available tpu available endian little endian core clock frequency option see 2.2.1 and ac specification on the datasheet. hpm bus frequency option see ac specification on the datasheet resource clock frequency option see ac specification on the datasheet embedded cr oscillation slow clock:100khz, fast clock: 4mhz (center frequency) see ac specification on the datasheet pll pll0, 1, 2, 3 sscg pll sscg0, 1, 2, 3 clock supervisor available dma 16 ch boot - rom 16 kbyte s jtag available data cache 16kbytes instruction cache 16kbytes program flash option see 2.2.1 work flash 112kbytes tc - ram option see 2.2.1 system - ram 128kbytes backup - ram 16kbytes security (she) option see 2.2.1 low latency interrupt available power domain 5 domains power supply 5v +/ - 0.5v, 3.3v +/ - 0.3v, 1.2v +/ - 0.1v embedded ldo power supply for 5.0v available low - voltage detection of external power supply available low - voltage detection of internal ldo output available hardware watchdog timer available software watchdog timer available package option see 2.2.1 autosar autosar 4.0.3 general purpose i/o option see 2.2.3 quad position & revolution counter (up/down counter) 2 ch i/o timer 3 unit x 8 ch 32bit reload timer 14 ch real time clock available a utomatic calibration sound generator 4 ch sound waveform generator option 1 unit x 5 outputs see 2.2.1
document number: 002 - 05682 rev.*a page 6 of 179 S6J3200 series function description remark sound mixer option 1 unit x 10 inputs see 2.2.1 stereo audio dac option 1 unit (l and r) see 2 .2.1 pcm - pwm option 1 unit (l and r) see 2.2.1 base timer 12 units (24ch) free - run timer 12 ch input capture unit 12 unit (24channels of capture) output compare unit 12unit (24 channels of compare match) stepping motor controller (smc) for 6 gauges 12bit - a/d converter option 1 unit x 50 input ports (max) see 2.2.3 crc 1 unit programmable crc 1 unit source clock timer 4 ch nmi available external interrupt 16 ch internal interrupt 512 vectors i2s 2 ch o ne only supports an output as a function of the sound system. ddr hsspi 2 ch a type of quad spi hyperbus (rpc2) option s ee 2.2.1 see ac specification on the datasheet. multi - function serial interface 12 ch can - fd 4 ch can - fd ram (ecc supported) 16kb/ch i t equivalent s to 128 message buffer per channel of ccan module ethernet avb option s ee 2.2.1 media - lb (most25) option see 2.2.1 lcd controller option 4com x 32 seg (max) see 2.2.3 i ndicator pwm 1 ch mpu for ahb 1 unit mpu for axi 1 unit internal vram option see 2.2.1 graphic engine clock option see 2.2.1 graphic axi clock op tion see 2.2.1 display clock option 80mhz (ch.0), 50mhz(ch.1) see 2.2.1 display clock source graphic display controller clock or external clock t arget frame rate 60 fps number of display outputs option maximum 2 outputs simultaneously see 2.2.1 ttl output (rgb888) option see 2.2.1 rsds/tcon support 1 output fpd - link (lvds) option 1 output, 350mbps (max) see 2.2.1 video capture unit option see 2.2.1 video capture format itu656 , ycbcr4:4:4, ycbcr4:2:2 , rgb888, rgb666 2d graphic engine 1 unit 2.5d support a vailable vector drawing on 2d engine available warping available scale/rotate/blend available 2d driver api cypress proprietary
document number: 002 - 05682 rev.*a page 7 of 179 S6J3200 series function description remark 3d graphic engine option see 2.2.1 vector drawing on 3d engine option see 2.2.1 3d driver api option see 2.2.1 notes: ? the options are described in 2.2 . ? the described specifications in the table which are rela ted the electric characteristics only show the typical values. they dont necessarily include the width of characteristics, errors, and so on. they should be seen in the datasheet in detailed. ? target resolution of graphics is wvga 800 x 480, wqvga 480 x 27 2. ? target capture resolution of graphics is wvga 800 x 480. ?
document number: 002 - 05682 rev.*a page 8 of 179 S6J3200 series 2.2 optional function 2.2.1 basic option t h e figure shows the optional function and the part number relations of the series. figure 2 - 1 : option and part number s 6 j 3 2 0 0 h a a x x x x x x x x ordering options 7 digit revision: revision version digit c support mcan 3.0.1, rtc limitation d support mcan 3.2. (iso certification), rtc limitation e support mcan 3.0.1. f support mcan 3.2. (iso certification) option digit she s on u off pin count digit pin count k 208 pin l 216 pin m 256 pin memory size digit program flash work flash tc-ram vram a 1088kb 64kb 1024kb c 2112kb 128kb 2048kb function see the function digit table. product series digit product type 2 graphic soc identifier: automotive mcu 112kb description
document number: 002 - 05682 rev.*a page 9 of 179 S6J3200 series table 2 - 2 : function digit table part number s6j32x (x = f unction d igit) function digit 3 4 5 6 7 8 a b c d cpu clock maximum 240mhz 240mhz 240mhz 240mhz 240mhz 240mhz 160 mhz 160 mhz 160 mhz 160 mhz graphics clock maximum 200mhz 200mhz 200mhz 200mhz 200mhz 200mhz 160mhz 160mhz 160mhz 160mhz display output support ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0 ch.0 ch.0 ch.0 video capture support 1 unit 1 unit 1 unit 1 unit 1 unit 1 unit off off off off graphic engine type 2d 2d 2d, 3d 2d, 3d 2d 2d, 3d 2d 2d 2d, 3d 2d, 3d hyperbus interface ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1, 2 ch.0, 1, 2 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 sound system off on off on on on off on off on fpd - link off off off on off on off off off off media system on on on on on on off off off off c hip select output of mfs on on on on on on off off off off notes: ? this table only shows the relations between the optional function and the part numbers. t hat is, all products are not necessarily available for orders. s ee the order number on the datasheet, and confirm actual availabilities of products. ? the sound system is composed of the sound waveform generator, the sound mixer, the audio dac, pcm - pwm, and i2s0. ? t he media system means both ethernet avb and media lb. ? hyperbus interface ch.1 of the function digit 3, 4, 5, and 6 support hyperram after revision b. ? multi - function serial interface of the function digit 3, 4, 5, 6, 7, and 8 support scl4, 10, 12 an d sda4, 10, 12 of i 2 c after revision d. ? the clk_cpu is assigned for cpu clock. the clk_cd3a0 is assigned for graphic clock. they are defined at the chapter of clock configuration. ? display output ch.0 is used for rsds and fpd - link (lvds) as well as drgb (d igital rgb). the ch.0 of the product which doesnt support fpd - link is used for rsds and drgb. ? display output ch.1 is used for fpd - link (lvds) and drgb (digital rgb). the ch.1 of the product which doesn't support fpd - link is used for drgb only.
document number: 002 - 05682 rev.*a page 10 of 179 S6J3200 series 2.2.2 id id is specified for each function digit and revision which is defined at figure 2 - 1 . chip id can be read from sysc0_sysidr. for sysc0_sysidr, see the traveotm platform hardware manual. function digit revision chip id jtag id 3, 4, 5, 6, 7, 8 a 0x 10100000 0x100085cf b - - c and d 0x 10100 10 0 0x1000c5cf e and f 0x10100101 0x1000c5cf a, b, c, d a - - b 0x 10110000 0x100095cf c and d - - e 0x 1011000 1 0x100095cf
document number: 002 - 05682 rev.*a page 11 of 179 S6J3200 series 2.2.3 restriction s ome functions have restrictions which depend on package pin counts. table 2 - 3 function teqfp256 teqfp216 teqfp208 analog input port (12bit - adc) an0 to an49 (50 ports) an0 to an49 (50 ports) an1 to an3, an5 to an17, an20 to an49 (46 ports) seg port of lcd controller seg0 to seg31 (32 ports) seg0 to seg31 (32 ports) seg0 to seg29 (30 ports)
document number: 002 - 05682 rev.*a page 12 of 179 S6J3200 series function teqfp256 teqfp216 teqfp208 general purpose i/o p0_00 , p0_01 , p0_02 , p0_03 , p0_04 , p0_05 , p0_06 , p0_07 , p0_08 , p0_09 , p0_10 , p0_11 , p0_12 , p0_13 , p0_14 , p0_15 , p0_16 , p0_17 , p0_18 , p0_19 , p0_26 , p0_27 , p0_28 , p0_30 , p0_31 , p1_00 , p1_01 , p1_02 , p1_03 , p1_04 , p1_05 , p1_06 , p1_07 , p1_08 , p1_09 , p2_16 , p2_17 , p2_19 , p2_22 , p2_24 , p2_25 , p2_26 , p2_27 , p2_28 , p2_29 , p2_30 , p2_31 , p3_00 , p3_01 , p3_02 , p3_03 , p3_04 , p3_05 , p3_06 , p3_07 , p3_08 , p3_09 , p3_10 , p3_11 , p3_12 , p3_13 , p3_14 , p3_15 , p3_16 , p3_17 , p3_18 , p3_19 , p3_20 , p3_21 , p3_22 , p3_23 , p3_24 , p3_25 , p3_26 , p3_27 , p3_28 , p3_29 , p3_30 , p3_31 , p4_00 , p4_01 , p4_02 , p4_03 , p4_04 , p4_05 , p4_06 , p4_07 , p4_08 , p4_09 , p4_10 , p4_11 , p4_12 , p4_25 , p4_26 , p4_27 , p4_28 , p4_29 , p4_30 , p4_31 , p5_00 , p5_01 , p5_02 , p5_03 , p5_04 , p5_05 , p5_06 , p5_07 , p5_08 , p5_09 , p5_10 , p5_11 , p5_12 , p5_13 , p5_14 , p5_15 , p5_16 , p5_17 , p5_18 , p5_19 , p5_20 , p5_21 , p5_22 , p5_27 , p5_28 , p5_29 , p5_30 , p5_31 , p6_00 , p6_01 , p6_02 , p6_03 , p6_04 , p6_05 , p6_06 , p6_07 , p6_08 , p6_09 , p6_10 , p6_11 , p6_12 , p6_13 , p6_14 , p6_15 , p6_16 , p6_17 , p6_18 , p6_19 , p6_20 , p6_21 , p6_22 , p6_23 , p6_24 , p6_25 , p6_26 (154 ports) p0_00 , p0_01 , p0_02 , p0_03 , p0_04 , p0_05 , p0_06 , p0_07 , p0_08 , p0_09 , p0_10 , p0_11 , p0_12 , p0_13 , p0_14 , p0_15 , p0_16 , p0_17 , p0_18 , p0_19 , p0_26 , p0_27 , p0_28 , p0_30 , p0_31 , p1_00 , p1_01 , p1_02 , p1_03 , p1_04 , p1_05 , p1_06 , p1_07 , p1_08 , p1_09 , p2_16 , p2_17 , p2_19 , p2_22 , p2_24 , p2_25 , p2_26 , p2_27 , p2_28 , p2_29 , p2_30 , p2_31 , p3_00 , p3_01 , p3_02 , p3_03 , p3_04 , p3_05 , p3_06 , p3_07 , p3_08 , p3_09 , p3_10 , p3_11 , p3_12 , p3_13 , p3_14 , p3_15 , p3_16 , p3_17 , p3_18 , p3_19 , p3_20 , p3_21 , p3_22 , p3_23 , p3_24 , p3_25 , p3_26 , p3_27 , p3_28 , p3_29 , p3_30 , p3_31 , p4_00 , p4_01 , p4_02 , p4_03 , p4_04 , p4_05 , p4_06 , p4_07 , p4_08 , p4_09 , p4_10 , p4_11 , p4_12 , p4_25 , p4_26 , p4_27 , p4_28 , p4_29 , p4_30 , p4_31 , p5_00 , p5_01 , p5_02 , p5_03 , p5_04 , p5_05 , p5_06 , p5_07 , p5_08 , p5_09 , p5_10 , p5_11 , p5_12 , p5_13 , p5_14 , p5_15 , p5_16 , p5_17 , p5_18 , p5_19 , p5_20 , p5_21 , p5_22 , p5_27 , p5_28 , p5_29 , p5_30 , p5_31 , p6_00 (128 ports) p0_00 , p0_01 , p0_04 , p0_05 , p0_06 , p0_07 , p0_08 , p0_09 , p0_10 , p0_11 , p0_12 , p0_13 , p0_14 , p0_15 , p0_16 , p0_17 , p0_18 , p0_19 , p0_26 , p0_27 , p0_28 , p0_30 , p0_31 , p1_00 , p1_01 , p1_02 , p1_03 , p1_04 , p1_05 , p1_06 , p1_07 , p1_08 , p1_09 , p2_16 , p2_17 , p2_19 , p2_22 , p2_25 , p2_26 , p2_27 , p2_29 , p2_30 , p2_31 , p3_00 , p3_01 , p3_02 , p3_03 , p3_04 , p3_05 , p3_06 , p3_07 , p3_08 , p3_09 , p3_12 , p3_13 , p3_14 , p3_15 , p3_16 , p3_17 , p3_18 , p3_21 , p3_22 , p3_23 , p3_24 , p3_25 , p3_26 , p3_27 , p3_28 , p3_29 , p3_30 , p3_31 , p4_00 , p4_01 , p4_02 , p4_03 , p4_04 , p4_05 , p4_06 , p4_07 , p4_08 , p4_09 , p4_10 , p4_11 , p4_12 , p4_25 , p4_26 , p4_27 , p4_28 , p4_29 , p4_30 , p4_31 , p5_00 , p5_01 , p5_02 , p5_03 , p5_04 , p5_05 , p5_06 , p5_07 , p5_08 , p5_09 , p5_10 , p5_11 , p5_12 , p5_13 , p5_14 , p5_15 , p5_16 , p5_17 , p5_18 , p5_19 , p5_20 , p5_21 , p5_22 , p5_27 , p5_28 , p5_29 , p5_30 , p5_31 , p6_00 (120 ports) ppg triggered input ppg0/1/2/3/4/5_tin1 , ppg6/7/8/9/10/11_tin ppg0/1/2/3/4/5_tin1 , ppg6/7/8/9/10/11_tin ppg6/7/8/9/10/11_tin notes: ? s ee multiplexed functions on pin assignment sheet. ? t he optional restriction will be added without notification. ? teqfp - 256 is a package option under planning
document number: 002 - 05682 rev.*a page 13 of 179 S6J3200 series 3. product description 3.1 overview this chapter explains the product features of S6J3200 series. t he description of this chapter should precede the duplicated description on platform manual. 3.2 product d escription the table shows features. table 3 - 1 feature description technology 55nm cmos technology with embedded flash fully automotive qualified according to iso/ts 16949 and aec - q100 functional safety the product series has some functional safety features suited for asil - b application. p eripheral s see function list. power domain (pd) see the platform manual and chapter state transition in detail. the product series supports the power off control of pd1, pd2 (including pd3 and 5), and pd6. the power domain resets of pd3 and pd5 included i n pd2 are not supported in the product series, and "0" is always read from the reset factor flags of them. this series doesn't support partial wakeup for pd6. debug and trace see the platform manual in detail. ? standard 5 - pin jtag interface ? 4k word embedded trace buffer 4 - bit trace support for teqfp package. full trace (dedicated 16 - bit port) with special bond - out package is planned. system control see the platform manual in detail. main and s ub o scillator is available. ? a wide range of 3.6 - 16 mhz is available for m ain oscillator ? 32khz is available for s ub oscillator sub clock is enable/disable by r egister settings clock see the platform manual in detail. clk_clko (clock output function) is not supported. embedded cr oscillation see the platform m anual in detail. stabilization time is as followings. ? 5us for 4mhz (fast clock) ? 20us for 100khz (slow clock) clock supervisor see the platform manual in detail. this product series doesnt support clock supervisor output port. (related register and intern al circuit is implemented .) reset see the platform manual in detail. following resets are not mounted on this device. ? initx ? srstx (and n s rst pin) hardware watchdog see the platform manual in detail. hardware watchdog function stops during pss mode. in the related register of hwdg_cfg , the bit allowstopclk is always read as 1 (hwdg_cfg.allowstopclk=1). the product series doesnt support watchdog counter monitor output port. (related register and internal circuit is implemented.) software watchdog see the platform manual in detail. the product series doesnt support watchdog counter monitor output port. (related register and inte rnal circuit is implemented.)
document number: 002 - 05682 rev.*a page 14 of 179 S6J3200 series feature description standby m ode see the platform manual in detail. standby mode with 5v single power supply is available. turn ing off the 3.3v supply and the external 1.2v supply in standby mode is available. the long term pulse of the indicator pwm can be outputted during rtc standby mode. pll / sscg pll see the platform manual in detail. use case assumption is following. ? pll ? sound system clock ? sound frequency master clock ? peripherals ? display clock ? trace clock ? sscg ? cpu core ? gdc core ? h yperbus ? ddr - hsspi down spread mode is only supported and available. external interrupts see the platform manual in detail. nmi see the platform manual in detail. 1 nmi pin . memory protection mpu16 ahb: see the platform manual in detail. mpu for axi: ch.0 (supervise ethernet) mpu for ahb: ch.1 (supervise media lb) a dditional mpu for graphic sub system, medialb and ethernet avb. they are described on the chapter of mpu for ahb and mpu for axi. to configure lock or unlock for both mpuxn_unlock and mpuhn _unlock, ? lock: 0x112abb56 ? unlock: 0xaccabb56 peripheral protection see the platform manual in detail. protected peripherals are described in the base address map. internal memories system ram see the platform manual in detail. 1 wait cycle is necessary for ram read at over 1 6 0mhz . no need to insert wait cycles for ram write. internal memories tcram see the platform manual in detail. internal memories backup ram 16kbytes backup ram can only be operated in run mode (normal operation mode). in other mode the memory content should be retained, but it cannot be operated. sleep control for buckup ram is not supported and cannot be used. internal memories vram ecc region is shared with user region. memory size available for user program become less when ecc is enabled. user can define ecc enable d area and ecc disable d area. single error correction, double error detection (secded) ecc support per 32 - bit word .
document number: 002 - 05682 rev.*a page 15 of 179 S6J3200 series feature description embedded program/work flash memory embedded program flash can be access ed with 0 - wait - cycle if cpu frequency is 80mhz or less. 0 - wait - cycle: 80mhz or less. 1 - wait - cycle: 160mhz or less. 2 - wait - cycle: more than 160mhz. the maximum frequency should be referred in datasheet. erase suspend is supported. read ing and w rit ing to the other sector are possible when flash erase is suspended. serial flash programing and parallel flash programing are supported. margin mode is not supported. internal power domain pd1: always on pd2: cortex r5f platform/ gdc/ additional p eripherals pd4: backup ram in always on domain pd 6 : p eripherals in always on domain * the chapter of the block diagram explains in detail. power supply external 5v, 3v, 1.2v is required. built in ldo provides internal 1.2v for always on region (pd1). external 1.2v power supply control pin is support ed . external 3.3v power supply should be controlled by gpio . there are constraints of power on/off sequence. low - v oltage detection lvd for external voltage is supported. lvd for internal voltage is supported. see the spe cification of the detected level on the datasheet. low - voltage detection for ram retention (rvd) r vd for ram retention is effective during the standby mode only. that is, it is only for the backup ram of 16kb that the function is available. resource inte r - connect the output signal of some r esource s can be input ted to the other resource. i/o ports 5v general purpose i/o 3v general purpose i/o multi input level and multi output drivability pull - up , pull - down function is available . r esource input and output is multiplexed. +b input is allowed many pins of 3.3v, 5v and 3.3v/5v i/o domain . a/d converter 12bit resolution, 1 unit 50 channels of analog input for teqfp256 and teqpf216 46 channel of analog input for teqfp208 24 channels of them are shared with th e smc for teqfp256/216/208 e xternal trigger and timer trigger are available. t he description of the a/d converter function should be referred in the S6J3200 hardware manual. though the chapter of i/o port in traveo pf v3 hardware manual describes another a /d converter function, do not refer it. crc see the platform manual in detail. programmable crc dma support sound generator produces sound/melody with varying frequency and amplitude for convenient duration square wave sound output automatic linear amplitude increment or decrement interrupt request generated when specified sound length has ended sound waveform g enerator sine waveform, s aw - t ooth waveform and square waveform are generated with easy configuration of the parameters which specified sound sources. fade - in and fade - out control for reverberation.
document number: 002 - 05682 rev.*a page 16 of 179 S6J3200 series feature description sound mixer the input channels of 0 - 4 are reserved for waveform generator. mixing different sampling frequency sounds . mixing internal sounds and external i2s input sounds . saturating addition f unction for keeping sound quality. cut a specific frequency data by digital filter. lpf is support by fir filter. fade - in and fade - out control. pcm - pwm conversion of pcm audio streaming to pulse width modulated signals . supports 2 output channels for stereo and mono data up to 16 - bit output sample resolution support for half and full h - bridges audio dac the sound source of the fixed 48khz sampling frequency can be outputted. 1unit, l/r channels support. btl connection is available. i2s 2ch. ? i2s0 can output sound sources which are processed by sound system. ? i2s1 can input sound sources which are processed by sound system. ? i2s has its own ppu, but the function is fixed to disable. see the "sound system c onfiguration" of S6J3200 hardware manual in detail. base timer see the platform manual in detail. a unit consists of a pair of 16bit base timers. 12 units, that is, 24 channels of base timers are available. reload timer see the platform manual in detail. i/o timer see the platform manual in de tail. quad position & revolution counter (up/down counter) see the platform manual in detail. multi - f unctional serial (mfs) see the platform manual in detail. 2 ports of mfs only support i 2 c. note ? n ot all pins support i2c. only pins which have the i2c i/o characteristics support it . see the datasheet in detail. the availability of chip select function can be seen at function digit table. chip select input is not supported. cts/rts is not mounted (hardware flow control is not supported for this series. ) wucr function is not supported for this product. can - fd flexible data rate is supported. 16kb/ch of message ram is available. the clock output from can pre - scaler is supplied to every can. ecc error generation function of the message ram is not support ed for this device. therefore can fd ecc error insertion control register (fdfecr) is not writeable. see the platform manual in detail real time clock (rtc) with a uto - calibration see the platform manual in detail. ddr h igh s peed spi ch.0: hsspi as a mcu peripheral ch.1: hsspi on graphic subsystem see the platform manual in detail
document number: 002 - 05682 rev.*a page 17 of 179 S6J3200 series feature description hyperbus i/f ch.0: hyperbus as a mcu peripheral ch.1: hyperbus on graphic subsystem ch.2: hyperbus on graphic subsystem the following register is not supported and cannot be us ed. ? controller status register (hyperbusin_csr) ? interrupt status register (hyperbusin_isr) ? write protection register (hyperbusin_wpr) ? test register (hyperbusin_test) gpo signal can only be used for "internal control example by gpo" in this product, that is , it can select using hyperbus of pf or using hyperbus of graphic sub system. see the "hyperbus interface port configuration" of S6J3200 hardware manual in detail . stepper motor control (smc) each channel has 4 motor drivers with high output capability external interrupt capture unit (eicu) see the platform manual in detail. ethernet avb 10/100 mb p s mii - interface supports audio - video bridging (avb) ethernetn_revision_reg : 0x30070106 (initial value) for revision b ethernetn_designcfg_debug6 : 0x0302000e (initial value) see 0 in details. m edialb most 25 ( 512 fs) 3 wires m aximum 15ch is available. lcd controller teqfp256 : 4com x 32seg teqfp216 : 4com x 32seg teqfp208 : 4com x 30seg lcdc pins are initialized with reset. (stop lcdc alternating current output) . duty and static of segment output is supported. (seg23/st0, seg24/st1, seg25/st2, seg26/st3, seg27/st4, seg28/st5, seg29/st6, seg30/st7, seg31/st8) she see the platform manual in detail. source clock timer see the platform manual in detail. graphics subsystem variable setting about gdc clock. (asynchronous with cpu clock) two drawing engines for 2d drawing and 3d drawing. parallel processing s upport. cpu can direct access to vram. p rogrammable panel timing controller with rgb888 and rsds support . note: ? t he description of the preliminary documentation will be changed without any notification.
document number: 002 - 05682 rev.*a page 18 of 179 S6J3200 series 3.2.1 ethernet the following functions are not supported. f unctions remark external fifo interface additional low latency tx fifo interface for dma configurations mac transmit block - half - duplex - collision - back_pressure mac filtering block - external address match - wakeup on lan energy efficient ethernet support lpi operation in cadence ip phy interface - gmii - sgmii - tbi 10/100/1000 operation - 1000 m sgmii operation jumbo frames physical control sub - layer
document number: 002 - 05682 rev.*a page 19 of 179 S6J3200 series 4. package and pin assignment 4.1 pin assignment the characters next to the pin number in the pin assignment drawing specify the i/o circuit type. figure 4 - 1 : pin number and i/o circuit type function digit teqfp - 216 teqfp - 208 teqfp - 256 s6j328 figure 4 - 2 figure 4 - 9 figure 4 - 16 s6j327 figure 4 - 3 figure 4 - 10 - s6j326 figure 4 - 4 figure 4 - 11 - s6j325 figure 4 - 5 figure 4 - 12 - s6j324 figure 4 - 6 figure 4 - 13 - s6j323 figure 4 - 7 figure 4 - 14 - a, b, c, d figure 4 - 8 figure 4 - 15 - pin number i/o circuit type 0 0 vcc53 dsp1_ctrl0 - y 216 215 0 0 vss - 1 0 0 avss - 2 0 0 dac_r a 3 0 0 c_r a 4 0 0 avss - 5 0 0 avcc3_dac - 6 0 0 dac_l a 7 0 0 c_l a 8 0 0 avss - 9 0 0 vss - 10 0 0 vcc12 - 11 0 0 avss_lvds_pll - 12 0 0 avcc3_lvds_pll - 13 0 0 vcc3_lvds_tx - 14 0 0 vss_lvds_tx - 15 0 0 txdout3+ b 16 0 0 txdout3- b 17 0 0 txdout2+ b 18
document number: 002 - 05682 rev.*a page 20 of 179 S6J3200 series 4.1.1 teqfp - 216 pin assignment figure 4 - 2 : teqfp - 216 (s6j328clxx) note: ? the pins which are described in "red" character are not supported for product with revision a and c. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_11 p3_10 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin19 tot19 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 0 0 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an19 an18 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w w w v v v u - - 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 162 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 161 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 160 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 159 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 158 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 157 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 156 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 155 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 154 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 153 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 152 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 151 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 150 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 149 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 148 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 147 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 146 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 145 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 144 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 143 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 142 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 141 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 140 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 139 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 138 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 137 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 136 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 135 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 134 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 133 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 132 - dvcc 0 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 131 - dvss 0 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 130 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 129 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 128 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 127 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 126 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 125 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 124 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 123 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 122 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 121 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 120 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 44 119 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 45 118 q rstx 0 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 46 117 p mode 0 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 47 116 n2 jtag_tms 0 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 48 115 n2 jtag_tck 0 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 49 114 n2 jtag_tdi 0 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 50 113 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 51 112 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 52 111 m x0 0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 53 110 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 54 109 - vss 0 0 0 0 0 0 0 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 tin0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 sga2 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 eint12 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p2_28 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-216
document number: 002 - 05682 rev.*a page 21 of 179 S6J3200 series figure 4 - 3 : teqfp - 216 (s6j327clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the followin g pins is not supported. package pin number condition on pcb 12 to 27 set to ground ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_11 p3_10 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin19 tot19 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 0 0 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an19 an18 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w w w v v v u - - 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 162 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 161 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 160 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 159 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 158 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 157 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 156 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 155 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 154 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 153 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 152 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 151 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 150 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 149 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 148 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 147 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 146 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 145 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 144 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 143 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 142 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 141 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 140 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 139 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 138 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 137 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 136 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 135 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 134 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 133 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 132 - dvcc 0 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 131 - dvss 0 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 130 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 129 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 128 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 127 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 126 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 125 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 124 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 123 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 122 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 121 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 120 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 44 119 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 45 118 q rstx 0 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 46 117 p mode 0 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 47 116 n2 jtag_tms 0 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 48 115 n2 jtag_tck 0 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 49 114 n2 jtag_tdi 0 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 50 113 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 51 112 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 52 111 m x0 0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 53 110 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 54 109 - vss 0 0 0 0 0 0 0 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 tin0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 sga2 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 eint12 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p2_28 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-216
document number: 002 - 05682 rev.*a page 22 of 179 S6J3200 series figure 4 - 4 : teqfp - 216 (s6j326clxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_11 p3_10 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin19 tot19 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 0 0 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an19 an18 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w w w v v v u - - 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 162 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 161 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 160 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 159 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 158 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 157 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 156 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 155 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 154 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 153 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 152 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 151 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 150 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 149 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 148 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 147 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 146 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 145 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 144 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 143 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 142 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 141 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 140 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 139 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 138 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 137 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 136 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 135 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 134 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 133 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 132 - dvcc 0 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 131 - dvss 0 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 130 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 129 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 128 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 127 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 126 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 125 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 124 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 123 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 122 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 121 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 120 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 44 119 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 45 118 q rstx 0 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 46 117 p mode 0 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 47 116 n2 jtag_tms 0 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 48 115 n2 jtag_tck 0 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 49 114 n2 jtag_tdi 0 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 50 113 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 51 112 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 52 111 m x0 0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 53 110 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 54 109 - vss 0 0 0 0 0 0 0 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 tin0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 sga2 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 eint12 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p2_28 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-216
document number: 002 - 05682 rev.*a page 23 of 179 S6J3200 series figure 4 - 5 : teqfp - 216 (s6j325clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the following pins is not supported. package pin number condition on pcb 2, 5, 6, 9, and 12 to 27 set to ground 3, 4, 7, 8 open 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_11 p3_10 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin19 tot19 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 0 0 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an19 an18 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w w w v v v u - - 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 162 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 161 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 160 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 159 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 158 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 157 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 156 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 155 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 154 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 153 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 152 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 151 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 150 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 149 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 148 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 147 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 146 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 145 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 144 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 143 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 142 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 141 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 140 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 139 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 138 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 137 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 136 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 135 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 134 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 133 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 132 - dvcc 0 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 131 - dvss 0 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 130 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 129 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 128 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 127 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 126 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 125 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 124 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 123 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 122 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 121 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 120 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 44 119 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 45 118 q rstx 0 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 46 117 p mode 0 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 47 116 n2 jtag_tms 0 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 48 115 n2 jtag_tck 0 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 49 114 n2 jtag_tdi 0 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 50 113 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 51 112 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 52 111 m x0 0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 53 110 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 54 109 - vss 0 0 0 0 0 0 0 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 tin0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 sga2 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 eint12 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p2_28 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-216
document number: 002 - 05682 rev.*a page 24 of 179 S6J3200 series figure 4 - 6 : teqfp - 216 (s6j324clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the following pins is not supported. package pin number condition on pcb 12 to 27 set to ground 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_11 p3_10 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin19 tot19 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 0 0 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an19 an18 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w w w v v v u - - 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 162 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 161 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 160 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 159 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 158 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 157 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 156 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 155 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 154 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 153 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 152 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 151 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 150 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 149 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 148 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 147 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 146 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 145 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 144 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 143 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 142 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 141 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 140 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 139 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 138 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 137 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 136 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 135 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 134 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 133 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 132 - dvcc 0 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 131 - dvss 0 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 130 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 129 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 128 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 127 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 126 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 125 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 124 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 123 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 122 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 121 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 120 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 44 119 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 45 118 q rstx 0 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 46 117 p mode 0 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 47 116 n2 jtag_tms 0 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 48 115 n2 jtag_tck 0 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 49 114 n2 jtag_tdi 0 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 50 113 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 51 112 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 52 111 m x0 0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 53 110 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 54 109 - vss 0 0 0 0 0 0 0 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 tin0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 sga2 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 eint12 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p2_28 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-216
document number: 002 - 05682 rev.*a page 25 of 179 S6J3200 series figure 4 - 7 : teqfp - 216 (s6j323clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the following pins is not supported. package pin number condition on pcb 2, 5, 6, 9, and 12 to 27 set to ground 3, 4, 7, 8 open 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_11 p3_10 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin19 tot19 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 0 0 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an19 an18 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w w w v v v u - - 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 162 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 161 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 160 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 159 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 158 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 157 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 156 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 155 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 154 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 153 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 152 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 151 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 150 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 149 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 148 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 147 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 146 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 145 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 144 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 143 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 142 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 141 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 140 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 139 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 138 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 137 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 136 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 135 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 134 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 133 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 132 - dvcc 0 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 131 - dvss 0 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 130 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 129 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 128 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 127 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 126 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 125 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 124 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 123 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 122 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 121 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 120 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 44 119 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 45 118 q rstx 0 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 46 117 p mode 0 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 47 116 n2 jtag_tms 0 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 48 115 n2 jtag_tck 0 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 49 114 n2 jtag_tdi 0 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 50 113 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 51 112 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 52 111 m x0 0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 53 110 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 54 109 - vss 0 0 0 0 0 0 0 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 tin0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 sga2 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 eint12 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p2_28 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-216
document number: 002 - 05682 rev.*a page 26 of 179 S6J3200 series figure 4 - 8 : teqfp - 216 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_11 p3_10 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin19 tot19 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 0 0 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an19 an18 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w w w v v v u - - 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 162 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 161 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 160 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 159 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 158 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 157 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 156 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 155 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 154 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 153 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 152 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 12 151 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 13 150 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 14 149 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 15 148 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 16 147 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 17 146 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 18 145 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 19 144 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 20 143 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 21 142 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 22 141 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 23 140 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 24 139 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 25 138 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 26 137 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 27 136 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 135 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 134 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 133 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 132 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 131 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 130 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 129 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 128 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 127 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 126 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 125 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 124 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 123 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 122 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 121 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 120 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 44 119 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 45 118 q rstx 0 0 0 0 0 0 0 0 cap0_data11 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 46 117 p mode 0 0 0 0 0 0 0 0 cap0_data12 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 47 116 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 48 115 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 49 114 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 50 113 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 51 112 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 52 111 m x0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 53 110 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 54 109 - vss 0 0 0 0 0 0 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 tin0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 sga2 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 eint12 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p2_28 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-216
document number: 002 - 05682 rev.*a page 27 of 179 S6J3200 series 4.1.2 teqpf - 208 pin assignment figure 4 - 9 : teqfp - 208 (s6j328clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w v v v u - - 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 156 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 155 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 154 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 153 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 152 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 151 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 150 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 149 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 148 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 147 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 146 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 145 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 144 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 143 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 142 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 141 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 140 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 139 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 138 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 137 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 136 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 135 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 134 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 133 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 132 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 131 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 130 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 129 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 128 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 127 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 126 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 125 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 124 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 123 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 122 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 121 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 120 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 119 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 118 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 117 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 116 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 115 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 114 q rstx 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 44 113 p mode 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 45 112 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 46 111 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 47 110 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 48 109 o jtag_tdo 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 49 108 n jtag_ntrst 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 50 107 m x0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 51 106 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 105 - vss 0 0 0 0 0 0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h j j i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an1 an2 an3 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 sot0 sck0 sin0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sga0 sga1 sgo1 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 bin8 zin8 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint9 eint10 eint11 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_25 p2_26 p2_27 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-208
document number: 002 - 05682 rev.*a page 28 of 179 S6J3200 series figure 4 - 10 : teqfp - 208 (s6j327clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the following pins is not supported. package pin number condition on pcb 12 to 27 set to ground 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w v v v u - - 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 156 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 155 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 154 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 153 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 152 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 151 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 150 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 149 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 148 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 147 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 146 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 145 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 144 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 143 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 142 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 141 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 140 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 139 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 138 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 137 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 136 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 135 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 134 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 133 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 132 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 131 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 130 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 129 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 128 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 127 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 126 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 125 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 124 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 123 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 122 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 121 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 120 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 119 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 118 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 117 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 116 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 115 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 114 q rstx 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 44 113 p mode 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 45 112 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 46 111 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 47 110 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 48 109 o jtag_tdo 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 49 108 n jtag_ntrst 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 50 107 m x0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 51 106 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 105 - vss 0 0 0 0 0 0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h j j i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an1 an2 an3 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 sot0 sck0 sin0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sga0 sga1 sgo1 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 bin8 zin8 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint9 eint10 eint11 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_25 p2_26 p2_27 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-208
document number: 002 - 05682 rev.*a page 29 of 179 S6J3200 series figure 4 - 11 : teqfp - 208 (s6j326clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w v v v u - - 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 156 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 155 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 154 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 153 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 152 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 151 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 150 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 149 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 148 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 147 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 146 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 145 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 144 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 143 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 142 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 141 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 140 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 139 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 138 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 137 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 136 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 135 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 134 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 133 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 132 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 131 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 130 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 129 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 128 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 127 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 126 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 125 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 124 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 123 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 122 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 121 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 120 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 119 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 118 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 117 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 116 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 115 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 114 q rstx 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 44 113 p mode 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 45 112 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 46 111 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 47 110 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 48 109 o jtag_tdo 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 49 108 n jtag_ntrst 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 50 107 m x0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 51 106 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 105 - vss 0 0 0 0 0 0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h j j i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an1 an2 an3 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 sot0 sck0 sin0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sga0 sga1 sgo1 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 bin8 zin8 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint9 eint10 eint11 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_25 p2_26 p2_27 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-208
document number: 002 - 05682 rev.*a page 30 of 179 S6J3200 series figure 4 - 12 : teqfp - 208 (s6j325clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the following pins is not supported. package pin number condition on pcb 2, 5, 6, 9, and 12 to 27 set to ground 3, 4, 7, 8 open 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w v v v u - - 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 156 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 155 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 154 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 153 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 152 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 151 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 150 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 149 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 148 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 147 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 146 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 145 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 144 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 143 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 142 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 141 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 140 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 139 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 138 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 137 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 136 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 135 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 134 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 133 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 132 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 131 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 130 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 129 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 128 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 127 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 126 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 125 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 124 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 123 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 122 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 121 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 120 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 119 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 118 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 117 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 116 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 115 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 114 q rstx 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 44 113 p mode 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 45 112 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 46 111 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 47 110 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 48 109 o jtag_tdo 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 49 108 n jtag_ntrst 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 50 107 m x0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 51 106 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 105 - vss 0 0 0 0 0 0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h j j i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an1 an2 an3 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 sot0 sck0 sin0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sga0 sga1 sgo1 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 bin8 zin8 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint9 eint10 eint11 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_25 p2_26 p2_27 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-208
document number: 002 - 05682 rev.*a page 31 of 179 S6J3200 series figure 4 - 13 : teqfp - 208 (s6j324clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the following pins is not supported. package pin number condition on pcb 12 to 27 set to ground 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w v v v u - - 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 156 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 155 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 154 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 153 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 152 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 151 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 150 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 149 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 148 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 147 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 146 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 145 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 144 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 143 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 142 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 141 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 140 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 139 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 138 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 137 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 136 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 135 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 134 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 133 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 132 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 131 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 130 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 129 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 128 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 127 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 126 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 125 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 124 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 123 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 122 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 121 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 120 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 119 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 118 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 117 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 116 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 115 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 114 q rstx 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 44 113 p mode 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 45 112 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 46 111 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 47 110 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 48 109 o jtag_tdo 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 49 108 n jtag_ntrst 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 50 107 m x0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 51 106 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 105 - vss 0 0 0 0 0 0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h j j i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an1 an2 an3 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 sot0 sck0 sin0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sga0 sga1 sgo1 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 bin8 zin8 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint9 eint10 eint11 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_25 p2_26 p2_27 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-208
document number: 002 - 05682 rev.*a page 32 of 179 S6J3200 series figure 4 - 14 : teqfp - 208 (s6j323clxx) notes: ? the pins which are described in "red" character are not supported for product with revision a and c. ? any function at the following pins is not supported. package pin number condition on pcb 2, 5, 6, 9, and 12 to 27 set to ground 3, 4, 7, 8 open 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w v v v u - - 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 156 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 155 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 154 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 153 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 152 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 151 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 150 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 149 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 148 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 147 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 146 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 145 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 144 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 143 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 142 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 141 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 140 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 139 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 138 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 137 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 136 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 135 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 134 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 133 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 132 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 131 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 130 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 129 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 128 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 127 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 126 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 125 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 124 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 123 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 122 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 121 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 120 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 119 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 118 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 117 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 116 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 115 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 114 q rstx 0 0 0 0 0 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 44 113 p mode 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 45 112 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 46 111 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 47 110 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 48 109 o jtag_tdo 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 49 108 n jtag_ntrst 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 50 107 m x0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 51 106 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 105 - vss 0 0 0 0 0 0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h j j i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an1 an2 an3 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 sot0 sck0 sin0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sga0 sga1 sgo1 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 bin8 zin8 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint9 eint10 eint11 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_25 p2_26 p2_27 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 g_dq6_2 g_dq7_2 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-208
document number: 002 - 05682 rev.*a page 33 of 179 S6J3200 series figure 4 - 15 : teqfp - 208 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p4_28 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 p5_16 p5_15 p5_14 p5_13 0 0 p5_12 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 p5_05 0 0 0 0 p5_04 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 p3_15 p3_14 p3_13 p3_12 p3_09 p3_08 p3_07 p2_19 0 0 0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 0 0 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0 0 0 0 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 0 0 seg24 seg25 seg26 seg27 seg28 seg29 v0 v1 v2 v3 0 0 0 eint12 eint11 eint10 eint9 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 0 0 0 0 eint4 eint3 eint2 eint1 eint0 eint15 eint14 eint13 0 0 0 eint0 eint1 eint1 eint0 eint15 eint14 eint13 eint12 eint9 eint8 eint7 eint3 0 0 0 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 ppg11_tout0 ppg10_tout2 0 0 ppg10_tout0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 ppg6_tout2 0 0 0 0 ppg6_tout0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 ppg0_tout2 ppg0_tout0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 ppg6/7/8/9/10/11_tin frt0/1/2/3_text tin48 0 0 0 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 icu11_in1 icu11_in0 icu10_in1 0 0 icu10_in0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 icu6_in1 0 0 0 0 icu6_in0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 icu0_in1 icu0_in0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 ocu11_otd0 ocu10_otd1 0 0 ocu10_otd0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 ocu6_otd1 0 0 0 0 ocu6_otd0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 ocu0_otd1 ocu0_otd0 ocu11_otd1 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 zin9 bin9 0 0 ain9 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 sgo2 sga2 sgo1 sga1 sga0 sgo0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 tin33 tot33 tin32 tot32 tin18 tot18 tot17 0 0 0 0 sin11 sck11 sot11 0 sin12 sck12 sot12 0 sin11 sck11 sot11 0 0 0 sin10 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 sin8 sck8 sot8 0 0 0 0 0 0 0 0 0 0 sin11 sck11 sot11 sin10 sck10 sot10 sin9 sck9 sot9 0 0 0 0 dsp0_ctrl11 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) 0 0 0 0 0 tx6 rx6 tx5 rx5 0 0 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 dsp1_data1_3 vss vcc53 dsp1_data0_4 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 an23 an22 an21 an20 an17 an16 an15 0 vss vcc5 - y y y y y y y y y y y y - - y y y y y y y y - - - - y y y y y y y y - - - x x w w w w w w v v v u - - 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 156 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 155 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 154 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 153 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 152 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 151 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 150 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 149 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 148 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 147 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 146 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 12 145 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 13 144 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 14 143 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 15 142 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 16 141 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 17 140 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 18 139 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 19 138 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 20 137 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 21 136 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 22 135 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 23 134 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 24 133 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 25 132 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 26 131 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nc - 27 130 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 129 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 128 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 127 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 126 - dvcc 0 0 0 0 0 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 125 - dvss 0 0 0 0 0 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 124 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 123 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 122 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 36 121 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 37 120 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 38 119 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 39 118 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 40 117 - c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 41 116 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 115 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 114 q rstx 0 0 0 0 0 0 0 0 cap0_data11 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 44 113 p mode 0 0 0 0 0 0 0 0 cap0_data12 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 45 112 n2 jtag_tms 0 0 0 0 0 0 0 0 cap0_data13 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 46 111 n2 jtag_tck 0 0 0 0 0 0 0 0 cap0_data14 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 47 110 n2 jtag_tdi 0 0 0 0 0 0 0 0 cap0_data15 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 48 109 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 49 108 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 50 107 m x0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 51 106 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 105 - vss 0 0 0 0 0 0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - d d d d d d c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h j j i i i i j j i i i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 dsp0_data0_10 dsp0_data1_10 dsp0_data0_11 dsp0_data1_11 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an1 an2 an3 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- dsp0_data_d10+ dsp0_data_d10- dsp0_data_d11+ dsp0_data_d11- dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 sot0 sck0 sin0 sot1 sck1 sin1 sot16 sck16 sin16 sot8 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 cap0_data23 cap0_data32 cap0_data33 cap0_clk cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 txclk rxclk rxer rxdv col 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 tx0 rx1 tx1 0 0 0 tot33 tin33 tot34 tin34 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 tin1 tin2 tin3 tot0 tot1 tot2 tot3 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck i2s1_eclk i2s1_sd i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sga0 sga1 sgo1 sgo2 sga3 sgo3 sgo0 sga0 sga1 sgo1 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 bin8 zin8 0 ain9 bin9 zin9 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 ocu6_otd1 ocu7_otd0 ocu7_otd1 ocu8_otd0 ocu8_otd1 ocu9_otd0 ocu9_otd1 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in1 icu5_in0 icu5_in1 icu6_in1 icu7_in0 icu7_in1 icu8_in0 icu8_in1 icu9_in0 icu9_in1 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 ppg6_tout2 ppg7_tout0 ppg7_tout2 ppg8_tout0 ppg8_tout2 ppg9_tout0 ppg9_tout2 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 eint15 eint0 eint1 eint2 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint9 eint10 eint11 eint13 eint14 eint15 eint0 eint1 eint2 eint3 eint4 eint5 eint6 0 0 0 p0_12 p0_13 p0_14 p0_15 p0_16 p0_17 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_25 p2_26 p2_27 p2_29 p2_30 p2_31 p3_00 p3_01 p3_02 p3_03 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 dsp0_clk dsp0_ctrl0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 trace2 trace3 trace_clk trace_ctl 0 0 0 top view teqfp-208
document number: 002 - 05682 rev.*a page 34 of 179 S6J3200 series 4.1.3 teqpf - 256 pin assignment figure 4 - 16 : teqfp - 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs10_scl mfs10_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs12_scl mfs12_sda 0 0 mfs8_cs2 mfs8_cs1 mfs8_cs3 0 0 0 0 mfs9_cs1 0 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_1 0 mfs8_cs2 mfs8_cs1 0 mfs8_cs3 mfs9_cs1 mfs9_cs0 mfs8_cs0 0 0 0 0 0 0 0 0 0 0 0 0 p6_26 0 0 0 0 0 0 0 p6_25 0 0 0 p6_24 0 0 0 0 p6_23 0 0 0 0 0 0 p6_22 0 0 0 0 0 0 p6_21 0 0 0 0 0 0 p6_20 0 0 0 0 0 0 0 0 p6_19 0 0 0 0 p6_18 0 0 0 0 p6_17 0 0 0 0 0 p4_28 0 p4_27 p4_26 p4_25 p5_20 p5_19 p5_18 p5_17 0 p5_16 p5_15 p5_14 0 p5_13 0 0 p5_12 0 p5_11 p5_10 p5_09 p5_08 p5_07 p5_06 0 p5_05 0 0 0 0 p5_04 0 p5_03 p5_02 p5_01 p5_00 p4_31 p4_30 0 p4_29 0 0 0 p2_16 p2_17 p3_17 p3_16 0 p3_15 p3_14 p3_13 p3_12 0 p3_11 p3_10 p3_09 p3_08 0 p3_07 p2_19 0 0 0 com0 0 com1 com2 com3 seg0 seg1 seg2 seg3 0 seg4 seg5 seg6 0 seg7 0 0 seg8 0 seg9 seg10 seg11 seg12 seg13 seg14 0 seg15 0 0 0 0 seg16 0 seg17 seg18 seg19 seg20 seg21 seg22 0 seg23 0 0 0 0 0 seg24 seg25 0 seg26 seg27 seg28 seg29 0 seg30 seg31 v0 v1 0 v2 v3 0 0 0 eint12 0 eint11 eint10 eint9 eint4 eint3 eint2 eint1 0 eint0 eint15 eint14 0 eint13 0 0 eint12 0 eint11 eint10 eint9 eint8 eint7 eint6 0 eint5 0 0 0 0 eint4 0 eint3 eint2 eint1 eint0 eint15 eint14 0 eint13 0 0 0 eint0 eint1 eint1 eint0 0 eint15 eint14 eint13 eint12 0 eint11 eint10 eint9 eint8 0 eint7 eint3 0 0 0 ppg2_tout0 0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg2_tout0 ppg1_tout2 ppg1_tout0 ppg0_tout2 0 ppg0_tout0 ppg11_tout2 ppg11_tout0 0 ppg10_tout2 0 0 ppg10_tout0 0 ppg9_tout2 ppg9_tout0 ppg8_tout2 ppg8_tout0 ppg7_tout2 ppg7_tout0 0 ppg6_tout2 0 0 0 0 ppg6_tout0 0 ppg5_tout2 ppg5_tout0 ppg4_tout2 ppg4_tout0 ppg3_tout2 ppg3_tout0 0 ppg2_tout2 0 0 0 ppg0_tout0 ppg0_tout2 ppg4_tout2 ppg4_tout0 0 ppg3_tout2 ppg3_tout0 ppg2_tout2 ppg2_tout0 0 ppg1_tout2 ppg1_tout0 ppg0_tout2 ppg0_tout0 0 ppg11_tout2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frt4/5/6/7_text 0 0 0 0 0 0 0 ppg6/7/8/9/10/11_tin 0 frt0/1/2/3_text tin48 0 0 0 icu2_in0 0 icu1_in1 icu1_in0 icu0_in1 icu2_in0 icu1_in1 icu1_in0 icu0_in1 0 icu0_in0 icu11_in1 icu11_in0 0 icu10_in1 0 0 icu10_in0 0 icu9_in1 icu9_in0 icu8_in1 icu8_in0 icu7_in1 icu7_in0 0 icu6_in1 0 0 0 0 icu6_in0 0 icu5_in1 icu5_in0 icu4_in1 icu4_in0 icu3_in1 icu3_in0 0 icu2_in1 0 0 0 icu0_in0 icu0_in1 icu4_in1 icu4_in0 0 icu3_in1 icu3_in0 icu2_in1 icu2_in0 0 icu1_in1 icu1_in0 icu0_in1 icu0_in0 0 icu11_in1 icu1_in1 0 0 0 ocu2_otd0 0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu2_otd0 ocu1_otd1 ocu1_otd0 ocu0_otd1 0 ocu0_otd0 ocu11_otd1 ocu11_otd0 0 ocu10_otd1 0 0 ocu10_otd0 0 ocu9_otd1 ocu9_otd0 ocu8_otd1 ocu8_otd0 ocu7_otd1 ocu7_otd0 0 ocu6_otd1 0 0 0 0 ocu6_otd0 0 ocu5_otd1 ocu5_otd0 ocu4_otd1 ocu4_otd0 ocu3_otd1 ocu3_otd0 0 ocu2_otd1 0 0 0 ocu0_otd0 ocu0_otd1 ocu4_otd1 ocu4_otd0 0 ocu3_otd1 ocu3_otd0 ocu2_otd1 ocu2_otd0 0 ocu1_otd1 ocu1_otd0 ocu0_otd1 ocu0_otd0 0 ocu11_otd1 0 0 0 0 0 0 sgo1 sga1 0 0 0 0 0 0 0 0 zin9 0 bin9 0 0 ain9 0 zin8 bin8 ain8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo3 sga3 0 0 0 0 0 0 0 sgo2 sga2 0 sgo1 sga1 sga0 sgo0 0 0 0 0 wot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin34 tot34 0 tin33 tot33 tin32 tot32 0 tin19 tot19 tin18 tot18 0 tot17 0 0 0 0 sin11 0 sck11 sot11 0 sin12 sck12 sot12 0 0 sin11 sck11 sot11 0 0 0 0 sin10 0 sck10 sot10 0 sin9 sck9 sot9 0 0 0 0 0 0 sin8 0 sck8 sot8 0 0 0 0 0 0 0 0 0 0 0 sin11 sck11 0 sot11 sin10 sck10 sot10 0 0 0 sin9 sck9 0 sot9 0 0 0 0 dsp0_ctrl11 0 dsp0_ctrl10 dsp0_ctrl9 dsp0_ctrl8 dsp0_ctrl7 dsp0_ctrl6 dsp0_ctrl5 dsp0_ctrl4 0 dsp0_ctrl3 dsp0_ctrl2 dsp0_ctrl1 0 dsp0_ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bn1(bl1) 0 bp1(bh1) an1(al1) ap1(ah1) bn0(bl0) bp0(bh0) an0(al0) 0 ap0(ah0) 0 0 0 0 0 tx6 rx6 0 tx5 rx5 0 0 0 tx6 rx6 tx5 rx5 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp1_ctrl1 dsp1_ctrl0 0 dsp1_clk dsp1_ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc53 dsp1_ctrl0 0 dsp1_ctrl1 dsp1_ctrl2 dsp1_clk dsp1_data0_0 dsp1_data1_0 dsp1_data0_1 dsp1_data1_1 0 dsp1_data0_2 dsp1_data1_2 dsp1_data0_3 0 dsp1_data1_3 vss vcc53 dsp1_data0_4 0 dsp1_data1_4 dsp1_data0_5 dsp1_data1_5 dsp1_data0_6 dsp1_data1_6 dsp1_data0_7 0 dsp1_data1_7 vcc53 vss vcc12 vcc12 dsp1_data0_8 0 dsp1_data1_8 dsp1_data0_9 dsp1_data1_9 dsp1_data0_10 dsp1_data1_10 dsp1_data0_11 trace_ctl dsp1_data1_11 vcc53 vss vcc5 x0a x1a an25 an24 trace_clk an23 an22 an21 an20 trace15 an19 an18 an17 an16 trace14 an15 0 vss vcc5 #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a #n/a - y y y y y y y y y y y y - - y y y y y y y y - 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 1 192 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 2 191 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_r a 3 190 s an49 sin4 tx1 pwm2m5 ocu6_otd0 icu6_in0 ppg6_tout0 eint12 p4_12 0 mfs0_cs2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_r a 4 189 s an48 sck4 rx1 pwm2p5 ocu5_otd1 icu5_in1 ppg5_tout2 eint11 p4_11 0 mfs0_cs1 mfs4_scl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 5 188 s an47 sot4 0 pwm1m5 ocu5_otd0 icu5_in0 ppg5_tout0 eint10 p4_10 0 mfs0_cs3 mfs4_sda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_dac - 6 187 s an46 0 0 pwm1p5 ocu4_otd1 icu4_in1 ppg4_tout2 eint9 p4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac_l a 7 186 t trace13 0 0 0 0 0 0 0 0 p6_16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_l a 8 185 s an45 sin3 0 pwm2m4 ocu4_otd0 icu4_in0 ppg4_tout0 eint8 p4_08 0 mfs2_cs1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss - 9 184 s an44 sck3 0 pwm2p4 ocu3_otd1 icu3_in1 ppg3_tout2 eint7 p4_07 0 mfs2_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 10 183 s an43 sot3 0 pwm1m4 ocu3_otd0 icu3_in0 ppg3_tout0 eint6 p4_06 0 mfs0_cs0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 11 182 t trace12 0 0 0 0 0 0 0 0 p6_15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avss_lvds_pll - 12 181 s an42 0 0 pwm1p4 ocu2_otd1 icu2_in1 ppg2_tout2 eint5 p4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 avcc3_lvds_pll - 13 180 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 14 179 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 15 178 s an41 sin2 0 pwm2m3 ocu2_otd0 icu2_in0 ppg2_tout0 eint4 p4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3+ b 16 177 t trace11 0 0 0 0 0 0 0 0 p6_14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout3- b 17 176 s an40 sck2 0 pwm2p3 ocu1_otd1 icu1_in1 ppg1_tout2 eint3 p4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2+ b 18 175 s an39 sot2 0 pwm1m3 ocu1_otd0 icu1_in0 ppg1_tout0 eint2 p4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout2- b 19 174 s an38 0 0 pwm1p3 ocu0_otd1 icu0_in1 ppg0_tout2 eint1 p4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk+ b 20 173 t trace10 0 0 0 0 0 0 0 0 p6_13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txclk- b 21 172 s an37 0 0 pwm2m2 ocu0_otd0 icu0_in0 ppg0_tout0 eint0 p4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1+ b 22 171 s an36 0 0 pwm2p2 ocu11_otd1 icu11_in1 ppg11_tout2 eint15 p3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout1- b 23 170 s an35 0 0 pwm1m2 ocu11_otd0 icu11_in0 ppg11_tout0 eint14 p3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0+ b 24 169 t trace9 0 0 0 0 0 0 0 0 p6_12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txdout0- b 25 168 s an34 0 0 pwm1p2 ocu10_otd1 icu10_in1 ppg10_tout2 eint13 p3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss_lvds_tx - 26 167 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3_lvds_tx - 27 166 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc12 - 28 165 s an33 0 bn1(bl1) pwm2m1 ocu10_otd0 icu10_in0 ppg10_tout0 eint12 p3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 29 164 t trace8 0 0 0 0 0 0 0 0 p6_11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 30 163 s an32 0 bp1(bh1) pwm2p1 ocu9_otd1 icu9_in1 ppg9_tout2 eint11 p3_27 0 0 0 dsp0_data1_10 0 0 0 0 0 p5_21 eint3 ppg9_tout2 icu9_in1 ocu9_otd1 0 dsp0_data0_4 mdc cap0_data0 0 dsp0_ctrl1 c 31 162 s an31 0 an1(al1) pwm1m1 ocu9_otd0 icu9_in0 ppg9_tout0 eint10 p3_26 0 0 0 dsp0_data0_11 0 0 0 0 0 p0_18 eint15 ppg3_tout2 icu3_in1 ocu3_otd1 0 0 mdio cap0_data1 dsp0_clk+ dsp0_clk d 32 161 s an30 0 ap1(ah1) pwm1p1 ocu8_otd1 icu8_in1 ppg8_tout2 eint9 p3_25 0 0 0 dsp0_data1_11 0 0 0 0 0 p0_19 eint0 ppg4_tout0 icu4_in0 ocu4_otd0 0 dsp0_data1_4 0 cap0_data2 dsp0_clk- dsp0_ctrl2 d 33 160 t trace7 0 0 0 0 0 0 0 0 p6_10 0 0 0 0 0 0 0 0 p5_27 eint11 ppg9_tout2 icu9_in1 ocu9_otd1 0 tot0 0 cap0_data3 dsp0_data_d0+ dsp0_data0_0 d 34 159 s an29 0 bn0(bl0) pwm2m0 ocu8_otd0 icu8_in0 ppg8_tout0 eint8 p3_24 0 0 0 0 0 0 0 0 0 p5_28 eint12 ppg10_tout0 icu10_in0 ocu10_otd0 0 tin0 0 cap0_data4 dsp0_data_d0- dsp0_data1_0 d 35 158 s an28 0 bp0(bh0) pwm2p0 ocu7_otd1 icu7_in1 ppg7_tout2 eint7 p3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 36 157 s an27 0 an0(al0) pwm1m0 ocu7_otd0 icu7_in0 ppg7_tout0 eint6 p3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 37 156 t trace6 0 0 0 0 0 0 0 0 p6_09 0 0 0 0 0 0 0 0 p5_29 eint13 ppg10_tout2 icu10_in1 ocu10_otd1 0 tot1 0 cap0_data5 dsp0_data_d1+ dsp0_data0_1 d 38 155 s an26 0 ap0(ah0) pwm1p0 ocu6_otd1 icu6_in1 ppg6_tout2 eint5 p3_21 0 0 0 0 0 0 0 0 0 p5_30 eint14 ppg11_tout0 icu11_in0 ocu11_otd0 sot0 tin1 0 cap0_data6 dsp0_data_d1- dsp0_data1_1 d 39 154 - dvcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p5_31 eint15 ppg11_tout2 icu11_in1 ocu11_otd1 sck0 tot2 0 cap0_data7 dsp0_data_d2+ dsp0_data0_2 d 40 153 - dvss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p6_00 eint0 ppg0_tout0 icu0_in0 ocu0_otd0 0 tin2 0 cap0_data8 dsp0_data_d2- dsp0_data1_2 d 41 152 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 42 151 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 43 150 - vcc12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_00 eint1 ppg0_tout2 icu0_in1 ocu0_otd1 0 tot3 0 cap0_data9 dsp0_data_d3+ dsp0_data0_3 d 44 149 - avss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p0_01 eint2 ppg1_tout0 icu1_in0 ocu1_otd0 0 tin3 txen cap0_data10 dsp0_data_d3- dsp0_data1_3 d 45 148 - avrh5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 46 147 - avcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 47 146 h 0 0 0 0 ocu6_otd0 icu6_in0 ppg6_tout0 eint4 p3_20 0 0 0 0 0 0 0 0 0 p0_02 eint3 ppg1_tout2 icu1_in1 ocu1_otd1 0 tot16 col cap0_data11 dsp0_data_d4+ dsp0_data0_4 d 48 145 h 0 0 sgo3 tin35 ocu5_otd1 icu5_in1 ppg5_tout2 eint3 p3_19 0 0 0 0 0 0 0 0 0 p0_03 eint4 ppg2_tout0 icu2_in0 ocu2_otd0 0 tin16 crs cap0_data12 dsp0_data_d4- dsp0_data1_4 d 49 144 h adtrg 0 sga3 tot35 ocu5_otd0 icu5_in0 ppg5_tout0 eint2 p3_18 0 0 0 cap0_data11 g_ck_2 0 0 0 0 p0_04 eint5 ppg2_tout2 icu2_in1 ocu2_otd1 0 tot17 txd0 cap0_data13 dsp0_data_d5+ dsp0_data0_5 d 50 143 - c 0 0 0 0 0 0 0 0 0 0 0 cap0_data12 g_dq3_2 0 0 0 0 p0_05 eint6 ppg3_tout0 icu3_in0 ocu3_otd0 sin0 tin17 txd1 cap0_data14 dsp0_data_d5- dsp0_data1_5 d 51 142 - vss 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 52 141 - vcc5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 53 140 q rstx 0 0 0 0 0 0 0 0 0 0 0 cap0_data13 g_dq2_2 0 0 0 0 p0_06 eint7 ppg3_tout2 icu3_in1 ocu3_otd1 0 tot18 txd2 cap0_data15 dsp0_data_d6+ dsp0_data0_6 d 54 139 p mode 0 0 0 0 0 0 0 0 0 0 0 cap0_data14 g_dq1_2 0 0 0 0 p0_07 eint8 ppg4_tout0 icu4_in0 ocu4_otd0 0 tin18 txd3 cap0_data16 dsp0_data_d6- dsp0_data1_6 d 55 138 i trace5 0 0 0 0 0 0 0 0 p6_08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 56 137 n2 jtag_tms 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 57 136 n2 jtag_tck 0 0 0 0 0 0 0 0 0 0 0 cap0_data15 g_dq0_2 0 0 0 0 p0_08 eint9 ppg4_tout2 icu4_in1 ocu4_otd1 0 tot19 rxd0 cap0_data17 dsp0_data_d7+ dsp0_data0_7 d 58 135 n2 jtag_tdi 0 0 0 0 0 0 0 0 0 0 0 0 g_cs#1_2 0 0 0 0 p0_09 eint10 ppg5_tout0 icu5_in0 ocu5_otd0 0 tin19 rxd1 cap0_data18 dsp0_data_d7- dsp0_data1_7 d 59 134 o jtag_tdo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 60 133 h trace4 0 0 0 0 0 0 0 0 p6_07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcc3 - 61 132 n jtag_ntrst 0 0 0 0 0 0 0 0 0 0 0 0 g_rwds_2 0 0 0 0 p0_10 eint11 ppg5_tout2 icu5_in1 ocu5_otd1 i2s0_eclk tot32 rxd2 cap0_data19 dsp0_data_d8+ dsp0_data0_8 d 62 131 m x0 0 0 0 0 0 0 0 0 0 0 0 0 g_cs#2_2 0 0 0 0 p0_11 eint12 ppg6_tout0 icu6_in0 ocu6_otd0 i2s0_sd tin32 rxd3 cap0_data20 dsp0_data_d8- dsp0_data1_8 d 63 130 m x1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vss - 64 129 - vss 0 0 0 0 0 0 0 0 0 0 0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 - d d - - d d - - d d c c - - e - - e e e e e - e - - e e e e e - - f f f - - - g h i j j i h i i h i i h j j h i i h i i i l - vcc3 dsp0_data0_9 dsp0_data1_9 vss vcc3 dsp0_data0_10 dsp0_data1_10 vss vcc3 dsp0_data0_11 dsp0_data1_11 0 dsp0_ctrl0 vcc12 vss m_sclk0 vss vcc3 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 vss 0 vss vcc3 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 vss vcc3 mlbdat mlbsig mlbclk vcc12 vss vcc5 psc_1 0 an0 an1 an2 an3 0 an4 an5 trace0 an6 an7 trace1 an8 an9 trace2 an10 an11 trace3 an12 an13 an14 nmix vcc5 0 dsp0_data_d9+ dsp0_data_d9- 0 0 dsp0_data_d10+ dsp0_data_d10- 0 0 dsp0_data_d11+ dsp0_data_d11- 0 dsp0_ctrl2 0 0 0 0 0 g_sdata1_0 g_sdata1_2 g_sdata1_1 g_ssel1 g_sdata1_3 0 g_sclk0 0 0 g_sdata0_0 g_sdata0_2 g_sdata0_1 g_ssel0 g_sdata0_3 0 0 dsp0_ctrl2 dsp0_ctrl3 dsp0_ctrl4 0 0 0 0 0 0 sot0 sck0 sin0 0 0 sot1 0 sck1 sin1 0 sot16 sck16 0 sin16 sot8 0 sck8 sin8 0 0 0 0 cap0_data21 cap0_data22 0 0 cap0_data23 cap0_data32 0 0 cap0_data33 cap0_clk 0 cap0_data34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data24 cap0_data25 0 0 0 0 0 0 0 sot17 sck17 sin17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap0_data32 cap0_data35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mfs17_sda mfs17_scl 0 0 0 0 0 0 0 0 mfs16_sda mfs16_scl 0 0 0 0 0 0 0 0 0 0 txclk rxclk 0 0 rxer rxdv 0 0 col 0 0 txer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rx0 0 tx0 rx1 tx1 0 0 0 tot33 tin33 0 0 tot34 tin34 0 0 tot35 tin35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tin49 0 0 0 0 0 tin0 tin1 0 tin2 tin3 0 tot0 tot1 0 tot2 tot3 0 tin16 tot16 tin17 0 0 0 i2s0_ws i2s0_sck 0 0 i2s1_eclk i2s1_sd 0 0 i2s1_ws i2s1_sck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgo0 sga0 sga1 sgo1 0 sga2 sgo2 0 sga3 sgo3 0 sgo0 sga0 0 sga1 sgo1 0 sga2 sgo2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sot1 sck1 sin1 0 0 0 0 0 ain8 bin8 zin8 0 0 0 ain9 0 bin9 zin9 0 0 0 0 0 0 0 0 0 0 0 0 0 ocu6_otd1 ocu7_otd0 0 0 ocu7_otd1 ocu8_otd0 0 0 ocu8_otd1 ocu9_otd0 0 ocu10_otd0 0 0 ocu11_otd0 0 0 ocu9_otd0 ocu10_otd0 ocu9_otd1 ocu8_otd1 ocu10_otd1 0 ocu5_otd1 0 0 ocu6_otd0 ocu7_otd0 ocu6_otd1 ocu8_otd0 ocu7_otd1 0 0 0 0 ocu4_otd1 0 0 0 0 ocu3_otd0 ocu4_otd0 ocu4_otd1 ocu5_otd0 ocu5_otd1 0 ocu6_otd0 ocu6_otd1 0 ocu7_otd0 ocu7_otd1 0 ocu8_otd0 ocu8_otd1 0 ocu9_otd0 ocu9_otd1 0 ocu10_otd0 ocu10_otd1 ocu11_otd0 0 0 0 icu6_in1 icu7_in0 0 0 icu7_in1 icu8_in0 0 0 icu8_in1 icu9_in0 0 icu10_in0 0 0 icu11_in0 0 0 icu9_in0 icu10_in0 icu9_in1 icu8_in1 icu10_in1 0 icu5_in1 0 0 icu6_in0 icu7_in0 icu6_in1 icu8_in0 icu7_in1 0 0 0 0 icu4_in1 0 0 0 0 icu3_in0 icu4_in0 icu4_in1 icu5_in0 icu5_in1 0 icu6_in0 icu6_in1 0 icu7_in0 icu7_in1 0 icu8_in0 icu8_in1 0 icu9_in0 icu9_in1 0 icu10_in0 icu10_in1 icu11_in0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg0/1/2/3/4/5_tin1 0 0 0 frt8/9/10/11_text 0 0 0 0 0 0 0 0 0 0 0 0 0 ppg6_tout2 ppg7_tout0 0 0 ppg7_tout2 ppg8_tout0 0 0 ppg8_tout2 ppg9_tout0 0 ppg10_tout0 0 0 ppg11_tout0 0 0 ppg9_tout0 ppg10_tout0 ppg9_tout2 ppg8_tout2 ppg10_tout2 0 ppg5_tout2 0 0 ppg6_tout0 ppg7_tout0 ppg6_tout2 ppg8_tout0 ppg7_tout2 0 0 0 0 ppg4_tout2 0 0 0 0 ppg3_tout0 ppg4_tout0 ppg4_tout2 ppg5_tout0 ppg5_tout2 0 ppg6_tout0 ppg6_tout2 0 ppg7_tout0 ppg7_tout2 0 ppg8_tout0 ppg8_tout2 0 ppg9_tout0 ppg9_tout2 0 ppg10_tout0 ppg10_tout2 ppg11_tout0 0 0 0 eint13 eint14 0 0 eint15 eint0 0 0 eint1 eint2 0 eint4 0 0 eint0 0 0 eint12 eint14 eint13 eint11 eint15 0 eint5 0 0 eint6 eint8 eint7 eint10 eint9 0 0 eint1 eint2 eint3 0 0 0 0 eint6 eint8 eint9 eint10 eint11 0 eint12 eint13 0 eint14 eint15 0 eint0 eint1 0 eint2 eint3 0 eint4 eint5 eint6 0 0 0 p0_12 p0_13 0 0 p0_14 p0_15 0 0 p0_16 p0_17 p6_01 p5_22 0 0 p1_09 0 0 p1_05 p1_07 p1_06 p1_04 p1_08 0 p0_30 0 0 p0_31 p1_01 p1_00 p1_03 p1_02 0 0 p0_26 p0_27 p0_28 0 0 0 0 p2_22 p2_24 p2_25 p2_26 p2_27 p6_02 p2_28 p2_29 p6_03 p2_30 p2_31 p6_04 p3_00 p3_01 p6_05 p3_02 p3_03 p6_06 p3_04 p3_05 p3_06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 m_ck_0 0 0 m_dq3_0 m_dq2_0 m_dq1_0 m_dq0_0 m_cs#1_0 0 m_rwds_0 0 0 m_cs#2_0 m_dq4_0 m_dq5_0 m_dq6_0 m_dq7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicator0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g_dq4_2 g_dq5_2 0 0 g_dq6_2 g_dq7_2 0 0 0 0 0 0 0 0 g_ck_1 0 0 g_dq3_1 g_dq2_1 g_dq1_1 g_dq0_1 g_cs#1_1 0 g_rwds_1 0 0 g_cs#2_1 g_dq4_1 g_dq5_1 g_dq6_1 g_dq7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp0_ctrl2 0 0 dsp0_clk dsp0_ctrl0 0 dsp0_ctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trace0 trace1 0 trace2 trace3 0 trace_clk trace_ctl 0 0 0 top view teqfp-256
document number: 002 - 05682 rev.*a page 35 of 179 S6J3200 series 4.2 package dimensions function digit teqfp - 216 teqfp - 208 3,4,5,6,7,8 figure 4 - 17 figure 4 - 18 a, b, c, d figure 4 - 19 note: ? s ame size is specified for min, nom, max, then it should be regarded as maximum size.
document number: 002 - 05682 rev.*a page 36 of 179 S6J3200 series 4.2.1 teqfp216 figure 4 - 17 leq216
document number: 002 - 05682 rev.*a page 37 of 17 9 S6J3200 series 4.2.2 teqfp208 figure 4 - 18 : let208
document number: 002 - 05682 rev.*a page 38 of 179 S6J3200 series figure 4 - 19 :ler208
document number: 002 - 05682 rev.*a page 39 of 179 S6J3200 series 5. i/o circuit type 5.1 i/o circuit type this section explains i/o circuit types. type circuit remark a ? analog output(3v) ? audio dac output b ? analog output(3v) ? lvds output c ? general - purpose i/o port ? output 2ma, 5ma, 10ma or 20ma selectable ? 33k with pull - up resistor control ? 33k with pull - down resistor control ? cmos hysteresis input ? ttl input analog output pull - up control digital output digital output pull - down control pss control ttl input pss control cmos - hys input
document number: 002 - 05682 rev.*a page 40 of 179 S6J3200 series type circuit remark d ? general - purpose i/o port ? output 2ma, 5ma, 10ma or 20ma selectable ? 33k with pull - up resistor control ? 33k with pull - down resistor control ? cmos hysteresis input ? ttl input ? rsds differential output data e ? general - purpose i/o port ? output 2ma, 5ma or 10ma se lectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? ttl input pull - up control digital output digital output pull - down control pss control ttl input pss control cmos - hys input pull - up control digital output digital output pull - down control pss control ttl input pss control cmos - hys input rsds mode control rsds output data rsds output enable control logic pull - up control digital output digital output pull - down control pss control ttl input pss control cmos - hys input
document number: 002 - 05682 rev.*a page 41 of 179 S6J3200 series type circuit remark f ? general - purpose i/o port ? output 2ma, 5ma, 6ma or 10ma selectable ? 33k with pull - up resistor control ? 33k with pull - down resistor control ? cmos hysteresis input ? medialb level hysteresis input g ? external 1.2v regulator control ? output 2ma h ? general - purpose i/o port ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input i ? general - purpose i/o port with analog input ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input pull - up control digital output digital output pull - down control pss control medialb - hys input pss control cmos - hys input digital output digital output pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input
document number: 002 - 05682 rev.*a page 42 of 179 S6J3200 series type circuit remark j ? general - purpose i/o port with analog input ? output 1ma, 2ma, 3ma(i 2 c) or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input l ? 50k with pull - up ? cmos hysteresi s input m ? main oscillation i/o n ? jtag_ntrst ? 50k with pull - down ? ttl input n2 ? jtag_tdi/tms/tck ? 50k with pull - up ? ttl input o ? jtag_tdo ? output 5ma pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input ttl input pss control cmos - hys input pss control osc input x0 x1 ttl input ttl input digital output digital output
document number: 002 - 05682 rev.*a page 43 of 179 S6J3200 series type circuit remark p ? mode input ? cmos hysteresis input q ? cmos hysteresis input ? 50k with pull - up s ? general - purpose i/o port with analog input ? output 1ma, 2ma, 5ma or 30ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input t ? general - purpose i/o port ? output 1ma, 2ma, 5ma or 30ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input control mode input cmos - hys input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input
document number: 002 - 05682 rev.*a page 44 of 179 S6J3200 series type circuit remark u ? general - purpose input port with lcdc reference voltage input ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input v ? general - purpose i/o port with analog input and lcdc reference voltage input ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input w ? general - purpose i/o port with analog input and lcdc com/seg output ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input pull - up control pull - down control pss control automotive input pss control cmos - hys input lcdc reference voltage input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input lcdc reference voltage input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input lcdc com/seg output
document number: 002 - 05682 rev.*a page 45 of 179 S6J3200 series type circuit remark x ? sub oscillation i/o shared general - purpose i/o port ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input y ? general - purpose i/o port with lcdc com/seg output ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input pss/osc control osc input pull - up control digital output digital output pull - down control pss/osc control automotive input pss/osc control cmos - hys input pull - up control digital output digital output pull - down control pss/osc control automotive input pss/osc control cmos - hys input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input lcdc com/seg output ttl input pss control
document number: 002 - 05682 rev.*a page 46 of 179 S6J3200 series type circuit remark z ? general - purpose i/o port ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input 5.2 note alphabet which shows i/o circuit type is described with corresponding pin number in pin assignment figure. pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input ttl input pss control
document number: 002 - 05682 rev.*a page 47 of 179 S6J3200 series 6. port description 6.1 p ort description list t he table shows the port function of description which is supported. t he port function which is not describe d in the table is not supported for the product. port name description package pin number remark teqfp208 teqfp216 vcc12 +1.2v power supply pin 11, 28, 61, 85, 122, 123, 182, 183 11, 28, 63, 87, 128, 129, 190, 191 vcc5 +5.0v power supply pin 87, 104, 115, 157, 171 89, 108, 119, 163, 179 vcc3 +3.3v power supply pin 30, 43, 53, 65, 74, 81 30, 43, 55, 67, 76, 83 vcc53 +3.3v/+5.0v selection power supply pin 173, 185, 194, 208 181, 193, 202, 216 vcc3_lvds_tx lvds tx power supply pin 14, 27 14, 27 vss gnd 1, 10, 29, 42, 52, 62, 64, 71, 73, 80, 86, 105, 116, 124, 158, 172, 184, 195 1, 10, 29, 42, 54, 64, 66, 73, 75, 82, 88, 109, 120, 130, 164, 180, 192, 203 vss_lvds_tx lvds tx gnd 15, 26 15, 26 avcc3_dac audio dac power supply pin 6 6 avcc3_lvds_pll lvds pll power supply pin 13 13 avss_lvds_pll lvds pll gnd 12 12 avcc5 a/d converter analog power supply pin 119 125 avrh5 a/d converter upper limit reference voltage pin 120 126 avss a/d converter gnd 2, 5, 9, 121 2, 5, 9, 127 dvcc smc large current port power supply pin 126, 136, 146,156 132, 142, 152,162 dvss smc large current port gnd 125, 135, 145,155 131, 141, 151, 161 x1 main clock oscillator output pin 106 110 x0 main clock oscillator input pin 107 111 x1a sub - clock oscillator output 169 177 x0a sub - clock oscillator input 170 178 nmix non - maskable interrupt input pin 103 107 rstx external reset input pin 114 118 psc_1 external power supply control pin 88 90 mode mode pin 113 117 c external capacity connection output pin 117 121 jtag_ntrst jtag test reset input pin 108 112 jtag_tdo jtag test data output pin 109 113 jtag_tdi jtag test data input pin 110 114 jtag_tck jtag test clock input pin 111 115 jtag_tms jtag test mode state input pin 112 116 trace0 trace data 0 output pin 96 100 trace1 trace data 1 output pin 97 101
document number: 002 - 05682 rev.*a page 48 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 trace2 trace data 2 output pin 98 102 trace3 trace data 3 output pin 99 103 trace_clk trace clock 100 104 trace_ctl trace control 101 105 adtrg a/d converter external trigger input pin 118 122 an0 adc analog 0 input pin - 92 an1 adc analog 1 input pin 90 93 an2 adc analog 2 input pin 91 94 an3 adc analog 3 input pin 92 95 an4 adc analog 4 input pin - 96 an5 adc analog 5 input pin 93 97 an6 adc analog 6 input pin 94 98 an7 adc analog 7 input pin 95 99 an8 adc analog 8 input pin 96 100 an9 adc analog 9 input pin 97 101 an10 adc analog 10 input pin 98 102 an11 adc analog 11 input pin 99 103 an12 adc analog 12 input pin 100 104 an13 adc analog 13 input pin 101 105 an14 adc analog 14 input pin 102 106 an15 adc analog 15 input pin 160 166 an16 adc analog 16 input pin 161 167 an17 adc analog 17 input pin 162 168 an18 adc analog 18 input pin - 169 an19 adc analog 19 input pin - 170 an20 adc analog 20 input pin 163 171 an21 adc analog 21 input pin 164 172 an22 adc analog 22 input pin 165 173 an23 adc analog 23 input pin 166 174 an24 adc analog 24 input pin 167 175 an25 adc analog 25 input pin 168 176 an26 adc analog 26 input pin 127 133 an27 adc analog 27 input pin 128 134 an28 adc analog 28 input pin 129 135 an29 adc analog 29 input pin 130 136 an30 adc analog 30 input pin 131 137 an31 adc analog 31 input pin 132 138 an32 adc analog 32 input pin 133 139 an33 adc analog 33 input pin 134 140 an34 adc analog 34 input pin 137 143 an35 adc analog 35 input pin 138 144 an36 adc analog 36 input pin 139 145 an37 adc analog 37 input pin 140 146 an38 adc analog 38 input pin 141 147 an39 adc analog 39 input pin 142 148 an40 adc analog 40 input pin 143 149 an41 adc analog 41 input pin 144 150 an42 adc analog 42 input pin 147 153 an43 adc analog 43 input pin 148 154
document number: 002 - 05682 rev.*a page 49 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 an44 adc analog 44 input pin 149 155 an45 adc analog 45 input pin 150 156 an46 adc analog 46 input pin 151 157 an47 adc analog 47 input pin 152 158 an48 adc analog 48 input pin 153 159 an49 adc analog 49 input pin 154 160 tx0 can transmission data 0 output pin 100 104 tx1 can transmission data 1 output pin 102, 154 106, 160 tx5 can transmission data 5 output pin 162, 166 168, 174 tx6 can transmission data 6 output pin 168 170, 176 rx0 can reception data 0 input pin 99 103 rx1 can reception data 1 input pin 101, 153 105, 159 rx5 can reception data 5 input pin 161, 165 167, 173 rx6 can reception data 6 input pin 167 169. 175 eint0 external interrupt input pin 33, 39, 57, 63, 96, 140, 167, 170, 177,199 33, 39, 59, 65, 100, 146, 175, 178, 185, 207 eint1 external interrupt input pin 40, 58, 82, 97, 141, 168, 169, 178, 200 40, 60, 84, 101, 147, 176, 177, 186,208, eint2 external interrupt input pin 41, 59, 83, 98, 118, 142, 179, 201, 41, 61, 85, 102, 122, 148, 187, 209 eint3 external interrupt input pin 31, 84, 99, 143, 159, 180, 202 31, 44, 86, 1 03, 123, 149, 165, 188, 210 eint4 external interrupt input pin 60, 100, 144, 181, 203 45, 62, 104, 124, 150, 189, 211 eint5 external interrupt input pin 44, 72, 101, 127, 147, 186 46, 74, 105, 133, 153, 194, eint6 external interrupt input pin 45, 75, 89, 102, 128, 148, 187, 47, 77, 91, 106, 134, 154, 195 eint7 external interrupt input pin 46, 77, 129, 149, 160, 188 48, 79, 135, 155, 166, 196 eint8 external interrupt input pin 47, 76, 130, 150, 161, 189 49, 78, 92, 136, 156, 167, 197 eint9 external interrupt input pin 48, 79, 90, 131, 151, 162, 190 204 50, 81, 93, 137, 157, 168, 198, 212, eint10 external interrupt input pin 49, 78, 91, 132, 152, 191,205 51, 80, 94, 138, 158, 169, 199, 213
document number: 002 - 05682 rev.*a page 50 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 eint11 external interrupt input pin 34, 50, 69, 92, 133, 153, 192, 206 34,52,71, 95,139,159, 170, 200, 214 eint12 external interrupt input pin 35, 51, 66, 134, 154, 163, 193, 207 35, 53, 68, 96, 140, 160, 171, 201, 215 eint13 external interrupt input pin 36, 54, 68, 93, 137, 164, 174, 196 36, 56, 70 , 97, 143, 172, 182, 204 eint14 external interrupt input pin 37, 55, 67, 94, 138, 165, 175, 197 37, 57, 69, 98, 144, 173, 183, 205 eint15 external interrupt input pin 32, 38, 56, 70, 95, 139, 166, 176, 198 32, 38, 58, 72, 99, 145, 174, 184, 206 mfs0_cs0 multi - function serial ch. 0 chip select 0 pin 148 154 mfs0_cs1 multi - function serial ch. 0 chip select 1 pin 153 159 mfs0_cs2 multi - function serial ch. 0 chip select 2 pin 154 160 mfs0_cs3 multi - function serial ch. 0 chip select 3 pin 152 158 mfs2_cs0 multi - function serial ch. 2 chip select 0 pin 149 155 mfs2_cs1 multi - function serial ch. 2 chip select 1 pin 150 156 mfs8_cs0 multi - function serial ch. 8 chip select 0 pin 163, 191 171, 199 mfs8_cs1 multi - function serial ch. 8 chip select 1 pin 167, 198 175, 206 mfs8_cs2 multi - function serial ch. 8 chip select 2 pin 168, 199 176, 207 mfs8_cs3 multi - function serial ch. 8 chip select 3 pin 166, 197 174, 205 mfs9_cs0 multi - function serial ch. 9 chip select 0 pin 164, 192 172, 200 mfs9_cs1 multi - function serial ch. 9 chip select 1 pin 165, 193 173, 201 sck0 multi - function serial ch.0 clock i/o pin 38, 91 38, 94 sck1 multi - function serial ch.1 clock i/o pin 83, 94 85, 98 sck2 multi - function serial ch.2 clock i/o pin 143 149 sck3 multi - function serial ch.3 clock i/o pin 149 155 sck4 multi - function serial ch.4 clock i/o pin 153 159 sck8 multi - function serial ch.8 clock i/o pin 100, 180 104, 188 sck9 multi - function serial ch.9 clock i/o pin 161, 188 167, 196 sck10 multi - function serial ch.10 clock i/o pin 164, 192 172, 200 sck11 multi - function serial ch.11 clock i/o pin 167, 198, 206 175, 206, 214 sck12 multi - function serial ch.12 clock i/o pin 202 210 sck16 multi - function serial ch.16 clock i/o pin 97 101 sck17 multi - function serial ch.17 clock i/o pin 91 94 sin0 multi - function serial ch.0 serial data input pin 45, 92 47, 95 sin1 multi - function serial ch.1 serial data input pin 84, 95 86, 99 sin2 multi - function serial ch.2 serial data input pin 144 150 sin3 multi - function serial ch.3 serial data input pin 150 156
document number: 002 - 05682 rev.*a page 51 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 sin4 multi - function serial ch.4 serial data input pin 154 160 sin8 multi - function serial ch.8 serial data input pin 101, 181 105, 189 sin9 multi - function serial ch.9 serial data input pin 162, 189 168, 197 sin10 multi - function serial ch.10 serial data input pin 165, 193 173, 201 sin11 multi - function serial ch.11 serial data input pin 168, 199, 207 176, 207, 215 sin12 multi - function serial ch.12 serial data input pin 203 211 sin16 multi - function serial ch.16 serial data input pin 98 102 sin17 multi - function serial ch.17 serial data input pin 92 95 sot0 multi - function serial ch.0 serial data output pin 37, 90 37, 93 sot1 multi - function serial ch.1 serial data output pin 82, 93 84, 97 sot2 multi - function serial ch.2 serial data output pin 142 148 sot3 multi - function serial ch.3 serial data output pin 148 154 sot4 multi - function serial ch.4 serial data output pin 152 158 sot8 multi - function serial ch.8 serial data output pin 99, 179 103, 187 sot9 multi - function serial ch.9 serial data output pin 160, 187 166, 195 sot10 multi - function serial ch.10 serial data output pin 163, 191 171, 199 sot11 multi - function serial ch.11 serial data output pin 166, 197, 205 174, 205, 213 sot12 multi - function serial ch.12 serial data output pin 201 209 sot16 multi - function serial ch.16 serial data output pin 96 100 sot17 multi - function serial ch.17 serial data output pin 90 93 s cl 4 i 2 c ch. 4 clock i/o pin 153 159 s cl10 i 2 c ch.1 0 clock i/o pin 192 200 scl12 i 2 c ch.1 2 clock i/o pin 202 210 scl16 i 2 c ch.16 clock i/o pin 97 101 scl17 i 2 c ch.17 clock i/o pin 91 94 sda 4 i 2 c ch. 4 serial data i/o pin 152 158 sda1 0 i 2 c ch.1 0 serial data i/o pin 191 199 sda1 2 i 2 c ch.1 2 serial data i/o pin 201 209 sda16 i 2 c ch.16 serial data i/o pin 96 100 sda17 i 2 c ch.17 serial data i/o pin 90 93 ppg0_tout0 base timer 0 output pin 39, 140, 161, 170, 199 39, 146, 167, 178, 207 ppg0_tout2 base timer 1 output pin 40, 141, 162, 169, 200, 204 40, 147, 168, 177, 208, 212
document number: 002 - 05682 rev.*a page 52 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 ppg1_tout0 base timer 2 output pin 41,142,201, 205 41,148,169, 209,213 ppg1_tout2 base timer 3 output pin 143, 202, 206 44, 149, 170, 210, 214 ppg2_tout0 base timer 4 output pin 144, 163, 203, 207 45, 150, 171, 211, 215 ppg2_tout2 base timer 5 output pin 44, 147, 164, 174 46, 153, 172, 182 ppg3_tout0 base timer 6 output pin 45, 89, 148, 165, 175 47, 91, 154, 173, 183 ppg3_tout2 base timer 7 output pin 32, 46, 149, 166, 176 32, 48, 155, 174, 184 ppg4_tout0 base timer 8 output pin 33, 47, 150, 167, 177 33, 49, 92, 156, 175, 185 ppg4_tout2 base timer 9 output pin 48, 84, 90, 151, 168, 178 50, 86, 93, 157, 176, 186 ppg5_tout0 base timer 10 output pin 49, 91, 118, 152, 179 51, 94, 122, 158, 187 ppg5_tout2 base timer 11 output pin 50, 72, 92, 153, 180 52, 74, 95, 123, 159, 188 ppg6_tout0 base timer 12 output pin 51, 75, 154, 181 53, 77, 96, 124, 160,189 ppg6_tout2 base timer 13 output pin 54, 77, 93, 127, 186 56, 79, 97, 133, 194 ppg7_tout0 base timer 14 output pin 55, 76, 94, 128, 187 57, 78, 98, 134, 195 ppg7_tout2 base timer 15 output pin 56, 79, 95, 129, 188 58, 81, 99, 135, 196 ppg8_tout0 base timer 16 output pin 57, 78, 96, 130, 189 59, 80, 100, 136, 197 ppg8_tout2 base timer 17 output pin 58, 69, 97, 131, 190 60, 71, 101, 137, 198 ppg9_tout0 base timer 18 output pin 59, 66, 98, 132, 191 61, 68, 102, 138, 199 ppg9_tout2 base timer 19 output pin 31, 34, 68, 99, 133, 192 31, 34, 70, 103, 139, 200 ppg10_tout0 base timer 20 output pin 35, 60, 67, 100, 134, 193 35, 62, 69, 104, 140, 201 ppg10_tout2 base timer 21 output pin 36, 70, 101, 137, 196 36, 72, 105, 143, 204 ppg11_tout0 base timer 22 output pin 37, 63, 102, 138, 197 37, 65, 106, 144, 205 ppg11_tout2 base timer 23 output pin 38, 139, 160, 198 38, 145, 166, 206 ppg0/1/2/3/4/5_tin 1 base timer 0/2/4/6/8/10 input pin - 96 ppg6/7/8/9/10/11_ tin 1 base timer 12/14/16/18/20/22 input pin 161 167 wot rtc overflow output pin 161 167 pwm1m0 smc ch.0 output pin 128 134 pwm1m1 smc ch.1 output pin 132 138 pwm1m2 smc ch.2 output pin 138 144 pwm1m3 smc ch.3 output pin 142 148
document number: 002 - 05682 rev.*a page 53 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 pwm1m4 smc ch.4 output pin 148 154 pwm1m5 smc ch.5 output pin 152 158 pwm1p0 smc ch.0 output pin 127 133 pwm1p1 smc ch.1 output pin 131 137 pwm1p2 smc ch.2 output pin 137 143 pwm1p3 smc ch.3 output pin 141 147 pwm1p4 smc ch.4 output pin 147 153 pwm1p5 smc ch.5 output pin 151 157 pwm2m0 smc ch.0 output pin 130 136 pwm2m1 smc ch.1 output pin 134 140 pwm2m2 smc ch.2 output pin 140 146 pwm2m3 smc ch.3 output pin 144 150 pwm2m4 smc ch.4 output pin 150 156 pwm2m5 smc ch.5 output pin 154 160 pwm2p0 smc ch.0 output pin 129 135 pwm2p1 smc ch.1 output pin 133 139 pwm2p2 smc ch.2 output pin 139 145 pwm2p3 smc ch.3 output pin 143 149 pwm2p4 smc ch.4 output pin 149 155 pwm2p5 smc ch.5 output pin 153 159 ocu0_otd0 output compare 0 ch.0 output pin 39, 140, 161, 170, 199 39, 146, 167, 178, 207 ocu0_otd1 output compare 0 ch. 1 output pin 40, 141, 162, 169, 200, 204 40, 147, 168, 177, 208, 212 ocu1_otd0 output compare 1 ch. 0 output pin 41, 142, 201, 205 41, 148, 169, 209, 213 ocu1_otd1 output compare 1 ch.1 output pin 143, 202, 206 44, 149, 170, 210, 214 ocu2_otd0 output compare 2 ch. 0 output pin 144, 163, 203, 207 45, 150, 171, 211, 215 ocu2_otd1 output compare 2 ch. 1 output pin 44, 147, 164, 174 46, 153, 172, 182 ocu3_otd0 output compare 3 ch. 0 output pin 45, 89, 148, 165, 175 47, 91, 154, 173, 183 ocu3_otd1 output compare 3 ch. 1 output pin 32, 46, 149, 166, 176 32, 48, 155, 174, 184 ocu4_otd0 output compare 4 ch. 0 output pin 33, 47, 150, 167, 177 33, 49, 92, 156, 175, 185 ocu4_otd1 output compare 4 ch. 1 output pin 48, 84, 90, 151, 168, 178 50, 86, 93, 157, 176, 186 ocu5_otd0 output compare 5 ch. 0 output pin 49, 91, 118, 152, 179 51, 94, 122, 158, 187 ocu5_otd1 output compare 5 ch. 1 output pin 50, 72, 92, 153, 180 52, 74, 95, 123, 159, 188 ocu6_otd0 output compare 6 ch. 0 output pin 51, 75, 154, 181 53, 77, 96, 124, 160, 189 ocu6_otd1 output compare 6 ch. 1 output pin 54, 77, 93, 127, 186 56, 79, 97, 133, 194
document number: 002 - 05682 rev.*a page 54 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 ocu7_otd0 output compare 7 ch. 0 output pin 55, 76, 94, 128, 187 57, 78, 98, 134, 195 ocu7_otd1 output compare 7 ch. 1 output pin 56, 79, 95, 129, 188 58, 81, 99, 135, 196 ocu8_otd0 output compare 8 ch. 0 output pin 57, 78, 96, 130, 189 59, 80, 100, 136, 197 ocu8_otd1 output compare 8 ch. 1 output pin 58, 69, 97, 131, 190 60, 71, 101, 137, 198 ocu9_otd0 output compare 9 ch. 0 output pin 59, 66, 98, 132, 191 61, 68, 102, 138, 199 ocu9_otd1 output compare 9 ch. 1 output pin 31, 34, 68, 99, 133, 192 31, 34, 70, 103, 139, 200 ocu10_otd0 output compare 10 ch. 0 output pin 35, 60, 67, 100, 134, 193 35, 62, 69, 104, 140, 201 ocu10_otd1 output compare 10 ch. 1 output pin 36, 70, 101, 137, 196 36, 72, 105, 143, 204 ocu11_otd0 output compare 11 ch. 0 output pin 37, 63, 102, 138, 197 37, 65, 106, 144, 205 ocu11_otd1 output compare 11 ch. 1 output pin 38, 139, 160, 198 38, 145, 166, 206 icu0_in0 input capture 0 ch.0 input pin 39, 140, 161, 170, 199 39, 146, 167, 178, 207 icu0_in1 input capture 0 ch. 1 input pin 40, 141, 162, 169, 200, 204 40, 147, 168, 177, 208, 212 icu1_in0 input capture 1 ch. 0 input pin 41, 142, 201, 205 41, 148, 169, 209, 213 icu1_in1 input capture 1 ch.1 input pin 143, 159, 202, 206 44, 149, 165, 170, 210, 214 icu2_in0 input capture 2 ch. 0 input pin 144, 163, 203, 207 45, 150, 171, 211, 215 icu2_in1 input capture 2 ch. 1 input pin 44, 147, 164, 174 46, 153, 172, 182 icu3_in0 input capture 3 ch. 0 input pin 45, 89, 148, 165, 175 47, 91, 154, 173, 183 icu3_in1 input capture 3 ch. 1 input pin 32, 46, 149, 166, 176 32, 48, 155, 174, 184 icu4_in0 input capture 4 ch. 0 input pin 33, 47, 150, 167, 177 33, 49, 92, 156, 175, 185 icu4_in1 input capture 4 ch. 1 input pin 48, 84, 90, 151, 168, 178 50, 86, 93, 157, 176, 186 icu5_in0 input capture 5 ch. 0 input pin 49, 91, 118, 152, 179 51, 94, 122, 158, 187 icu5_in1 input capture 5 ch. 1 input pin 50, 72, 92, 153, 180 52, 74, 95, 123, 159, 188 icu6_in0 input capture 6 ch. 0 input pin 51, 75, 154, 181 53, 77, 96, 124, 160, 189 icu6_in1 input capture 6 ch. 1 input pin 54, 77, 93, 127, 186 56, 79, 97, 133, 194 icu7_in0 input capture 7 ch. 0 input pin 55, 76, 94, 128, 187 57, 78, 98, 134, 195
document number: 002 - 05682 rev.*a page 55 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 icu7_in1 input capture 7 ch. 1 input pin 56, 79, 95, 129, 188 58, 81, 99, 135, 196 icu8_in0 input capture 8 ch. 0 input pin 57, 78, 96, 130, 189 59, 80, 100, 136, 197 icu8_in1 input capture 8 ch. 1 input pin 58, 69, 97, 131, 190 60, 71, 101, 137, 198 icu9_in0 input capture 9 ch. 0 input pin 59, 66, 98, 132, 191 61, 68, 102, 138, 199 icu9_in1 input capture 9 ch. 1 input pin 31, 34, 68, 99, 133, 192 31, 34, 70, 103, 139, 200 icu10_in0 input capture 10 ch. 0 input pin 35, 60, 67, 100, 134, 193 35, 62, 69, 104, 140, 201 icu10_in1 input capture 10 ch. 1 input pin 36, 70, 101, 137, 196 36, 72, 105, 143, 204 icu11_in0 input capture 11 ch. 0 input pin 37, 63, 102, 138, 197 37, 65, 106, 144, 205 icu11_in1 input capture 11 ch. 1 input pin 38, 139, 160, 198 38, 145, 166, 206 sga0 sound generator ch.0 sga output pin 90, 97, 164 93, 101, 172 sga1 sound generator ch.1 sga output pin 91, 98, 165, 205 94, 102, 173, 213 sga2 sound generator ch.2 sga output pin 100, 167 96, 104, 175 sga3 sound generator ch.3 sga output pin 94, 118, 175 98, 122, 183 sgo0 sound generator ch.0 sgo output pin 96, 163 92, 100, 171 sgo1 sound generator ch.1 sgo output pin 92,99,166,2 06 95,103,174,2 14 sgo2 sound generator ch.2 sgo output pin 93, 101, 168 97, 105, 176 sgo3 sound generator ch.3 sgo output pin 95, 176 99, 123, 184 an0(al0) pcm pwm ch.0 output pin 128, 175 134, 183 an1(al1) pcm pwm ch.1 output pin 132, 179 138, 187 ap0(ah0) pcm pwm ch.0 output pin 127, 174 133, 182 ap1(ah1) pcm pwm ch.1 output pin 131, 178 137, 186 bn0(bl0) pcm pwm ch.0 output pin 130, 177 136, 185 bn1(bl1) pcm pwm ch.1 output pin 134, 181 140, 189 bp0(bh0) pcm pwm ch.0 output pin 129, 176 135, 184 bp1(bh1) pcm pwm ch.1 output pin 133, 180 139, 188 i2s0_eclk i2s external clock ch.0 input pin 50 52 i2s1_eclk i2s external clock ch.1 input pin 56 58 i2s0_sck i2s continuous serial clock ch.0 pin 55 57 i2s1_sck i2s continuous serial clock ch.1 pin 59 61 i2s0_sd i2s serial data ch.0 pin 51 53 i2s1_sd i2s serial data ch.1 pin 57 59 i2s0_ws i2s word select ch.0 pin 54 56 i2s1_ws i2s word select ch.1 pin 58 60 c_l audio dac external capacity connection output pin (l) 8 8 c_r audio dac external capacity connection output pin (r) 4 4 dac_l audio dac output pin (l) 7 7 dac_r audio dac output pin (r) 3 3 frt0/1/2/3_text free - run timer ch.0/1/2/3 clock input pin 160 166 frt4/5/6/7_text free - run timer ch.4/5/6/7 clock input pin 166 174
document number: 002 - 05682 rev.*a page 56 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 frt8/9/10/11_tex t free - run timer ch.4/5/6/7 clock input pin 95 99 tin0 reload timer ch.0 event input pin 35 35, 96 tin1 reload timer ch.1 event input pin 37, 93 37, 97 tin2 reload timer ch.2 event input pin 39, 94 39, 98 tin3 reload timer ch.3 event input pin 41, 95 41, 99 tin16 reload timer ch.16 event input pin 100 45, 104 tin17 reload timer ch.17 event input pin 45, 102 47, 106 tin18 reload timer ch.18 event input pin 47, 162 49, 168 tin19 reload timer ch.19 event input pin 49 51, 170 tin32 reload timer ch.32 event input pin 51, 164 53, 172 tin33 reload timer ch.33 event input pin 55, 166 57, 174 tin34 reload timer ch.34 event input pin 57, 168 59, 176 tin35 reload timer ch.35 event input pin 59 61, 123 tin48 reload timer ch.48 event input pin 159 165 tin49 reload timer ch.49 event input pin 89 91 tot0 reload timer ch.0 output pin 34, 96 34, 100 tot1 reload timer ch.1 output pin 36, 97 36, 101 tot2 reload timer ch.2 output pin 38, 98 38, 102 tot3 reload timer ch.3 output pin 40, 99 40, 103 tot16 reload timer ch.16 output pin 101 44, 105 tot17 reload timer ch.17 output pin 44, 160 46, 166 tot18 reload timer ch.18 output pin 46, 161 48, 167 tot19 reload timer ch.19 output pin 48 50, 169 tot32 reload timer ch.32 output pin 50, 163 52, 171 tot33 reload timer ch.33 output pin 54, 165 56, 173 tot34 reload timer ch.34 output pin 56,167 58, 175 tot35 reload timer ch.35 output pin 58, 118 60, 122 ain8 up/down counter ain input pin ch.8 190 92, 198 ain9 up/down counter ain input pin ch.9 93, 193 97, 201 bin8 up/down counter bin input pin ch.8 90, 191 93, 199 bin9 up/down counter bin input pin ch.9 94, 196 98, 204 zin8 up/down counter zin input pin ch.8 91, 192 94, 200 zin9 up/down counter zin input pin ch.9 95, 197 99, 205 rxd0 ethernet pin 48 50 rxd1 ethernet pin 49 51 rxd2 ethernet pin 50 52 rxd3 ethernet pin 51 53 txd0 ethernet pin 44 46 txd1 ethernet pin 45 47 txd2 ethernet pin 46 48 txd3 ethernet pin 47 49 col ethernet pin 58 44, 60 crs ethernet pin 84 45, 86 rxer ethernet pin 56 58 rxdv ethernet pin 57 59 rxclk ethernet pin 55 57 txer ethernet pin 60 62 txen ethernet pin 41 41 txclk ethernet pin 54 56
document number: 002 - 05682 rev.*a page 57 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 mdc ethernet pin 31 31 mdio ethernet pin 32 32 mlbclk medialb pin 84 86 mlbdat medialb pin 82 84 mlbsig medialb pin 83 85 txclk - lvds clock output pin 21 21 described as txout 4 m in fpd - link converter txclk+ lvds clock output pin 20 20 described as txout 4 p in fpd - link converter txdout0 - lvds data output pin 25 25 described as txout0m in fpd - link converter txdout0+ lvds data output pin 24 24 described as txout0p in fpd - link converter txdout1 - lvds data output pin 23 23 described as txout 1m in fpd - link converter txdout1+ lvds data output pin 22 22 described as txout 1 p in fpd - link converter txdout2 - lvds data output pin 19 19 described as txout 2m in fpd - link converter txdout2+ lvds data output pin 18 18 described as txout 2 p in fpd - link converter txdout3 - lvds data output pin 17 17 described as txout 3m in fpd - link converter txdout3+ lvds data output pin 16 16 described as txout 3 p in fpd - link converter g_sclk0 graphic hs - spi clock output pin 72 74 g_sdata0_0 graphic hs - spi0 data 0 pin 75 77 g_sdata0_1 graphic hs - spi0 data 1 pin 77 79 g_sdata0_2 graphic hs - spi0 data 2 pin 76 78 g_sdata0_3 graphic hs - spi0 data 3 pin 79 81 g_sdata1_0 graphic hs - spi1 data 0 pin 66 68 g_sdata1_1 graphic hs - spi1 data 1 pin 68 70 g_sdata1_2 graphic hs - spi1 data 2 pin 67 69 g_sdata1_3 graphic hs - spi1 data 3 pin 70 72 g_ssel0 graphic hs - spi0 select output pin 78 80 g_ssel1 graphic hs - spi1 select output pin 69 71 g_ck _1 hyper bus 1 clock output pin 63 65 g_cs#1 _1 hyper bus 1 select 1 output pin 70 72 g_cs#2 _1 hyper bus 1 select 2 output pin 75 77 g_dq0 _1 hyper bus 1 data 0 pin 69 71 g_dq1 _1 hyper bus 1 data 1 pin 68 70 g_dq2 _1 hyper bus 1 data 2 pin 67 69 g_dq3 _1 hyper bus 1 data 3 pin 66 68 g_dq4 _1 hyper bus 1 data 4 pin 76 78
document number: 002 - 05682 rev.*a page 58 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 g_dq5 _1 hyper bus 1 data 5 pin 77 79 g_dq6 _1 hyper bus 1 data 6 pin 78 80 g_dq7 _1 hyper bus 1 data 7 pin 79 81 g_rwds _1 hyper bus 1 rwds pin #699 72 74 g_ck _2 hyper bus 2 clock output pin 44 46 g_cs#1 _2 hyper bus 2 select 1 output pin 49 51 g_cs#2 _2 hyper bus 2 select 2 output pin 51 53 g_dq0 _2 hyper bus 2 data 0 pin 48 50 g_dq1 _2 hyper bus 2 data 1 pin 47 49 g_dq2 _2 hyper bus 2 data 2 pin 46 48 g_dq3 _2 hyper bus 2 data 3 pin 45 47 g_dq4 _2 hyper bus 2 data 4 pin 54 56 g_dq5 _2 hyper bus 2 data 5 pin 55 57 g_dq6 _2 hyper bus 2 data 6 pin 56 58 g_dq7 _2 hyper bus 2 data 7 pin 57 59 g_rwds _2 hyper bus 2 rwds pin 50 52 m_sclk0 mcu hs - spi clock output pin 63 65 m_sdata0_0 mcu hs - spi0 data 0 pin 66 68 m_sdata0_1 mcu hs - spi0 data 1 pin 68 70 m_sdata0_2 mcu hs - spi0 data 2 pin 67 69 m_sdata0_3 mcu hs - spi0 data 3 pin 70 72 m_sdata1_0 mcu hs - spi1 data 0 pin 75 77 m_sdata1_1 mcu hs - spi1 data 1 pin 77 79 m_sdata1_2 mcu hs - spi1 data 2 pin 76 78 m_sdata1_3 mcu hs - spi1 data 3 pin 79 81 m_ssel0 mcu hs - spi0 select output pin 69 71 m_ssel1 mcu hs - spi1 select output pin 78 80 m_ck _0 mcu hyper bus clock output pin 63 65 m_cs#1 _0 mcu hyper bus select 1 output pin 70 72 m_cs#2 _0 mcu hyper bus select 2 output pin 75 77 m_dq0 _0 mcu hyper bus data 0 pin 69 71 m_dq1 _0 mcu hyper bus data 1 pin 68 70 m_dq2 _0 mcu hyper bus data 2 pin 67 69 m_dq3 _0 mcu hyper bus data 3 pin 66 68 m_dq4 _0 mcu hyper bus data 4 pin 76 78 m_dq5 _0 mcu hyper bus data 5 pin 77 79 m_dq6 _0 mcu hyper bus data 6 pin 78 80 m_dq7 _0 mcu hyper bus data 7 pin 79 81 m_rwds _0 mcu hyper bus rwds pin #699 72 74 com0 lcdc segment(duty) common output pin 207 215 com1 lcdc segment(duty) common output pin 206 214 com2 lcdc segment(duty) common output pin 205 213 com3 lcdc segment(duty) common output pin 204 212 seg0 lcdc segment(duty) output pin 203 211 seg1 lcdc segment(duty) output pin 202 210 seg2 lcdc segment(duty) output pin 201 209 seg3 lcdc segment(duty) output pin 200 208
document number: 002 - 05682 rev.*a page 59 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 seg4 lcdc segment(duty) output pin 199 207 seg5 lcdc segment(duty) output pin 198 206 seg6 lcdc segment(duty) output pin 197 205 seg7 lcdc segment(duty) output pin 196 204 seg8 lcdc segment(duty) output pin 193 201 seg9 lcdc segment(duty) output pin 192 200 seg10 lcdc segment(duty) output pin 191 199 seg11 lcdc segment(duty) output pin 190 198 seg12 lcdc segment(duty) output pin 189 197 seg13 lcdc segment(duty) output pin 188 196 seg14 lcdc segment(duty) output pin 187 195 seg15 lcdc segment(duty) output pin 186 194 seg16 lcdc segment(duty) output pin 181 189 seg17 lcdc segment(duty) output pin 180 188 seg18 lcdc segment(duty) output pin 179 187 seg19 lcdc segment(duty) output pin 178 186 seg20 lcdc segment(duty) output pin 177 185 seg21 lcdc segment(duty) output pin 176 184 seg22 lcdc segment(duty) output pin 175 183 seg23 lcdc segment(duty /static ) output pin 174 182 seg24 lcdc segment(duty /static ) output pin 168 176 seg25 lcdc segment(duty /static ) output pin 167 175 seg26 lcdc segment(duty /static ) output pin 166 174 seg27 lcdc segment(duty /static ) output pin 165 173 seg28 lcdc segment(duty /static ) output pin 164 172 seg29 lcdc segment(duty /static ) output pin 163 171 seg30 lcdc segment(duty /static ) output pin - 170 seg31 lcdc segment(duty /static ) output pin - 169 v0 lcdc reference voltage v0 input pin 162 168 v1 lcdc reference voltage v1 input pin 161 167 v2 lcdc reference voltage v2 input pin 160 166 v3 lcdc reference voltage v3 input pin 159 165 dsp0_clk display 0 clock output pin 32, 58 32, 60 dsp0_clk - display 0 rsds clock output pin 33 33 dsp0_clk+ display 0 rsds clock output pin 32 32 dsp0_ctrl0 display 0 control output pin 59, 60, 196 61, 62, 204 dsp0_ctrl1 display 0 control output pin 31, 60, 197 31, 62, 205 dsp0_ctrl2 display 0 control output pin 33, 57, 60, 82, 198 33, 59, 62, 84, 206 dsp0_ctrl3 display 0 control output pin 83, 199 85, 207 dsp0_ctrl4 display 0 control output pin 84, 200 86, 208 dsp0_ctrl5 display 0 control output pin 201 209 dsp0_ctrl6 display 0 control output pin 202 210 dsp0_ctrl7 display 0 control output pin 203 211 dsp0_ctrl8 display 0 control output pin 204 212 dsp0_ctrl9 display 0 control output pin 205 213 dsp0_ctrl10 display 0 control output pin 206 214 dsp0_ctrl11 display 0 control output pin 207 215 dsp0_data0_0 display 0 data output pin 34 34 dsp0_data0_1 display 0 data output pin 36 36
document number: 002 - 05682 rev.*a page 60 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 dsp0_data0_2 display 0 data output pin 38 38 dsp0_data0_3 display 0 data output pin 40 40 dsp0_data0_4 display 0 data output pin 31 31, 44 dsp0_data0_5 display 0 data output pin 44 46 dsp0_data0_6 display 0 data output pin 46 48 dsp0_data0_7 display 0 data output pin 48 50 dsp0_data0_8 display 0 data output pin 50 52 dsp0_data0_9 display 0 data output pin 54 56 dsp0_data0_10 display 0 data output pin 56 58 dsp0_data0_11 display 0 data output pin 32, 58 32, 60 dsp0_data1_0 display 0 data output pin 35 35 dsp0_data1_1 display 0 data output pin 37 37 dsp0_data1_2 display 0 data output pin 39 39 dsp0_data1_3 display 0 data output pin 41 41 dsp0_data1_4 display 0 data output pin 33 33, 45 dsp0_data1_5 display 0 data output pin 45 47 dsp0_data1_6 display 0 data output pin 47 49 dsp0_data1_7 display 0 data output pin 49 51 dsp0_data1_8 display 0 data output pin 51 53 dsp0_data1_9 display 0 data output pin 55 57 dsp0_data1_10 display 0 data output pin 31, 57 31, 59 dsp0_data1_11 display 0 data output pin 33, 59 33, 61 dsp0_data_d0 - display 0 rsds data output pin 35 35 dsp0_data_d0+ display 0 rsds data output pin 34 34 dsp0_data_d1 - display 0 rsds data output pin 37 37 dsp0_data_d1+ display 0 rsds data output pin 36 36 dsp0_data_d2 - display 0 rsds data output pin 39 39 dsp0_data_d2+ display 0 rsds data output pin 38 38 dsp0_data_d3 - display 0 rsds data output pin 41 41 dsp0_data_d3+ display 0 rsds data output pin 40 40 dsp0_data_d4 - display 0 rsds data output pin - 45 dsp0_data_d4+ display 0 rsds data output pin - 44 dsp0_data_d5 - display 0 rsds data output pin 45 47 dsp0_data_d5+ display 0 rsds data output pin 44 46 dsp0_data_d6 - display 0 rsds data output pin 47 49 dsp0_data_d6+ display 0 rsds data output pin 46 48 dsp0_data_d7 - display 0 rsds data output pin 49 51 dsp0_data_d7+ display 0 rsds data output pin 48 50 dsp0_data_d8 - display 0 rsds data output pin 51 53 dsp0_data_d8+ display 0 rsds data output pin 50 52 dsp0_data_d9 - display 0 rsds data output pin 55 57 dsp0_data_d9+ display 0 rsds data output pin 54 56 dsp0_data_d10 - display 0 rsds data output pin 57 59 dsp0_data_d10+ display 0 rsds data output pin 56 58 dsp0_data_d11 - display 0 rsds data output pin 59 61 dsp0_data_d11+ display 0 rsds data output pin 58 60 dsp1_clk display 1 clock output pin 199, 204 207, 212 dsp1_ctrl0 display 1 control output pin 200, 207 208, 215 dsp1_ctrl1 display 1 control output pin 201, 206 209, 214
document number: 002 - 05682 rev.*a page 61 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 dsp1_ctrl2 display 1 control output pin 198, 205 206, 213 dsp1_data0_0 display 1 data output pin 203 211 dsp1_data0_1 display 1 data output pin 201 209 dsp1_data0_2 display 1 data output pin 199 207 dsp1_data0_3 display 1 data output pin 197 205 dsp1_data0_4 display 1 data output pin 193 201 dsp1_data0_5 display 1 data output pin 191 199 dsp1_data0_6 display 1 data output pin 189 197 dsp1_data0_7 display 1 data output pin 187 195 dsp1_data0_8 display 1 data output pin 181 189 dsp1_data0_9 display 1 data output pin 179 187 dsp1_data0_10 display 1 data output pin 177 185 dsp1_data0_11 display 1 data output pin 175 183 dsp1_data1_0 display 1 data output pin 202 210 dsp1_data1_1 display 1 data output pin 200 208 dsp1_data1_2 display 1 data output pin 198 206 dsp1_data1_3 display 1 data output pin 196 204 dsp1_data1_4 display 1 data output pin 192 200 dsp1_data1_5 display 1 data output pin 190 198 dsp1_data1_6 display 1 data output pin 188 196 dsp1_data1_7 display 1 data output pin 186 194 dsp1_data1_8 display 1 data output pin 180 188 dsp1_data1_9 display 1 data output pin 178 186 dsp1_data1_10 display 1 data output pin 176 184 dsp1_data1_11 display 1 data output pin 174 182 cap0_clk video capture 0 clock input pin 59 61 cap0_data0 video capture 0 data input pin 31 31 cap0_data1 video capture 0 data input pin 32 32 cap0_data2 video capture 0 data input pin 33 33 cap0_data3 video capture 0 data input pin 34 34 cap0_data4 video capture 0 data input pin 35 35 cap0_data5 video capture 0 data input pin 36 36 cap0_data6 video capture 0 data input pin 37 37 cap0_data7 video capture 0 data input pin 38 38 cap0_data8 video capture 0 data input pin 39 39 cap0_data9 video capture 0 data input pin 40 40 cap0_data10 video capture 0 data input pin 41 41 cap0_data11 video capture 0 data input pin 44 44, 46 cap0_data12 video capture 0 data input pin 45 45, 47 cap0_data13 video capture 0 data input pin 44, 46 46, 48 cap0_data14 video capture 0 data input pin 45, 47 47, 49 cap0_data15 video capture 0 data input pin 46, 48 48, 50 cap0_data16 video capture 0 data input pin 47 49 cap0_data17 video capture 0 data input pin 48 50 cap0_data18 video capture 0 data input pin 49 51 cap0_data19 video capture 0 data input pin 50 52 cap0_data20 video capture 0 data input pin 51 53 cap0_data21 video capture 0 data input pin 54 56 cap0_data22 video capture 0 data input pin 55 57
document number: 002 - 05682 rev.*a page 62 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 cap0_data23 video capture 0 data input pin 56 58 cap0_data24 video capture 0 data input pin 82 84 cap0_data25 video capture 0 data input pin 83 85 cap0_data32 video capture 0 data input pin 56, 57 58, 59 cap0_data33 video capture 0 data input pin 58 60 cap0_data34 video capture 0 data input pin 60 62 cap0_data35 video capture 0 data input pin 57 59 indicator0_0 indicator pwm output pin 0 it can also obtained from indicator0_1) 92 95 indicator0_1 indicator pwm output pin (it can also obtained from indicator0_0) 170 178 p0_00 general - purpose i/o port 40 40 p0_01 general - purpose i/o port 41 41 p0_02 general - purpose i/o port - 44 p0_03 general - purpose i/o port - 45 p0_04 general - purpose i/o port 44 46 p0_05 general - purpose i/o port 45 47 p0_06 general - purpose i/o port 46 48 p0_07 general - purpose i/o port 47 49 p0_08 general - purpose i/o port 48 50 p0_09 general - purpose i/o port 49 51 p0_10 general - purpose i/o port 50 52 p0_11 general - purpose i/o port 51 53 p0_12 general - purpose i/o port 54 56 p0_13 general - purpose i/o port 55 57 p0_14 general - purpose i/o port 56 58 p0_15 general - purpose i/o port 57 59 p0_16 general - purpose i/o port 58 60 p0_17 general - purpose i/o port 59 61 p0_18 general - purpose i/o port 32 32 p0_19 general - purpose i/o port 33 33 p0_26 general - purpose i/o port 82 84 p0_27 general - purpose i/o port 83 85 p0_28 general - purpose i/o port 84 86 p0_30 general - purpose i/o port 72 74 p0_31 general - purpose i/o port 75 77 p1_00 general - purpose i/o port 77 79 p1_01 general - purpose i/o port 76 78 p1_02 general - purpose i/o port 79 81 p1_03 general - purpose i/o port 78 80 p1_04 general - purpose i/o port 69 71 p1_05 general - purpose i/o port 66 68 p1_06 general - purpose i/o port 68 70 p1_07 general - purpose i/o port 67 69 p1_08 general - purpose i/o port 70 72 p1_09 general - purpose i/o port 63 65 p2_16 general - purpose i/o port 170 178 p2_17 general - purpose i/o port 169 177 p2_19 general - purpose i/o port 159 165
document number: 002 - 05682 rev.*a page 63 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 p2_22 general - purpose i/o port 89 91 p2_24 general - purpose i/o port - 92 p2_25 general - purpose i/o port 90 93 p2_26 general - purpose i/o port 91 94 p2_27 general - purpose i/o port 92 95 p2_28 general - purpose i/o port - 96 p2_29 general - purpose i/o port 93 97 p2_30 general - purpose i/o port 94 98 p2_31 general - purpose i/o port 95 99 p3_00 general - purpose i/o port 96 100 p3_01 general - purpose i/o port 97 101 p3_02 general - purpose i/o port 98 102 p3_03 general - purpose i/o port 99 103 p3_04 general - purpose i/o port 100 104 p3_05 general - purpose i/o port 101 105 p3_06 general - purpose i/o port 102 106 p3_07 general - purpose i/o port 160 166 p3_08 general - purpose i/o port 161 167 p3_09 general - purpose i/o port 162 168 p3_10 general - purpose i/o port - 169 p3_11 general - purpose i/o port - 170 p3_12 general - purpose i/o port 163 171 p3_13 general - purpose i/o port 164 172 p3_14 general - purpose i/o port 165 173 p3_15 general - purpose i/o port 166 174 p3_16 general - purpose i/o port 167 175 p3_17 general - purpose i/o port 168 176 p3_18 general - purpose i/o port 118 122 p3_19 general - purpose i/o port - 123 p3_20 general - purpose i/o port - 124 p3_21 general - purpose i/o port 127 133 p3_22 general - purpose i/o port 128 134 p3_23 general - purpose i/o port 129 135 p3_24 general - purpose i/o port 130 136 p3_25 general - purpose i/o port 131 137 p3_26 general - purpose i/o port 132 138 p3_27 general - purpose i/o port 133 139 p3_28 general - purpose i/o port 134 140 p3_29 general - purpose i/o port 137 143 p3_30 general - purpose i/o port 138 144 p3_31 general - purpose i/o port 139 145 p4_00 general - purpose i/o port 140 146 p4_01 general - purpose i/o port 141 147 p4_02 general - purpose i/o port 142 148 p4_03 general - purpose i/o port 143 149 p4_04 general - purpose i/o port 144 150 p4_05 general - purpose i/o port 147 153 p4_06 general - purpose i/o port 148 154 p4_07 general - purpose i/o port 149 155
document number: 002 - 05682 rev.*a page 64 of 179 S6J3200 series port name description package pin number remark teqfp208 teqfp216 p4_08 general - purpose i/o port 150 156 p4_09 general - purpose i/o port 151 157 p4_10 general - purpose i/o port 152 158 p4_11 general - purpose i/o port 153 159 p4_12 general - purpose i/o port 154 160 p4_25 general - purpose i/o port 204 212 p4_26 general - purpose i/o port 205 213 p4_27 general - purpose i/o port 206 214 p4_28 general - purpose i/o port 207 215 p4_29 general - purpose i/o port 174 182 p4_30 general - purpose i/o port 175 183 p4_31 general - purpose i/o port 176 184 p5_00 general - purpose i/o port 177 185 p5_01 general - purpose i/o port 178 186 p5_02 general - purpose i/o port 179 187 p5_03 general - purpose i/o port 180 188 p5_04 general - purpose i/o port 181 189 p5_05 general - purpose i/o port 186 194 p5_06 general - purpose i/o port 187 195 p5_07 general - purpose i/o port 188 196 p5_08 general - purpose i/o port 189 197 p5_09 general - purpose i/o port 190 198 p5_10 general - purpose i/o port 191 199 p5_11 general - purpose i/o port 192 200 p5_12 general - purpose i/o port 193 201 p5_13 general - purpose i/o port 196 204 p5_14 general - purpose i/o port 197 205 p5_15 general - purpose i/o port 198 206 p5_16 general - purpose i/o port 199 207 p5_17 general - purpose i/o port 200 208 p5_18 general - purpose i/o port 201 209 p5_19 general - purpose i/o port 202 210 p5_20 general - purpose i/o port 203 211 p5_21 general - purpose i/o port 31 31 p5_22 general - purpose i/o port 60 62 p5_27 general - purpose i/o port 34 34 p5_28 general - purpose i/o port 35 35 p5_29 general - purpose i/o port 36 36 p5_30 general - purpose i/o port 37 37 p5_31 general - purpose i/o port 38 38 p6_00 general - purpose i/o port 39 39 6.2 remark notes: ? t he port description list shows the port function of description which is mounted and supported on the product. t he function which is not described in this table is not supported and assured. ? see the function list of the product as well.
document number: 002 - 05682 rev.*a page 65 of 179 S6J3200 series 7. precautions and handling devices 7.1 handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this pa ge describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 7.1.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semic onductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represente d on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semicon ductor devices to power supply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extr eme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
document number: 002 - 05682 rev.*a page 66 of 179 S6J3200 series 7.1.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under cypress recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto prin ted circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave sold ering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mountin g conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to c ondense inside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 ? c and 30 ?c. w hen you open dry packag e that recommends humidity 40% to 70% relative humidity. (3) when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. cond ition: 125 ?c/24 h static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
document number: 002 - 05682 rev.*a page 67 of 179 S6J3200 series (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to groun d through high resistance (on the level of 1 m). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measure s. (5) avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. 7.1.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described abov e. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 05682 rev.*a page 68 of 179 S6J3200 series 7.2 h andling d evices for latch - up prevention the latch - up phenomenon may occur on a cmos ic in the following cases: the voltage applied to an inp ut or output pin is higher than vcc or lower than vss; or the voltage applied between a vcc pin and a vss pin exceeds the rating. a latch - up causes a rapid increase in the power supply current, possibly resulting in thermal damage to an element. when using the device, take sufficient care not to exceed the maximum rating. also be careful that analog power supplies (avcc, avrh) and analog inputs do not exceed the digital power supply (vcc) at the analog system power - on and power - off times. the power - on seq uence is as follows. simultaneously turn on the digital supply voltage (vcc) and analog supply voltages (avcc, avrh), or turn on the digital supply voltage (vcc) and then the analog supply voltages (avcc, avrh). about handling unused pins leaving unused in put pins open may cause permanent damage from a malfunction or latch - up. take measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 kilo ohms or higher. if there are any unused input/output pins, set them to the outp ut state and then open them, or set them to the input state and handle them in the same way as input pins. about power supply pins if the device has multiple vcc and vss pins, the device is designed in such a way that the pins that should be at the same po tential are connected to each other inside the device to prevent malfunctions such as latch - up. however, to reduce unwanted emissions, prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total output c urrent, be sure to connect all the vcc and vss pins to the power source and ground externally. also handle all the vss power supply pins in this way as shown in the following diagram. if there are multiple vcc or vss systems, the device does no t operate no rmally even within the guaranteed operating range. figure 7 - 1 pin assignment in addition, consider connecting with low impedance from the power supply source to the vcc and vss of this device. we recommend connecting a ceramic capacitor as a bypass capacitor between vcc and vss, near this device. about the crystal oscillation circuit noise entering the x0 or x1 pin may cause a malfunction. design the printed circuit board in such a way that the x0 and x1 pi ns, the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to t he device. we recommend that the printed circuit board artwork have the x0 and x1 pins enclosed by ground.
document number: 002 - 05682 rev.*a page 69 of 179 S6J3200 series about the mode pin (md) use mode pin md by directly connecting it to a vcc or vss pin. to prevent noise from causing the device to accidentally ente r test mode, reduce the pattern length between each mode pin and a vcc or vss pin on the printed circuit board, and connect them with low impedance. about the power - on time to prevent the internal built - in voltage step - down circuit from malfunctioning, sec ure a voltage rising time of 50 s (between 0.2 v and 2.7 v) or longer at the power - on time. point to note during pll clock operation while a pll clock is selected, if the oscillator breaks off or input stops, the pll clock may continue operating with the free running frequency of the internal self - oscillator circuit. this operation is outside of the guaranteed range. power supply pin processing of an a/d converter even when no a/d converter is used, establish a connection such that av cc =avrh=v cc and av ss / avrl=v ss . points to note about using external clocks external clocks are not supported. external direct clock input cannot be used. power - on sequence of the power supply analog inputs of an a/d converter be sure to turn on the digital power supply (vcc) b efore the application of the power supplies (av cc , avrh, and avrl) and analog inputs (an0 to an63) of an a/d converter. at the power - off time, turn off the power supplies and analog inputs of the a/d converter, and then turn off the digital power supply ( vcc). perform these power - on and power - off operations without avrh exceeding avcc. even when using a pin shared with an analog input as an input port, do not allow the input voltage to exceed avcc. (turning on or off the analog supply vo ltage and digital s upply voltage simultaneously is not a problem.) about c pin processing this device has a built - in voltage step - down circuit. be sure to connect a capacitor to the c pin (pin 154 in s6j311ejaa specifications and pin 126 in s6j311ahaa specifications) for int ernal stabilization of the device. for the standard values, see "recommended operating conditions" in the latest data sheet. precautions on designing a mounting substrate measures against heat generation from the package must be taken for the mounting sub strate to observe the absolute maximum rating (operating temperature). design a mounting substrate with 4 or more layers. connect the back of the package stage and the substrate pad with solder paste. arrange thermal via holes on the substrate pad. notes o n writing to a register containing a status flag in writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a function, it is important to take care not to accidentally clear the status flag. therefore, bef ore the write operation, configure the status bit such that the flag is not cleared, and then set the control bit to the desired value. especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions hav e only 1 - bit access). in such cases, byte, half - word, or word access is used to write to the control bits and a status flag simultaneously. however, at this time, be careful not to accidentally clear bits other than the intended ones (the status flag bit i n this case). note: bit instructions take this point into account for registers that support bit - band units, so it does not need to be a concern. you need to take care when using bit instructions for registers that do not support bit - band units.
document number: 002 - 05682 rev.*a page 70 of 179 S6J3200 series 8. electric characteristics 8.1 absolute maximum rating parameter symbol rating unit remarks min max power supply voltage * 1, * 2 v cc 5 v ss - 0.3 v ss +6.0 v v cc 53 v ss - 0.3 v ss +6.0 v v cc 53 v cc 5 v cc 3 v ss - 0.3 v ss + 4 .0 v v cc 3 v cc 5 dv cc v ss - 0.3 v ss + 6 .0 v dv cc v cc 5 v cc 12 v ss - 0.3 v ss + 1.8 v v cc 12 v cc 53 v cc 12 v cc 3 v cc 12 dv cc v cc 12 a v cc 5 analog supply voltage * 1, * 2 av cc 5 v ss - 0.3 v ss +6.0 v a v cc 5 v cc 5 av cc 3_dac v ss - 0.3 v ss + 4 .0 v for dac v cc 3_lvds_tx v ss - 0.3 v ss + 4 .0 v for lvds av cc 3_lvds_p ll v ss - 0.3 v ss + 4 .0 v for lvds pll analog reference vo ltage *1 avrh 5 v ss - 0.3 v ss +6.0 v avrh 5 av cc 5 input voltage * 1 v i 1 v ss - 0.3 v cc 5 +0.3 v 5v pins not shared smc v i 2 v ss - 0.3 d v cc +0.3 v 5v pins shared smc v i 3 v ss - 0.3 v cc 3 +0.3 v 3v pins v i e v ss - 0.3 v cc 53 +0.3 v 5v/3v pins analog pin input voltage * 1 v ia v ss - 0.3 v cc 5 +0.3 v output voltage * 1 v o 1 v ss - 0.3 v cc 5 +0.3 v 5v pins not shared smc v o 2 v ss - 0.3 d v cc +0.3 v 5v pins shared smc v o 3 v ss - 0.3 v cc 3 +0.3 v 3v pins v o 4 v ss - 0.3 v cc 53 +0.3 v 5v/3v pins maximum clamp current |i clamp | - 4 ma *12, * a total m aximum clamp current |i clamp | - 20 ma *12, * a total m aximum clamp current |i clamp | - 5 0 ma special spec * a "l" - level maximum output current * 3 i ol1 - 3.5 ma when setting is 1 ma *6 , *7, *8 i ol2 - 7 ma when setting is 2 ma *6 , *7, *8, *9 i ol 3 - 10 ma when setting is 5 ma *6 , *7, *8, * 9 i ol 4 - 16 ma when setting is 10 ma * 9 i ol 5 - 30 ma when setting is 20 ma * 9 i ol 6 - 40 ma when setting is 30ma *7 i ol 7 - 8 ma when setting is 3ma *10 i ol 8 - 11 ma when setting is 6ma *11
document number: 002 - 05682 rev.*a page 71 of 179 S6J3200 series parameter symbol rating unit remarks min max "l" - level average output current * 4 i olav1 - 1 ma when setting is 1 ma *6 , *7, *8 i olav2 - 2 ma when setting is 2 ma *6 , *7, *8, *9 i olav 3 - 5 ma when setting is 5 ma *6 , *7, *8, * 9 i olav 4 - 10 ma when setting is 10 ma * 9 i olav 5 - 20 ma when setting is 20 ma * 9 i olav 6 - 30 ma when setting is 30ma *7 i olav 7 - 3 ma when setting is 3ma *10 i olav 8 - 6 ma when setting is 6ma *11 "l" - level total output current * 5 i ol 1 - 50 ma *6, *10 i ol 2 - 250 ma *7 i ol 3 - 50 ma *8 i ol 4 - 50 ma *9, *11 "h" - level maximum output current * 3 i oh1 - - 3.5 ma when setting is 1 ma *6 , *7, *8 i oh2 - - 7 ma when setting is 2 ma *6 , *7, *8, *9 i oh 3 - - 10 ma when setting is 5 ma *6 , *7, *8, * 9 i oh 4 - - 16 ma when setting is 10 ma * 9 i oh 5 - - 30 ma when setting is 20 ma * 9 i oh 6 - - 40 ma when setting is 30ma *7 i oh 8 - - 11 ma when setting is 6ma *11 "h" - level average output current * 4 i ohav1 - - 1 ma when setting is 1 ma *6 , *7, *8 i ohav2 - - 2 ma when setting is 2 ma *6 , *7, *8, *9 i ohav 3 - - 5 ma when setting is 5 ma *6 , *7, *8, * 9 i ohav 4 - - 10 ma when setting is 10 ma * 9 i ohav 5 - - 20 ma when setting is 20 ma * 9 i ohav 6 - - 30 ma when setting is 30ma *7 i ohav 8 - - 6 ma when setting is 6ma *11 "h" - level total output current * 5 i oh 1 - - 50 ma *6, *10 i oh 2 - - 250 ma *7 i oh 3 - - 50 ma *8 i oh 4 - - 50 ma *9, *11 power dissipation and operation temperature case 1 p d - 3300 mw - t a - 40 + 97 o c both should be satisfied. t c - 40 +144 o c power dissipation and operation temperature case 2 p d - 3150 mw - t a - 40 + 100 o c both should be satisfied. t c - 40 +144 o c power dissipation and operation temperature case 3 p d - 3000 mw - t a - 40 + 102 o c both should be satisfied. t c - 40 +144 o c power dissipation and operation temperature case 4 p d - 2900 mw - t a - 40 + 105 o c both should be satisfied. t c - 40 +144 o c power dissipation and operation temperature case 5 p d - 2800 mw - t a - 40 + 105 o c both should be satisfied. t c - 40 +144 o c
document number: 002 - 05682 rev.*a page 72 of 179 S6J3200 series parameter symbol rating unit remarks min max system thermal resistance theta j - a - 16 o c/w the minimum value depends on the system specification of heat radiation. the described value is estimated under the condition which is specified at operation assurance condition. package thermal resistance theta j - c - 7.5 o c/w - storage temperature tstg - 55 +150 o c - *1 : these parameters are based on the condition that v ss =av ss = dv ss = 0.0 v . *2 : take care that dv cc , av cc 5 do not exceed v cc 5 at, for example, the power - on time. *3 : the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4 : the average output current is defined as the value of the average current flowing through any one of the corresponding pins fo r a 10 m s period. the average value is the operation current the operation ratio. *5 : the total output current is defined as the maximum current value flowing through all of corresponding pins. *6: output of 5v pins. *7: output of smc pins. *8: outpu t of 5v/3v pins. *9: output of 3v pins. *10: output of i 2 c. *11 : output of media lb pins * 12: vi or vo should never exceed the specified ratings. however, if the maximum current to/from an input is limited by a suitable external resistor, the iclamp rating supersedes the vi rating. * a: relevant pins: all general - purpose ports and analog input pins ? corresponding pins : all general - purpose ports ? use within the operation assurance condition (see 8.2 . operation assurance ) . ? use at dc voltage (current). ? the +b signal should always be applied by connec ting a limiting resistor between the +b signal and the microcontroller. ? the value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated v alues at any time regardless of instantaneously or constant ly when the +b signal is input. ? note that when the microcontroller drive current is low, such as in the low power consumption modes, the + b input potential can increase the potential at the vcc pin via a protective diode, possibly affecting other devices. ? note that if the + b signal is input when the microcontroller is off (not fixed at 0 v), since the power is supplied through the pin, the microcontroller may operate incompletely. ? note that if the +b signal is input at power - on, since the power is supplie d through the pin, the power - on reset may not function in the power supply voltage. ? do not leave + b input pins open.
document number: 002 - 05682 rev.*a page 73 of 179 S6J3200 series example of a recommended circuit warning: ? semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these rati ngs. S6J3200 series
document number: 002 - 05682 rev.*a page 74 of 179 S6J3200 series 8.2 operation assurance condition parameter symbol value unit remarks power supply corresponding ground min max supply voltage v cc 5 v ss 4.5 5.5 v specified electric characteristics are assured in this range. v cc 53 v ss 4.5 5.5 v 3.0 3.6 v dv cc dv ss 4.5 5.5 v av cc 5 av ss 4.5 5.5 v v cc 3 v ss 3.0 3.6 v v cc 12 v ss 1.15 *1 1.3 v 1.1 1.3 v av cc 3_dac av ss 3_dac 3.0 3.6 v v cc 3_lvds_tx v ss 3_lvds_tx 3.0 3.6 v av cc 3_lvds_pll av ss 3_lvds_pll 3.0 3.6 v v cc 5 v ss 3.5 5.5 v specified electric characteristics are not assured in this range. v cc 53 v ss 2.7 5 . 5 v dv cc dv ss 3.5 5 . 5 v av cc 5 av ss 3.5 5.5 v v cc 3 v ss 2.7 3.6 v av cc 3_dac av ss 3_dac 2.7 3.6 v v cc 3_lvds_tx v ss 3_lvds_tx 2.7 3.6 v av cc 3_lvds_pll av ss 3_lvds_pll 2.7 3.6 v smoothing capacitor * 2 c s - 4.7 f tolerance of up to 40% operating temperature t a - - 40 +1 0 5 o c see the notes below. t c - - 40 +1 44 o c notes: ? *1. the value is only applied to the product series with revision digit a. ? * 2. for the connections of smoothing capacitor c s , see the following diagram. ? power supply sequence is recommended as vcc5 ? [dvcc or avcc5 or vcc3 or avcc3] ? vcc12 ? [avcc3_lvds_pll or vcc3_lvds_tx] . ? note that power supplies inside "[ ]" can be turned on in arb itrary order. c pin connection diagram c s c v ss av ss d v ss
document number: 002 - 05682 rev.*a page 75 of 179 S6J3200 series warning: 1. the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. any use of semiconducto r devices will be under their recommended operating condition. 3. operation under any conditions other than these conditions may adversely affect reliability of device and could result in dev ice failure. 4. no warranty is made with respect to any use, operatin g conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. notes: ? t a : ambient temperature (jedec) ? t c : case temperature (jedec), the maximum measured temperature of package case top. ? both rating of t a and t c should simultaneously be satisfied as maximum operation temperature. ? the following condition should be satisfied in order to facilitate heat dissipation. 1. 4 or more lay ers pcb should be used. 2. the area of pcb should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (jedec standard) 3. 1 layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90% or more. the layer can be used for system ground. 4. 35~50% of the die stage area which is exposed at back surface of package should be soldered to a part of 1 st layer. 5. t he part of 1 st layer should be connected to the dedicated heat radiation layer with more th an 10 thermal via holes. figure 8 - 1 : example thermal via holes on pcb. notes: ? figure 8 - 1 is a schematic diagram showing pcb in section. ? figure 8 - 2 , figure 8 - 3 , and figure 8 - 4 in the following pages are recommended land patterns for each package series. thermal via h oles should closely be placed and aligned with lands. ? when thermal via holes cannot be with lands, the followings are recommended as represented by figure 8 - 5 which is an example for leq216. ? (1). i ncrease pattern area size as much as possible inside the package outline. ? (2). place thermal via holes to be with lands as close as possible. ? 0.25mm a 0.30mm in figure 8 - 1 , figure 8 - 2 , figure 8 - 3 , and figure 8 - 4
document number: 002 - 05682 rev.*a page 76 of 179 S6J3200 series figure 8 - 2 : land pattern and thermal via leq216 0.25mm a 0.30mm figure 8 - 3 : land pattern and thermal via let208 0.25mm a 0.30mm
document number: 002 - 05682 rev.*a page 77 of 179 S6J3200 series figure 8 - 4 : land pattern and thermal via ler208 0.25mm a 0.30mm
document number: 002 - 05682 rev.*a page 78 of 179 S6J3200 series figure 8 - 5 : optional land pattern 0.25mm a 0.30mm
document number: 002 - 05682 rev.*a page 79 of 179 S6J3200 series 8.3 dc characteristics 8.3.1 port function characteristics ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage v ih1 p4_25 to 31, p5_00 to 20, p6_20 to 26 cmos hysteresis input level is selected 0.7v cc 53 - v cc 53 +0.3 v v ih2 automotive input level is selected 0.8v cc 53 - v cc 53 +0.3 v v ih 3 ttl input level is selected 2.0 - v cc 53 +0.3 v v ih 4 p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p6_02 to 19 cmos hysteresis input level is selected 0. 7 v cc 5 - v cc 5 +0.3 v *1 v ih 5 automotive input level is selected 0.8v cc 5 - v cc 5 +0.3 v *1 v ih 6 p2_25, 26, p3_00, 01 ttl input level is selected 2.0 - v cc 5 +0.3 v v ih 7 rstx nmix - 0.7v cc 5 - v cc 5 +0.3 v v ih 8 md - 0.7v cc 5 - v cc 5 +0.3 v v ih 9 jtag_n trst jtag_ tck jtag_ tdi jtag_ tms - 2. 3 - v cc 5 +0.3 v v ih 10 p0_00 to 19, 26 to 28, 30, 31, p1_00 to 09, p5_21, 22, 27 to 31, p6_00, 01 cmos hysteresis input level is selected 0.7v cc 3 - v cc 3 +0.3 v v ih 11 p0_00 to 19, 30, 31, p1_00 to 09, p5_21, 22, 27 to 31, p6_00, 01 ttl input level is selected 2.0 - v cc 3 +0.3 v v ih 12 p0_26 to 28 - 1.8 - v cc 3 +0.3 v medialb
document number: 002 - 05682 rev.*a page 80 of 179 S6J3200 series parameter symbol pin name conditions value unit remarks min typ max "l" level input voltage v i l 1 p4_25 to 31, p5_00 to 20, p6_20 to 26 cmos hysteresis input level is selected v ss - 0.3 - 0.3v cc 53 v v i l 2 automotive input level is selected v ss - 0.3 - 0.5v cc 53 v v i l3 ttl input level is selected v ss - 0.3 - 0.8 v v i l4 p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p6_02 to 19 cmos hysteresis input level is selected v ss - 0.3 - 0.3v cc 5 v *1 v i l5 automotive input level is selected v ss - 0.3 - 0.5v cc 5 v *1 v i l6 p2_25, 26, p3_00, 01 ttl input level is selected v ss - 0.3 - 0.8 v v i l7 rstx nmix - v ss - 0.3 - 0.3v cc 5 v v i l8 md - v ss - 0.3 - 0.3v cc 5 v v i l9 jtag_n trst jtag_ tck jtag_ tdi jtag_ tms - v ss - 0.3 - 0.8 v v i l10 p0_00 to 19, 26 to 28, 30, 31, p1_00 to 09, p5_21, 22, 27 to 31, p6_00, 01 cmos hysteresis input level is selected v ss - 0.3 - 0.3v cc 3 v v i l11 p0_00 to 19, 30, 31, p1_00 to 09, p5_21, 22, 27 to 31, p6_00, 01 ttl input level is selected v ss - 0.3 - 0.8 v v i l12 p0_26 to 28 - v ss - 0.3 - 0.7 v medialb *1: p3_21 to p3_31, p4_00 to p4_12 and p6_9 to p6 - 16 are supplied with power by dvcc.
document number: 002 - 05682 rev.*a page 81 of 179 S6J3200 series ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max "h" level output voltage v oh1 p4_25 to 31, p5_00 to 20, p6_20 to 26 v cc 53 = 3.0 v i oh = - 1 .0 ma v cc 53 - 0.5 - v cc 53 v v oh2 v cc 53 = 3.0 v i oh = - 2 .0 ma v cc 53 - 0.5 - v cc 53 v v oh 3 v cc53 = 3.0 v i oh = - 5.0 ma v cc 53 - 0.5 - v cc 53 v v oh 4 p2_16, 17, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p6_02 to 19 v cc 5 =4.5 v i oh = - 1 .0 ma v cc 5 - 0.5 - v cc 5 v *1, smc v oh 5 v cc 5 =4.5 v i oh = - 2 .0 ma v cc 5 - 0.5 - v cc 5 v *1, smc tj= - 40 o c v oh 6 v cc5 = 4.5 v i oh = - 5.0 ma v cc 5 - 0.5 - v cc 5 v *1 v oh 7 psc_1 v cc5 = 4.5 v i oh = - 2.0 ma v cc5 - 0.5 - v cc 5 v v oh 8 jtag_tdo v cc 5 = 4.5 v i oh = - 5 .0 ma v cc5 - 0.5 - v cc 5 v v oh 10 p3_21 to 31, p4_00 to 12, p6_09 to 16 d v cc =4.5 v i oh = - 30 .0 ma d v cc - 0.5 - d v cc v smc v oh 11 d v cc =4.5 v i oh = - 40 .0 ma d v cc - 0.5 - d v cc v smc tj= - 40 o c v oh 12 p0_00 to 19, 26 to 28, 30, 31, p1_00 to 09, p5_21, 22, 27 to 31, p6_00, 01 v cc 3 = 3 . 0 v i oh = - 2 .0 ma v cc3 - 0.5 - v cc 3 v v oh 13 v cc 3 = 3.0 v i oh = - 5 .0 ma v cc3 - 0.5 - v cc 3 v v oh 14 v cc3 = 3.0 v i oh = - 10.0 ma v cc3 - 0.5 - v cc 3 v v oh 15 p0_00 to 19, p5_21, 22, 27 to 31, p6_00, 01 v cc3 = 3.0 v i oh = - 20.0 ma v cc3 - 0.5 - v cc 3 v v oh 16 p0_26 to 28 v cc 3 = 3.0 v i oh = - 6.0 ma 2.0 - v cc 3 v medialb
document number: 002 - 05682 rev.*a page 82 of 179 S6J3200 series ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max "l" level output voltage v o l 1 p4_25 to 31, p5_00 to 20, p6_20 to 26 v cc 53 = 3.0 v i o l = 1 .0 ma 0 - 0.4 v v o l 2 v cc 53 = 3.0 v i o l = 2 .0 ma 0 - 0.4 v v o l3 v cc53 = 3.0 v i o l = 5.0 ma 0 - 0.4 v v o l4 p2_16, 17, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p6_02 to 19 v cc 5 =4.5 v i o l = 1 .0 ma 0 - 0.4 v *1 v o l5 v cc 5 =4.5 v i o l = 2 .0 ma 0 - 0.4 v *1 v o l6 v cc5 = 4.5 v i o l = 5.0 ma 0 - 0.4 v *1 v o l7 psc_1 v cc5 = 4.5 v i o l = 2.0 ma 0 - 0.4 v v o l8 jtag_tdo v cc 5 = 4.5 v i o l = 5 .0 ma 0 - 0.4 v v o l9 p2_25, 26, p3_00, 01 v cc 5 = 4.5 v i o l = 3 .0 ma 0 - 0.4 v i 2 c v o l10 p3_21 to 31, p4_00 to 12, p6_09 to 16 d v cc =4.5 v i o l = 30 .0 ma 0 - 0.55 v smc v o l11 d v cc =4.5 v i o l = 40 .0 ma 0 - 0.55 v smc tj= - 40 o c v o l12 p0_00 to 19, 26 to 28, 30, 31, p1_00 to 09, p5_21, 22, 27 to 31, p6_00, 01 v cc 3 = 3 . 0 v i o l = 2 .0 ma 0 - 0.4 v v o l13 v cc 3 = 3.0 v i o l = 5 .0 ma 0 - 0.4 v v o l14 v cc3 = 3.0 v i o l = 10.0 ma 0 - 0.4 v v o l15 p0_00 to 19, p5_21, 22, 27 to 31, p6_00, 01 v cc3 = 3.0 v i o l = 20.0 ma 0 - 0.4 v v o l16 p0_26 to 28 v cc 3 = 3.0 v i o l = 6.0 ma 0 - 0.4 v medialb *1 :p3_21 to p3_31, p4_00 to p4_12 and p6_9 to p6 - 16 are supplied with power by dvcc.
document number: 002 - 05682 rev.*a page 83 of 179 S6J3200 series ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max input leakage current i il p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p4_25 to 31, p5_00 to 20, p6_02 to 31 v cc 5= v cc 53 = dv cc = av cc =5.5 v v ss < vi < v cc - 5 - +5 a 5v pins 5v/3v pins p0_00 to 31, p1_00 to 09, p5_21, 22, 27 to 31 , p6_00, 01 v cc 3=3 . 6 v v ss < vi < v cc 3 - 10 - +10 a 3v pins pull - up resistor r up1 rstx, nmix - 25 50 100 k up2 p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p4_25 to 31, p5_00 to 20, p6_02 to 31 pull - up resistor selected vcc53 = 4.5v to 5.5v 25 50 100 k k up 3 p0_00 to 31, p1_00 to 09, p5_21, 22, 27 to 31 , p6_00, 01 pull - up resistor selected 17 33 66 k up 4 jtag_ tdi, jtag_ tms, jtag_ tck - 25 50 100 k down1 p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p4_25 to 31,p5_00 to 20, p6_02 to 31 pull - down resistor selected vcc53 = 4.5v to 5.5v 25 50 100 k k down 2 p0_00 to 31, p1_00 to 09, p5_21, 22, 27 to 31 , p6_00, 01 pull - down resistor selected 17 33 66 k down 3 jtag_n trst - 25 50 100 k in 1 p0_00 to 31, p1_00 to 09, p2_16, 17, 19, 22, 24 to 31, p3_00 to 20, p4_25 to 31, p5_00 to 20, p5_ 21 22, 27 to 31, p6_00 to 08, 17 to 26 - - 5 15 pf c in 2 p3_21 to 31, p4_00 to 12, p6_09 to 16 - - 15 45 pf when using smc
document number: 002 - 05682 rev.*a page 84 of 179 S6J3200 series ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max high current output drive capacity phase - to - phase deviation1 delta - v oh8 p3_21 to 31, p4_00 to 12, p6_09 to 16 dv cc =4.5v i oh = - 30.0ma maximum deviation of v oh 8 - - 90 mv * high current output drive capacity phase - to - phase deviation2 delta - v ol8 dv cc =4.5v i o l =30.0ma maximum deviation of v o l84 - - 90 mv * lcd divider resistor r lcd v0 to v1, v1 to v2, v2 to v3 - 6.25 12.5 25 k vcom comm (m=0 to 3) - - - 4.5 k vseg segn (n=00 to 31) - - - 17 k lcdc v0 to v3, comm (m=0 to 3), segn (n=00 to 31) t a = + 25 ? oh 4 / v ol 4 for each pin is defined. same for other channels.
document number: 002 - 05682 rev.*a page 85 of 179 S6J3200 series ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max output differential voltage | v od | dsp0_datan+, dsp0_datan - n=0 to 11 boost=0 ( drivability 2ma) r l = 100 l = 50 os boost=0 ( drivability 2ma) r l = 100 l = 50 v rsds n ground level / 0v v os v oh v ol v rsds p (v rsds n) - ( v rsds p) 0 v differential +v od - v od single ended differential
document number: 002 - 05682 rev.*a page 86 of 179 S6J3200 series 8.3.2 power supply current 8.3.2.1 run mode ? this characteristics is specified for the series with the function digit 3, 4, 5, 6, 7, and 8. ( condition: see 8.2 . operation assurance ) symbol pin name conditions value unit t a ( o c) remark typ max i cc 5 v cc 5 normal operation 45 - m a 25 - - 70 ma 105 adder for work flash programming or erasing. - 20 ma 105 - i cc 12 v cc 12 cpu:240mhz, hpm:120mhz, gdc 2d and 3d engine:200mhz 820 - m a 25 - - 1600 m a 105 cpu:240mhz, hpm:120mhz, gdc 2d engine only:200mhz 700 - ma 25 - - 1 480 ma 105 cpu:120mhz, hpm:60mhz, gdc:0mhz for tc flash programming or erasing - 1120 ma 105 - cpu:80mhz, hpm:40mhz, gdc:0mhz for tc flash programming or erasing - 1040 ma 105 - adder for work flash programming or erasing. - 20 ma 105 - ilvds v cc 3_lvds_tx 50mhz - 56 ma 105 *1 av cc 3_lvds_pll - - 7 ma 105 - note: ? the output port current is not included in the specified value *1. a few ma which depends on usage for fpd - link data transfer should be estimated for each port in an actual application, and then it should be added to the current consumption at vcc3_lvds_tx. ? the current consumption at vcc3_lvds_tx is specified under rl=100ohm, cl=5pf, f=50mhz, and 0/1 alternation pattern output.
document number: 002 - 05682 rev.*a page 87 of 179 S6J3200 series ? this ch aracteristics is specified for the series with the function digit a, b, c, and d. ( condition: see 8.2 . operation assurance ) symbol pin name conditions value unit t a ( o c) remark typ max i cc 5 v cc 5 normal operation 45 - m a 25 - - 70 ma 105 adder for work flash programming or erasing. - 20 ma 105 - i cc 12 v cc 12 cpu:160mhz, hpm:160mhz, gdc 2d and 3d engine:160mhz 880 - m a 25 - - 1410 m a 105 cpu:120mhz, hpm:60mhz, gdc:0mhz for tc flash programming or erasing - 1120 ma 105 - cpu:80mhz, hpm:40mhz, gdc:0mhz for tc flash programming or erasing - 1040 ma 105 - adder for work flash programming or erasing. - 20 ma 105 -
document number: 002 - 05682 rev.*a page 88 of 179 S6J3200 series 8.3.2.2 pss timer mode shutdown (pd6=off) ? this characteristics is specified for the series with the function digit 3, 4, 5, 6, 7, and 8. ( condition: see 8.2 . operation assurance ) symbol pin name conditions value unit t a ( o c) remark typ max i cct5 v cc 5 4mhz crystal for main oscillator pd1=on, pd4_0=on, pd4_1=on 350 600 a 25 - 4mhz crystal for main oscillator pd1=on, pd4_0 or pd4_1=on 345 575 a 25 *1 4mhz crystal for main oscillator pd1=on 340 550 a 25 *1 8mhz crystal for main oscillator pd1=on, pd4_0=on, pd4_1=on 450 730 a 25 - 8mhz crystal for main oscillator pd1=on, pd4_0 or pd4_1=on 445 705 a 25 *1 8mhz crystal for main oscillator pd1=on 440 680 a 25 *1 32khz crystal for sub oscillator pd1=on, pd4_0=on, pd4_1=on 85 300 a 25 - 32khz crystal for sub oscillator pd1=on, pd4_0 or pd4_1=on 80 275 a 25 *1 32khz crystal for sub oscillator pd1=on 75 250 a 25 *1 notes: ? t he values will be evaluated after engineering samples release. ? as for *1 the operation of shutting down pd4_0, or pd4_1, or both is now not supported.
document number: 002 - 05682 rev.*a page 89 of 179 S6J3200 series ? this characteristics is specified for the series with the function digit a, b, c, and d. ( condition: see 8.2 . operation assurance ) symbol pin name conditions value unit t a ( o c) remark typ max i cct5 v cc 5 4mhz crystal for main oscillator pd1=on, pd4_0=on, pd4_1=on 350 650 a 25 - 4mhz crystal for main oscillator pd1=on, pd4_0 or pd4_1=on 345 615 a 25 *1 4mhz crystal for main oscillator pd1=on 340 590 a 25 *1 8mhz crystal for main oscillator pd1=on, pd4_0=on, pd4_1=on 450 775 a 25 - 8mhz crystal for main oscillator pd1=on, pd4_0 or pd4_1=on 445 750 a 25 *1 8mhz crystal for main oscillator pd1=on 440 725 a 25 *1 32khz crystal for sub oscillator pd1=on, pd4_0=on, pd4_1=on 85 345 a 25 - 32khz crystal for sub oscillator pd1=on, pd4_0 or pd4_1=on 80 320 a 25 *1 32khz crystal for sub oscillator pd1=on 75 295 a 25 *1 notes: ? t he values will be evaluated after engineering samples release. ? as for *1 the operation of shutting down pd4_0, or pd4_1, or both is now not supported.
document number: 002 - 05682 rev.*a page 90 of 179 S6J3200 series 8.3.2.3 pss stop mode shutdown ? this characteristics is specified for the series with the function digit 3, 4, 5, 6, 7, and 8. ( condition: see 8.2 . operation assurance ) symbol pin name conditions value unit t a ( o c) remark typ max i cc h 5 v cc 5 pd1=on, pd4_0=on, pd4_1=on 65 270 a 25 - pd1=on, pd4_0 or pd4_1=on 60 245 a 25 *1 pd1=on 55 220 a 25 *1 ? this characteristics is specified for the series with the function digit a, b, c, and d. ( condition: see 8.2 . operation assurance ) symbol pin name conditions value unit t a ( o c) remark typ max i cc h 5 v cc 5 pd1=on, pd4_0=on, pd4_1=on 65 315 a 25 - pd1=on, pd4_0 or pd4_1=on 60 290 a 25 *1 pd1=on 55 265 a 25 *1 notes: ? t he values will be evaluated after engineering samples release. ? as for *1 the operation of shutting down pd4_0, or pd4_1, or both is now not supported.
document number: 002 - 05682 rev.*a page 91 of 179 S6J3200 series 8.4 ac c haracteristics 8.4.1 source clock timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max source oscillation clock frequency fc x0, x1 - 3.6 - 16 mhz source oscillation clock cycle time tcyl x0, x1 - 250.0 - 277.8 ns can pll jitter (when locked) tpj - - - 10 - 10 ns internal slow cr oscillation frequency fcrs - - 50 100 150 khz internal fast cr oscillation frequency fcrf - - 2.40 4.00 5.61 - mhz before trim 3.20 4.00 4.81 mhz after trim notes: ? the maximum/minimum values have been standardized with the main clock and pll clock in use. ? the error of source oscillator frequency must be smaller than 300 0 ppm . ? enough evaluation and adjustment are recommended using oscillator on your system board. ? x0 and x1 clock timing can pll jitter a time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles. ideal clock slow fast pll output x0 t cyl
document number: 002 - 05682 rev.*a page 92 of 179 S6J3200 series 8.4.2 sub clock timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max source oscillation clock frequency f cl x0a, x1a - - 32.768 - khz source oscillation clock cycle time t lcyl x0a, x1a - - 30.52 - s ? x0 a and x1 a clock timing x0 a t lc yl
document number: 002 - 05682 rev.*a page 93 of 179 S6J3200 series 8.4.3 internal clock timing ? this chapter shows the characteristics for internal clock timing at the current stage. ? in the column symbol, same clock names as described in chapter 5: clock system of platform hardware manu al are used. ? corresponding functions for these clocks are described in chapter 5: clock configuration of S6J3200 series hardware manual. ( condition: see 8.2 . operation assurance ) table 8 - 1 : assured combination of clock frequency symbol max value combination unit remarks function digit 3,4,5,6,7,8 function digit a,b,c,d max *1 max *2 max *3 max *4 f sscg0 232 (480) 200 (800) 160 (640) 160 (640) mhz sscg0 output clock f sscg1 200 (800) 200 (800) 200 (800) 200 (800) mhz sscg1 output clock f sscg2 200 (800) 200 (800) 200 (800) 160 (640) mhz sscg2 output clock f sscg3 400 (800) 400 (800) 400 (800) 400 (800) mhz sscg3 output clock f pll0 240 (720) 200 (800) 200 (800) 160 (640) mhz pll0 output clock f pll1 400 (800) 400 (800) 400 (800) 320 (640) mhz pll1 output clock f pll2 200 (800) 200 (800) 200 (800) 200 (800) mhz pll2 output clock f pll3 240 (480) 240 (480) 240 (480) 240 (480) mhz pll3 output clock f clk_cpu0 240 200 160 160 mhz f clk_ she 240 200 160 160 mhz f clk_fclk 80 66.7 80 80 mhz f clk_atb 120 100 80 80 mhz f clk_dbg 120 100 80 80 mhz f clk_hpm 120 200 160 160 mhz f clk_hpm2 60 100 80 80 mhz f clk_dma 120 200 160 160 mhz f clk_memc 120 200 160 160 mhz f clk_extbus 40 40 40 40 mhz unused f clk_sysc1 40 40 40 40 mhz f clk_happ0a0 40 40 40 40 mhz unused f clk_happ0a1 40 40 40 40 mhz unused f clk_happ1b0 60 50 80 80 mhz f clk_happ1b1 40 40 40 40 mhz unused f clk_llpbm 240 200 160 160 mhz f clk_llpbm2 120 100 80 80 mhz f clk_lcp 60 50 80 80 mhz f clk_lcp0 40 40 40 40 mhz f clk_lcp0a 60 66.7 80 80 mhz f clk_lcp1 40 40 40 40 mhz unused f clk_lcp1a 60 66.7 80 80 mhz f clk_lapp0 40 40 40 40 mhz unused f clk_lapp0a 40 40 40 40 mhz unused f clk_lapp1 40 40 40 40 mhz unused f clk_lapp1a 40 40 40 40 mhz unused f clk_trc 100 100 100 100 mhz f clk _cd1 400 400 400 400 mhz f clk _cd1a0 100 100 100 100 mhz unused f clk _cd1a1 100 100 100 100 mhz unused
document number: 002 - 05682 rev.*a page 94 of 179 S6J3200 series symbol max value combination unit remarks function digit 3,4,5,6,7,8 function digit a,b,c,d max *1 max *2 max *3 max *4 f clk _cd1b0 100 100 100 100 mhz unused f clk _cd1b1 100 100 100 100 mhz unused f clk _cd2 400 400 400 320 mhz unused f clk _cd2a0 400 400 400 320 mhz f clk _cd2a1 400 400 400 320 mhz unused f clk _cd2b0 400 400 400 320 mhz unused f clk _cd2b1 400 400 400 320 mhz unused f clk _cd3 200 200 200 160 mhz unused f clk _cd3a0 200 200 200 160 mhz f clk _cd3a1 200 200 200 160 mhz unused f clk _cd3b0 200 200 200 160 mhz unused f clk _cd3b1 200 200 200 160 mhz unused f clk _cd4 200 200 200 200 mhz f clk _cd4a0 200 200 200 200 mhz unused f clk _cd4a1 200 200 200 200 mhz unused f clk _cd4b0 200 200 200 200 mhz unused f clk _cd4b1 200 200 200 200 mhz unused f clk _cd5 240 240 240 240 mhz f clk _cd5a0 120 120 120 120 mhz f clk _cd5a1 120 120 120 120 mhz unused f clk _cd5b0 60 60 60 60 mhz f clk _cd5b1 60 60 60 60 mhz unused f clk_hsspi 200 200 200 200 mhz f clk_sysc0h 60 66.7 80 80 mhz f clk_comh 60 66.7 80 80 mhz f clk_ram0h 60 66.7 80 80 mhz f clk_ram1h 60 66.7 80 80 mhz f clk_sysc0p 60 66.7 80 80 mhz f clk_comp 60 66.7 80 80 mhz f clk_c an 40 40 40 40 mhz notes: ? *1: maximum clock frequencies when cpu clock = 240mhz. ? 232mhz or less is available for sscg down spread on/off. ? 240mhz or less is available for pll. ? *2: maximum clock frequencies when cpu clock = 200mhz. ? *3: maximum clock frequencies when cpu clock = 160mhz. this is also a combination of maximum clock frequencies for tc flash p rogramming or erasing. ? from *1 to *3, they are applied to the product series with function digit 3, 4, 5, 6, 7, and 8. ? *4: maximum clock frequencies when cpu clock = 160mhz for the product series with the function digit a, b, c, and d. this is also a combination of maximum clock frequencies for tc flash programming or erasing. ? even if a c ombination of clock frequency is able to be configured by software, the frequency should be configured under maximum frequency described in table 8 - 1 . for example, 80mhz of clk_lcp0a seems to be configurable from both divided 240mhz and 160mhz of clk_cpu. but each duty ratio of configured 80mhz as an internal signal is different fr om one another. in this series, the 80mhz from the 160mhz divided by 2 can only be assured, but the 240mhz divided by 3 cannot be assured from the internal timing design point of view. ? f clk_trc /2 (half frequency of f clk_trc ) comes out of the trace clock po rt of package external pin. ? the frequency described in () is maximum output frequency of sscg pll / pll multiplier circuit. ? the configurable minimum frequency of plln and sscgn output is 400mhz. ? "unused" means a clock source which doesn t have any supply d estinations. configure it as disable with performing at the lower clock frequency than the described maximum.
document number: 002 - 05682 rev.*a page 95 of 179 S6J3200 series ? operation assurance range relationship between the internal clock frequency and supply voltage note: cpu will be reset, when the power supply voltage is equal to or less than lvd setting voltage. 5.5 4.5 3.5 2 4 maximum frequency of each clock frequency [mhz] power supply v cc 5 [v] 1.3 1.2 1.15 2 4 maximum frequency of each clock frequency [mhz] power supply v cc12 [v] recommended guaranteed operation range guaranteed operation range pll guaranteed operation range
document number: 002 - 05682 rev.*a page 96 of 179 S6J3200 series ? relationship between the oscillation clock frequency and internal clock frequency internal operation clock frequency main clock pll clock multiplied by 1 multiplied by 2 multiplied by 3 multiplied by 4 multiplied by 40 multiplied by 60 oscillation clock frequency [mhz] 4 2 4 8 12 16 160 240 ? oscillation circuit example note: for the configuration of an oscillation circuit, request the oscillator manufacturer to perform a circuit matching evaluation before starting design. x1 x0 r c 2 c 1
document number: 002 - 05682 rev.*a page 97 of 179 S6J3200 series ac characteristics are specified by the following measurement reference voltage values. ? input signal waveform ? outp ut signal waveform hysteresis input pin (automotive) output pin hysteresis input pin (cmos schmitt) hysteresis input pin (ttl) 0.5v cc 5 0.8v cc 5 0.8v 2.4v 0.3v cc 5 0.7v cc 5 0.3v cc 3 0.7v cc 3 0. 8 v 2.0 v
document number: 002 - 05682 rev.*a page 98 of 179 S6J3200 series 8.4.4 reset input ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max reset input time t rstl rstx - 10 - s width for r eset input removal 1 - s 8.4.5 power - on conditions ( condition: see 8. 2 . operation assurance ) parameter symbol pin name conditions value unit remarks min typ max level detection voltage - v cc5 - 2. 1 5 2. 3 5 2. 5 5 v r eset release voltage - vcc5 - 2.25 2.45 2.65 v level detection time - - - - - 30 s * 1 slope detection undetected standard - v cc5 v cc5 = at level detection release level time - - 4 mv/s * 2 power off time - v cc5 - 50 - - ms *3 *1: if a power fluctuation precedes the low - voltage detection time, the detection may occur or be canceled after the supply voltage passes the detection voltage range. *2: t his time is a period that begins when the power supply is turned off and ends when an int ernal charge is released and tilt detection becomes possible for the next power - on. *3: t his time is to start the slope detection at next power on after power down and internal charge loss. rstx 0. 2 v cc 0. 2 v cc t rstl
document number: 002 - 05682 rev.*a page 99 of 179 S6J3200 series 8.4.6 multi - function serial 8.4.6.1 uart (asynchronous serial interface) t iming (smr:md2 - 0=0b000, 0b001) (1) external clock selected (bgr:ext=1) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min ma x serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 (cl = 50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a *1 +10 - ns sck16 to sck17 t clk _comp +10 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 t clk_lcp n a *1 +10 - ns sck16 to sck17 t clk _comp +10 - ns sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 - 5 ns sck rising time t r - 5 ns *1: n=0:ch.0 to ch. 4 , n=1:ch. 8 to ch.1 2 external clock selected external clock selected sck t shsl v il v ih v ih t r t slsh t f v il v ih v il
document number: 002 - 05682 rev.*a page 100 of 179 S6J3200 series 8.4.6.2 csio t iming (smr:md2 - 0=0b010) (1) normal synchronous transfer (scr:spi=0) and mark level "h" of serial clock output (smr:scinv=0) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck4, sck8 to sck12 master m ode (cl = 50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 6 t clk_lcp n a *1 - ns sck16 to sck17 3 t clk_ comp - ns sck sot slovi sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 15 +15 ns valid sin sck ivshi sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 20 - ns sck valid sin shixi 0 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 slave m ode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a *1 - 5 - ns sck16 to sck17 t clk_ comp - 5 - ns serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 2 t clk_lcp n a *1 - 5 - ns sck16 to sck17 2 t clk_ comp - 5 - ns sck sot slove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 20 ns valid sin sck ivshe sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 10 - ns sck valid sin shixe 10 - ns
document number: 002 - 05682 rev.*a page 101 of 179 S6J3200 series parameter symbol pin name conditions value unit remarks min max sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 slave m ode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) - 5 ns sck rising time t r sck0 to sck4, sck8 to sck12, sck16 to sck17 - 5 ns *1: n=0:ch.0 to ch. 4 , n=1:ch. 8 to ch.1 2 note s: ? this table provides the alternate current standard for clk synchronous mode. ? cl is the load capability value connected to the pin at the test time. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode t scyc v ol t slovi t ivshi t shixi v ih v il v oh v ol sck sot sin v ih v il v oh
document number: 002 - 05682 rev.*a page 102 of 179 S6J3200 series slave mode t slsh v i l t slove t ivshe t shixe v ih v il v oh v ol sck sot sin v ih v il t f v ih v i l v ih t shsl t r v ih
document number: 002 - 05682 rev.*a page 103 of 179 S6J3200 series (2) normal synchronous transfer (scr:spi=0) and mark level "l" of serial clock output (smr:scinv=1) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck4, sck8 to sck12 master m ode (cl = 50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 6 t clk_lcp n a *1 - ns sck16 to sck17 3 t clk_ comp - ns sck sot shovi sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 15 +15 ns valid sin sck ivsli sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 20 - ns sck valid sin slixi 0 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 sck16 to sck17 slave m ode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a *1 - 5 - ns t clk_ comp - 5 - ns serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 sck16 to sck17 2 t clk_lcp n a *1 - 5 - ns 2 t clk_ comp - 5 - ns sck sot shove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 20 ns valid sin sck ivsle sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 10 - ns sck valid sin slixe 10 - ns sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 - 5 ns sck rising time t r sck0 to sck4, sck8 to sck12, sck16 to sck17 - 5 ns *1: n=0:ch.0 to ch. 4 , n=1:ch. 8 to ch.1 2 note s : ? this table provides the alternate current standard for clk synchronous mode. ? cl is the load capability value connected to the pin at the test time. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002 - 05682 rev.*a page 104 of 179 S6J3200 series slave mode t shsl v i l t shove t ivsle t slixe v ih v il v oh v ol sck sot sin v ih v il t r v ih v i l v ih t slsh t f v i l master mode t scyc v oh t shovi t ivsli t slixi v ih v il v oh v ol sck sot sin v ih v il v ol
document number: 002 - 05682 rev.*a page 105 of 179 S6J3200 series (3) spi supported (scr:spi=1), and mark level "h" of serial clock output (smr:scinv=0) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck4, sck8 to sck12 master m ode (cl = 50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 6 t clk_lcp n a *1 - ns sck16 to sck17 3 t clk_ comp - ns sck sot shovi sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 15 +15 ns valid sin sck ivsli sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 20 - ns sck valid sin slixi 0 - ns sot sck sovli sck0 to sck4, sck8 to sck12 sot0 to sot4, sot8 to sot12 t clk_lcp n a *1 - 15 - ns sck16 to sck17 t clk_ comp *1 - 15 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 sck16 to sck17 slave m ode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a *1 - 5 - ns t clk_ comp - 5 - ns serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 sck16 to sck17 2 t clk_lcp n a *1 - 5 - ns 2 t clk_ comp - 5 - ns sck sot shove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 20 ns
document number: 002 - 05682 rev.*a page 106 of 179 S6J3200 series parameter symbol pin name conditions value unit remarks min max valid sin sck setup time t ivsle sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 slave m ode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 10 - ns sck valid sin hold time t slixe 10 - ns sck falling time t f sck0 to sck4, sck8 to sck12 sck16 to sck17 - 5 ns sck rising time t r sck0 to sck4, sck8 to sck12 sck16 to sck17 - 5 ns *1: n=0:ch.0 to ch. 4 , n=1:ch. 8 to ch.1 2 note s : ? this table provides the alternate current standard for clk synchronous mode. ? cl is the load capability value connected to the pin at the test time. ? the maximum baud rate is limited by the internal operating clock used and other par ameters. for details, see the hardware manual. master mode t scyc v ol t sovli t slixi v ih v il v oh v ol sck sot sin v ih v il v oh v oh v ol t ivsli t shovi v ol
document number: 002 - 05682 rev.*a page 107 of 179 S6J3200 series slave mode t slsh v i l t f t slixe v ih v il v oh v ol sck sot sin v ih v il v ih v oh v ol t ivsle t shove v i l v ih v ih v i l t shsl t r * * changes when writing to the tdr register
document number: 002 - 05682 rev.*a page 108 of 179 S6J3200 series (4) spi supported (scr:spi=1), and mark level "l" of serial clock output (smr:scinv=1) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck4, sck8 to sck12 master m ode (cl = 50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 6 t clk_lcp n a *1 - ns sck16 to sck17 3 t clk_ comp - ns sck slovi sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 15 +15 ns valid sin - > sck ivshi sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 20 - ns sck shixi 0 - ns sot - > sck sovhi sck0 to sck4, sck8 to sck12 sot0 to sot4, sot8 to sot12 t clk_lcp n a *1 - 15 - ns sck16 to sck17 sot16 to sot17 t clk_ comp - 15 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 slave m ode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a *1 - 5 - ns sck16 to sck17 t clk_ comp - 5 - ns serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 2 t clk_lcp n a *1 - 5 - ns sck16 to sck17 2 t clk_ comp - 5 - ns sck slove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 20 ns
document number: 002 - 05682 rev.*a page 109 of 179 S6J3200 series parameter symbol pin name conditions value unit remarks min max valid sin - > sck setup time t ivshe sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 slave m ode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 10 - ns sck - > valid sin hold time t shixe 10 - ns sck falling time t f sck0 to sck4, sck8 to sck12 sck16 to sck17 - 5 ns sck rising time t r sck0 to sck4, sck8 to sck12 sck16 to sck17 - 5 ns *1: n=0:ch.0 to ch. 4 , n=1:ch. 8 to ch.1 2 note s : ? this table provides the alternate current standard for clk synchronous mode . ? cl is the load capability value connected to the pin at the test time . ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode t scyc v oh t sovhi t shixi v ih v il v oh v ol sck sot sin v ih v il v ol v oh v ol t ivshi t slovi v oh
document number: 002 - 05682 rev.*a page 110 of 179 S6J3200 series slave mode t shsl v i l t r t shixe v ih v il v oh v ol sck sot sin v ih v il v ih v oh v ol t ivshe t slov e v i l v ih v ih v i l t slsh t f * * changes when writing to the tdr register
document number: 002 - 05682 rev.*a page 111 of 179 S6J3200 series 8.4.6.3 lin i nterface (v2.1) (lin communication control interface (v2.1)) t iming (smr:md2 - 0=0b011) (1) external clock selected (bgr:ext=1) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 (cl = 50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a *1 +1 0 - ns sck16 to sck17 t clk _comp +10 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 t clk_lcp n a *1 +1 0 - ns sck16 to sck17 t clk _comp +10 - ns sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 - 5 ns sck rising time t r - 5 ns *1: n=0:ch.0 to ch. 4 , n=1:ch. 8 to ch.1 2 external clock selected external clock selected sck t shsl v il v ih v ih t r t slsh t f v il v ih v il
document number: 002 - 05682 rev.*a page 112 of 179 S6J3200 series 8.4.6.4 i 2 c timing (smr:md2 - 0=0b1 0 0) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions standard mode high - speed mode unit remar ks min ma x min ma x scl clock frequency f s cl scl4, 10, 12, 16, and 17 (cl = 50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 0 100 0 400 khz repeat "start" condition hold time sda hdsta sda4, 10, 12, 16, and 17 scl4, 10, 12, 16, and 17 4.0 - 0.6 - s period of "l" for scl clock t low scl4, 10, 12, 16, and 17 4.7 - 1.3 - s period of "h" for scl clock t high scl4, 10, 12, 16, and 17 4.0 - 0.6 - s repeat "start" condition setup time scl susta sda4, 10, 12, 16, and 17 scl4, 10, 12, 16, and 17 4.7 - 0.6 - s data hold time scl hddat sda4, 10, 12, 16, and 17 scl4, 10, 12, 16, and 17 0 3.45 *1 0 0.9 *2 s data setup time sda sudat sda4, 10, 12, 16, and 17 scl4, 10, 12, 16, and 17 250 - 100 - ns "stop" condition setup time scl susto sda4, 10, 12, 16, and 17 scl4, 10, 12, 16 and 17 4.0 - 0.6 - s bus - free time between "stop" condition and "start" condition t buf - 4.7 - 1.3 - s noise filter t sp - 2 t clk _ comp - 2 t clk _ comp - ns notes: ? *1: the maximum t hddat only has to be met if the device does not extend the "l" width (t low ) of the scl signal. ? *2: a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". ? scl4, 10, 12 and sda4, 10, 12 only support the standard mode.
document number: 002 - 05682 rev.*a page 113 of 179 S6J3200 series sda scl t hdsta t low t hddat t sudat t high t susta t hdsta t sp t buf t susto
document number: 002 - 05682 rev.*a page 114 of 179 S6J3200 series 8.4.7 timer input ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max input pulse width t twh , t twl ppg0_tin1 to ppg11_tin1 - 4t clk_lcpna * 1 - ns 4t clk_lcpna * 1 clk_lcpna * 1 <100 ns icu0_in0 to icu11_in0, icu0_in1 to icu11_in1 - 4t clk_lcpna * 2 - ns 4t clk_lcpna * 2 clk_lcpna * 2 <100 ns frt0_text to frt11_text - 4t clk_lcpna * 2 - ns 4t clk_lcpna * 2 clk_lcpna * 2 <100 ns tin0 to tin3, tin16 to tin19 - 4t clk_lcpna * 3 - ns 4t clk_lcpna * 3 clk_lcpna * 2 <100 ns tin32 to tin35 - 4t clk_l lpbm2 - ns 4t clk_llpbm2 clk_lcpna * 2 <100 ns tin48 to tin49 - 4t clk_ comp - ns 4t clk_ comp clk_lcpna * 2 <100 ns *1: n=0:ch.0 to ch. 5 , n=1:ch. 6 to ch.1 1 * 2 : n=0:ch.0 to ch. 7 , n=1:ch. 8 to ch.1 1 * 3 : n=0:ch.0 to ch. 3 , n=1:ch. 16 to ch.1 9 ? timer input timing v ih v il icu x _ in 0/1 t tiwl t tiwh v ih v il frtx_ text tinx ppg x _ t in 1
document number: 002 - 05682 rev.*a page 115 of 179 S6J3200 series 8.4.8 trigger input ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trg l eint0 to eint15 - 100 - ns rx0 to rx1, rx5 to rx6 - 5t clk_ llpbm2 - ns eint0 to eint15 rx0 to r1, rx5 to rx6 - 1 - s stop mode ? trigger input timing v ih v il e intx t trgl t trgh v ih v il rxx
document number: 002 - 05682 rev.*a page 116 of 179 S6J3200 series 8.4.9 nmi input ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remark s min max input pulse width t nmil nmix - 300 - ns ? nmix input timing v ih nmix t n mil v ih v il v il
document number: 002 - 05682 rev.*a page 117 of 179 S6J3200 series 8.4.10 low - voltage detection 8.4.10.1 lvdl0 ( condition: see 8.2 . operation assurance ) parameter pin name conditions value unit remarks min typ max detection voltage - - 0.9 0.95 1.0 v - release voltage - - 0.975 1.025 1.075 v - level detection time - - - - 30 ? note: ? if the power fluctuation time is less than the low - voltage detection time and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range.
document number: 002 - 05682 rev.*a page 118 of 179 S6J3200 series 8.4.10.2 lvdh0 ( condition: see 8.2 . operation assurance ) parameter pin name conditions value unit remarks min typ max detection voltage v cc 5 - 2.2 2.35 2.5 v - release voltage v cc 5 - 2.3 2.45 2.6 v - level detection time v cc 5 - - - 30 ? cc 5 - - - 4 mv/ ? notes: ? *1: if a power fluctuation precedes the low - voltage detection time, the detection may occur or be canceled after the supply voltage passes the detection voltage range. ? *2: t his time is a period that begins when the power supply is turned off and ends when an int ernal charge is released and tilt detection becomes possible for the next power - on. ? *3: t his time is to start the slope detection at next power on after power down and internal charge loss.
document number: 002 - 05682 rev.*a page 119 of 179 S6J3200 series 8.4.10.3 lvdl1 ( condition: see 8.2 . operation assurance ) parameter pin name conditions value unit remarks min typ max detection voltage - lvdl1v=01 0.82 0.87 0.92 v release voltage - 0.895 0.945 0.995 v detection voltage - lvdl1v=10 (default) 0.92 0.97 1.02 v release voltage - 0.995 1.045 1.095 v detection voltage - lvdl1v=11 1.02 1.07 1.12 v release voltage - 1.095 1.145 1.195 v detection time - - - - 30 s n otes: ? if the power fluctuation time is less than the low - voltage detection time and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range.
document number: 002 - 05682 rev.*a page 120 of 179 S6J3200 series 8.4.10.4 lvdh1 ( condition: see 8.2 . operation assurance ) parameter pin name conditions value unit remarks min typ max supply voltage range v cc 5 - 4.5 - 5.5 v - detection voltage v cc 5 lvdh1v=0000 2.20 2.35 2.50 v - release voltage v cc 5 2.30 2.45 2.60 v - detection voltage v cc 5 lvdh1v=0001 2.60 2.75 2.90 v - release voltage v cc 5 2.70 2.85 3.00 v - detection voltage v cc 5 lvdh1v=0010 2.70 2.85 3.00 v - release voltage v cc 5 2.80 2.95 3.10 v - detection voltage v cc 5 lvdh1v=0011 3.40 3.60 3.80 v - release voltage v cc 5 3.50 3.70 3.90 v - detection voltage v cc 5 lvdh1v=0100 3.60 3.80 4.00 v - release voltage v cc 5 3.70 3.90 4.10 v - detection voltage v cc 5 lvdh1v=0101 3.80 4.00 4.20 v - release voltage v cc 5 3.90 4.10 4.30 v - detection voltage v cc 5 lvdh1v=0110 (default) 4.00 4.20 4.40 v - release voltage v cc 5 4.10 4.30 4.50 v - detection voltage v cc 5 lvdh1v=0111 4.20 4.40 4.60 v - release voltage v cc 5 4.30 4.50 4.70 v - detection voltage v cc 5 lvdh1v=other 4.40 4.65 4.90 v - release voltage v cc 5 4.50 4.75 5.00 v - detection time - - - - 30 s cc 5 - - 2 - 2 v/ms - notes: ? if the fluctuation of the power supply is faster than the low - voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. ? please suppress the change of the power supply within the range of the power - supply voltage regulation to do a low - voltage detection by detecting voltage .
document number: 002 - 05682 rev.*a page 121 of 179 S6J3200 series 8.4.10.5 lvdl2 ( condition: see 8.2 . operation assurance ) parameter pin name conditi ons value unit remarks min typ max supply voltage range v cc 12 - 1.1 - 1.3 v - detection voltage v cc 12 lvdl2v=00 (default) 0.72 0.77 0.82 v - release voltage v cc 12 0.795 0.845 0.895 v - detection voltage v cc 12 lvdl2v=01 0.82 0.87 0.92 v - release voltage v cc 12 0.895 0.945 9.995 v - detection voltage v cc 12 lvdl2v=10 0.92 0.97 1.02 v - release voltage v cc 12 0.995 1.045 1.095 v - detection voltage v cc 12 lvdl2v=11 1.02 1.07 1.12 v - release voltage v cc 12 1.095 1.145 1.195 v - detection time - - - - 30 s note: ? if the power fluctuation time is less than the low - voltage detection time and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range.
document number: 002 - 05682 rev.*a page 122 of 179 S6J3200 series 8.4.10.6 lv dh2 ( condition: see 8.2 . operation assurance ) parameter pin name conditions value unit remarks min typ max supply voltage range v cc 3 - 3.0 - 3.6 v - detection voltage v cc 3 lvdh2v=0000 (default) 2.2 2.35 2.5 v - release voltage v cc 3 2.3 2.45 2.6 v - detection voltage v cc 3 lvdh2v=0001 2.6 2.75 2.9 v - release voltage v cc 3 2.7 2.75 3.0 v - detection voltage v cc 3 lvdh2v=0010 2.7 2.85 3.0 v - release voltage v cc 3 2.8 2.95 3.1 v - detection time - - - - 30 s notes: ? if the fluctuation of the power supply is faster than the low - voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. ? please suppress the change of the power supply within the range of the power - supply voltage regulation to do a low - voltage detection by detecting voltage .
document number: 002 - 05682 rev.*a page 123 of 179 S6J3200 series 8.4.11 high current output slew rate ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditio ns value unit remarks min typ max output rise / fall time t r2 , t f2 p3_21 to 31, p4_00 to 12 - 15 - 100 ns l oad capacitance 85pf v h =v ol8 +0.9 x (v oh8 - v ol8 ) v l =v ol8 +0.1 x (v oh8 - v ol8 )
document number: 002 - 05682 rev.*a page 124 of 179 S6J3200 series 8.4.12 display controller 8.4.12.1 display controller0 timing (ttl mode) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value uni t remarks min max clock cycle t dc0cyc dsp0_clk (cl = 20pf, i ol = - 10 ma, i oh = 10 ma) 12.5 - ns *1 20 - ns *2 ou tp ut delay from dsp0_clk dc0d | dsp0_data0_11 - 0 dsp0_data1_11 - 0 dsp0_ctrl11 - 0 - 8.5 ns *3 output data valid time t dc0v dsp0_data0_11 - 0 dsp0_data1_11 - 0 dsp0_ctrl4 - 0 t dc0cyc - 3.2 - ns *1 dsp0_ctrl11 - 0 (cl = 20pf, iol= - 5ma, ioh=5ma) t dc0cyc - 5.12 - ns *2 notes: ? for *1, when used with dsp0_data* and dsp0_ctrl4 - 0 in vcc3 area. ? for *2, when used with dsp0_ctrl11 - 0 in vcc53 area. ? for *3, the value can be configured and adjusted. t dc 0 cyc dsp0_clk v oh v oh dsp0_data0_11 - 0 dsp0_data1_11 - 0 dsp0_ctrl11 - 0 valid t dc 0 d t dc 0 v
document number: 002 - 05682 rev.*a page 125 of 179 S6J3200 series 8.4.12.2 display controller0 timing (rsds) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max clock cycle t rscyc dsp0_clk+ dsp0_clk - (cl = 20pf, i ol = - 4 ma, i oh = 4 ma) 12.5 - ns ou tp ut delay from dsp0_clk rsd | dsp0_data_d11~0+ dsp0_data_d11~0 - - 7.3 ns *1 output data valid time t rsv dsp0_data_d11~0+ dsp0_data_d11~0 - t rscyc /2 - 1.6 - ns sp ou tp ut delay from dsp0_cl k spd dsp0_ctrl11~0 - 10.4 ns sp high time t spv dsp0_ctrl11~0 t rscyc - ns *2 rsds transition time rise and fall trtf dsp0_data_d11~0+ dsp0_data_d11~0 - 20 to 80% cl = 5pf, vod=200m v - - ps typ : 500ps notes: ? for *1, the value can be configured and adjusted. ? for *2, sp high time can be configured. t rs cyc dsp0_clk+ dsp0_clk - v oh v oh v oh v oh v ol t spv dsp0_data_d11~0+ dsp0_data_d11~0 - valid v oh v ol sp (dsp 0 _ctrl 0 ~ 11 ) t rsv v o l t spd valid v o l t sprs v oh t rsd t rsd t rsv t rsv
document number: 002 - 05682 rev.*a page 126 of 179 S6J3200 series 8.4.12.3 display controller1 timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max clock cycle t dc1cyc dsp1_clk (cl = 20pf, i ol = - 5 ma, i oh = 5 ma), 20.0 - ns ou tp ut delay from dsp1_clk dc1d dsp1_data0_11 - 0 dsp1_data1_11 - 0 dsp1_ctrl2 - 0 - 4.8 ns *1 output data valid time t dc1v dsp1_data0_11 - 0 dsp1_data1_11 - 0 dsp1_ctrl2 - 0 t dc1cyc - 5.12 - ns notes: ? for *1, the value can be configured and adjusted. dsp1_data0_11 - 0 dsp1_data1_11 - 0 dsp1_ctrl2 - 0 dsp1_clk t dc 1 cyc v oh v oh valid t dc 1 d t dc 1 v
document number: 002 - 05682 rev.*a page 127 of 179 S6J3200 series 8.4.13 video capture 8.4.13.1 video capture timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max clock cycle t cap0cyc cap0_clk - 12.5 - ns capture data setup time t cap0su cap0_data35~0 4.0 - ns capture data hold time t cap0hd cap0_data35~0 1.0 - ns t cap 0 cyc cap0_clk v ih v ih v ih valid t cap 0 su t cap 0 hd cap0_data35 - 0 v ih v il
document number: 002 - 05682 rev.*a page 128 of 179 S6J3200 series 8.4.14 fpd - link (lvds) ( condition: see 8.2 . operation assurance ) parameter symbol conditions value unit remarks min typ max output clock frequency f - - - 50 mhz differential output voltage v od r l = 100 ohm 210 300 390 mv one of three is selectable 250 350 450 mv 295 400 505 mv variation of v od delta v od - - 25 mv common mode voltage v cm 1.075 1.200 1.325 v one of three is selectable 1.125 1.250 1.375 v v ariation of v cm delta v cm - - 25 mv cycle time of txclkp/m t cip - 20 t 1000 ns duty of txclkp/m t cdt - - 4/7 * t - ns channel to channel skew of txoutxp/m t csk - - - 200 ps skew of txoutxp and txoutxm t dsk - - - 50 ps output pulse position for bit 0 t 0 f = 50mhz - 0.25 0 +0.25 ns output pulse position for bit 1 t 1 t/7 - 0.25 t/7 t/7 + 0.25 ns output pulse position for bit 2 t 2 2t/7 - 0.25 2t/7 2t/7 + 0.25 ns output pulse position for bit 3 t 3 3t/7 - 0.25 3t/7 3t/7 + 0.25 ns output pulse position for bit 4 t 4 4t/7 - 0.25 4t/7 4t/7 + 0.25 ns output pulse position for bit 5 t 5 5t/7 - 0.25 5t/7 5t/7 + 0.25 ns output pulse position for bit 6 t 6 6t/7 - 0.25 6t/7 6t/7 + 0.25 ns note: ? all the corresponding ports of products which don't support fpd - link should be connected to gnd. avcc3_lvds_pll, avss3_lvds_pll, vcc3_lvds_tx, vss3_lvds_tx, txdoutn+/ - , txclk+/ - .
document number: 002 - 05682 rev.*a page 129 of 179 S6J3200 series figure 8 - 6 : lvds ac timing chart d1 d0 d6 d5 d4 d3 d2 d1 d2 d3 d0 d6 t xdout3 t xclk d1 d0 d6 d5 d4 d3 d2 d1 d2 d3 d0 d6 t xdout2 d1 d0 d6 d5 d4 d3 d2 d1 d2 d3 d0 d6 t xdout1 d1 d0 d6 d5 d4 d3 d2 d1 d2 d3 d0 d6 t xdout0 t cip t h t l t 0 t 1 t 2 t 3 t 4 t 5 t 6 t csk t cdt = t h / (t h + t l )
document number: 002 - 05682 rev.*a page 130 of 179 S6J3200 series figure 8 - 7 : lvds ac timing chart tx - m tx - p d elta v cm 0 voltage [v] v cm v od d elta v od = v od .max C v od .min single end tx - m tx - p 0 voltage [v] v cm t dsk common voltage for each data bit
document number: 002 - 05682 rev.*a page 131 of 179 S6J3200 series 8.4.15 ddr - hsspi 8.4.15.1 ddr - hsspi interface timing (sdr mode) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max hsspi clock cycle t cyc g_sclk0 m_sclk0 (cl = 20pf, i ol = - 10 ma, i oh = 10 ma), 10 - ns 20 - when quad page program g_sclk spcnt - 0 31.5 ns gsdata - > g_sclk isdata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 *1 - ns g_sclk ihdata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 *1 - ns g_sclk oddata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 - tcyc/2 + 2 ns g_sclk ohdata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 tcyc/2 - 3 - ns gssel odsel g_ssel0, 1 m_ssel0, 1 - 1 2.00 +( ss2cd+ 0.5)*tcyc - ns g_sclk ohsel g_ssel0, 1 m_ssel0, 1 tcyc - 2 - ns notes: ? ss2cd [1:0] should be configured as 01, 10, or 11. ? for *1, the delay of the delay sample clock can be configured (dlp function).
document number: 002 - 05682 rev.*a page 132 of 179 S6J3200 series t cyc v ih v il g_sclk 0 g_sdata 0 _ 0 - 3 , g_sdata 1 _ 0 - 3 (input timing) v oh v oh v ih v il valid t isdata delayed sample clock t ihdata v oh t spcnt v oh v ol g_sdata 0 _ 0 - 3 , g_sdata 1 _ 0 - 3 (output timing) v oh v ol valid t oddata t ohdata v oh v ol gssel 0 , 1 (output timing) v oh v ol valid t odsel t ohsel
document number: 002 - 05682 rev.*a page 133 of 179 S6J3200 series 8.4.15.2 ddr - hsspi interface timing (ddr mode) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max hsspi clock cycle t cyc g_sclk0 m_sclk0 (cl = 20pf, i ol = - 10 ma, i oh = 10 ma), 12.5 - ns g_sclk spcnt - 0 31.5 ns gsdata - > g_sclk isdata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 *1 - ns g_sclk ihdata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 *1 - ns g_sclk oddata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 - tcyc/4 + 1.5 ns g_sclk ohdata g_sdata0_0 - 3 g_sdata1_0 - 3 m_sdata0_0 - 3 m_sdata1_0 - 3 t cyc/4 - 1.0 - ns gssel odsel g_ssel0, 1 m_ssel0, 1 - 15.75+(s s2cd+0.5) *tcyc - ns g_sclk ohsel g_ssel0, 1 m_ssel0, 1 0.75*tcyc - 2.0 - ns notes: ? ss2cd [1:0] should be configured as 01, 10, or 11. ? for *1, the delay of the delay sample clock can be configured (dlp function). ?
document number: 002 - 05682 rev.*a page 134 of 179 S6J3200 series v oh v ol v oh v ol v oh v ol v oh v ol t cyc v ih v il g_sclk 0 g_sdata 0 _ 0 - 3 , g_sdata 1 _ 0 - 3 (input timing) v oh v oh v ih v il valid t isdata delayed sample clock t ihdata v oh t spcnt g_sdata 0 _ 0 - 3 , g_sdata 1 _ 0 - 3 (output timing) valid t oddata gssel 0 , 1 (output timing) valid t odsel t ohsel valid v ol t ohdata t oddata t ohdata
document number: 002 - 05682 rev.*a page 135 of 179 S6J3200 series 8.4.16 hyperbus 8.4.16.1 hyperbus write timing (hyperflash) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max hyper bus clock cycle t ckcyc g_ck m_ck (cl = 20pf, i ol = - 10 ma, i oh = 10 ma), 12.5 - ns (a) 10 - ns (b) cs css g_cs#_1,2 m_cs#_1,2 t ckcyc - 3.25 - ns (a) t ckcyc - 2.0 - ns (b) dq - > ck is g_dq7 - 0 m_dq7 - 0 1.25 - ns ck ih g_dq7 - 0 m_dq7 - 0 1.25 - ns ck csh g_cs#_1,2 m_cs#_1,2 t ckcyc /2 - ns note s : ? (a): the value will be targeted by the product series with revision digit a. ? (b): the value will be targeted by the product series with revision digit b. v ih v oh t css v ol v il ca0 47 - 40 ca0 39 - 32 ca1 31 - 24 ca1 23 - 16 ca2 15 - 8 ca2 7 - 0 dn 15 - 8 dn 7 - 0 v ol t dsv t cshi t is t dsz v oh t css t csh t ih t ckcyc g_ck m_ck g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 g_cs#_ 1 , 2 m_cs#_ 1 , 2
document number: 002 - 05682 rev.*a page 136 of 179 S6J3200 series 8.4.16.2 hyper bus write timing (hyperram) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max hyper bus clock cycle t ckcyc g_ck m_ck (cl = 20pf, i ol = - 10 ma, i oh = 10 ma), 12.5 - ns (a) 10 - ns (b) cs css g_cs#_1,2 m_cs#_1,2 t ckcyc - 3.25 - ns (a) t ckcyc - 2.0 - ns (b) dq - > ck is g_dq7 - 0 m_dq7 - 0 1.25 - ns ck ih g_dq7 - 0 m_dq7 - 0 1.25 - ns ck csh g_cs#_1,2 m_cs#_1,2 t ckcyc /2 - ns rwds dmv g_rwds m_rwds 1 - ns ck riv g_rwds m_rwds - 6 ns ck rih g_rwds m_rwds 0 - ns notes: ? (a): the value is targeted by the product series with revision digit a. ? (b): the value is targeted by the product series with revision digit b. v ih v oh t css v il v il ca0 47 - 40 ca0 39 - 32 ca1 31 - 24 ca1 23 - 16 ca2 15 - 8 ca2 7 - 0 dn 15 - 8 dn 7 - 0 v ol t rih t riv t cshi t csm t po t rwr t is t ih t ih t is t dmv v ih v oh v ol t css t csh t ckcyc g_ck m_ck g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 g_cs#_ 1 , 2 m_cs#_ 1 , 2
document number: 002 - 05682 rev.*a page 137 of 179 S6J3200 series 8.4.16.3 hyper bus read timing (hyperflash) ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value uni t remark s min max hyper bus clock cycle t rdscyc g_ck, g_rwds m_ck, m_rwds (cl = 20pf, i ol = - 10 ma, i oh = 10 ma), 12.5 - ns (a) 10 - ns (b) cs css g_cs#_1,2 m_cs#_1,2 t rdscyc - 3.25 - ns (a) t rdscyc - 2.0 ns (b) dq - > ck is g_dq7 - 0 m_dq7 - 0 1.25 - ns ck ih g_dq7 - 0 m_dq7 - 0 1.25 - ns ck csh g_cs#_1,2 m_cs#_1,2 t rdscyc / 2 - ns rds > dss g_dq7 - 0 m_dq7 - 0 - 0.8 - ns rds > dsh g_dq7 - 0 m_dq7 - 0 - 0.8 - ns ? (a): the value is targeted by the product series with revision digit a. ? (b): the value is targeted by the product series with revision digit b. v ih g_ck m_ck v oh t css v ol v il g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 ca0 47 - 40 ca0 39 - 32 ca1 31 - 24 ca1 23 - 16 ca2 15 - 8 ca2 7 - 0 dn 15 - 8 dn 7 - 0 v ol t dsv t cshi t acc t ih t dsh t dqlz v oh v oh t css t csh g_cs#_ 1 , 2 m_cs#_ 1 , 2 dn+1 15 - 8 dn+1 7 - 0 t is t dss t oz t dsz t ckds t rdscyc v oh v ol
document number: 002 - 05682 rev.*a page 138 of 179 S6J3200 series 8.4.16.4 hyper bus read timing (hyperram) ( condition: see 8.2 . operation assurance ) parameter symb ol pin name conditions value unit remarks min max hyper bus clock cycle t rdscyc g_ck, g_rwds m_ck, m_rwds (cl = 20pf, i ol = - 10 ma, i oh = 10 ma), 12.5 - ns (a) 10 - ns (b) cs css g_cs#_1,2 m_cs#_1,2 t rdscyc - 3.25 - ns (a) t rdscyc - 2.0 - ns (b) dq - > ck is g_dq7 - 0 m_dq7 - 0 1.25 - ns ck ih g_dq7 - 0 m_dq7 - 0 1.25 - ns ck csh g_cs#_1,2 m_cs#_1,2 t rdscyc /2 - ns rwds > dss g_dq7 - 0 m_dq7 - 0 - 0.8 - ns rwds > dsh g_dq7 - 0 m_dq7 - 0 - 8 - ns ck riv g_rwds m_rwds - 6 ns ck rih g_rwds m_rwds 0 - ns notes: ? (a): the value is targeted by the product series with revision digit a. ? (b): the value is targeted by the product series with revision digit b. v ih v oh t css v ol v il ca0 47 - 40 ca0 39 - 32 ca1 31 - 24 ca1 23 - 16 ca2 15 - 8 ca2 7 - 0 dn 15 - 8 dn 7 - 0 v ol t rih t riv t cshi t csm t po t rwr t is t dsh t dqlz v oh v oh t css t csh dn+1 15 - 8 dn+1 7 - 0 t ih t dss t oz t dsz t ckds t rdscyc g_ck m_ck g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 g_cs#_ 1 , 2 m_cs#_ 1 , 2 v oh v ol
document number: 002 - 05682 rev.*a page 139 of 179 S6J3200 series 8.4.17 ethernet avb 8.4.17.1 ethernet receive timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max rxclk cylcle t rxcyc rxclk - 40.0 - ns rx setup time t rxs rxer rxdv rxd0 - 3 10.0 - ns t rxcyc - 30ns rx hold time t rxh rxer rxdv rxd0 - 3 0 - ns t rxcyc rxclk v ih v ih valid v ih v il t rxs t rxh rxer rxdv rxd 0 - 3
document number: 002 - 05682 rev.*a page 140 of 179 S6J3200 series 8.4.17.2 ethernet transmit timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max txclk cylcle t txcyc rxclk (cl = 20pf, iol= - 5ma, ioh=5ma), 40.0 - ns col/crs input setup time t crxs col crs 12.0 - ns col/crs input hold time t crxh col crs 0.5 - ns tx delay time t txd txer txdv txd0 - 3 0.5 25 ns t txcyc txclk valid t crxs t crxh col crs valid v oh v ol txer txdv txd 0 - 3 t txd t txd v ih v ih v ih v ih v ih v il
document number: 002 - 05682 rev.*a page 141 of 179 S6J3200 series 8.4.17.3 mdio timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max mdc cylcle t mdcyc mdc (cl = 20pf, iol= - 5ma, ioh=5ma), 400.0 - ns mdio input setup time t mdis mdio 100.0 - ns mdio input hold time t mdih mdio 0.0 - ns mdio output delay time t mdod mdio 10.0 190.0 ns t mdcyc mdc v oh v oh v oh v ol valid v ih v il t mdis t mdih mdio (in) valid v oh v ol t mdod t mdod mdio (out) v oh
document number: 002 - 05682 rev.*a page 142 of 179 S6J3200 series 8.4.18 medialb 8.4.18.1 medialb input timing (condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max mlbclk cycle t mckc mlbclk - 40 - ns mlbsig, mlbdat i nput setup t dsmcf mlbsig mlbdat 1.0 - ns mlbsig, mlbdat i nput hold t dhmcf mlbsig mlbdat 4.0 - ns note s : ? clk_happ1b0(internal) frequency > mlbclk(external) frequency input t mckc v i l t dsmcf v i h v i l mlbclk mlbdat, mlbsig v i h t dhmcf v i h v ih v il valid
document number: 002 - 05682 rev.*a page 143 of 179 S6J3200 series 8.4.18.2 medialb output timing ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max mlbclk cycle t mckc mlbclk (cl = 20pf, i ol = - 6 ma, i oh = 6 ma), 40 - ns mlbsig, mlbdat output stop t mcfdz mlbsig mlbdat 26.5 - ns t mckc - t dout mlbsig, mlbdat output delay t dout mlbsig mlbdat 0 13.5 ns note s : ? clk_happ1b0(internal) frequency > mlbclk(external) frequency t mckc t dout v oh v ol mlbclk mlbdat, mlbsig v ih t mcfdz v ih v oh v ol valid
document number: 002 - 05682 rev.*a page 144 of 179 S6J3200 series 8.4.19 port noise filter ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions value unit remarks min max width for input removal - all gpio - - 67 ns * *: input pulse width less than at least t yp 25ns to m ax 67ns is removed when port noise filter is enabled. *: input pulse width 100ns or more is recommended to be effective .
document number: 002 - 05682 rev.*a page 145 of 179 S6J3200 series 8.5 a/d converter 8.5.1 electrical characteristics ( condition: see 8.2 . operation assurance ) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit total error - - - - 12 lsb *3 integral non linearity - - - - 4.0 lsb *4 differential non linearity - - - - 1.9 lsb *4 zero transition voltage v z t an0 to an 49 avrl - 11.5lsb - avrl +12.5lsb v *5 full - scale transition voltage v fst an0 to an 49 avrh - 13.5lsb - avrh +10.5lsb v sampling time t smp - 0.3 - - s * 1 compare time t cmp - 0. 8 - 28 s * 1 a/d conversion time t cnv - 1.1 - - s * 1 a/d trigger input time adtrg 4t clk_lcp1a - - ns 4t clk_lcp1a clk_lcp1a < 100ns resumption time - - - - 1 us - analog port input current i ain an0 to an 17 - 1.0 - 1.0 a v avss ? v ain v avcc an18 to an25 - 2.0 - 2.0 a an26 to an49 - 3.0 - 3.0 a analog input voltage v ain an0 to an 49 avss - avrh v reference voltage avrh avr h5 4.5 - 5.5 v av cc avrh avrl avrl 5/avs s - 0.0 - v power supply current i a avcc - 500 900 a i ah - 1.0 100 a *2 i r avrh - 1 .0 2 .0 ma i rh - - 5.0 a * 2 variation between channels - an 0 to an 49 - - 4 .0 lsb *1 : time per channel *2 : definition of the power supply current (when v cc =av cc =5.0 v) while the a/d converter is not operating and in stop mode * 3: total error is a comprehensive static error that includes the linearity after trimming by software. 1lsb=( avrh - avr l)/4096 * 4: 1lsb=(vfst - vzt)/4094 * 5: 1lsb=( a v r h - a vrl)/4096
document number: 002 - 05682 rev.*a page 146 of 179 S6J3200 series 8.5.2 notes on a/d converters about the output impedance of an external circuit for analog input when the external impedance is too high, the analog voltage sampling time may become insufficient. in this case, we recommend attaching a capacitor (about 0.1 f) to an analog input pin. analog input circuit model r c 12 - bit a/d 3.9 kiloohms (max) 11.0 pf (max) (4.5 va cc 5. 8.5.3 glossary resolution: analog change that can be identified by an a/d converter integral linearity error: deviation of the straight line connecting the zero transition point ("0000 0000 0000" < -- > "0000 0000 0001") and full - scale transition point ("1111 1111 1110" < -- > "1111 1111 1111") from actual conv ersion characteristics includes zero transition error, full - scale transition error, and non linearity error. differential linearity error: deviation from the ideal value of the input voltage required for changing the output code by 1 lsb total error : diff erence between the actual value and the theoretical value. the total error 8.5.4 calibration condition calibration condition should be the followings. ? avcc=5.0v ? avrh=5.0v ? ta=25 ? system clock frequency (clk_lcp1a)= 10mhz see a/d converter calibration on the S6J3200 hardware manual. r c sampling on c omparator analog input
document number: 002 - 05682 rev.*a page 147 of 179 S6J3200 series total error total error of digital output n = v nt - {1 lsb (n - 1) + 0.5lsb } [lsb] 1lsb 1lsb (ideal value) = a v rh - a v rl [v] 409 6 n : a/d converter digital output value. v zt ( ideal value) = avrl + 0.5lsb[v] v fs t ( ideal value) = avrh - 1.5lsb[v] v n t : voltage at which the digital output changes from " (n C 1) " to " n ". fff ffe ffd 004 003 002 001 a v rl (a v ss ) avrh {1 lsb (n - 1) + 0.5lsb } 1.5lsb v nt 0.5lsb ideal characteristics actual conversion characteristics ( actually - measured value) analog input actual con ver sion cha ract eris tics (measured value) digital output
document number: 002 - 05682 rev.*a page 148 of 179 S6J3200 series integral linearity error differential linearity error integral linearity error of digital output n = v nt - {1 lsb (n - 1) + v zt } [lsb] 1lsb differential linearity error of digital output n = v (n+1) t - v nt - 1 lsb [lsb] 1lsb 1lsb = v fst - v zt [v] 4094 v zt : voltage for which digital output changes from "0x000" to "0x001" v fst : voltage for which digital output changes from "0xffe" to "0xfff". fff ffe ffd 004 003 002 001 a vss ( a vrl) avrh avrh actual conversion characteristics {1 lsb (n - 1) + v zt } n - 1 a vss ( a vrl) n - 2 n n + 1 v fst v nt v zt v (n+1)t v nt ideal characteristics actual conversion characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output (measured value) (measured value) (measured value) (measured value) analog input analog input (measured value) digital output
document number: 002 - 05682 rev.*a page 149 of 179 S6J3200 series 8.6 audio dac 8.6.1 electrical characteristics ( condition: see 8.2 . operation assurance ) parameter symbol pin name conditions *1 value unit remarks min typ max system clock frequency f clkda0 - - 2.048 - 18.43 2 mhz sampling clock fs - - 8 - 48 khz analog output load resistance *2 r l dac_ l dac_ r - 20 - - k *2 c l - - - 100 pf capacitance - c_ l c_ r - 5 10 20 f analog output single - end output range (full scale) - dac_ l dac_ r rl=20k p - p analog output voltage (zero) - - - 0.5 avcc3_da c - v thd+n *3 - - signal frequency: 1khz lpf(fc: 20khz) - - 82 - 72 db snr *3 - - signal frequency: 1khz lpf(fc: 20khz) *3 - - 83 86 - db out - of - band energy - - 20khz to 64fs - - - 33 db channel separation - - - - 80 - db output impedance - - - 150 200 250 *4 - - dae * 5 - ms notes: ? *1 : all parameters specified fs=44.1 khz, system clock 256fs and 16 - bit data, rl - 20k, c l =100pf, unless otherwise noted. ? * 2: refer to bellow note on r l load connection. ? * 3: these values do not include the noise caused by the analog power supply. (refer to 7 . use examples) ? * 4: 10f is connected to c _ l, c _ r. ? * 5: startup time ( figure 8 - 8 )
document number: 002 - 05682 rev.*a page 150 of 179 S6J3200 series figure 8 - 8 : startup time startup time can be calculated as follows. 1. startup time (typ) = 650[ms] (table 5.2) 2. ccom=10uf(1/100) ccom is a capacitor connected to termi n al c_l/c_r including capacitance variance. =capacitance variance[%] 3. startup time = start up time(typ)(1) [ms] for example, ccom=11f then =(11f - 10f)/10f=10[%] so, startup time = 650ms 1+10/100 = 715[ms] notes: ? two usages of r l l oad connection . ? case1 : r l is connected to avcc3_dac /2 ( figure 8 - 9 ) ? case2: t he coupling capacitance must be inserted as shown in ( figure 8 - 10 ). figure 8 - 9 : r l is connected to avcc_dac/2 (example) last volgate 10mv time [sec] dae startup time dac_l/dac_r c l : max 100pf dac_l/dac_r r l : min 20k avcc3_dac/2
document number: 002 - 05682 rev.*a page 151 of 179 S6J3200 series figure 8 - 10 : coupling c apacitance (example) notes: ? c1: more than 10f low esr capacitors ? c2: 0.1f ceramic capacitors ? c 3 , c 4 , c 5 , c 6 : 10f low esr capacitors ? impedance of each power line must be as low as possible. notes: ? when dac is not used in your system, the related pins should be ? avcc3_dac=gnd and av ss=gnd ? c_l=open and c_r=open ? dac_l=open and dac_r=open c_r c_l c3 c4 avcc3_dac avss avss avss c1 c2 low noise regulator dac_r dac_l post lpf/ buffer post lpf/ buffer c5 c6
document number: 002 - 05682 rev.*a page 152 of 179 S6J3200 series 8.7 flash memory 8.7.1 electrical characteristics parameter value unit remarks min typ max * 3 sector erase time - 300 1100 ms 8 k b sector *1 internal preprogramming time in cluded - 800 3700 ms 64k b sector *1 internal preprogramming time in cluded 8bit write time - 15 288 s system - level overhead time excluded *1 16bit write time - 19 384 s system - level overhead time excluded *1 32bit write time - 27 567 s system - level overhead time excluded *1 64bit write time - 45 945 s system - level overhead time excluded *1 8bit (with ecc) write time - 19 384 s system - level overhead time excluded *1 16bit (with ecc) write time - 23 483 s system - level overhead time excluded *1 32bit (with ecc) write time - 31 651 s system - level overhead time excluded *1 64bit (with ecc) write time - 49 1029 s system - level overhead time excluded *1 erase count * 2 / data retention time 1,000/20 years 10,000/10 years 100,000/5 years - - - temperature at write/erase time average temperature t a =+85 degrees celsius notes: ? *1 : g uaranteed value for up to 100,000 erases ? *2 : number of erases for each sector 8.7.2 notes while the flash memory is written or erased, shutdown of the external power (v cc 5) is prohibited. in the application syste m where v cc 5 might be shut down while writing or erasing, be sure to turn the power off by using an external voltage detection function. to put it concretely, after the external power supply voltage falls below the detection voltage (v dl ), hold v cc 5 at 2.7v or more within the duration calculated by the following expression: td * 1 [s] + ( 1 / f crf * 2 [mhz] ) x 1029 + 25 [s] * 1 : see " 8.4.10 low - voltage detection " *2 : see " 8.4.1 source clock "
document number: 002 - 05682 rev.*a page 153 of 179 S6J3200 series 9. abbreviation abbreviation definition remark a/d converter analog to digital converter adc analog to digital converter ahb advanced high performance bus ambatm advanced microcontroller bus architecture apb advanced peripheral bus atcm tcm - a port axi advanced extensible interface b0tcm tcm b0 port b1tcm tcm b1 port bbu bit banding unit bdr boot description record bt base timer btl bridge - tied load can control area network cd clock domain cpu central processing unit cr cr oscillator crc cyclic redundancy check csv clock supervisor dac digital analog converter dap debug access port ded dual error detection dma direct memory access dmac dma controller eam exclusive access memory ecc error correction code etm embedded trace macro ext - irc external interrupt controller fiq fast interrupt request fpu floating point unit frt free - run timer gpio general purpose i/o hpm high performance matrix hw - wdt hardware watchdog timer i/o input or output i2s inter - ic sound icu input capture unit ipcu inter - processor communication unit irc interrupt controller irq interrupt request isr interrupt service routine jtag joint test action group llpp low latency peripheral port lvd low voltage detector mcu microcontroller unit mfs multi - function serial interface mlb media lb
document number: 002 - 05682 rev.*a page 154 of 179 S6J3200 series abbreviation definition remark nf noise filter nmi non maskable interrupt ocu output compare unit osc oscillator pcb printed circuit board pcba printed circuit board assembly pcm pulse coded module pd power domain pll phase locked loop ponr power on reset ppc port pin configuration psc power supply control pss power saving state pwm pulse width modulation ram random access memory ric resource input configuration rlt reload timer rom read only memory rsds reduced swing differential signal rtc real time clock rvd low voltage detection and reset for ram retention sct source clock timer sec single error correction secded single error correction and dual error detection sg sound generator she secure hardware extension smc stepper motor controller smix sound mixer spi serial peripheral interface sram static ram sscg spread spectrum clock generation swfg sound waveform generator sw - wdt software watchdog timer sysc system controller tcflash flash connected to tcm tcm tightly coupled memory tcram ram connected to tcm tpu timing protection unit tsu time stamp unit udc up - down counter vic vectored interrupt controller vram video ram wdr watchdog description record wdt watchdog timer wfg waveform generator workflash work flash memory
document number: 002 - 05682 rev.*a page 155 of 179 S6J3200 series 10. ordering information table 10 - 1 : order part number table part number package s6j326cksfee20000 let208 (208 - pin plastic teqfp) s6j326clsfee20000 leq216 (216 - pin plastic teqfp) s6j328cksfee20000 let208 (208 - pin plastic teqfp) s6j328clsfee20000 leq216 (216 - pin plastic teqfp)
document number: 002 - 05682 rev.*a page 156 of 179 S6J3200 series 11. major changes spansion publication number: S6J3200_ds708 - 00003 page section change results revision 0.1 - - initial release revision 0.2 - - see 11.1 supplementary information as described in " 1 . overview 1. 2. document definition revision 0.3 - - see 11.1 supplementary information as described in " 1 . overview 1. 2. document definition revision 0.4 - - see 11.1 supplementary information as described in " 1 . overview 1. 2. document definition revision 1.0 - - see 11.1 supplementary information as described in " 1 . overview 1. 2. document definition note: please see document history about later revised information. 11.1 supplementary information all the changes between previous and current document edition are described in this sheet. following "id" is a number which is owned by every change. a change which is applied to other documents of same family should have a same id. summary error page error correct page correct id original document code: ds708 - 00003 - 0v02 - e, previous document code: ds708 - 00003 - 0v01 - e rev. 1.0 december 26, 2014 pin assignment 22, 23 (relation on pin assignment) ||function||port || ||mfs8_cs0||p3_08|| ||mfs9_cs0||p3_09|| ||mfs9_cs1||p3_10|| ||mfs8_cs3||p3_11|| ||mfs8_cs1||p3_12|| ||mfs8_cs2||p3_13|| 22, 23 (relation on pin assignment) ||function||port || ||mfs8_cs0||p3_12|| ||mfs9_cs0||p3_13|| ||mfs9_cs1||p3_14|| ||mfs8_cs3||p3_15|| ||mfs8_cs1||p3_16|| ||mfs8_cs2||p3_17|| #150 i2s port name 22,23 i2s1_ws1 i2s1_sck1 22,23 i2s1_ws i2s1_sck #190 ethernet port name 22,23 rdx0, rdx1, rdx2, rdx3 22,23 rxd0, rxd1, rxd2, rxd3 #191
document number: 002 - 05682 rev.*a page 157 of 179 S6J3200 series summary error page error correct page correct id vcc12 power supply 62 vss12: 1.15(min), 1.3(max) 62 vss12: 1.15(min), 1.3(max) 1.1(min)*1, 1.3(max) ? *1. the value will be for the product series with revision digit b. #169 current consumption 69 icc12: - (typ), 1900(max) icct5: - (typ), 2620(max) icch5: - (typ), 2620(max) 68 icc12: 950(typ),1900(max) icct5: 350(typ),700(max) icch5: 150(typ),450(max) #170 vcc5 current consumption 69 icc5 normal operation 60ma(max) 68 icc5 normal operation 45ma(typ), 75ma(max) #181 current consumption of fpd link 69 - 68 ilvds: vcc3_lvds_tx,avcc3_lvds_pll: 70ma (fpd - link) #204 source clock error 72 note: - ,,,, - jitter of source oscillator must be smaller than 300ppm. 71 note: - ,,,, - the error of source oscillator frequency must be smaller than 300ppm. #178 trace clock 74, 75 fclk_trc: 50mhz 73, 74 fclk_trc: 100mhz note; - fclk_trc/2 (half frequency of fclk_tr c) comes out of the trace clock port of package external pin. #182 internal clock frequency 75 notes; - ,,, 74 notes; - ,,, - even if a combination of clock frequency is able to be configured by software, the frequency should be configured under maximum frequency described in table. for example, 80mhz of clk_lcp0a seems to be configurable from both divided 240mhz and 160mhz of clk_cpu. but each duty ratio of configured 80mhz as an internal signal is different from one another. in this series, the 80mhz fr om the 160mhz divided by 2 can only be assured, but the 240mhz divided by 3 cannot be assured from the internal timing design point of view. #180 power on condition 79 level detection voltage: 2.25(min) 2.45(typ) 2.65(max) 78 level detection voltage: 2.15(min) 2.35(typ) 2.55(max) reset release voltage: 2.25(min) 2.45(typ) 2.65(max) #138
document number: 002 - 05682 rev.*a page 158 of 179 S6J3200 series summary error page error correct page correct id display controller ac specification 101 display controller0 timing (ttl mode) tdc0cyc: 12.5ns (min) |tdc0d|: - (remarks) tdc0v: - (remarks) notes: - ,,,, display controller0 timing (rsds) |trsd|: - (remarks) tspv: - (remarks) notes: - ,,,, 100 display controller0 timing (ttl mode) tdc0cyc: 12.5ns (min) *1 20ns(min) *2 |tdc0d|: *3 (remarks) tdc0v: *1, *4 (remarks) notes: - ,,,, ? for *1, when used with dsp0_d ata* and dsp0_ctrl4 - 0 in vcc3 area. ? for *2, when used with dsp0_data* and dsp0_ctrl4 - 0 in vcc53 area. ? for *3, the value can be configured and adjusted. ? for *4, the value is defined as tdc0cyc - |tdc0d| and depends on adjustment of *3. display contro ller0 timing (rsds) |trsd|: *1 (remarks) tspv: *2 (remarks) notes: - ,,,, ? for *1, the value can be configured and adjusted. ? for *2, the value is defined as tdc0cyc - |tdc0d| and depends on adjustment of *1. #187 video capture 104 tcap0cyc: 11.11ns (min) tcap0su: 2ns (min) 103 tcap0cyc: 12.5ns (min) tcap0su: 4ns (min) #188 note of nc pins, lvds pins, and other no - used pin 105 - 104 note: ? all the corresponding ports of products which don't support fpd - link should be connected to gnd. avcc3_lvds_pll, avss3_lvds_pll, vcc3_lvds_tx, vss3_lvds_tx, txdoutn+/ - . #143 fpd - link timing chart 105 - 105, 106 figure: lvds ac characteristics (timing chart) #183
document number: 002 - 05682 rev.*a page 159 of 179 S6J3200 series summary error page error correct page correct id hyperbus ac specification 108 - 11 2 16 - 1 (3 items) cs - > rds chip select active to rds valid (low): cs - > rds(hi - z) chip select inactive to rds high - z: cs - > cs chip select high between operation: 16 - 2 (4 items) cs - > cs chip select high between transaction: cs - > cs chip select maximum low time: read - writer recovery time : ck - > ck (4th) page open time : 16 - 3 (7 items) read initial access time : cs - > ck chip select active to rds valid (low): cs - > rds(hi - z) chip select inactive to rds high - z: ck - > dq (low z) clock to dqs low z: cs - > dq (hi - z) ch ip select inactive to dqs high - z: ck - > rds ck transition to rds transition: cs - > cs chip select high between operation: 16 - 4 (8 items) ck - > ck (4th) page open time: cs - > rwds(hi - z) chip select inactive to rwds high - z: ck - > dq (low z) clock to dqs low z: cs - > dq (hi - z) chip select inactive to dqs high - z: ck - > rwds ck transition to rwds transition: cs - > cs chip select high between transition: cs - > cs chip select maximum low time: read - writer recovery time 109 - 11 2 (removed) #173
document number: 002 - 05682 rev.*a page 160 of 179 S6J3200 series summary error page error correct page correct id hyperbus ac specification 108, 109 tckcyc: 12.5ns(min) tcss: 3ns (min) tis: 1.25ns (min) tcsh: 1.25ns (min) notes; - ,,,, 109,110 tckcyc: 12.5ns(min) (a) 10ns(min) (b) tcss: 3.25ns (max) (a) 2ns (max) (b) tis: 5.25ns (max) (a) 4ns (max) (b) tcsh: 1ns (min) notes; - ,,,, - (a): the value will be targeted by the product series with revision digit a. - (b): the value will be targeted by the product series with revision digit b. #184 hyperbus ac specification 109 tdmv: 0ns (min) notes; - ,,,, 110 tdmv: 5.25ns (max) (a) 4ns (max) (b) notes; - ,,,, - (a): the value will be targeted by the product series with revision digit a. - (b): the value will be targeted by the product series with revision digit b. #185 hyperbus ac specification 110,111 trdscyc: 12.5ns (min) tdss: - 0.8ns (min) 0.8ns (max) tdsh: - 0.8ns (min) 0.8ns (max) notes; - ,,,, 111,112 trdscyc: 12.5ns (min) (a) 10ns (min) (b) tdss: - 0.8ns (min) - (max) tdsh: - 4.2ns (min) - (max) notes; - ,,,, - (a): the value will be targeted by the product series with revision digit a. - (b): the value will be targeted by the product series with revision digit b. #186
document number: 002 - 05682 rev.*a page 161 of 179 S6J3200 series summary error page error correct page correct id original document code: ds708 - 00003 - 0v02 - e, previous document code: ds708 - 00003 - 0v01 - e rev. 2.0 may 20, 2015 note for basic option 11 notes; - ,,, 11 notes; - ,,, ? the clk_cpu is assigned for cpu clock. the clk_cd3a0 is assigned for graphic clock. they are defined at the chapter of clock configuration. #194 power domain reset 15 - 15 power domain (pd): ---- see the platform manual and chapter state transition in detail. the product series supports the power off control of pd1, pd2 (including pd3 and 5), and pd6. the power domain resets of pd3 and pd5 included in pd2 are not supported in the product series, and "0" is always read from the reset factor flags of them. #175 original document code: ds708 - 00003 - 0v03 - e, previous document code: ds708 - 00003 - 0v02 - e rev. 1.0 may 20, 2015 display output 10 number of display outputs: 2 outputs simultaneously selectable from 2 x drgb, 1 x rsds, or 1 x lvds (fpd - link) 10 number of display outputs: option maximum 2 outputs simultaneously #210 display output 11 notes; - ,,,, - ,,,, 12 notes; - ,,,, - ,,,, ? display output ch.0 is used for rsds and fpd - link (lvds) as well as drgb (digital rgb). the ch.0 of the product which doesnt support fpd - link is used for rsds and drgb. display output ch.1 is used for drgb only. #211 revision b description 11 note: - ,,, - the function digit a, b, c, and d supports hyper sram. its 3, 4, 5, an d 6 doesnt support hyper sram. hyper bus interface ch.2 on graphic sub system will be embedded on product which is specified with function digit 7and 8 after revision b. revision a only has ch.0 and 1 of hyper bus interface. 12 note: - ,,, - hyperbus inte rface ch.1 of the function digit 3, 4, 5, and 6 support hyperram after revision b. #267
document number: 002 - 05682 rev.*a page 162 of 179 S6J3200 series summary error page error correct page correct id chip id information 12 - 12 function digit: a, b, c, d revision b: chip id: 0x10110000 jtag id: 0x100095cf #140 clock supervisor output function 15 - 15 clock supervisor: see the platform manual in detail. this product series doesnt support clock supervisor output port. (related register and internal circuit is implemented.) #224 cr oscillation stabilization time 15 - 15 embedded cr oscillation see the platfor m manual in detail. stabilization time is as followings. ? 5us for 4mhz (fast clock) ? 20us for 100khz (slow clock) #259 most physical channel 19 medialb: --- most25 (512fs) 3 wires maximum 15ch is available. (1ch is occupied by the system) 19 medialb: --- most25 (512fs) 3 wires maximum 15ch is available. #128 pin assignment 23, 25 - 24, 27 (figures are added) #141 io type 29 - 31 (x0 and x1 symbol are added in fugure.) #253 absolute maximum rating 59,60 iol3,,, when setting is 5 ma*9 iolav3,,, when setting is 5 ma*9 iol2 50ma *7 iol3 250ma *8 ioh3,,, when setting is 5 ma*9 iohav3,,, when setting is 5 ma*9 ioh2 - 50ma *7 ioh3 - 250ma *8 61,62 iol3,,, when setting is 5 ma*6, *7, *8, *9 iolav3,,, when setting is 5 ma*6, *7, *8, *9 iol2 250ma *7 iol3 50ma *8 ioh3,,, when setting is 5 ma*6, *7, *8, *9 iohav3,,, when setting is 5 ma*6, *7, *8, *9 ioh2 - 250ma *7 ioh3 - 50ma *8 #234 8kb backup ram current consumption 68 - 70 icct5: 345ua(typ),675ua(max):when shutting down 8kb backup ram. 450ua(typ),820ua(max):power only supplies to backup ram and system controllers. when using 8mhz crystal for main oscillator. 445ua(typ),795ua(max):when shutting down 8kb backup ram. icch5: 145ua(typ),425ua(max):when shutting down 8kb backup ram. #206
document number: 002 - 05682 rev.*a page 163 of 179 S6J3200 series summary error page error correct page correct id dc characterization of pss 68 icct5: timer mode icch5: stop mode notes: - ,,, 70 icct5: pss timer mode shutdown (pd6=off) icch5: pss stop mode shutdown notes: - ,,, - the definition of timer mode and stop mode can be seen at the chapter of state transition of S6J3200 hardware manual. #214 current consumption 68 icc12 - (typ) 1700ma(max):cpu:160mhz, hpm:80mhz, gdc:160mhz 70 icc12 900(typ) 1700ma(max):cpu:160mhz, hpm:80mhz, gdc:160mhz #260 oscillator frequency range 71 source oscillation clock frequency: x0, x1: 3.6mhz(min), 4.0mhz(max) notes: ,,, 73 source oscillation clock frequency: x0, x1: 3.6mhz(min), 16mhz(max) notes: ,,, ? enough evaluation and adjustment are recommended using oscillator on your system board. #230 pll/sscg maximum frequency 73 - 75, 76 fsscg0:480,800(400),640,640 mhz, sscg0 output clock fsscg1:800(400),800(400), 800(400),800(400) mhz, sscg1 output clock fsscg2:800(400),800(400), 800(400),640 mhz, sscg2 output clock fsscg3:800,800,800,800 mhz, sscg3 output clock fpll0:720,800,800,640 mhz, pll0 output clock fpll1:800,800,800,640 mhz, pll1 output clock fpll2:800(400),800(400),800(400), 800 mhz, pll2 output clock fpll3:480,480,480,480 mhz, pll3 output clock notes: - ,,,, ? the frequency described in () is not maximum value but recommended configuration value. #208 minimum pll/sscg frequency 74 note: - ,,, - ,,, 76 note: - ,,, - ,,, ? the configurable minimum frequency of plln and sscgn output is 400mhz. #219 can clock frequency 74 - 76 fclk_can 40mhz(max) #222
document number: 002 - 05682 rev.*a page 164 of 179 S6J3200 series summary error page error correct page correct id "unused" clock configuration 74 notes: ,,, ,,, 76 notes: ,,, ,,, - "unused" means a clock source which doesnt have any supply destinations. configure it as disable with performing at the lower clock frequency than the described maximum. #229 output short circuit current 104 output short circuit current ios: 106 (removed) #203 ac spec of ddrhsspi 107,108 [sdr mode] toddata: 6.5ns (max) tohdata: 3.5ns (min) todsel: 5.5ns (max) tohsel: 4.5ns (min) [ddr mode] toddata: 6.5ns (max) todsel: 7.0ns (max) 109, 110 [sdr mode] toddata: tcyc/2 + 2ns (max) tohdata: 2.0ns (min) todsel: - 12.0ns + (ss2cd+0.5)*tcyc ns (min) tohsel: 3.5ns (min) [ddr mode] toddata: tcyc/4 + 1.5ns (max) todsel: - 15.75ns + (ss2cd+0.5)*tcyc ns (min) notes: ? this is target spec. ? ss2cd [1:0] shou ld be configured as 01, 10, or 11. #164 sdr/ddr (hsspi) remark 107,108 remark: tcyc - 3.5ns tcyc - 4.5ns tcyc/2 - 1.5ns tcyc - 3.0ns 109,110 (delete) #232 adc trigger input 119 - 121 a/d trigger input time:adtrg 4tclk_lcp1a ns (min) 4tclk_lcp1a 100ns 100 ns (min) 4tclk_lcp1a < 100ns #231 adc resumption time 119 - 121 resumption time: 1us(max) #239
document number: 002 - 05682 rev.*a page 165 of 179 S6J3200 series summary error page error correct page correct id original document code: ds708 - 00003 - 0v04 - e, previous document code: ds708 - 00003 - 0v03 - e rev. 1.0 june 30, 2015 fpd - link port definition 45 - 60 - 61 txclk - lvds clock output pin: described as txout4m in fpd - link converter txclk+ lvds clock output pin: described as txout4p in fpd - link converter txdout0 - lvds data output pin: described as txout0m in fpd - link converter txdout0+ lvds data output pin: described as txo ut0p in fpd - link converter txdout1 - lvds data output pin: described as txout1m in fpd - link converter txdout1+ lvds data output pin: described as txout1p in fpd - link converter txdout2 - lvds data output pin: described as txout2m in fpd - link converter txdout2 + lvds data output pin: described as txout2p in fpd - link converter txdout3 - lvds data output pin: described as txout3m in fpd - link converter txdout3+ lvds data output pin: described as txout3p in fpd - link converter #146 non support port 21, 23 - 25, 27, 28, 29, 32, 34, 35, 36 (added the note for non - supported pin condition on pcb) #215 current consumption of fpd link 70 vcc3_lvds_tx, avcc3_lvds_pll: 70 ma(max) 92 vcc3_lvds_tx: 56ma(max) avcc3_lvds_pll: 7ma(max) #246 avcc and avrh description 58 (avcc0, avcc1, avrh0, and avrh1) 73 (avcc,avrh) #250 teqfp256 support 11 pin count n:320 12 pin count m:256 #272
document number: 002 - 05682 rev.*a page 166 of 179 S6J3200 series summary error page error correct page correct id teqfp256 support 13, 14 bga320 notes: - ,,, - bga is a package option under planning. 15, 16 teqfp256 notes: - ,,, - teqfp - 256 is a package option under planning. #273 teqfp256 support 17 a/d converter: 50 channels of analog input for teqfp216 ,,, 24 channels of them are shared with the smc for teqfp216/208 19 a/d converter: 50 channels of analog input for teqfp256 and teqpf216 ,,, 24 channels of them are shared with the smc for teqfp256/216/208 #274 teqfp256 support 19 lcd controller: teqfp216 : 4com x 32seg teqfp208 : 4com x 30seg ,,, 21 lcd controller: teqfp256 : 4com x 32seg teqfp216 : 4com x 32seg teqfp208 : 4com x 30seg ,,, #275 teqfp256 support 20, 24 - 23, 38 (teqfp256 assignment is added.) #276 chip id 12 revision:b, chip id:0x10100010 14 revision:b, chip id: - revision:c and d, chip id:0x10100100 #278
document number: 002 - 05682 rev.*a page 167 of 179 S6J3200 series summary error page error correct page correct id case temperature issue 64, 65 operating temperature ta: - 40(min), +105(max) 80, 81 operating temperature ta: - 40(min), +105(max) tc: - 40(min), +144(max) notes: ? both rating of ta and tc should simultaneously be satisfied as maximum operation temperature. ? the following condition should be satisfied in order to facilitate heat dissipat ion. 1. 4 or more layers pcb should be used. 2. the area of pcb should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (jedec standard) 3. 1 layer of middle layers at least should be used for dedicated layer to radiate heat wi th residual copper rate 90% or more. the layer can be used for system ground. 4. 35~50% of the die stage area which is exposed at back surface of package should be soldered to a part of 1st layer. 5. the part of 1st layer should be connected to the dedic ated heat radiation layer with more than 10 thermal via holes. #283 main clock frequency 15 main and sub oscillator is available. ? a wide range of 3.6 - 4mhz is available for main oscillator 17 main and sub oscillator is available. ? a wide range of 3.6 - 16mhz is available for main oscillator #311 revision description 11 - 12 (inside figure 2 - 1: option and part number) c: support mcan 3.0.1. d: support mcan 3.2. #313 cpu clock maximum 11 200mhz (cpu clock of function digit a, b, c, and d) 13 160mhz (cpu clock of function digit a, b, c, and d) #314 maximum gap between package and board 24 - 39 note: ? same size is specified for min, nom, max, then it should be regarded as maximum size. #315
document number: 002 - 05682 rev.*a page 168 of 179 S6J3200 series summary error page error correct page correct id power dissipation and operation temperature 62 - 77, 78 power dissipation and operation temperature case 1, pd - 3300 mw, ta - 40 +97 degc, both should be satisfied. tc - 40 +144 degc, power dissipation and operation temperature case 2, pd - 3150 mw, ta - 40 +100 degc, both should be satisfied. tc - 40 +144 degc, power dissipation and operation temperature case 3, pd - 3000 mw ta - 40 +102 degc, both should be satisfied. tc - 40 +144 degc, power dissipation and operation temperature case 4, pd - 2900 mw, ta - 40 +105 degc, both should be satisfied. tc - 40 +144 degc, power dissipation and operation temperature case 5, pd - 2800 mw, ta - 40 +105 degc, both should be satisfied. tc - 40 +144 degc, system thermal resistance, theta j - a - 16 degc/w, the minimum value depends on the system specification of heat radiation. th e described value is estimated under the condition which is specified at operation assurance condition. package thermal resistance, theta j - c - 7.5 degc/w, #317
document number: 002 - 05682 rev.*a page 169 of 179 S6J3200 series summary error page error correct page correct id hyperbus gpo remark 18 hyperbus ,,, 21 hyperbus ,,, gpo signal can only be used for "internal control example by gpo" in this product, that is, it can select using hyperbus of pf or using hyperbus of graphic sub system. #345 chip select output 11 - 13 (part number is added to show chip select output of mfs) #346 revision b description 12 notes: ,,, - scl4, 10, 12 and sda4, 10, 12 of i2c is not supported yet, and will be enhanced after revision b. 13 notes: ,,, - multi - function serial interface of the function digit 3, 4, 5, 6, 7, and 8 support scl4, 10, 12 and sda4, 10, 12 of i2c after revision d . #349 mpu lock and unlock value 16 - 18 to configure lock or unlock for both mpuxn_unlock and mpuhn_unlock, - lock: 0x112abb56 - unlock: 0xaccabb56 #351 flash access speed 17 1 - wait - cycle with 80 - 160mhz. 2 - wait - cycle with 160 - 240mhz. 19 0 - wait - cycle: 80mhz or less. 1 - wait - cycle: 160mhz or less. 2 - wait - cycle: more than 160mhz. the maximum frequency should be referred in datasheet. #357 oscillator error 73 ? the error of source oscillator frequency must be smaller than 300ppm. 97 ? the error of source oscillator frequency must be smaller than 3000ppm. #360 input leakage current,pull - up resistor,pull - down resistor and input capacitance for p4_25 to p4_31 69 input leakage current:iil:p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p6_02 to 31 input capacitance:cin1:p0_00 to 31, p1_00 to 09, p2_16, 17, 19, 22, 24 to 31, p3_00 to 20, p5_21, 22, 27 to 31, p6_00 to 08, 17 to 26 89 input leakage current:iil:p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p4_25 to 31, p5_00 to 20, p6_02 to 31 input capacitance:p0_00 to 31, p1_00 to 09, p2_16, 17, 19, 22, 24 to 31, p3_00 to 20, p4_25 to 31, p5_00 to 20, p5_21, 22, 27 to 31, p6_00 to 08, 17 to 26 #363 clk_hpm frequency 16 1 wait cycle is necessary to read at over 180mhz (target). 18 see the platform manual in detail. 1 wait cycle is necessary for ram read at over 160mhz. no need to insert wait cycles for ram write. #366 nsrst description 15 ? initx - srstx - nstrst 17 ? initx ? srstx (and nsrst pin) #367
document number: 002 - 05682 rev.*a page 170 of 179 S6J3200 series summary error page error correct page correct id hardware flow control 18 multi - functional serial (mfs):,,, 20 multi - functional serial (mfs):cts/rts is not mounted (hardware flow control is not supported for this series.) #373 pin assignment and pin list should be separately instead of the red characters 20 - 24 - 37 (the figure of pin assignment are added) #374 ddr - hsspi ddr mode 110 note: ,,, - ss2cd [1:0] should be configured as 01, 10, or 10. 140 notes: ,,, - ss2cd [1:0] should be configured as 01, 10, or 11. #376 oscillator error issue 76 notes: ? *1: target maximum clock frequencies when cpu clock = 240mhz - ,,, 100 notes: ? *1: target maximum clock frequencies when cpu clock = 240mhz - 232mhz or less is available for sscg down spread. - 240mhz or less is available for pll. - ,,, #380 input pulse width 120 port noise filter: width for input removal: all gpio: 25ns(max) *: input pulse width less than at least 25nm is removed when port noise filter is enabled. 151 port noise filter: width for input removal: all gpio: 67ns(max) *: input pulse width less than at least typ 25ns to max 67ns is removed when port noise filter is enabled. *: input pulse width 100ns or more is recommended to be effective. #382 typo in 216 pin assign 21,22 p0_26 0 p0_27 0 p0_28 0 24 - 30 ("0"s are removed) p0_26 p0_27 p0_28 #384 chip id 12 - 14 function digit: 3,4,5,6,7,8 e and f: chip id: 0x10100101, jtag id: 0x1000c5cf --- function digit: a,b,c,d e and f: chip id: 0x10110001, jtag id: 0x100095cf #409 rvd detection/release voltage 99 - 124 (lvdl0 spec is added.) #410 ddh - hsspi ac specification 109, 110 (old value) 138, 140 (new values are added in the table) #411 hyperbus ac specification 111 - 11 4 (old value) 142 - 14 5 (new values are added in the table) #412
document number: 002 - 05682 rev.*a page 171 of 179 S6J3200 series summary error page error correct page correct id power supply current 72 - 92 - 96 (new table is added, and the value of icc12, icc5, icct5, and icch5 are improved.) #413 unsupport partial wakeup 15 power domain (pd): ,,, 17 power domain (pd): ,,,this series doesn't support partial wakeup for pd6. #416 vcc12 power supply limit 64 vss12: 1.15 1.1*1 notes: ? *1. the value will be for the product series with revision digit b. - ,,, 80 vss12: 1.15*1 1.1*1 notes: - *1. the value is only applied to the product series with revision digit a. - ,,, #417 fpd - link dc spec 106 vod: 270, 300, 340 mv 310, 350, 400 mv 360, 400, 450 mv vcm: 1.120, 1.150, 1.175 v 1.170, 1.200, 1.225 v 1.220, 1.250, 1.280 v 135 vod: 210, 300, 390 mv 250, 350, 450 mv 295, 400, 505 mv vcm: 1.075, 1.200, 1.325 v 1.125, 1.250, 1.375 v #418 land pattern for thermal via 65 - 81 - 84 (land pattern of thermal via hole is added.) #429 power on sequence recommendation 64 80 notes: - ,,, ? power supply sequence is recommended as vcc5 - > [dvcc or avcc5 or vcc3 or avcc3] - > vcc12 - > [avcc3_lvds_pll or vcc3_lvds_tx] #431
document number: 002 - 05682 rev.*a page 172 of 179 S6J3200 series summary error page error correct page correct id internal clock timing for fsscg0 - 3 and fpll0 - 3 75, 76 fsscg0 480 800(400) 640 640 fsscg1 800(400) 800(400) 800(400) 800(400) fsscg2 800(400) 800(400) 800(400) 640 fsscg3 800 800 800 800 fpll0 720 800 800 640 fpll1 800 800 800 640 fpll2 800(400) 800(400) 800(400) 800 fpll3 480 480 480 480 notes: ,,, ? the frequency described in () is not maximum value but recommended configuration value. 99, 100 fsscg0 232(480) 200(800) 160(640) 160(640) fsscg1 200(800) 200(800) 200(800) 200(800) fsscg2 200(800) 200(800) 200(800) 160(640) fsscg3 200(800) 20 0(800) 200(800) 200(800) fpll0 240(720) 200(800) 200(800) 160(640) fpll1 400(800) 400(800) 400(800) 320(640) fpll2 200(800) 200(800) 200(800) 200(800) fpll3 240(480) 240(480) 240(480) 240(480) notes: ,,, ? the frequency described in () is maximum output f requency of sscg pll / pll multiplier circuit. #432 vih spec(ttl level) for jtag - pins 65 vih9: 2.0(min) 85 vih9: 2.3(min) #437 vih of media lb port 65 vih12: 1.7(v) 85 vih12: 1.8(v) #438 original document code: ds708 - 00003 - 1v0 - e, previous document code: ds708 - 00003 - 0v04 - e rev. 1.0 september 30, 2015 resource clock frequency 9 resource clock frequency : 40mhz (max) 8 resource clock frequency : option : see ac specification on the datasheet #465 description for up/down counter 10, 20 up/down counter 9, 19 quad position & revolution counter (up/down counter) #530 display output 13 notes: ,,, - display output ch.0 is used for rsds and fpd - link (lvds) as well as drgb (digital rgb). the ch.0 of the product which doesnt support fpd - link is used for rsds and drgb. display output ch.1 is used for drgb only. 12 notes: ,,, - display output ch.0 is used for rsds and fpd - link (lvds) as well as drgb (digital rgb). the ch.0 of the product which doesnt support fpd - link is used for rsds and drgb. - display output ch .1 is used for fpd - link (lvds) and drgb (digital rgb). the ch.1 of the product which doesn't support fpd - link is used for drgb only. #452
document number: 002 - 05682 rev.*a page 173 of 179 S6J3200 series summary error page error correct page correct id relationship sysc0_sysidr and chipid 14 id is specified for each function digit and revision which is defined at figu re 2 - 1. 13 id is specified for each function digit and revision which is defined at figure 2 - 1. chip id can be read from sysc0_sysidr. for sysc0_sysidr, see the traveotm platform hardware manual. #471 typo in trace buffer size 17 4kb embedded trace buffer 16 4k word embedded trace buffer #528 wucr function 20 mfs: ,,, 19 mfs: ,,, wucr function is not supported for this product. #284 cs port availability 20 mfs:chip select function of csio is not supported yet and will be enhanced with next revision. 19 mfs:the availability of chip select function can be seen at function digit table. #448 not support cs input 20 - 19 chip select input is not supported. #467 usage for i2s ch1 20 ? i2s0 only supports the output of sound sources. ? i2s1 supports both the input and the output. ? ,,, 19 - i2s0 can output sound sources which are processed by sound system. - i2s1 can input sound sources which are processed by sound system. ? ,,, see the "sound system configuration" of S6J3200 hardware manual in detail. #529 i mporvement of descritption for i2c 20 note all pins do not necessarily support i2c, but the pins which have the dedicated i/o characteristics only support it. 19 note - not all pins support i2c. only pins which have the i2c i/o characteristics support it. #531 reference for ddr high speed spi & can - fd 20 - 19, 20 (added "see the platform manual in detail" for can - fd & ddr high speed spi) #532 reference information for gpo 21 gpo signal can only be used for "internal control example by gpo" in this product, that is, it can select using hyperbus of pf or using hyperbus of graphic sub system. 20 gpo signal can only be used for "internal control example by gpo" in this product, that is, it can select using hyperbus of pf or using hyperbus of graphic sub system. see the "hyperbus interface port configuration" of S6J3200 hardware manual in detail. #533 delete unnecessary description for graphic subsystem 21 order replacement of rgb pins. 20 (deleted) #534
document number: 002 - 05682 rev.*a page 174 of 179 S6J3200 series summary error page error correct page correct id delete ethernet restriction for product 22 direct memory access interface, mac filtering block - vlan tag, ieee 1588 and ieee 802.1as support, mac pfc priority based pause frame support, and 802.1qav support C credit based shaping 21 (delete) #516 improvement of description for pin assignment 23 alphabets with pin numbers are signs specify i/o circuit type. 22 the characters next to the pin number in the pin assignment drawing specify the i/o circuit type. (figure added) #535 regarding "red" character in pin assignment 23 - 38 the pins which are de scribed in "red" character are not supported, and will be enhanced with next revision products. 23 - 35 the pins which are described in "red" character are not supported product with revision a and c. #524 note for input voltage and max clamp current 76 maximum clamp current:*a (remarks) total maximum clamp current:*a (remarks) 75 maximum clamp current:*12, *a (remarks) total maximum clamp current:*12, *a (remarks) #503 typo in absolute maximum rating 76 input voltage:vi2:vcc5+0.3(max) ,,, input voltage:vie:vcc5+0.3(max) 75 input voltage:vi2:dvcc+0.3(max) ,,, input voltage:vie:vcc53+0.3(max) #518 note for input voltage and max clamp current 78 - 77 *12: vi or vo should never exceed the specified ratings. however, if the maximum current to/from an input is limited by a suitable external resistor, the iclamp rating supersedes the vi rating. #470 power supply sequence 80 power supply sequence is recommended as vcc5 - > [dvcc or avcc5 or vcc3 or avcc3] - > vcc12 - > [avcc3_lvds_pll or vcc3_lvds_tx] 79 power supply sequence is recommended as vcc5 - > [dvcc or avcc5 or vcc3 or avcc3] - > vcc12 - > [avcc3_lvds_pll or vcc3_lvds_tx]. note that power supplies inside "[]" can be turned on in arbitrary order. #474 vih/vil characteristics for i/o of dvcc 85, 86 - 84, 85 (added the "*1" for note of some characteristics and the description) #439 ds 8.3.1 port function characteristics 86 vil10(max) 0.3xvcc5 85 vil10(max) 0.3xvcc3 #453 voh characteristic for i/o of medialb 87 voh16:vcc3 - 0.5(min) 86 voh16:2.0(min) #441
document number: 002 - 05682 rev.*a page 175 of 179 S6J3200 series summary error page error correct page correct id voh/l4, voh/l5, voh/l6 characteristics for i/o of vcc5 and dvcc 87, 88 - 86, 87 (added the "*1" for note of some characteristics and the description) #442 vol4, vol5 characteristics 88 vol4:0.55(max) vol5:0.55(max) 87 vol4:0.4(max) vol5:0.4(max) #443 pull - up/pull - down resistor for 5v/3v pins (p4_25 to 31, p5_00 to 20) 89 pup2:p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p6_02 to 31:pull - up registor selected ,,, pdown2:p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p6_02 to 31:pull - down registor selected 88 pup2:p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p4_25 to 31, p5_00 to 20, p6_02 to 31:pull - up registor selected vcc53 = 4.5v to 5.5v ,,, pdown2:p2_16, 17, 19, 22, 24 to 31, p3_00 to 31, p4_00 to 12, p4_25 to 31 , p5_00 to 20, p6_02 to 31:pull - down registor selected vcc53 = 4.5v to 5.5v #430 typo in condition of iil characterisistics for 3v i/o 89 vcc3=3.3 v vss < vi < vcc3 88 vcc3=3.6 v vss < vi < vcc3 #444 typo in symbol for input capacitance 89 cin1:p3_21 to 31, p4_00 to 12, p6_09 to 16 88 cin2:p3_21 to 31, p4_00 to 12, p6_09 to 16 #445 pull - up/pull - down resistor for 5v/3v pins 89 - 88 pull - up resistor:rup2:p4_25 to 31, p5_00 to 20:pull - up resistor selected vcc53 = 3.0v to 3.6v:40(min):100(typ):200(max):k:5v/3 v pins ,,, pull - down resistor:rdown1:p4_25 to 31,p5_00 to 20:pull - down resistor selected vcc53 = 3.0v to 3.6v:40(min):100(typ):200(max):k:5v/3 v pins #501 fpd - link dc spec 92 - 91 note: - ,,, - the current consumption at vcc3_lvds_tx is specified under rl=100ohm, cl=5pf, f=50mhz, and 0/1 alternation pattern output. #433 ds 8.3.2.1 run mode 93 (icc5 is only defined) 92 (current values related cpu operation should be specified as icc12) #454 maximu clock frequency of sscg3 99 fsscg3:200(800), 200(800), 200(800), 200(800) 98 fsscg3:400(800), 400(800), 400(800), 400(800) #458
document number: 002 - 05682 rev.*a page 1 76 of 179 S6J3200 series summary error page error correct page correct id delete "taget spec" 99, 100, 131 - 13 4, 138, 140,142 - 150, 159 - 98, 99, 100, 131 - 13 4, 138, 140, 142 - 15 0, 159 (deleted explanation for target spec) #504 sscg max frequency 100 notes: ? *1: target maximum clock frequencies when cpu clock = 240mhz - 232mhz or less is available for sscg down spread. - 240mhz or less is available for pll. 99 notes: ? *1: target maximum clock frequencies when cpu cloc k = 240mhz - 232mhz or less is available for sscg down spered on/off. - 240mhz or less is available for pll. #487 internal clock timing 100 notes: ,,, - *3: target maximum clock frequencies when cpu clock = 160mhz - from *1 to *3, they are not applied to the product series with function digit a, b, c, and d. - *4: target maximum clock frequencies when cpu clock = 160mhz for the product series with the function digit a, b, c, and d. 100 notes: ,,, - *3: target maxim um clock frequencies when cpu clock = 160mhz. this is also a combination of maximum clock frequencies for tc flash programming or erasing. - from *1 to *3, they are applied to the product series with function digit 3, 4, 5, 6, 7, and 8. - *4: target maximu m clock frequencies when cpu clock = 160mhz for the product series with the function digit a, b, c, and d. this is also a combination of maximum clock frequencies for tc flash programming or erasing. #406 level detection hysteresis width 105 level detection hysteresis width 104 (delete) #457 default value of lvdl1 126 lvdl1v=01(default),,, lvdl1v=10 125 lvdl1v=01,,, lvdl1v=10(default) #502 display ac specification 131 - 131 ( - updated the min/max value in |tdc0d| and tdc0v. - added the new definition for dsp0_ctrl11 - 0 of tdc0v. - update the note for *2 and delete the note for *4. - updated figure for definition of tdc0v.) #347
document number: 002 - 05682 rev.*a page 177 of 179 S6J3200 series summary error page error correct page correct id display ac specification 132 - 132 ( - updated the min/max value for |trsd|, trsv, tspd, tspv. - delete the note for *2. - updated figure for definition of tspv and trsv.) #506 display ac specification 133 - 133 ( - updated the min/max value for tdc1d, tdc1v and delete the remarks for tdc1v. - updated figure for definition of tdc1v.) #505 fpd - link output clock frequency 135 output clock frequency: 1mhz(min),50mhz(max) 135 output clock frequency: - (min),50mhz(max) #522 add "txclk+/ - " in case of don't support fpd - link 135 note: ? all the corresponding ports of products which don't support fpd - link should be connected to gnd. avcc3_lvds_pll, avss3_lvds_pll, vcc3_lvds_tx, vss3_lvds_tx, txdoutn+/ - . 135 note: ? all the corresponding ports of products which don't support fpd - link should be connected to gnd. avcc3_lvds_pll, avss3_lvds_pll, vcc3_lvds_tx, vss3_lvds_t x, txdoutn+/ - , txclk+/ - . #525 ddrhsspi (sdr) clock cycle for quad page program 138 - 138 hsspi clock cycle:20(min):when quad page program #484 hyperbus ac specification 144 rds> dq (valid) setup time ,,, rds> dq (invalid)hold time 144 rds> dq setup time ,,, rds> dq hold time #519 adc software trimming 153 - 153 8.5.4 calibration condition calibration condition a/d converter should be calibrated under the following condition. avcc=5.0v avrh=5.0v ta=25 system clock frequency (clk_lcp1a)= 10mhz see a/d converter calibration on the S6J3200 hardware manual. #358
document number: 002 - 05682 rev.*a page 178 of 179 S6J3200 series document history document title: S6J3200 series 32 - bit microcontroller traveo tm family document number: 002 - 05682 revision ecn orig. of change submission date description of change ** - nnas 09 / 30/2015 migrated to cypress and assigned document number 002 - 05682. no change to document contents or format. *a 5234352 nnas 04/22/2016 updated formatting
document number: 002 - 05682 rev.*a april 22, 2016 page 179 of 179 S6J3200 series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing c ypress.com/touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training | co mp onents technical support cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. ? cypress semiconductor corporation, 2014 - 2016. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypress). this document, including any software or firmware included or referenced in this document (software), is owned by cypress under the intell ectual property laws and treaties of the united states and other countries worldwide. cypress res erves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any licens e under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a licens e agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non - exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your or ganization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product u nits, and (2) under those claims of cypresss patents that are infringed by the software (as provided by cypress, unmodified) to ma ke, use, distribute, and import the software solely for use with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no w arranty of any kind, express or implied, with regard to this document or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particul ar purpose. to the extent permitted by applic able law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any lia bility arising out of the application or use of any product or circuit described in this document. any information provided in thi s document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application m ade of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the ope ration of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution con trol or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, deat h, or property damage (unintended uses). a critical component is any component of a device or system whose failure to perf orm can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress i s not liable, in whole or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall ind emnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsen se, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respe ctive owners.

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