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? 2016 microchip technology inc. ds20005505a-page 1 features ? input voltage range of v dd regulator - hv9110: 10v to 120v - HV9112: 9v to 80v - hv9113: 10v to 120v ? maximum duty, feedback accuracy - hv9110: 49%, 1% - HV9112: 49%, 2% - hv9113: 99%, 1% ? current mode control ? <1 ma supply current ? >1 mhz clock applications ? dc/dc power converters general description hv9110/HV9112/hv9113 are switch-mode power supp ly (smps) controllers suitable for the control of a variety of converter topologies, including the flyback converter and the forward converter. the v dd regulator supports an input voltage as high as 80v or 120v. hv9110/HV9112/hv9113 controllers include all essen - tials for a power converter design, such as a bandgap referen ce, an error amplifier, a ramp generator, a high- speed pwm comparator, and a gate driver. a shutdown latch provides on/off control. the hv9110 and hv9113 feature an input voltage rang e of 10v to 120v, and the HV9112 has an input voltage range of 9v to 80v. the hv9110 and HV9112 have a maximum duty of 49%, while the hv9113 has a maximum duty of 99%. package type see table 3-1 for pin information. 1 14 14-ead soic hv9110/HV9112/hv9113 high-voltage current-mode pwm controller
hv9110/HV9112/hv9113 ds20005505a-page 2 ? 2016 microchip technology inc. functional block diagram hv9110/HV9112 v dd v in v ref
? 2016 microchip technology inc. ds20005505a-page 3 hv9110/HV9112/hv9113 functional block diagram hv9113 v in v ref v dd
hv9110/HV9112/hv9113 ds20005505a-page 4 ? 2016 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? input voltage, v in hv9110/hv9113 .................................................................................................................. .......................... 120v HV9112......................................................................................................................... ... ................................ 80v device supply voltage, v dd ............................................................................................................................... .... 15.5v logic input voltage range ...................................................................................................... .. ...... ?0.3v to v dd + 0.3v linear input voltage range..................................................................................................... .. ...... ?0.3v to v dd + 0.3v storage temperature range ...................................................................................................... .......... ?65c to +150c operating temperature range.................................................................................................... ......... ?55c to +125c power dissipation: 14-lead soic.............................. ... ............................................................... ....................... 750 mw ? notice: s tresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect devi ce reliability. electrical characteristics electrical specifications: v dd = 10v, v in = 48v, v disc = 0v, r bias = 390 k ? , r osc = 330 k ? , t a = 25c unless otherwise noted. parameters sym. min. typ. max. units conditions reference output voltage hv9110/13 v ref 3.92 4 4.08 v r l = 10 m ? HV9112 3.88 4 4.12 hv9110 /13 3.82 4 4.16 r l = 10 m? , t a = ?55c to +125c output impedance z out 15 30 45 k? (note 1 ) short circuit current i short ? 125 250 a v ref = gnd change in v ref with temperature ? v ref ? 0.25 ? mv/c t a = ?55c to +125c (note 1 ) oscillator oscillator frequency f max 1 3 ? mhz r osc = 0 ? initial accuracy f osc 80 100 120 khz r osc = 330 k ? ( note ) 160 200 240 r osc = 150 k ? ( note ) v dd regulation ? ? ? 15 % 9.5v < v dd < 13.5v temperature coefficient ? ? 170 ? ppm/c t a = ?55c to +125c (note 1 ) pwm maximum duty cycle hv9110 /HV9112 d max 49 49.4 49.6 % (note 1 ) hv9113 95 97 99 dead time hv9113 d min ? 225 ? ns hv9113 only ( note 1 ) minimum duty cycle ? ? 0 % pulse width where pulse drops out ? 80 125 ns (note 1 ) current limit maximum input signal v lim 1 1.2 1.4 v v fb = 0v delay to output t d ? 80 120 ns v cs = 1.5v, v comp 2v (note 1 )
? ? ? ? ?
temperature specifications parameters sym. min. typ. max. units conditions temperature ranges operating temperature ? ?55 ? 125 c storage temperature ? ?65 ? 150 c package thermal resistance 14-lead soic ja ? 83 ? c/w hv9110/HV9112/hv9113 ds20005505a-page 6 ? 2016 microchip technology inc. 1.1 truth table truth table shutdown reset output h h normal operation h h l normal operation, no change l h off, not latched l l off, latched l h l off, latched, no change
? 2016 microchip technology inc. ds20005505a-page 7 hv9110/HV9112/hv9113 2.0 typical performance curves note: the graphs and tables provided following this note ar e a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or ta bles, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore outside the warranted range. figure 2-1: 1m 100k 10k 1k 100 10 1 100m 100 1k 10k 100k 1m 10m z 0 () frequency (hz) error amplifier output impedance (z 0 ). 0 -10 -20 -30 -40 -50 -60 -70 -80 pssr (db) frequency (hz) 10 100 1k 10k 100k 1m figure 2-2: psrr ?error amplifier and reference. bias resistance () 100k 1m 10m bias current (a) 100 10 1 v dd = 12v v dd = 10v figure 2-3: bias current vs. bias resistance. figure 2-4: 10k 100k 1m r osc () f out (hz) 1m 100k 10k hv9113 hv9110, HV9112 output switching frequency vs. oscillator resistance. 80 70 60 50 40 30 20 10 0 -10 gain (db) phase ( o c) 180 120 60 0 -60 -120 -180 frequency (hz) 100 1k 10k 100k 1m figure 2-5: error amplifier open-loop gain/phase. r discharge () 100m 1 10 100 1k 10k 100k 1m 100 t off (ns) 1k 10k r osc = 100k r osc = 10k r osc = 1k figure 2-6: r discharge vs. t off (hv9113 only).
hv9110/HV9112/hv9113 ds20005505a-page 8 ? 2016 microchip technology inc. 3.0 pin description table 3-1 shows the pin description for hv9110/HV9112/hv9113 . the locations of the pins are listed in features . table 3-1: pin description pin number hv9110/HV9112/hv9113 pin name description 1 bias internal bias , cur rent set 2 v in high-voltage v dd regulator input 3 cs current sense input 4 gate gate drive output 5 gnd ground 6 v dd high-voltage v dd regulator output 7 osco oscillator output 8 osci oscillator input 9 disc oscillator dischar ge, current se t 10 v ref 4v reference output ? reference voltage level can be overridden by an externally applied voltage sourc e. 11 nsd active low input to set shutdown latch 12 rst active high input to reset shut down latch 13 comp error amplifier output 14 fb feedback voltage input
? 2016 microchip technology inc. ds20005505a-page 9 hv9110/HV9112/hv9113 4.0 test circuits the test circuits for characterizing error amplifier output impedance, z out , and error amplifier, power supply rejection ratio, psrr, are shown in figure 4-1 and figure 4-2 . + C reference 60k 40k 1v swept 100 hz-2.2 mhz tektronix p6021 (1 turn secondary) +10 v dd gnd fb note: set feedback voltage so that v comp = v divide 1 mv before connecting transformer 100 nf v 1 v 2 figure 4-1: error amp z out . + C reference 0.1v swept 10 hz-1.0 mhz 100 nf 10.0v 4.0v 100k1% 100k1% v 2 v 1 figure 4-2: psrr.
hv9110/HV9112/hv9113 ds20005505a-page 10 ? 2016 microchip technology inc. 5.0 detailed description 5.1 high-voltage regulator the high-voltage regulator included in hv9110/HV9112/hv9113 consists of a high-voltage n- channel depletion-mode dmos transistor driven by an error amplifier, providing a current path between the v in terminal and the v dd terminal. the maximum cur - rent, about 20 ma, occurs when v dd = 0, with current reducing as v dd rises. this path shuts off when v dd rises to somewhere between 8v and 9.4v. so, if v dd is held at 10v or 12v by an external source, no current other than leakage is draw n through the high voltage transistor. this minimizes dissipation within the high- voltage regulator. use an external capacitor between v dd and gnd. this capacitor should have good high-frequency character - istics. ceramic caps work well. the device uses a compound resistor divider to monitor v dd for both the undervoltage lockout circuit and the shutoff circuit of the high-voltage fet. setting the undervoltage sense point about 0.6v lower on the string than the fet shutoff point guarantees that the undervoltage lockout releases before the fet shuts off. 5.2 bias circuit hv9110/HV9112/hv9113 require an external bias resistor, connected between the bias pin and gnd , to set currents in a series of current mirrors used by the analog sections of the chip. the nominal external bias current requirement is 15 a to 20 a, which can be set by a 390 k ? to 510 k ? resistor if v dd = 10v, or a 510 k ? to 680 k ? resistor if v dd = 12v. a precision resistor is not required , 5% meets device require - ments. 5.3 clock oscillator the clock oscillator of the hv9110/HV9112/hv9113 consists of a ring of cmos inverters, timing capacitors, and a capacitor-discharge fet. a single external resis - tor between the osci and osco sets the oscillator fre - quency. (see figure 2-4 .) the hv9110 and HV9112 include a frequency-dividing flip-flop that allows the pa rt to operate with a 50% duty limit. accordingly, the effe ctive switching frequency of the power converter is half the oscillator frequency. (see figure 2-4 .) an internal discharge fet resets the oscillator ramp at the end of the oscillator cycle. the discharge fet is externally connected to gnd, by way of a resistor. the resistor programs the oscillator dead time at the end of the oscillator period. the oscillator turns off during shutdown to reduce sup - ply current by about 150 a. 5.4 reference the reference of the hv9110/HV9112/hv9113 consists of a band-gap reference, followed by a buffer amplifier, which scales the voltage up to 4v. the scaling resistors of the buffer amplifier are trimmed during manufacture so that the output of the error amplifier, when con - nected in a gain of ?1 config uration, is as close to 4v as possible. this nulls out t he input offset of the error amplifier. as a consequence, even though the observed reference voltage of a specific part may not be exactly 4v, the feedback voltage required for proper regulation will be 4v. an approximately 50 k ? resistor is located internally between the output of the reference buffer amplifier and the circuitry it feeds?reference output pin and non-inverting input to the error amplifier. this allows overriding the internal reference with a low impedance voltage source 6v. using an external reference rein - states the input offset voltage of the error amplifier. overriding the reference should seldom be necessary. the reference of the hv9110/HV9112/hv9113 is a high-impedance node, and us ually there will be signifi - cant electrical noise nearby. therefore, a bypass capacitor between the reference pin and gnd is strongly recommended. the reference buffer amplifier is compensated to be stable with a capacitive load of 0.01 f to 0.1 f. 5.5 error amplifier the error amplifier on hv9110/HV9112/hv9113 is a low-power, differential-input, operational amplifier. a pmos input stage is used, so the common mode range includes ground and the input impedance is high. 5.6 current sense comparators the hv9110/HV9112/hv9113 use a dual-comparator system with independent comparators for modulation and current limiting. this pr ovides the designer greater latitude in compensation design, as there are no clamps, except esd protection, on the compensation pin. 5.7 remote shutdown the nsd and rst pins control the shutdown latch. these pins have internal current-source pull-ups so they can be driven from o pen drain logic. when not used they should be left open or connected to v dd .
? 2016 microchip technology inc. ds20005505a-page 11 hv9110/HV9112/hv9113 5.8 output buffer the output buffer of hv9110/HV9112/hv9113 is of st andard cmos construction p-channel pull-up and n- channel pull-down. thus, the body-drain diodes of the output stage can be used for spike clipping. external schottky diode clamping of th e output is not required. 50% t d 1.5v cs 0 t sd 50% 90% 90% vdd nsd 0 t lw 50% 50% t sw 50% 50% t rw 50% t r 10ns t f 10ns t r , t f 10ns vdd nsd 0 vdd rst 0 vdd gate 0 vdd gate 0 figure 5-1: shutdown timing waveforms.
hv9110/HV9112/hv9113 ds20005505a-page 12 ? 2016 microchip technology inc. 6.0 packaging information 6.1 package marking information legend: xx...x product code or customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week ?01?) ? nnn alphanumeric traceability code ? pb-free jedec ? designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or custom er-specific information. package may or not include the corporate logo. 3 e 3 e 14-lead soic example xxxxxxxxx xxxxxxxxxxx yywwnnn e 3 1632888 hv9110ng e 3
? 2016 microchip technology inc. ds20005505a-page 13 hv9110/HV9112/hv9113 14-lead soic (narrow body) package outline (ng) 8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 dimension (mm) min 1.35* 0.10 1.25 0.31 8.55* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom---- 8.65 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 8.75* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ab, issue e, sept. 2005. 7klvglphqvlrqlvqrwvshfl?hglqwkh-('(&gudzlqj drawings are not to scale. d seating plane gauge plane l l1 l2 top view side view view a-a view b view b 1 e1 e a a2 a1 a a 14 1 1 a 1 1 1 7klvfkdpihuihdwxuhlvrswlrqdo,ilwlvqrwsuhvhqwwkhqd 3lqlghqwl?hupxvwehorfdwhglqwkhlqgh[duhdlqglfdwhg7k h3lqlghqwl?hufdqeh dproghgpdunlghqwl?hudqhpehgghgphwdopdunhurudsulqwhg lqglfdwru note: for the most current package drawings, see the microchip packaging specification at www.microchip.com/packaging. note: for the most current package drawings, see the microchip packaging specification at www.microchip.com/packaging.
hv9110/HV9112/hv9113 ds20005505a-page 14 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005505a-page 15 hv9110/HV9112/hv9113 appendix a: revision history revision a (june 2016) ? merged supertex doc #s dsfp-hv9110, dsfp- HV9112 and dsfp-dsfp-hv9113 to microchip ds20005505a . ?revised electrical characteristics to accommo - date the merged products. ? updated pin names to reflect new naming con - vention. ? significant text changes to detailed description . ? minor text changes throughout.
hv9110/HV9112/hv9113 ds20005505a-page 16 ? 2016 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: hv9110 = high-voltage current-mode pwm controller, 10v to 120v input voltage range, 49% duty cycle HV9112 = high-voltage current-mode pwm ? controller, 9v to 80v input voltage range, 49% duty cycle hv9113 = high-voltage current-mode pwm ? controller, 10v to 120v input voltage range, 99% duty cycle package: ng = 14-lead soic environmental g = lead (pb)-free/rohs-compliant package media type: (blank) = 53/tube for an ng package ? examples: a) hv9110ng-g: high-voltage current-mode pwm controller 10v to 120v input volt- age range, 49% duty cycle, 14-lead soic package, 53/tube b) HV9112ng-g: high-voltage current-mode pwm controller, 9v to 80v input voltage range, 49% duty cycle,14-lead soic package, 53/tube c) hv9113ng-g: high-voltage current-mode pwm controller, 10v to 120v input volt- age range, 99% duty cycle, ? 14-lead soic package, 53/tube part no. x device x environmental x x package options media - - type
? 2016 microchip technology inc. ds20005505a-page 17 ds20005505ainformation contained in this publication regard- ing device applications and the like is provided only for your convenience and may be superse ded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representa- tions or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0736-2 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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