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rev: 1.04a 10/2002 1/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u 64k x 16 1mb asynchronous sram 7, 8, 10, 12 ns 3.3 v v dd center v dd and v ss soj, tsop, fp-bga commercial temp industrial temp features ? fast access time: 7, 8, 10, 12 ns ? cmos low power operation: 145/125/100/85 ma at minimum cycle time ? single 3.3 v power supply ? all inputs and outputs are ttl-compatible ? byte control ? fully static operation ? industrial temperature option: ? 40 to 85c ? package line up j: 400 mil, 44-pin soj package tp: 400 mil, 44-pin tsop type ii package u: 6 mm x 8 mm fine pitch ball grid array package description the gs71116a is a high speed cmos static ram organized as 65,536-words by 16-bits. static design eliminates the need for external clocks or timing strobes. operating on a single 3.3 v power supply and all inputs and outputs are ttl- compatible. the gs71116a is available in a 6 mm x 8 mm fine pitch bga package, as well as in 400 mil soj and 400 mil tsop type-ii packages. pin descriptions soj 64k x 16-pin configuration package j fine pitch bga 64k x 16-bump configuration 6 mm x 8 mm, 0.75 mm bump pitch (package u) symbol description a 0 ? a 15 address input dq 1 ? dq 16 data input/output ce chip enable input lb lower byte enable input (dq1 to dq8) ub upper byte enable input (dq9 to dq16) we write enable input oe output enable input v dd +3.3 v power supply v ss ground nc no connect 123456 alb oe a 0 a 1 a 2 nc bdq 16 ub a 3 a 4 ce dq 1 cdq 14 dq 15 a 5 a 6 dq 2 dq 3 d v ss dq 13 nc a 7 dq 4 v dd e v dd dq 12 nc nc dq 5 v ss fdq 11 dq 10 a 8 a 9 dq 7 dq 6 gdq 9 nc a 10 a 11 we dq 8 hnca 12 a 13 a 14 a 15 nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 4 a 3 a 2 a 1 a 0 ce dq 1 dq 2 dq 3 dq 4 v dd v ss dq 5 dq6 dq7 dq 8 we a 15 a 14 a 13 a 5 a 6 a 7 oe ub lb dq 16 dq 15 dq 14 dq 13 v ss v dd dq 12 dq 11 dq 10 dq 9 nc a 8 a 9 a 10 top view 21 22 24 23 a 12 a 11 44-pin soj nc nc
rev: 1.04a 10/2002 2/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u top view tsop-ii 64k x 16-pin configuration package tp 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 4 a 3 a 2 a 1 a 0 ce dq 1 dq 2 dq 3 dq 4 v dd v ss dq 5 dq 6 dq 7 dq 8 we a 15 a14 a 13 a 5 a 6 a 7 oe ub lb dq 16 dq 15 dq 14 dq 13 v ss v dd dq 12 dq 11 dq 10 dq 9 nc a 8 a 9 a 10 top view 21 22 24 23 a 12 a 11 44-pin tsop ii nc nc memory array row decoder column decoder address input buffer control i/o buffer a 0 ce we oe dq 1 a 15 block diagram dq 16 ub _____ lb _____
rev: 1.04a 10/2002 3/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u note: x: ?h? or ?l? note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operatio n shall be restricted to rec- ommended operating conditions. exposure to higher than recommen ded voltages for extended periods of time could affect device reliability. truth table ce oe we lb ub dq 1 to dq 8 dq 9 to dq 16 v dd current h x x x x not selected not selected isb 1 , isb 2 llh l l read read i dd l h read high z h l high z read lxl ll write write l h write not write, high z h l not write, high z write l h h x x high z high z l x x h h high z high z absolute maximum ratings parameter symbol rating unit supply voltage v dd ?0.5 to +4.6 v input voltage v in ?0.5 to v dd +0.5 ( 4.6 v max.) v output voltage v out ?0.5 to v dd +0.5 ( 4.6 v max.) v allowable power dissipation pd 0.7 w storage temperature t stg ?55 to 150 o c
rev: 1.04a 10/2002 4/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u notes : 1. input overshoot voltage should be less than v dd +2 v and not exceed 20 ns. 2. input undershoot voltage should be greater than ?2 v and not exceed 20 ns. notes : 1. tested at t a = 25c, f = 1 mhz 2. these parameters are sampled and are not 100% tested. recommended oper ating conditions parameter symbol min typ max unit supply voltage for -7/-8/-10/-12 v dd 3.0 3.3 3.6 v input high voltage v ih 2.0 ? v dd +0.3 v input low voltage v il ? 0.3 ? 0.8 v ambient temperature, commercial range t ac 0 ? 70 o c ambient temperature, industrial range t a i ? 40 ? 85 o c capacitance parameter symbol test condition max unit input capacitance c in v in = 0 v 5 pf output capacitance c out v out = 0 v 7 pf dc i/o pin characteristics parameter symbol test conditions min max input leakage current i il v in = 0 to v dd ?1 ua 1ua output leakage current i lo output high z v out = 0 to v dd ?1 ua 1ua output high voltage v oh i oh = ?4 ma 2.4 output low voltage v ol i lo = +4 ma 0.4v
rev: 1.04a 10/2002 5/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u power supply currents parameter symbol test conditions 0 to 70c ?40 to 85c 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns operating supply current i dd ce v il all other inputs v ih or v il min. cycle time i out = 0 ma 145 ma 125 ma 100 ma 85 ma 150 ma 130 ma 105 ma 90 ma standby current i sb1 ce v ih all other inputs v ih or v il min. cycle time 25 ma 20 ma 20 ma 15 ma 30 ma 25 ma 25 ma 20 ma standby current i sb2 ce v dd ? 0.2 v all other inputs v dd ? 0.2 v or 0.2 v 2 ma 5 ma
rev: 1.04a 10/2002 6/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u ac test conditions dq vt = 1.4 v 50 ? 30pf 1 dq 3.3 v output load 1 output load 2 589 ? 434 ? 5pf 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz parameter conditions input high level v ih = 2.4 v input low level v i l = 0.4 v input rise time tr = 1v/ns input fall time tf = 1 v/ns input reference level 1.4 v output reference level 1.4 v output load fig. 1& 2
rev: 1.04a 10/2002 7/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u ac characteristics * these parameters are sampled and are not 100% tested. read cycle 1: ce = oe = v il , we = v ih , ub and, or lb = v il read cycle parameter symbol -7 -8 -10 -12 unit min max min max min max min max read cycle time t rc 7?8?10 ? 12 ? ns address access time t aa ?7?8?10?12ns chip enable access time (ce )t ac ?7?8?10?12ns byte enable access time (ub , lb )t ab ?3?3.5? 4 ? 5 ns output enable to output valid (oe )t oe ?3?3.5? 4 ? 5 ns output hold from address change t oh 3?3?3 ? 3 ?ns chip enable to output in low z (ce ) t lz * 3?3?3 ? 3 ?ns output enable to output in low z (oe ) t olz * 0?0?0 ? 0 ?ns byte enable to output in low z (ub , lb ) t blz * 0?0?0 ? 0 ?ns chip disable to output in high z (ce ) t hz * ?3.5? 4 ? 5 ? 6 ns output disable to output in high z (oe ) t ohz * ?3?3.5? 4 ? 5 ns byte disable to output in high z (ub , lb ) t bhz * ?3?3.5? 4 ? 5 ? t aa t oh t rc address data out previous data data valid
rev: 1.04a 10/2002 8/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u read cycle 2: we = v ih * these parameters are sampled and are not 100% tested. write cycle parameter symbol -7 -8 -10 -12 unit minmaxminmaxminmaxminmax write cycle time twc 7 ? 8 ? 10 ? 12 ? ns address valid to end of write taw 5 ? 5.5 ? 7 ? 8 ? ns chip enable to end of write tcw 5 ? 5.5 ? 7 ? 8 ? ns byte enable to end of write tbw 5 ? 5.5 ? 7 ? 8 ? ns data set up time tdw 3.5 ? 4 ? 5 ? 6 ? ns data hold time tdh 0 ? 0 ? 0 ? 0 ? ns write pulse width twp 5 ? 5.5 ? 7 ? 8 ? ns address set up time tas 0 ? 0 ? 0 ? 0 ? ns write recovery time (we ) twr 0?0?0?0?ns write recovery time (ce ) twr10?0?0?0?ns output low z from end of write twlz * 3?3?3?3?ns write to output in high z twhz * ?3?3.5?4?5 ns taa trc address tac tlz tab tblz toe tolz ce ub , lb oe data out thz tbhz tohz data valid high impedance
rev: 1.04a 10/2002 9/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u write cycle 1: we control write cycle 2: ce control twc address ce ub , lb we data in oe data out taw tcw tbw tas twp twr tdw tdh twlz twhz data valid high impedance twc address ce ub , lb we data in oe data out taw twp tas tcw twr1 tdw tdh data valid high impedance tbw
rev: 1.04a 10/2002 10/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u write cycle 3: ub , lb control twc address ce ub , lb we data in oe data out taw twp tas tcw twr1 tdw tdh data valid high impedance tbw
rev: 1.04a 10/2002 11/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u 44-pin, 400 mil soj 122 23 44 e b1 d a1 a2 y e h e q c l g e detail a a b a notes: 1. dimension d& e do not include interlead flash. 2. dimension b1 does not incl ude dambar protrusion/intrusion. 3. controlling dimension: inches symbol dimension in inch dimension in mm min nom max min nom max a ? ? 0.148 ? ? 3.759 a1 0.025 ? ? 0.635 ? ? a2 0.105 0.110 0.115 2.667 2.794 2.921 b ? 0.018 ? ? 0.457 ? b1 0.026 0.028 0.032 0.660 0.711 0.813 c ? 0.008 ? ? 0.203 ? d 1.120 1.125 1.130 28.44 28.58 28.70 e 0.395 0.400 0.405 10.033 10.160 10.287 e ? 0.05 ? ? 1.27 ? h e 0.435 0.440 0.445 11.049 11.176 11.303 g e 0.360 0.370 0.380 9.144 9.398 9.652 l 0.082 0.087 0.106 2.083 2.210 2.70 y ? ? 0.004 ? ? 0.102 q 0 o ? 7 o 0 o ? 7 o
rev: 1.04a 10/2002 12/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u 44 pin, 400 mil tsop-ii d 122 23 44 e b q a a1 a2 y c detail a e h e l l1 a notes: 1. dimension d& e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: mm symbol dimension in inch dimension in mm min nom max min nom max a ? ? 0.047 ? ? 1.20 a1 0.002 ? ? 0.05 ? ? a2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.01 0.014 0.018 0.25 0.35 0.45 c ? 0.006 ? ? 0.15 ? d 0.721 0.725 0.729 18.31 18.41 18.51 e 0.396 0.400 0.404 10.06 10.16 10.26 e ? 0.031 ? ? 0.80 ? h e 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 l1 ? 0.031 ? ? 0.80 ? y ? ? 0.004 ? ? 0.10 q 0 o ? 5 o 0 o ? 5 o
rev: 1.04a 10/2002 13/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u 6 mm x 8 mm fine pitch bga c 5.25 0.75(typ). 3.75 pin a1 index 654321 a b d e f g h 0.22 0.05 1.20(max) 0.36(typ) ball dia. 0.35 pitch 0.75 d 0.10 pin a1 index bottom view top view 6.00 0.10 8.00 0.10 units: mm
rev: 1.04a 10/2002 14/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u * customers requiring delivery in tape and reel should add th e character ?t? to the end of the part number. for example: gs71116atp-10t ordering information part number * package access time temp. range status gs71116atp-7 400 mil tsop-ii 7 ns commercial gs71116atp-8 400 mil tsop-ii 8 ns commercial gs71116atp-10 400 mil tsop-ii 10 ns commercial gs71116atp-12 400 mil tsop-ii 12 ns commercial gs71116atp-7i 400 mil tsop-ii 7 ns industrial GS71116ATP-8I 400 mil tsop-ii 8 ns industrial gs71116atp-10i 400 mil tsop-ii 10 ns industrial gs71116atp-12i 400 mil tsop-ii 12 ns industrial gs71116aj-7 400 mil soj 7 ns commercial gs71116aj-8 400 mil soj 8 ns commercial gs71116aj-10 400 mil soj 10 ns commercial gs71116aj-12 400 mil soj 12 ns commercial gs71116aj-7i 400 mil soj 7 ns industrial gs71116aj-8i 400 mil soj 8 ns industrial gs71116aj-10i 400 mil soj 10 ns industrial gs71116aj-12i 400 mil soj 12 ns industrial gs71116au-7 6 mm x 8 mm fine pitch bga 7 ns commercial gs71116au-8 6 mm x 8 mm fine pitch bga 8 ns commercial gs71116au-10 6 mm x 8 mm fine pitch bga 10 ns commercial gs71116au-12 6 mm x 8 mm fine pitch bga 12 ns commercial gs71116au-7i 6 mm x 8 mm fine pitch bga 7 ns industrial gs71116au-8i 6 mm x 8 mm fine pitch bga 8 ns industrial gs71116au-10i 6 mm x 8 mm fine pitch bga 10 ns industrial gs71116au-12i 6 mm x 8 mm fine pitch bga 12 ns industrial
rev: 1.04a 10/2002 15/15 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs71116atp/j/u 1mb asynchronous datasheet revision history rev. code: old; new types of changes format or content page #/revisions/reason 71116a_r1 ? creation of new datasheet 71116a_r1; 71116_r1_01 content ? added 6 ns speed bin to entire document 71116a_r1_01; 71116a _r1_02 content ? updated all power numbers ? changed 6 mm x 10 mm fpbga package designator from u to x 71116a_r1_02; 71116a _r1_03 content ? updated recommended operating conditions table on page 4 ? changed fpbga package from 6 x 10 to 6 x 8 (package u) ? updated read cycle ac characteristics table 71116a_r1_03; 71116a _r1_04 content ? removed 6 ns speed bi n from entire document ? added 7 ns speed bin to entire document

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