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preliminary rev 1.0.8 7/12/02 characteristics subject to change without notice. 1 of 24 www.xicor.com x40020/40021 dual voltage monitor with integrated cpu supervisor and system battery switch features dual voltage detection and reset assertion three standard reset threshold settings (4.6v/2.9v, 4.6v/2.6v, 2.9v/1.6v) ? trip2 programmable down to 0.9v adjust low voltage reset threshold voltages using special programming sequence reset signal valid to v cc = 1v monitor two voltages or detect power fail battery switch backup ? out : 5ma to 50ma from v cc ; 250? from v batt fault detection register selectable power on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) selectable watchdog timer interval (25ms, 200ms, 1.4s, off) debounced manual reset input low power cmos 25? typical standby current, watchdog on 6? typical standby current, watchdog off 1? battery current in backup mode 400khz 2-wire interface 2.7v to 5.5v power supply operation available packages 14-lead soic, tssop applications communications equipment routers, hubs, switches disk arrays industrial systems process control intelligent instrumentation computer systems desktop computers network servers x40020/21 description the x40020 combines power-on reset control, watch- dog timer, supply voltage supervision, and secondary supervision, and manual reset, in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. applying voltage to v cc activates the power on reset circuit which holds reset/reset active for a period of time. this allows the power supply and system oscillator to stabilize before the processor can execute code. low v cc detection circuitry protects the users system from low voltage conditions, resetting the system when v cc falls below the minimum v trip1 point. reset/ reset is active until v cc returns to proper operating level and stabilizes. a second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. standard v trip1 level standard v trip2 , level suffix 4.6v (+/-1%) 2.9v(+/-1.7%) -a 4.6v (+/-1%) 2.6v (+/-2%) -b 2.9v(+/-1.7%) 1.6v (+/-3%) -c see ?rdering information?for more details for custom settings, call xicor. monitor voltages: 5v to 1.6v memory security battery switch backup ? out 5ma to 50ma new features block diagram v2f ail wdo mr lo wline reset reset x40020 X40021 + - v2 monitor logic v trip2 fault detection register status register data register command decode test & control logic power on, manual reset low voltage reset generation v cc monitor logic v2mon sda wp scl v cc (v1mon) watchdog and reset logic system switch battery v batt v out batt-on + - v trip1 v out v out v out preliminary datasheet
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 2 of 24 rev 1.0.8 7/12/02 www.xicor.com three common low voltage combinations are available. however, xicors unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet speci? system level requirements or to ?e-tune the threshold for applications requiring higher precision. a manual reset input provides debounce circuitry for minimum reset component count. a battery switch circuit compares v cc with v batt input and connects v out to whichever is higher. this pro- vides voltage to external sram or other circuits in the event of main power failure. the x40020/21 can drive 50ma from v cc to 250? from v batt . the device only switches to v batt when v cc drops below the low v cc voltage threshold and v batt . the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the wdo signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device features an 2-wire interface and software protocol allowing operation on a two-wire bus. the device utilizes xicors proprietary direct write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. pin configuration pin description pin name function 1 v2fail v2 voltage fail output. this open drain output goes low when v2mon is less than v trip2 and goes high when v2mon exceeds v trip2 . there is no power up reset delay circuitry on this pin. 2 v2mon v2 voltage monitor input. when the v2mon input is less than the v trip2 voltage, v2fail goes low. this input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. connect v2mon to v ss or v cc when not used. 3 lowline early low v cc detect. this open drain output signal goes low when v cc < v trip1 . when v cc > v trip1 , this pin is pulled high with the use of an external pull up resistor. 4 wdo wdo output. wdo is an active low, open drain output which goes active whenever the watch- dog timer goes active. 5mr manual reset input. pulling the mr pin low initiates a system reset. the reset/reset pin will remain high/low until the pin is released and for the t purst thereafter. it has an internal pull up resistor. v batt v ss v cc sda scl 3 2 4 1 12 13 11 14 lo wline wdo reset 7 6 5 8 9 10 v2mon mr wp 3 2 4 1 12 13 11 14 7 6 5 8 9 10 v out batt-on v2f ail v batt v cc sda scl wp v out batt-on v ss lo wline wdo reset v2mon mr v2f ail x40020 X40021 14-pin soic, tssop 14-pin soic, tssop
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 3 of 24 rev 1.0.8 7/12/02 www.xicor.com 6 reset / reset reset output. (X40021) this open drain pin is an active low output which goes low whenever v cc falls below v trip1 voltage or if manual reset is asserted. this output stays active for the pro- grammed time period (t purst ) on power up. it will also stay active until manual reset is released and for t purst thereafter. reset output. (x40020) this pin is an active high open drain output which goes high when- ever v cc falls below v trip1 voltage or if manual reset is asserted. this output stays active for the programmed time period (t purst ) on power up. it will also stay active until manual reset is released and for t purst thereafter. 7v ss ground 8 sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). watchdog input. a high to low transition on the sda (while scl is toggled from high to low and followed by a stop condition) restarts the watchdog timer. the absence of this transition within the watchdog time out period results in wdo going active. 9 scl serial clock. the serial clock controls the serial bus timing for data input and output. 10 wp write protect. wp high prevents writes to any location in the device (including all the registers). it has an internal pull down resistor. (>10m ? typical) 11 v batt battery supply voltage. this input provides a backup supply in the event of a failure of the primary v cc voltage. the v batt voltage typically provides the supply voltage necessary to maintain the contents of sram and also powers the internal logic to ?tay awake.?if the battery is not used, connect v batt to ground. 12 v out output voltage. (v) v out = v cc if v cc > v trip1 . if v cc < v trip1 then v out = v cc if v cc > v batt + 0.03v else v out = v batt (ie if v cc < v batt ?0.03v) note: there is hysteresis around v batt ?0.03v point to avoid oscillation at or near the switchover voltage. a capacitance of 0.1? must be connected to v out to ensure stability. 13 batt-on battery on. this cmos output goes high when the v out switches to v batt and goes low when v out switches to v cc . it is used to drive an external pnp pass transistor when v cc = v out and current requirements are greater than 50ma. the purpose of this output is to drive an external transistor to get higher operating currents when the v cc supply is fully functional. in the event of a v cc failure, the battery voltage is applied to the v out pin and the external transistor is turned off. in this ?ackup condition,?the battery only needs to supply enough voltage and current to keep sram devices from losing their data?here is no communication at this time. 14 v cc supply voltage pin description (continued) pin name function
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 4 of 24 rev 1.0.8 7/12/02 www.xicor.com principles of operation power on reset applying power to the x40020/21 activates a power on reset circuit that pulls the reset/reset pins active. this signal provides several bene?s. it prevents the system microprocessor from starting to operate with insuf?ient voltage. it prevents the processor from operating prior to sta- bilization of the oscillator. it allows time for an fpga to download its con?ura- tion prior to initialization of the circuit. it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power up. when v cc exceeds the device v trip1 threshold value for t purst (selectable) the circuit releases the reset (X40021) and reset (x40020) pin allowing the system to begin operation. figure 1. connecting a manual reset push-button manual reset by connecting a push-button directly from mr to ground, the designer adds manual system reset capa- bility. the mr pin is low while the push-button is closed and reset/reset pin remains low for t purst or till the push-button is released and for t purst thereafter. a weak pull up resistor is connected to the mr pin. low voltage v1 monitoring during operation, the x40020/21 monitors the v cc level and asserts reset if supply voltage falls below a preset minimum v trip1 . the reset signal prevents the microprocessor from operating in a power fail or brownout condition. the v1f ail signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip1 for t purst . low voltage v2 monitoring the x40020/21 also monitors a second voltage level and asserts v2f ail if the voltage falls below a preset minimum v trip2 . the v2f ail signal is either ored with reset to prevent the microprocessor from oper- ating in a power fail or brownout condition or used to interrupt the microprocessor with noti?ation of an impending power failure. the v2f ail signal remains active until the v cc drops below 1v (v cc falling). it also remains active until v2mon returns and exceeds v trip2 . v2mon voltage monitor is powered by v out. if v cc and v batt go away, v2mon cannot be monitored. figure 2. two uses of multiple voltage monitoring watchdog timer the watchdog timer circuit monitors the microproces- sor activity by monitoring the sda and scl pins. a standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the wdo signal to go active. a minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a start, clock low, clock high and stop. the state of two nonvolatile control bits in the status register determine the watchdog timer period. the microprocessor can change these watchdog bits by writing to the x40020/21 control register (also refer to page 21). mr system reset manual reset x40020 reset unreg. supply v cc 5v reg v2mon x40020 resistors selected so 3v appears on v2mon when unregulated supply reaches 6v. unreg. supply v cc X40021 reset v2fail system v out reset reset v2f ail v out system reset notice: no external components required to monitor two voltages. r r v2mon 5v reg 3v reg
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 5 of 24 rev 1.0.8 7/12/02 www.xicor.com figure 4. watchdog restart v1 and v2 threshold program procedure (optional) the x40020/21 is shipped with standard v1 and v2 threshold (v trip1, v trip2 ) voltages. these values will not change over normal operating and storage conditions. however, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the x40020 trip points may be adjusted. the procedure is described below, and uses the applica- tion of a high voltage control signal. setting a v tripx voltage (x=1, 2) there are two procedures used to set the threshold volt- ages (v tripx ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v tripx is 2.9 v and the new v tripx is 3.2 v, the new voltage can be stored directly into the v tripx cell. if however, the new setting is to be lower than the present setting, then it is necessary to ?eset the v tripx voltage before setting the new value. setting a higher v tripx voltage (x=1, 2) to set a v tripx threshold to a new voltage which is higher than the present threshold, the user must apply the desired v tripx threshold voltage to the corresponding input pin (vcc(v1mon) or v2mon). then, a program- ming voltage (vp) must be applied to the wdo pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h, followed by the byte address 01h for v trip1 , and 09h for v trip2 , and a 00h data byte in order to program v tripx . the stop bit following a valid write operation initiates the programming sequence. pin wdo must then be brought low to complete the operation. to check if the v tripx has been set, set vxmon to a value slightly greater than v tripx (that was previously set). slowly ramp down vxmon and observe when the corresponding outputs (lo wline and v2f ail ) switch. the voltage at which this occurs is the v tripx (actual). c ase a now if the desired v tripx is greater than the v tripx (actual), then add the difference between v tripx (desired) ?v tripx (actual) to the original v tripx desired. this is your new v tripx that should be applied to vxmon and the whole sequence should be repeated again (see figure 5). c ase b now if the v tripx (actual), is higher than the v tripx (desired), perform the reset sequence as described in the next section. the new v tripx voltage to be applied to vxmon will now be: v tripx (desired) ?(v tripx (actual) ?v tripx (desired)). note: 1. this operation does not corrupt the memory array. 2. set v cc = 5v, when v trip2 is being pro- grammed setting a lower v tripx voltage (x=1, 2) in order to set v tripx to a lower voltage than the present value, then v tripx must ?st be ?eset accord- ing to the procedure described below. once v tripx has been ?eset? then v tripx can be set to the desired voltage using the procedure described in ?etting a higher v tripx voltage? scl sda .6? 1.3? wdt reset start stop figure 3. v tripx set/reset conditions v cc /v2mon v tripx v p t wc a0h 0 7 70 7 0 scl wdo sda (x = 1, 2) 00h
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 6 of 24 rev 1.0.8 7/12/02 www.xicor.com resetting the v tripx voltage to reset a v tripx voltage, apply the programming voltage (vp) to the wdo pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 03h for v trip1 and 0bh for v trip2 , followed by 00h for the data byte in order to reset v tripx . the stop bit following a valid write oper- ation initiates the programming sequence. pin wdo must then be brought low to complete the operation. after being reset, the value of v tripx becomes a nominal value of 1.7v or lesser. note: this operation does not corrupt the registers. system battery switch as long as v cc exceeds the low voltage detect threshold v trip , v out is connected to v cc through a 5 ohm (typi- cal) switch. when the v cc has fallen below v1 trip , then v cc is applied to v out if v cc is or equal to or greater than v batt ?0.03v. when v cc drops to less than v batt ?0.03v, then v out is connected to v batt through an 80 ohm (typical) switch. v out typically supplies the system static ram voltage, so the switchover circuit operates to protect the contents of the static ram during a power fail- ure. typically, when v cc has failed, the srams go into a lower power state and draw much less current than in their active mode. when v cc returns, v out switches back to v cc when v cc exceeds v batt + 0.03v. there is a 60mv hysteresis around this battery switch threshold to prevent oscillations between supplies. while v cc is connected to v out the batt-on pin is pulled low. the signal can drive an external pnp tran- sistor to provide additional current to the external circuits during normal operation. operation the device is in normal operation with v cc as long as v cc > v trip1 . it switches to the battery backup mode when v cc goes away. control register the control register provides the user a mechanism for changing the block lock and watchdog timer settings. the block lock and watchdog timer bits are nonvolatile and do not change when power is removed. the control register is accessed with a special preamble in the slave byte (1011) and is located at address 1ffh. it can only be modi?d by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. prior to writing to the control register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. see "writing to the control registers" on page 8. the user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores wd1, wd0, pup1, and pup0. the x40020 will not ack-nowl- edge any data bytes written after the ?st byte is entered. the state of the control register can be read at any time by performing a random read at address 01fh, using the special preamble. only one byte is read by each register read operation. the master should supply a stop condi- tion to be consistent with the bus protocol, but a stop is not required to end this operation. rwel: register write enable latch (volatile) the rwel bit must be set to ? prior to a write to the control register. condition mode of operation v cc > v trip1 normal operation v cc > v trip1 & v batt = 0 normal operation without battery backup capability 0 v cc v trip1 and v cc < v batt battery backup mode; reset signal is asserted. no communica- tion to the device is allowed. 76543210 pup1 wd1 wd0 0 0 rwel wel pup0 figure 5. sample v trip reset circuit 1 6 2 7 14 13 9 8 x40020 v trip1 adj. v p reset 4.7k sda scl ? adjust run v2fail v trip2 adj.
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 7 of 24 rev 1.0.8 7/12/02 www.xicor.com figure 6. v tripx set/reset sequence (x = 1, 2) v tripx programming apply v cc and voltage decrease v x actual v tripx - desired v tripx done set higher v x sequence error < mde | error | < | mde | yes no error > mde + > desired v tripx to v x desired present value v tripx < execute no yes execute v tripx reset sequence set v x = desired v tripx new v x applied = old v x applied + | error | new v x applied = old v x applied - | error | execute reset v tripx sequence output switches? note: x = 1, 2 let: mde = maximum desired error vx = v cc , vxmon mde + desired value mde acceptable error range error = actual - desired wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ? to the wel bit and zeroes to the other bits of the control register. once set, wel remains set until either it is reset to 0 (by writing a ? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. writes to the wel bit do not cause a high volt- age write cycle, so the device is ready for the next operation immediately after the stop condition.
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 8 of 24 rev 1.0.8 7/12/02 www.xicor.com bp: block protect bit (nonvolatile) the block protect bits bp determines which blocks of the array are write protected. a write to a protected block of memory is ignored. the block protect bit will prevent write operations to half the array segment. pup1, pup0: power up bits (nonvolatile) the power up bits, pup1 and pup0, determine the t purst time delay. the nominal power up times are shown in the following table. wd1, wd0: watchdog timer bits the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. writing to the control registers changing any of the nonvolatile bits of the control and trickle registers requires the following steps: write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation preceded by a start and ended with a stop). write a 06h to the control register to set the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation proceeded by a start and ended with a stop). write a one byte value to the control register that has all the control bits set to the desired state. the control register can be represented as qxy 0 001 r in binary, where xy are the wd bits, and qr are the power up bits. this operation proceeded by a start and ended with a stop bit. since this is a nonvolatile write cycle it will take up to 10ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. if bit 2 is set to ? in this third step ( qxy 0 011 r ) then the rwel bit is set, but the wd1, wd0, pup1, and pup0, bits remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and returns a nack. a read operation occurring between any of the previ- ous operations will not interrupt the register write operation. the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequence of writes to the device consist- ing of [02h, 06h, 02h] will reset all of the nonvolatile bits in the control register to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. note: 1. t purst is set to 200ms as factory default. 2. watchdog timer bits are shipped disabled. fault detection register (fdr) the fault detection register provides the user the sta- tus of what causes the system reset active. the man- ual reset fail, watchdog timer fail and three low voltage fail bits are volatile the fdr is accessed with a special preamble in the slave byte (1011) and is located at address 0ffh. it can only be modi?d by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. there is no need to set the wel or rwel in the con- trol register to access this fault detection register. bp protected addresses (size) memory array lock 0 none none 1 100h ?1ffh (256 bytes) upper half of memory array pup1 pup0 power on reset delay ( t purst ) 0 0 50ms 0 1 200ms (default) 1 0 400ms 1 1 800ms wd1 wd0 watchdog time out period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory default) 7 6543210 lv1f lv2f 0 wdf mrf 0 0 0
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 9 of 24 rev 1.0.8 7/12/02 www.xicor.com figure 7. valid data changes on the sda bus scl sda data stable data change data stable at power-up, the fault detection register is defaulted to all ?? the system needs to initialize this register to all ? before the actual monitoring take place. in the event of any one of the monitored sources failed. the corresponding bits in the register will change from a ? to a ? to indicate the failure. at this moment, the sys- tem should perform a read to the register and noted the cause of the reset. after reading the register the system should reset the register back to all ? again. the state of the fault detection register can be read at any time by performing a random read at address 0ffh, using the special preamble. the fdr can be read by performing a random read at 0ffh address of the register at any time. only one byte of data is read by the register read operation. mrf, manual reset fail bit (volatile) the mrf bit will set to ? when manual reset input goes active. wdf, watchdog timer fail bit (volatile) the wdf bit will set to ? when wdo goes active. lv1f, low v cc reset fail bit (volatile) the lv1f bit will be set to ? when v cc (v1mon) falls below v trip1 . lv2f, low v2mon reset fail bit (volatile) the lv2f bit will be set to ? when v2mon falls below v trip2 . interface conventions the device supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this family operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 7. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 8. serial stop condition all communications must be terminated by a stop condi- tion, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 8.
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 10 of 24 rev 1.0.8 7/12/02 www.xicor.com figure 8. valid start and stop conditions scl sda start stop serial acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. see figure 9. the device will respond with an acknowledge after rec- ognition of a start condition and if the correct device identi?r and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identi?r and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the mas- ter. the sda output is at high impedance. figure 9. acknowledge response from receiver data output from transmitter data output from receiver 8 1 9 start acknowledge scl from master
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 11 of 24 rev 1.0.8 7/12/02 www.xicor.com figure 10. byte write sequence s t a r t s t o p slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master 0 stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing the write. the con- tents of the array will not be effected. acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the masters byte load operation, the device initiates the internal high voltage cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. see figure 11. serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. figure 11. acknowledge polling sequence ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 12 of 24 rev 1.0.8 7/12/02 www.xicor.com read operation prior to issuing the slave address byte with the r/w bit set to one, the master must ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immedi- ately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. see figure 12 for the address, acknowledge, and data transfer sequence. serial device addressing memory address map cr, control register, cr7: cr0 address: 1ff hex fdr, fault detectionregister, fdr7: fdr0 address: 0ff hex slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: a device type identi?r that is always ?011 when accessing the control register and fault detection register. two bits of ?? one bit that becomes the msb of the memory address x 4 . last bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte de?es the opera- tion to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. see figure 13. figure 12. read sequence 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master 101 0 0 1 11111111
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 13 of 24 rev 1.0.8 7/12/02 www.xicor.com word address the word address is either supplied by the master or obtained from an internal counter. operational notes the device powers-up in the following state: the device is in the low power standby state. the wel bit is set to ?? in this state it is not possible to write to the device. sda pin is the input mode. reset/reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: the wel bit must be set to allow write operations. the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. the wp pin, when held high, prevents all writes to the array and all the register. figure 13. slave address, word address, and data bytes general purpose memory control register fault detection register 1 1 0 0 1 1 0 1 a8 r/w word address slave byte 1 0 1011 0 0 0 0 0 0 r/w r/w general purpose memory control register fault detection register a7 1 a6 a5 a4 a1 a0 1 a3 a2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 14 of 24 rev 1.0.8 7/12/02 www.xicor.com absolute maximum ratings temperature under bias ................... ?5? to +135? storage temperature ........................ ?5? to +150? voltage on any pin with respect to v ss ......................................?.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds)........ 300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. recommended operating conditions *see ordering info temperature min. max. commercial 0? 70? industrial ?0? +85? version chip supply voltage monitored voltages* -a or -b 2.7v to 5.5v 2.6 to 5.5v -c 2.7v to 5.5v 1.6v to 3.6v d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d) symbol parameter min. typ. (5) max. unit test conditions i cc1 (1) active supply current ( v cc ) read (excludes i out ) 1.5 ma v il = v cc x 0.1 v ih = v cc x 0.9, f scl = 400khz i cc2 (1) active supply current ( v cc ) write non volatile memory (excludes i out ) 3.0 ma i sb1 (1)(7) standby current ( v cc ) ac (wdt off) 6 10 a v il = v cc x 0.1 vih = v cc x 0.9 f scl , f sda = 400khz i sb2 (2)(7) standby current ( v cc ) dc (wdt on) 25 30 ? v sda = v scl = v cc others = gnd or v cc i batt1 (3)(7) v batt current (excludes i out ) 0.2 1 a v out = v cc i batt2 (7) v batt current (excludes i out ) (battery backup mode) 0.2 6 a v batt = 2.8v v out = open v out1 (7) output voltage (v cc > v batt + 0.03v or v cc > v trip1 ) v cc ?.05v v cc ?.5v vi out = 5ma v cc = (4.5?.5v) i out = 50ma v cc = (4.5?.5v) v out2 (7) output voltage (v cc < v batt ? 0.03v and v cc < v trip1 ) {battery backup} v batt ?.2 v i out = 250? v olb output (batt-on) low voltage 0.4 v i ol = 3.0ma (4.5?.5v) v ohb output (batt-on) high voltage v out ?.8 v i oh = -0.4ma (4.5?.5v) v bsh (7) battery switch hysteresis (v cc < v trip1 ) 30 -30 mv power up power down i li input leakage current (scl, mr , wp) 10 ? v il = gnd to v cc
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 15 of 24 rev 1.0.8 7/12/02 www.xicor.com notes: (1) the device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t wc after a stop that ini- tiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the sl ave address byte. (3) negative numbers indicate charging current, positive numbers indicate discharge current. (4) v il min. and v ih max. are for reference only and are not tested. (5) at 25?, v cc = 3v. (6) see ordering information for standard programming levels. for custom programming levels, contact factory. (7) based on characterization data. equivalent input circuit for vxmon (x = 1, 2) i lo output leakage current (sda, v2fail , wdo , reset ) 10 ? v sda = gnd to v cc device is in standby (2) v il (3) input low voltage (sda, scl, mr , wp) -0.5 v cc x 0.3 v v ih (3) input high voltage (sda, scl, mr , wp) v cc x 0.7 v cc + 0.5 v v hys (7) schmitt trigger input hysteresis ?fixed input level ? v cc related level 0.2 .05 x v cc v v v ol output low voltage (sda, re- set/reset , lowline , v2fail , wdo ) 0.4 v i ol = 3.0ma (2.7?.5v) i ol = 1.8ma (2.4?.6v) v cc supply v trip1 (6) v cc reset trip point voltage range 2.0 4.75 v 4.55 4.6 4.65 a, b version 2.85 2.9 2.95 c version t rpdl (7) v trip 1 to lo wline 5s second supply monitor v trip2 (6) v2mon reset trip point voltage range 0.9 3.5 v 2.85 2.9 2.95 a version 2.55 2.6 2.65 b version 1.55 1.6 1.65 c version t rpd2 (7) v trip 2 to v2f ail 5s d.c. operating characteristics (continued) (over the recommended operating conditions unless otherwise speci?d) symbol parameter min. typ. (5) max. unit test conditions + v ref t rpdx = 5? worst case output vxmon r c ? v = 100mv ? v v ref
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 16 of 24 rev 1.0.8 7/12/02 www.xicor.com capacitance note: (1) this parameter is not 100% tested. symbol parameter max. unit test conditions c out (1) output capacitance (sda, reset, reset /lowline , v2fail , wdo ) 8pfv out = 0v c in (1) input capacitance (scl, wp) 6 pf v in = 0v equivalent a.c. output load circuit for v cc = 5v a.c. test conditions) symbol table input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load 5v sda 30pf v2mon 4.6k ? reset 30pf 2.06k ? v2fail v out 4.6k ? 30pf wdo /lowline must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 17 of 24 rev 1.0.8 7/12/02 www.xicor.com a.c. characteristics note: (1) cb = total capacitance of one bus line in pf. timing diagrams bus timing symbol parameter 400khz unit min. max. f scl scl clock frequency 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 ? t buf time the bus free before start of new transmission 1.3 ? t low clock low time 1.3 ? t high clock high time 0.6 ? t su:sta start condition setup time 0.6 ? t hd:sta start condition hold time 0.6 ? t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 ? t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (1) 300 ns t f sda and scl fall time 20 +.1cb (1) 300 ns t su:wp wp setup time 0.6 ? t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t r t dh t aa
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 18 of 24 rev 1.0.8 7/12/02 www.xicor.com wp pin timing write cycle timing nonvolatile write cycle timing note: (1) t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. power fail timings symbol parameter min. typ. (1) max. unit t wc (1) write cycle time 5 10 ms t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start scl sda t wc 8 th bit of last byte ack stop condition start condition v2mon v2f ail t r t f t rpdx v rvalid lo wline or v cc or v tripx t rpdx t rpdx t rpdl t rpdl t rpdl x = 1, 2
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 19 of 24 rev 1.0.8 7/12/02 www.xicor.com reset/reset /mr timings low voltage and watchdog timings parameters (@25?, vcc = 5v) note: (1) based on characterization data. symbol parameters min. typ. max. unit t rpd1 (1) t rpdl v trip1 to reset /reset (power down only) v trip1 to lowline 5s t lr (1) lowline to reset/reset delay (power down only) [= t rpd1 -t rpdl ] 500 ns t rpd2 (1) v trip2 to v2fail 5s t purst power on reset delay: pup1=0, pup0=0 pup1=0, pup0=1 (factory default) pup1=1, pup0=0 pup1=1, pup0=1 50 (1) 200 400 (1) 800 (1) ms ms ms ms t f v cc, v2mon fall time 20 mv / ? t r v cc, v2mon rise time 20 mv / ? v rvalid reset valid v cc 1v t md (1) mr to reset/ reset delay (activation only) 500 ns t in1 pulse width suppression time for mr 50 ns t wdo watchdog timer period: wd1=0, wd0=0 wd1=0, wd0=1 wd1=1, wd0=0 wd1=1, wd0=1 (factory default) 1.4 (1) 200 (1) 25 off s ms ms t rst1 watchdog reset time out delay wd1=0, wd0=0 wd1=0, wd0=1 100 200 300 ms t rst2 watchdog reset time out delay wd1=1, wd0=0 12.5 25 37.5 ms t rsp watchdog timer restart pulse width 1 s v cc v trip1 reset reset t purst t purst t r t f t rpd1 v rvalid mr t md
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 20 of 24 rev 1.0.8 7/12/02 www.xicor.com watchdog time out for 2-wire interface v tripx set/reset conditions < t wdo t rst wdo sda start t wdo t rst scl start t rsp wdt restart start sda scl minimum sequence to reset wdt clockin (0 or 1) scl sda v cc /v2mon (v tripx ) wdo t tsu t thd t vph t vps v p t wc t vpo a0h 0 7 70 7 sets v trip1 sets v trip2 *01h *09h *03h *0bh resets v trip2 resets v trip1 0 start * all others reserved 00h *
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 21 of 24 rev 1.0.8 7/12/02 www.xicor.com v trip1 , v trip2 programming specifications: v cc = 2.0?.5v; temperature = 25? parameter description min. max. unit t vps wdo program voltage setup time 10 ? t vph wdo program voltage hold time 10 ? t tsu v tripx level setup time 10 ? t thd v tripx level hold (stable) time 10 ? t wc v tripx program cycle 10 ms t vpo program voltage off time before next cycle 1 ms v p programming voltage 15 18 v v tran1 v trip1 set voltage range 2.0 4.75 v v tran2 v trip2 set voltage range 0.9 3.5 v v tv v tripx set voltage variation after programming (0-75?). -25 +25 mv t vps wdo program voltage setup time 10 ? v tripx programming parameters are periodically sampled and are not 100% tested.
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 22 of 24 rev 1.0.8 7/12/02 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14-lead plastic small outline gullwing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050"typical 0.030"typical 14 places footprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0??8 x 45
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 23 of 24 rev 1.0.8 7/12/02 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0?- 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
preliminary x40020/40021 ?preliminary characteristics subject to change without notice. 24 of 24 rev 1.0.8 7/12/02 www.xicor.com ?icor, inc. 2001 patents pending limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. copyrights and trademarks xicor, inc., the xicor logo, e 2 pot, xdcp, xbga, autostore, direct write cell, concurrent read-write, pass, mps, pushpot, block lock, identiprom, e 2 key, x24c16, secureflash, and serialflash are all trademarks or registered trademarks of xicor, inc. all other brand and produc t names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ordering information part mark information monitored v cc supplies v trip1 range v trip2 range package operating temperature range part number with reset part number with reset 2.9-5.5 4.6v?0mv 2.9v?0mv 14l soic 0 o c - 70 o c x40020s14-a X40021s14-a -40 o c - 85 o c x40020s14i-a X40021s14i-a 14l tssop 0 o c - 70 o c x40020v14-a X40021v14-a -40 o c - 85 o c x40020v14i-a X40021v14i-a 2.6-5.5 4.6v?0mv 2.6v?0mv 14l soic 0 o c - 70 o c x40020s14-b X40021s14-b -40 o c - 85 o c x40020s14i-b X40021s14i-b 14l tssop 0 o c - 70 o c x40020v14-b X40021v14-b -40 o c - 85 o c x40020v14i-b X40021v14i-b 1.6-3.6 2.9v?0mv 1.6v?0mv 14l soic 0 o c - 70 o c x40020s14-c X40021s14-c -40 o c - 85 o c x40020s14i-c X40021s14i-c 14l tssop 0 o c - 70 o c x40020v14-c X40021v14-c -40 o c - 85 o c x40020v14i-c X40021v14i-c 14-lead soic x4002xx yywwxx i ?industrial 0/1 package - s/v blank ?commercial ww ?workweek yy ?year a, b, or c

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