 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? semiconductor components industries, llc, 2015 october, 2015 ? rev. 4 1 publication order number: ncv7428/d ncv7428 system basis chip with integrated lin and voltage regulator description ncv7428 is a system basis chip (sbc) integrating functions typically found in automotive electronic control units (ecus). ncv7428 provides and monitors the low?voltage power supply for the application microcontroller and other loads and includes a lin transceiver. features ? control logic ? ensures safe power?up sequence and the correct reaction to different supply conditions ? controls mode transitions including the power management and bus wakeup treatment ? generates reset ? 3.3 v or 5 v v out supply depending on the version from a low?drop v oltage regulator ? can deliver up to 70 ma with accuracy of 2% ? supplies typically the ecu?s microcontroller ? undervoltage detector with a reset output to the supplied microcontroller ? lin transceiver ? lin2.x and j2602 compliant ? txd dominant timeout protection ? transceiver mode controlled by dedicated input pin ? protection and monitoring functions ? thermal shutdown protection ? load dump protection (45 v) ? lin bus pin protected against transients in an automotive environment ? esd protection level for lin and v s > 8 kv ? wettable flank package for enhanced optical inspection quality ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? automotive ? industrial networks www. onsemi.com (top view) 5 6 7 8 1 2 3 4 gnd lin en txd see detailed ordering, marking and shipping information in the package dimensions section on page 17 of this data sheet. ordering information v s rxd rstn pin assignment marking diagrams 1 8 soic?8 d suffix case 751az a = assembly location l = wafer lot y = year w = work week = pb?free package nv7428xx alyw 1 8 ncv7428 (note: microdot may be in either location) v out dfn8 mw suffix case 506cs 1 nv7428xx alyw 1
ncv7428 www. onsemi.com 2 block diagram txd v out en rxd control logic ncv7428 lin timeout driver & slope control thermal shutdown osc v s v s v out undervoltage detection v out v s v?reg ref receiver gnd rstn v out wakeup detection v out lin wakeup lin active figure 1. block diagram table 1. pin description pin number pin name pin type pin function 1 v s battery supply input principle power supply of the device 2 en lv lin enable input; internal pull?down input of the lin block enable signal 3 gnd ground connection ground connection 4 lin lin bus interface lin bus line 5 rxd lv digital output; push?pull output of data received on lin bus 6 txd lv digital input; internal pull?up input of the data to be transmitted from lin bus 7 rstn lv digital output; open drain; internal pull?up system reset 8 v out lv supply output output of the 5 v or 3.3 v/70 ma low?drop regulator (for the mcu) ep ep exposed pad connect to gnd or leave floating note: (lv = low voltage; hv = high voltage) ncv7428 www. onsemi.com 3 application information kl30 lin?bus kl31 vbat gnd lin mcu r pu_lin d pu_lin c lin_m en rxd txd rstn lin gnd v s v out r pu_ rstn c vs c vout v cc gnd d rev ncv7428 vbat gnd lin mcu c lin_s en rxd txd rstn lin gnd v s v out r pu_ rstn c vs c vout v cc gnd d rev ncv7428 ecu1 (master) ecu2 (slave) figure 2. example application diagram external components overview of external components from application schematic in figure 2 is given in table 2 together with their recommended or required values. table 2. external components overview component name description value note d rev reverse polarity protection diode parameters application?specific; e.g. 0.5 a / 50 v required values and types depend on the v out load and the application needs c vs filtering capacitor for the battery input recommended >100 nf ceramic c vout voltage regulator output filtering and stabilization capacitor > 1.8 f, esr < 7 d pu_lin master node pull?up diode on lin line required only for master lin node r pu_lin master node pull?up resistor on lin line 1 k nominal, 500 mw c lin_m filtering capacitor on lin line (master node) typically 1 nf optional; is function of the entire lin network c lin_s filtering capacitor on lin line (slave node) typically 100 pf ? 220 pf optional; is function of the entire lin network r pu_rstn pull?up resistor at rstn pin recommended 10 k nominal optional; depends on application needs ncv7428 www. onsemi.com 4 table 3. absolute maximum ratings symbol parameter min max units v s maximum dc voltage at v s pin ?0.3 45 v v out maximum voltage at v out pin ?0.3 6 v v lin maximum voltage at lin bus pin ?45 45 v v dig_io_inputs maximum voltage at digital input pins (txd, en) ?0.3 45 v v dig_io_outputs maximum voltage at digital output pins (rxd, rstn) ?0.3 v out +0.3 v t amb ambient temperature range ?40 +125 c t j junction temperature range ?40 +170 c t stg storage temperature range ?55 +150 c v esd system esd at pins vs, lin as per iec 61000?4?2: 330 / 150 pf (verified by external test house) 14 kv human body model at pins vs, lin stressed towards gnd with 1500 / 100 pf 8 kv human body model at all pins as per jesd22?a114 / aec?q100?002 4 kv charge device model at all pins as per jesd22?c101 / aec?q100?011 500 v machine model; (200 pf; 0.75 h; 10 ) as per jesd22?a115 / aec?q100?003 200 v msl moisture sensitivity level soic dfn 2 1 ? t sld lead temperature soldering ? reflow (smd styles only), pb?free (note 1) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d. table 4. operating ranges symbol parameter min max units v s vs operating voltage for parametric operation (note 2) 5.5 28 v vs operating voltage for limited operation (note 2) 4 28 v v out5 regulated voltage at v out supply output for 5 v versions 4.9 5.1 v v out33 regulated voltage at v out supply output for 3.3 v versions 3.234 3.366 v i vout current delivered by the v out regulator 70 ma v lin operating voltage at lin bus pin 0 v s v v dig_io_inputs operating voltage at digital input pins (txd, en) 0 5.5 v v dig_io_outputs operating voltage at digital output pins (rxd, rstn) 0 v out v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 2. below 5.5 v at v s pin in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time specifications as required by sae j2602. it is ensured by the battery monitoring circuit. above 28 v at v s pin, lin communication is operational (lin pin toggling) but parameters cannot be guaranteed. for higher battery voltage operation above 28 v, lin pull?u p resistor must be selected large enough to avoid clamping of lin pin by voltage drop over external pull?up resistor and lin pin min current limit ation. table 5. thermal characteristics rating symbol value unit thermal characteristics, soic?8 (note 3) thermal resistance junction?to?air, free air, 1s0p pcb (note 4) thermal resistance junction?to?air, free air, 2s2p pcb (note 5) r ja r ja 125 75 c/w c/w thermal characteristics, dfn?8 (note 3) thermal resistance junction?to?air, free air, 1s0p pcb (note 4) thermal resistance junction?to?air, free air, 2s2p pcb (note 5) r ja r ja 133 55 c/w c/w 3. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 4. values based on test board according to eia/jedec standard jesd51?3, signal layer with 10% trace coverage. 5. values based on test board according to eia/jedec standard jesd51?7, signal layers with 10% trace coverage for the signal lay er and 4 thermal vias connected between exposed pad and first inner cu layer. ncv7428 www. onsemi.com 5 definitions the characteristics defined in this section are guaranteed within the operating ranges listed in table 4, unless stated otherwise. all voltages are referenced to gnd (pin 3). positive currents flow into the respective pin. table 6. dc characteristics (v s = 5.5 v to 28 v; t j = ?40 c to +150 c; bus load = 500 (v s to lin); unless otherwise specified. typical values are given at v s = 12 v and t j = 25 c, unless otherwise specified.) symbol parameter conditions min typ max unit supply monitoring v s_porh v s threshold for the power?up of the circuit v s rising 3.3 4 v v s_porl v s threshold for the shutdown of the circuit v s falling 2.2 3 v v out_res_5 v out monitoring threshold nv7428?5 v out falling 4.55 4.75 v v out_res_33 v out monitoring threshold nv7428?3 v out falling 2.97 3.135 v v out_res_hys5 v out monitoring threshold hysteresis for nv7428?5 0.1 v v out_res_hys33 v out monitoring threshold hysteresis for nv7428?3 0.06 v current consumption i vs_lin_active_rec v s supply current lin active, lin bus recessive 1.8 ma i vs_lin_wakeup v s supply current (note 8) standby mode; lin wakeup, lin bus recessive; i vout = 0 ma v s = 13.5 v, t j < 105 c 25 40 a i vs_sleep v s supply current (note 8) sleep mode; lin wakeup, lin bus recessive; v out off, v out < 0.5 v v s = 13.5 v, t j < 105 c 12 25 a v out regulator v out_5 v out regulator output voltage (note 6) v out regulator active, 0 < i vout < 70 ma, static regulation, v s = 5.5 v to 28 v 4.9 5 5.1 v v out_33 v out regulator output voltage (note 6) v out regulator active, 0 < i vout < 70 ma, static regulation, v s = 4.5 v to 28 v 3.234 3.3 3.366 v v out_5_emc v out regulator output voltage under emc (note 8) dpi emc test applied to lin pin. no bus capacitor. soic8 package; (note 7) 4.85 5 5.15 v v out_33_emc v out regulator output voltage under emc (note 8) dpi emc test applied to lin pin. no bus capacitor. soic8 package; (note 7) 3.201 3.3 3.399 v i lim_vout v out current limitation v out regulator active; current flowing to v out load 70 120 350 ma v drop_vout drop?out voltage between v s and v out 5.5 v < v s < 40 v; i vout = 70 ma 0.55 v i sink_vout v out sink current v out regulator active, current flowing into the v out pin 100 240 400 a c vout v out regulator filtering capacitance (note 9) equivalent series resistance < 7 1.8 10 f product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. in case lin bus capacitor of at least 82 pf is not used v out_5_emc and v out_33_emc needs to be taken into account. 7. tested according to: lin conformance test specification package for lin 2.1, october 10 th , 2008. verified by external test house. 8. values based on design and characterization. not tested in production. 9. in parallel with this capacitor any other capacitor can be placed with no limit to esr and capacitance value 10. the voltage drop in normal mode between lin and v s pin is the sum of the diode drop and the drop at serial pull?up resistor. the drop at the switch is negligible. see figure 1. ncv7428 www. onsemi.com 6 table 6. dc characteristics (v s = 5.5 v to 28 v; t j = ?40 c to +150 c; bus load = 500 (v s to lin); unless otherwise specified. typical values are given at v s = 12 v and t j = 25 c, unless otherwise specified.) symbol unit max typ min conditions parameter lin transmitter v lin_dom_losup lin dominant output voltage txd = low; v s = 7.3 v 1.2 v v lin_dom_hisup lin dominant output voltage txd = low; v s = 18 v 2.0 v v lin_rec lin recessive output voltage txd = high; i lin = 10 a (note 10) v s ? 1.5 v s v i lin_lim short circuit current limitation v lin = v s = 18 v 40 200 ma r slave internal pull?up resistance lin normal or receive?only mode 20 33 47 k c lin capacitance at pin lin (note 8) 20 30 pf lin receiver v bus_dom bus voltage for dominant state 0.4 v s v bus_rec bus voltage for recessive state 0.6 v s v rec_dom receiver threshold lin bus going from recessive to dominant 0.4 0.6 v s v rec_rec receiver threshold lin bus going from dominant to recessive 0.4 0.6 v s v rec_cnt receiver center voltage (v rec_dom + v rec_rec )/2 0.475 0.525 v s v rec_hys receiver hysteresis v rec_rec ? v rec_dom 0.05 0.175 v s i lin_off_dom lin output current, bus in dominant state lin active mode, driver off; v s = 12 v, v lin = 0 v ?1 ma i lin_off_dom_wake lin output current, bus in dominant state lin wakeup mode; v s = 12 v, v lin = 0 v ?20 ?15 ?2 a i lin_off_rec lin output current, bus in recessive state driver off; v s < 18 v; v s < v lin < 18 v 1 a i lin_no_gnd lin current with missing gnd v s = gnd = 12 v; 0 < v lin < 18 v ?1 1 ma i lin_no_vbb lin current with missing v s v s = gnd = 0 v; 0 < v lin < 18 v 5 a pin en v il_en low?level input voltage ?0.3 0.8 v v ih_en high?level input voltage 2 5.5 v r pulldown_en pull?down resistance to gnd 55 100 185 k pin txd v il_txd low?level input voltage ?0.3 0.8 v v ih_txd high?level input voltage 2 5.5 v r pullup_txd pull?up resistance to v out 55 100 185 k i leak_txd leakage current v txd = v out = 5.5 v ?1 0 1 a pin rstn i ol_rstn low?level output driving current v s = 4 v to 28 v; v rstn = 0.4 v 4 30 ma v ol_rstn low?level output voltage v s = 2 v to 4 v; v out = 0 v to 5.5 v; i rstn = 100 a 0.1 v out v s < 2 v; v out = 1 v to 5.5 v; i rstn = 100 a 0.1 v out product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. in case lin bus capacitor of at least 82 pf is not used v out_5_emc and v out_33_emc needs to be taken into account. 7. tested according to: lin conformance test specification package for lin 2.1, october 10 th , 2008. verified by external test house. 8. values based on design and characterization. not tested in production. 9. in parallel with this capacitor any other capacitor can be placed with no limit to esr and capacitance value 10. the voltage drop in normal mode between lin and v s pin is the sum of the diode drop and the drop at serial pull?up resistor. the drop at the switch is negligible. see figure 1. ncv7428 www. onsemi.com 7 table 6. dc characteristics (v s = 5.5 v to 28 v; t j = ?40 c to +150 c; bus load = 500 (v s to lin); unless otherwise specified. typical values are given at v s = 12 v and t j = 25 c, unless otherwise specified.) symbol unit max typ min conditions parameter pin rstn r pullup_rstn pull?up resistance to v out 55 100 185 k v s_digout_low v s level guaranteeing low level at rstn pin shutdown mode; low level guar- anteed for v s > v s_digout_low 2 v pin rxd i ol_rxd low?level output driving current v rxd = 0.4 v 0.4 ma i oh_rxd high?level output driving current v rxd = v out ? 0.4 v ?0.16 ma thermal shutdown t j_sd junction temperature for ther- mal shutdown 160 180 200 c t j_sd_hys thermal shutdown hysteresis 10 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. in case lin bus capacitor of at least 82 pf is not used v out_5_emc and v out_33_emc needs to be taken into account. 7. tested according to: lin conformance test specification package for lin 2.1, october 10 th , 2008. verified by external test house. 8. values based on design and characterization. not tested in production. 9. in parallel with this capacitor any other capacitor can be placed with no limit to esr and capacitance value 10. the voltage drop in normal mode between lin and v s pin is the sum of the diode drop and the drop at serial pull?up resistor. the drop at the switch is negligible. see figure 1. ncv7428 www. onsemi.com 8 table 7. ac characteristics (v s = 5.5 v to 28 v; t j = ?40 c to +150 c; unless otherwise specified. for the transmitter parameters, the following bus loads are considered: l1 = 1 k / 1 nf; l2 = 660 / 6.8 nf; l3 = 500 / 10 nf) symbol parameter conditions min typ max unit lin transmitter d1 duty cycle 1 = t bus_rec(min) / (2 x t bit ) th rec(max) = 0.744 x v s th dom(max) = 0.581 x v s t bit = 50 s v s = 7 v to 18 v 0.396 0.5 d2 duty cycle 2 = t bus_rec(max) / (2 x t bit ) th rec(min) = 0.422 x v s th dom(min) = 0.284 x v s t bit = 50 s v s = 7.6 v to 18 v 0.5 0.581 d3 duty cycle 3 = t bus_rec(min) / (2 x t bit ) th rec(max) = 0.778 x v s th dom(max) = 0.616 x v s t bit = 96 s v s = 7 v to 18 v 0.417 0.5 d4 duty cycle 4 = t bus_rec(max) / (2 x t bit ) th rec(min) = 0.389 x v s th dom(min) = 0.251 x v s t bit = 96 s v s = 7.6 v to 18 v 0.5 0.590 t fallns lin falling edge normal slope normal mode; v s = 12 v 22.5 s t risens lin rising edge normal slope normal mode; v s = 12 v 22.5 s t symns lin slope symmetry normal slope normal mode; v s = 12 v ?4 0 4 s t fallls lin falling edge low slope (note 12) normal mode; v s = 12 v 45 s t risels lin rising edge low slope (note 12) normal mode; v s = 12 v 45 s t tx_prop_down propagation delay of txd to lin. txd high to low (note 11) 10 s t tx_prop_up propagation delay of txd to lin. txd low to high (note 11) 10 s t txd_timeout txd dominant timeout txd = low; lin dominant timeout enabled 7 13 24 ms lin receiver t rec_prop_down propagation delay of receiver falling edge 0.1 6 s t rec_prop_up propagation delay of receiver rising edge 0.1 6 s t rec_sym propagation delay symmetry t rec_prop_down ? t rec_prop_up ?2 2 s t lin_wake dominant duration for wakeup lin in wakeup mode 30 80 150 s mode transitions and timeouts t synch input signal synchronization delay 5 15 40 s t synch_action delay from the asynchronous input pin change to the system state change 11 25 55 s t modsel_set low power mode selection delay 17 30 55 s t reset rstn pulse extension 2 5 10 ms t vout_res_filt undervoltage detection filter time 11 25 55 s 11. values based on design and characterization. not tested in production. 12. for low slope versions only (nv7428l5 and nv7428l3) ncv7428 www. onsemi.com 9 functional description vs supply input v s pin of ncv7428 is typically connected to the car battery through a reverse?protection diode and can be exposed to all relevant automotive disturbances (iso7637 pulses, system esd ...). v s supplies mainly the integrated lin transceiver. filtering capacitors should be connected between v s and gnd. during power?up of the battery supply, v s pin must reach v s_porh level in order for the circuit to become functional ? the internal state machine is initiated and the v out regulator is activated. the circuit remains functional until v s falls back below v s_porl level, when the device enters the shutdown mode. vout low?drop voltage regulator the application low?voltage supply is provided by an integrated low?drop voltage regulator delivering a 5 v or 3.3 v output v out . it is able to deliver up to 70 ma with given precision and is primarily intended to supply the application microcontroller unit (mcu) and related 5 v or 3.3 v loads (e.g. its own mcu?related digital inputs/ outputs). an external capacitor needs to be connected on v out pin in order to ensure the regulator?s stability and to filter the disturbances caused by the connected loads. all low?voltage digital pins are related to v out . lin transceiver ncv7428 integrates on?chip lin transceiver interface between physical lin bus and the lin protocol controller. this lin physical layer is compatible to lin2.x and j2602 specifications. ncv7428 lin2.2 compliant physical layer can be combined on the network with all previous lin physical layers. ncv7428 lin transceiver consists of a transmitter, receiver and wakeup detector. the lin transceiver can be connected to the bus line via lin pin, and to the digital control through pins txd and rxd. the functional mode of the lin transceiver depends on the operating mode and on en pin state ? see figure 3. the lin transceiver is supplied directly from the v s pin. lin operating modes in lin active mode the transceiver can transmit and receive data via lin bus with speed up to 20 kbaud for normal slope mode and 10 kbaud/s for low slope version. the transmit data stream of the lin protocol is present on the txd pin and converted by the transmitter into a lin bus signal with controlled slew rate to minimize emc emission. the receiver consists of the comparator that has a threshold with hysteresis in respect to the supply voltage and an input filter to remove bus noise. the lin output is pulled high via an internal pull?up resistor (typ. 30 k ). for master applications, it is needed to put an external resistor (typ. 1k ) with a serial diode between lin and v s . the mode selection is done by en = high. the transmission is only initiated with the txd falling edge in lin active mode. entering this mode with txd already low will not lead to transmitting bus dominant signal. when leaving normal mode (en pin falling edge), the transmitter is deactivated immediately. the lin wakeup mode can be entered if the en pin is low. the lin receiver stays active to be able to detect a remote wake?up via bus. the lin transmitter is disabled and the slave internal termination resistor of 30 k between lin and v s is disconnected in order to minimize current consumption. only a pull?up current source between vs and lin is active. the valid lin wakeup event causes driving rxd low until en pin is pulled high. a wakeup pattern that is initiated in lin active mode and ends in lin w akeup mode is also considered a valid w akeup event. the lin wakeup mode is also forced if the device enters to the sleep operating mode. the lin off mode provides extreme low current consumption, lin transceiver is fully deactivated. pin rxd stays high (as long as v out is provided) and logical level on txd is ignored. the bus pin is internally pulled to v s with a current source (thus limiting v s consumption in case of a permanent lin short to gnd). this mode is entered when ncv7428 is in shutdown mode (v s < v s_porl ) or in thermal shutdown mode (t j > t j_sd ). ncv7428 www. onsemi.com 10 ignored lin off lin wakeup lin active lin mode lin txd rxd bus pin pull?up current source 30 k resistor lin wakeup detected lin active mode set recessive dominant en t txd_timeout ignored figure 3. lin modes < t lin_wake rxd en lin wakeup detected lin active mode restored lin recessive dominant t lin_wake figure 4. lin wakeup detection ncv7428 www. onsemi.com 11 operating modes the principal operating modes of ncv7428 are shown in figure 5 and described in the following paragraphs. sleep ?v out :off ?rstn: low ?lin: wakeup mode ?rxd: pulled to v out en = 1 lin_en = 0 and txd = 0 en = 0 and txd = 1 thermal shutdown ?v out :off ?rstn: low ?lin: wakeup mode ?rxd: low after wakeup/ pulled to v out otherwise t j < t j_sd t j > t j_sd shutdown ?v out :off ?rstn: low ?lin: off mode ?rxd: pulled to v out v s >v s _ porh and t j < t j_sd v s power?up v s ncv7428 www. onsemi.com 13 standby reset shutdown standby v s v s_porh t vout_res_ filt v out_res v out ncv7428 www. onsemi.com 14 en operating mode txd rstn rxd lin wakeup indication rstn pulse released en sampled reset normal ignored ignored mode change lin wakeup flag cleared t reset v out >v out_res t synch_action figure 8. operating modes, transition from reset to normal mode en operating mode txd standby rstn rxd lin wakeup indication txd sampling ignored lin transmission blocked ignored t synch normal t modsel_set t synch_action normal figure 9. operating modes, transition from normal to standby mode ncv7428 www. onsemi.com 15 lin wakeup indication en operating mode txd sleep rstn rxd v out off txd sampling ignored lin transmission blocked ignored t synch normal t modsel_set t synch_action reset figure 10. operating modes, transition from normal to sleep mode t bus_dom(min) lin t th rec(max) th rec(min) th dom(max) th dom(min) t bus_dom(max) t bus_rec(max) t bus_rec(min) thresholds of receiving node 1 thresholds of receiving node 2 50% t bit txd t t bit figure 11. definition of lin duty cycle parameters ncv7428 www. onsemi.com 16 t fall t rise lin 60% 40% 60% 40% 100% 0% t figure 12. definition of lin edge parameters 50% t bit txd 60% v s 40% v s t tx_prop_down t bit t tx _prop_up v s lin t t figure 13. definition of lin transmitter timing parameters 50% t rec_prop_up rxd lin t v s 60% v s 40% v s t rec_prop_down t figure 14. definition of lin receiver timing parameters ncv7428 www. onsemi.com 17 ordering information part number description marking package shipping ? NCV7428D15R2G lin transceiver with 5 v regulator nv7428?5 soic?8 (pb?free) 3000 / tape & reel ncv7428d13r2g lin transceiver with 3.3 v regulator nv7428?3 ncv7428d1l5r2g lin transceiver with 5 v regulator, low slope lin nv7428l5 ncv7428d1l3r2g lin transceiver with 3.3 v regulator, low slope lin nv7428l3 ncv7428mw5r2g lin transceiver with 5 v regulator nv7428?5 dfn8 wettable flanks (pb?free) 3000 / tape & reel ncv7428mw3r2g lin transceiver with 3.3 v regulator nv7428?3 ncv7428mwl5r2g lin transceiver with 5 v regulator, low slope lin nv7428l5 ncv7428mwl3r2g lin transceiver with 3.3 v regulator, low slope lin nv7428l3 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncv7428 www. onsemi.com 18 package dimensions soic 8 case 751az issue b 7.00 8x 0.76 8x 1.52 1.27 dimensions: millimeters 1 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.004 mm in excess of maximum material condition. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006 mm per side. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.010 mm per side. 5. the package top may be smaller than the package bot- tom. dimensions d and e1 are determined at the outer- most extremes of the plastic body at datum h. 6. dimensions a and b are to be determined at datum h. 7. dimensions b and c apply to the flat section of the lead between 0.10 to 0.25 from the lead tip. 8. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 14 85 seating plane detail a 0.10 c a1 dim min max millimeters h 0.25 0.41 a --- 1.75 b 0.31 0.51 l 0.40 1.27 e 1.27 bsc c 0.10 0.25 a1 0.10 0.25 l2 m 0.25 a-b b 8x c d a b c top view side view 0.25 bsc e1 3.90 bsc e 6.00 bsc d e d 0.20 c 0.10 c 2x note 6 notes 4&5 notes 4&5 side view end view e e1 d 0.10 c d d notes 3&7 note 6 note 8 a a2 a2 1.25 --- d 4.90 bsc h seating plane detail a l c l2 h 45 chamfer c note 7 ncv7428 www. onsemi.com 19 package dimensions dfn8, 3x3, 0.65p case 506cs issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. a b e d d2 e2 bottom view b e 8x 0.10 b 0.05 a c c note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 14 5 8 dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 3.00 bsc d2 2.30 2.50 e 3.00 bsc e2 1.50 1.70 e 0.65 bsc l 0.30 0.40 ?? ?? ?? ?? ? ? ? ? ?? ?? ?? ?? ? ? ? ? 1 0.65 pitch 3.30 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 8x dimensions: millimeters l1 detail a l alternate terminal constructions l detail b detail a l1 0.00 0.15 note 4 e/2 soldering footprint* ?? ?? on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv7428/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative |
Price & Availability of NCV7428D15R2G
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |