View CMX983_8548271.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CMX983 analogue front end (afe) for digital radio ? features ? rx channel ? two 16 - bit - a/d converters ? programmable channel filter ? tx channel ? two 14 - bit - d/a converters ? programmable channel filter ? rf support ? two 2.1ghz fractional - n synthesisers ? auxiliary functions ? 10 - bit a/d converter s upporting 10 inputs ? five analogue comparators ? 10 - bit d/a converters driving 9 outputs ? dsp interface ? c - bus control and configuration port ? fast serial interface for rx/tx data ? duplex and half duplex operation ? direct connection to: ? cmx998 cartesian loop transmitter ? cmx994 direct co nversion receiver ? low power operation ? 3.3v and 1.8v supplies ? small 64 - pin vqfn package applications ? software defined radio (sdr) ? satellite communication ? wireless data terminals ? digital pmr/lmr radio ? tetra ? dmr ? pdt cml microcircuits communication semiconductors
analogue front end (afe) for digital radio CMX983 ? 1 brief descript ion the CMX983 is an analogue front end (afe) ic that bridges the gap between a digital radios rf section and the dsp. specifically designed to meet the needs of a software designed radio (sdr), the CMX983 performs critical dsp - intensive functions, provides d ual channel analogue to digital and digital to analogue conversion, includes two rf fractional - n synthesisers, and embeds a host of auxiliary adcs and dacs for use within the radio system. the CMX983 meets the low operating power requirements of sdr - based terminals and is powered from separate 3.3v and 1.8v power supplies. a facility is provided to allow the pll charge pumps to be operated at up to 5v, providing low noise operation. the device is available in a small 64 - lead vqfn package.
analogue front end (afe) for digital radio CMX983 ? contents section page 1 brief description ................................ ................................ ................................ ..... 2 2 block diagram ................................ ................................ ................................ ........ 7 3 general desc ription ................................ ................................ ............................... 8 4 pin and signal list ................................ ................................ ................................ . 9 5 external components ................................ ................................ ........................... 13 6 c - bus interface ................................ ................................ ................................ ... 16 6.1 c - bus operation ................................ ................................ ........................... 16 6.2 c - bus register details ................................ ................................ ................. 18 6.3 c - bus general reset ................................ ................................ ................... 19 6.4 c - bus status and interrupt ................................ ................................ ........... 20 7 bias generator ................................ ................................ ................................ ..... 22 8 system clock generator ................................ ................................ ...................... 23 9 receive channel ................................ ................................ ................................ .. 26 9.1 rx sig nal routing and adcs ................................ ................................ ........ 26 9.2 receive channel filters ................................ ................................ ................ 29 10 transmit channel ................................ ................................ ................................ . 37 11 seria l ports ................................ ................................ ................................ ........... 44 11.1 rx serial port ................................ ................................ ................................ 44 11.2 tx serial port ................................ ................................ ................................ . 47 12 fractional - n frequency synthesizers ................................ ................................ .. 49 12.1 register loading order ................................ ................................ ................. 57 12.2 fractional - n programming examples ................................ ........................... 57 12.3 lock detector configuration guidelines ................................ ........................ 58 12.3.1 digital lock detector ................................ ................................ ............... 59 12.3.2 analogue lock detector ................................ ................................ .......... 60 13 auxiliary adc and comparators ................................ ................................ .......... 63 13.1 auxiliary adc ................................ ................................ ................................ 64 13.2 auxil iary comparators ................................ ................................ ................... 70 14 auxiliary dacs ................................ ................................ ................................ ..... 72 15 performance specification ................................ ................................ ................... 76 15.1 absolute maximum ratings ................................ ................................ ........... 76 15.2 operating limits ................................ ................................ ............................ 76 15.3 operating characteristics ................................ ................................ .............. 77 15.4 timing diagrams ................................ ................................ ........................... 83
analogue front end (afe) for digital radio CMX983 ? 15.5 typ ical performance characteristics ................................ ............................. 85 16 packaging ................................ ................................ ................................ ............ 93 table page table 1 pin and signal list ................................ ................................ .............................. 10 table 2 definition of power supply and reference voltages ................................ .......... 12 table 3 c - bus register map ................................ ................................ .......................... 19 table 4 operational characteristics - test conditions ................................ .................... 77 figure page figure 1 block diagram ................................ ................................ ................................ ...... 7 figure 2 CMX983q1 pin arrangement (top view) ................................ ............................. 9 figure 3 recommended external components - general ................................ ............... 13 figure 4 power supply decoupling ................................ ................................ .................. 14 figure 5 recommended external components C rx inputs ................................ ........... 15 figure 6 recommended external components C tx outputs ................................ ......... 15 figure 7 basic c - bus transactions ................................ ................................ ................ 16 figure 8 c - bus data - streaming operation ................................ ................................ ..... 17 figure 9 c - bus status and interrupt ................................ ................................ ............... 20 figure 10 bias voltage generator ................................ ................................ ................... 22 figure 11 system clock generator ................................ ................................ .................. 23 figure 12 rx input switching ................................ ................................ ........................... 26 figure 13 rx channel filters ................................ ................................ ........................... 29 figure 14 tx channel a and b ................................ ................................ ......................... 37 figure 15 rx serial port ................................ ................................ ................................ ... 44 figure 16 rx port timing (channel a and b both selected) ................................ ............ 44 figure 17 rx port timing (channel b only selected) ................................ ....................... 45 figure 18 tx serial port ................................ ................................ ................................ ... 47 figure 19 tx port t iming (channel a and b both selected) ................................ ............ 47 figure 20 tx port timing (channel b only selected) ................................ ....................... 48 figure 21 fractional - n frequency synthesizer ................................ ............................... 49 figure 22 digital lock detector ................................ ................................ ........................ 59 figure 23 digital lock detector state transitions ................................ ........................... 60 figure 24 analogue lock detector ................................ ................................ .................. 61 figure 25 auxiliary adc and comparators ................................ ................................ ...... 63 figure 26 auxiliary adc threshold trigger range ................................ ......................... 68 figure 27 comparator and threshold status flag ................................ .......................... 71 figure 28 auxiliary dacs ................................ ................................ ................................ . 72 figure 29 aux dac ram contents example ................................ ................................ .... 75 figure 30 ac test load for digital outputs ................................ ................................ ..... 83 figure 31 c - bus timings ................................ ................................ ................................ 83 figure 32 serial port timings ................................ ................................ .......................... 84 figure 33 adc sinad vs. input level ................................ ................................ ............. 85
analogue front end (afe) for digital radio CMX983 ? figure 34 adc sfdr vs. input level ................................ ................................ .............. 85 figure 35 adc two tone test ................................ ................................ ........................ 86 figure 36 dac sinad vs. input code level ................................ ................................ ... 87 figure 37 dac sfdr vs. input code level ................................ ................................ ..... 87 figure 38 pll1 output spectra ................................ ................................ ....................... 88 figure 39 pll1 lock time ................................ ................................ ............................... 89 figure 40 pll1 indicated lock time vs. fast lock current (965 to 875.525 mhz) ........ 89 figure 41 pll2 output spectra ................................ ................................ ....................... 90 figure 42 pll2 lock time ................................ ................................ ............................... 91 figure 43 pll2 indicated lock time vs. fast lock current (2125 to 2043 mhz) ........... 91 figure 44 relative performance of pll options ................................ ............................. 92 figure 45 64 - lead vqfn mechanical outline: order as part no. CMX983q1 ................. 93 it is always recommended that you check for the latest product datasheet version from the datasheets page of the cml website: [www.cmlmicro.com].
analogue front end (afe) for digital radio CMX983 ? history version changes date 6 ? section 15.3 (operating characteristics), synthesiser 1 and 2, rf input sensitivity: note 12 added, providing additional clarification and qualification to the stated figures. 30 th june 2015 5 ? section 15.5 C typical performance characteristics added 28 th nov 2014 4 ? section 12 C diagram modified, advice regarding co nnection to single ended vco added ? section 12 C pll1_con and pll2_con bits 13 - 11 description expanded ? section 12 C pll1_flck and pll2_flck bits 1 - 0 description expanded ? section 12 C pll1_bleed and pll2_bleed guidelines added ? section 12.2 C references to modulator type corrected ? section 12.3, 12.3.1, 12.3.2 C lock detector configuration g uidelines added ? section 15 C performance specification: corrections made 22 nd sept 2014 3 ? new title for device and datasheet ? front page C features, applications and system diagram replaced ? brief description and general description rewritten ? s ection 12 C frac - n synthesisers: expanded to include mode select options ? section 12 C pll1_bleed - $51: 8 - bit write and pll2_bleed - $5a: 8 - bit write registers added ? section 12 C pll_cfg - $ce: 16 - bit write register added ? section 13, figure 22 edited to show alternate routing for auxadc channels 6 and 7 ? section 15 C performance specification: entire section rewritten to include data from evaluation testing 6 th may 2014 2 front page applications list added and brief description updated , addition of 2 extra auxadc inputs, pll lock detect output, clarification of pll status and the application of resetn , standardisation of power supply nomenclature . 2 nd aug 2013 1 first release, a dvance information 20 th may 2013
analogue front end (afe) for digital radio CMX983 ? 2 block diagram figure 1 block diagram a u x d a c p l l 1 a u x a d c & c o m p a r a t o r s b i a s t x s e r i a l p o r t s r x - a d c - a d c s e r i a l p o r t r x i q - d a c - d a c i q m u x r x q s c l k c s n r d a t a c d a t a i r q n a u x d a c 7 a u x d a c 6 a u x d a c 5 a u x d a c 4 a u x a d c 4 a u x a d c 3 a u x a d c 2 a u x a d c 1 a u x a d c 0 c h a r g e p u m p p h a s e d e t e c t f r a c - n d i v i d e r r e f c l o c k 1 c p 1 r f 1 p c p 1 v d d ( < 5 . 0 v ) q t x n q t x p i t x n i t x p t x c l k t x f s t x d r x c l k r x f s r x d u p s a m p l e / i n t e r p o l a t e u p s a m p l e / h o l d u p s a m p l e / i n t e r p o l a t e u p s a m p l e / h o l d i r x p i r x n q r x p q r x n c a l i c a l q s i n c n / d e c i m a t e 1 2 8 t a p f i r / d e c i m a t e s i n c n / d e c i m a t e 1 2 8 t a p f i r / d e c i m a t e i n p u t s w i t c h r a m p r a m v b i a s d v s s d v d d ( 1 . 8 v ) i o v s s a v d d ( 3 . 3 v ) a v s s * s e r i a l p o r t t x x 4 x 2 x 2 r f 1 n * a v s s i s c o n n e c t e d d i r e c t l y t o t h e m e t a l p a d o n t h e u n d e r s i d e o f t h e p a c k a g e v b b u f a u x d a c 3 a u x d a c 2 a u x d a c 1 a u x d a c 0 9 x a u x d a c i o v d d ( 3 . 3 v ) x 2 a u x d a c 8 x 2 r e s e t n m c l k - - - - - + + + + + v o l t a g e r e f e r e n c e l a t c h c - b u s c o n f i g u r a t i o n a n d c o n t r o l a u x a d c a u x a d c 5 - + m a s t e r c l k d i v c l k r x i f l c k 1 r f 1 v d d ( 1 . 8 v ) p l l 2 c h a r g e p u m p p h a s e d e t e c t f r a c - n d i v i d e r r e f c l o c k 2 c p 2 c p 2 v d d ( < 5 . 0 v ) f l c k 2 r f 2 v d d ( 1 . 8 v ) r f 2 p r f 2 n
analogue front end (afe) for digital radio CMX983 ? 3 general description the CMX983 is an analogue front end (afe) for a dsp used in software defined radio systems and acts as a bridge between the analogue and digital sections of advanced digital radio systems. the device also performs critical dsp - intensive functions with low operating power thereby reducing the over all system power consumption. the receive path accepts differential analogue baseband i/q signals. these are converted to digital, decimated and passed through programmable fir channel filters to simplify host dsp processing and data extraction. the trans mit path accepts digital i/q data streams. these are up - sampled, interpolated and converted to analogue format, then driven off - chip for external up - conversion and transmission. two fractional - n rf synthesisers are provided which are capable of operating with external vcos of up to 2.1ghz. these have the advantage, over integer - n synthesisers, of allowing a higher pll reference frequency, which gives improved noise performance and agility. the fractional modulator can be configured for either 16 - bit or 24 - bit operation, enabling very fine frequency resolution. the synthesisers also include a fast - lock feature that helps minimise lock time when switching channels and provides an indication of when lock is achieved. an auxiliary adc (with multiplexed inputs) and a number of auxiliary dacs are included for control and measurement functions such as afc, agc and rssi. the adc has a digital threshold compare function, and one of the dacs has a programmable auto - ramping feature that is especially useful for contro lling the ramp - up and ramp - down profile of the transmitter power amplifier. five analogue comparators with programmable thresholds are provided; these share the auxiliary adc input pins and give the user the option of sensing monitoring signals with very low power consumption. the CMX983 is clocked from a full - swing logic level, or by low - amplitude sine wave or clipped sine wave. this may be used directly as a reference source or fed to an on - chip pll capable of generating a wi de range of internal clock frequencies. the CMX983 is suitable for radio systems employing channel bandwidths up to 25khz and is usable in satellite communication, high performance wireless data and professional two - way radio systems. the CMX983 features a high level of configurability, supporting numerous sample rates and filtering characteristics. this configurability enables a high level of functionality, integration and connectivity with rf building block ics. the CMX983 connects seamlessly with cmls cmx994 direct conversion receiver and the cmx998 cartesian feedback loop transmitter, to provide a complete, small form factor, rf - to - digitised baseband solution operating at up to 1ghz. the rx and tx channels interface to t he external dsp through dedicated fast serial ports. a separate c - bus port is provided for general control and configuration of the CMX983 , and a configurable interrupt generator may be used to minimise the load on the host processor .
analogue front end (afe) for digital radio CMX983 ? 4 pin and signal list vbbuf calq cali mclk rf2 vdd rf2n rf2p flck2 cp2 cp2 vdd cp1 vdd cp1 flck1 rf1n rf1p rf1 vdd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vbias 1 48 resetn a vdd 2 47 d vdd irxp 3 46 d vss irxn 4 45 irqn qrxp 5 44 csn qrxn 6 43 cdata a vdd 7 42 rdata itxp 8 41 sclk itxn 9 40 io vdd qtxp 10 39 io vss qtxn 11 38 txclk auxadc0 12 37 txfs auxadc1 13 36 txd auxadc2 14 metal pad 35 rxclk auxad c3 15 34 rxfs auxadc4 16 33 rxd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 auxadc5 a vdd auxdac0 auxdac1 auxdac2 auxdac3 a vdd auxdac4 auxdac5 auxdac6 auxdac7 auxdac8 io vss io vdd d vss d vdd the exposed metal pad at the underside of the package must connect to a vss figure 2 CMX983q1 pin a rrangement (top view)
analogue front end (afe) for digital radio CMX983 ? table 1 pin and signal list package q1 pin no. pin name type signal description 1 vbias o/p internally generated bias voltage of vdda/2 2 a vdd pwr analogue power (3.3v) 3 irxp i/p i channel positive input 4 irxn i/p i channel negative input 5 qrxp i/p q channel positive input 6 qrxn i/p q channel negative input 7 a vdd pwr analogue power (3.3v) 8 itxp o/p positive output for i channel 9 itxn o/p negative output for i channel 10 qtxp o/p positive output for q channel 11 qtxn o/p negative output for q channel 12 auxadc0 i/p auxiliary adc 0 input 13 auxadc1 i/p auxiliary adc 1 input 14 auxadc2 i/p auxiliary adc 2 input 15 auxadc3 i/p auxiliary adc 3 input 16 auxadc4 i/p auxiliary adc 4 input 17 auxadc5 i/p auxiliary adc 5 input 18 a vdd pwr analogue power (3.3v) 19 auxdac0 o/p auxiliary dac 0 output 20 auxdac1 o/p auxiliary dac 1 output 21 auxdac2 o/p auxiliary dac 2 output 22 auxdac3 o/p auxiliary dac 3 output 23 a vdd pwr analogue power (3.3v) 24 auxdac4 o/p auxiliary dac 4 output 25 auxdac5 o/p auxiliary dac 5 output 26 auxdac6 o/p auxiliary dac 6 output 27 auxdac7 o/p auxiliary dac 7 output (auxiliary adc 6 input can be selected) 28 auxdac8 o/p auxiliary dac 8 output (auxiliary adc 7 input can be selected) 29 io vss pwr io driver ground (0v) 30 io vdd pwr io driver power (3.3v) 31 d vss pwr digital ground (0v) 32 d vdd pwr core power (1.8v) 33 rxd o/p serial port receive data 34 rxfs o/p serial port receive frame sync
analogue front end (afe) for digital radio CMX983 ? package q1 pin no. pin name type signal description 35 rxclk o/p serial port receive clock 36 txd i/p serial port transmit data 37 txfs o/p serial port transmit frame sync 38 txclk o/p serial port transmit clock 39 io vss pwr io driver ground (0v) 40 io vdd pwr io driver power (3.3v) 41 sclk i/p c - bus serial clock input from the c 42 rdata t/s c - bus serial data output (3 - state) to the c 43 cdata i/p c - bus serial data input from the c 44 csn i/p c - bus chip select input (active low) from the c 45 irqn o/p c - bus interrupt request (open drain, active low) to the c 46 d vss pwr digital ground (0v) 47 d vdd pwr core power (1.8v) 48 resetn i/p device reset pin (active low) 49 rf1 vdd pwr rf power (1.8v) 50 rf1p i/p pll1 vco positive input 51 rf1n i/p pll1 vco negative input 52 flck1 o/p pll1 fast - lock output 53 cp1 o/p pll1 charge pump output 54 cp1 vdd pwr pll1 charge pump input supply 55 cp2 vdd pwr pll2 charge pump input supply 56 cp2 o/p pll2 charge pump output 57 flck2 o/p pll2 fast - lock output 58 rf2p i/p pll2 vco positive input 59 rf2n i/p pll2 vco negative input 60 rf2 vdd pwr rf power (1.8v) 61 mclk i/p master clock input 62 cali i/p i channel test calibration input 63 calq i/p q channel test calibration input 64 vbbuf o/p buffered mid - rail reference voltage pad a vss pwr analogue ground (0v) signal definitions notes: i/p = input o/p = output bi = bidirectional
analogue front end (afe) for digital radio CMX983 ? t/s = 3 - state output pwr = power connection nc = no connection table 2 definition of power supply and reference voltages signal name pins usage v dd analogue , av dd a vdd 3.3v positive supply rail for the analogue circuits v bias vbias internal analogue reference level, derived from av dd v bbuf vbbuf buffered mid - rail reference voltage (=av dd /2) v dd rf , rf1v dd , rf2v dd rf1vdd, rf2vdd 1.8v positive supply rail for rf power v dd charge pump , cp1v dd , cp2v dd cp1vdd, cp2vdd <5.0 v positive supply rail for the charge pumps v ss analogue , av ss avss ground for all analogue circuits (central metal pad) io v dd iovdd 3.3v positive supply rail for the i/o pads dv dd d vdd 1.8v positive supply rail for the digital core circuits v ss digital , dv ss d vss, iovss ground for all digital circuits
analogue front end (afe) for digital radio CMX983 ? 5 external components figure 3 recommended external components - general c1 = 10 nf (qty = 4) c3 = 1nf (qty = 4) r3 = 6.2k
analogue front end (afe) for digital radio CMX983 ? figure 4 power supply decoupling to achieve good noise performance, v dd and v bias decoupling and protection of the receive path from extraneous in - band signals are very important. it is recommended that the printed circuit board is laid out with ground plane s in the CMX983 area to provide a low impedance connection between the vss pin s and the v dd and v bias decoupling capacitors. 100nh inductors or 10 resistors , in combination with 10nf capacitors, should be used to decouple the powe r supplies, as shown in figure 4 .
analogue front end (afe) for digital radio CMX983 ? differential i/q inputs and outputs : rx inputs figure 5 recommended external components C rx inputs example values : r4 = 1.2k ? , c4 = 3.9nf (r4 x c 4 time constant give s - 3db at 34khz ? 10%) the anti - alias filter stage formed by r4 and c4 should have a low enough cutoff frequency to give adequate attenuation of unwanted signals near the main adc clock frequ ency f cr1 , but also have a high enough cutoff frequency to minimise the group delay variation within the passband in order to prevent intersymbol interference (isi). if these conflicting requirements cannot be achieved simultaneously, then the filter shoul d be designed to give adequate attenuation of the unwanted signals near f cr1 , and compensation for the group delay variation should be applied in the rx channel fir filter. alternatively, a higher order anti - alias filter with a flat group delay response co uld be used to replace components r4 and c4. in either case, positioning the anti - alias filter components close to the chip inputs may help to remove any pick - up from other noise sources. tx outputs figure 6 rec ommended external components C t x outp uts example values: r3 = 22k ? , c3 = 68 p f (r3 x c3 time constant should give - 3db at 10 6khz ? 10%) for each transmit channel, the rc stage formed by r3 and c3 combine with the internal 2 nd - order continuous time filter to create a 3 rd - order bessel filter with a - 3db cutoff f requency of approximately 80khz. r4 irxp qrxp irxn qrxn c4 c4 c4 c4 r4 filter 1 r4 r4 r3 r3 r3 r3 itxp qtxp itxn qtxn c3 c3 c3 c3
analogue front end (afe) for digital radio CMX983 ? 6 c - bus interface 6.1 c - bus operation this block provides for the transfer of data and control or status information between the CMX983 and t he host processor over the c - bus serial bus. each transaction consists of a single register address byte sent from the host which may be followed by a data word sent from the host to be written into one of the c - buss write - only registers, or a data word r ead out from one of the c - buss read - only registers; all c - bus data words are a multiple of 8 bits wide, the width depending on the source or destination register. note that certain c - bus transactions require only an address byte to be sent from the host, no data transfer being required. the operation of the c - bus is illustrated in figure 7 . data sent from the host on the cdata (command data) line is clocked into the CMX983 on the rising edge of the sclk input. data sent from the CMX983 to the host on the rdata (reply data) line is valid when sclk is high. the csn line must be held low during a data transfer and kept high between transfers. the c - bus interface is compatible with most common c serial interfaces and may al so be easily implemented with general - purpose c i/o pins controlled by a simple software routine. c - bus single byte command (no data) note: the sclk line may be high or low at the start and end of each transaction. ? = level not important c - bus n - bit register write csn sclk cdata 7 6 5 4 3 2 1 0 n - 1 n - 2 n - 3 2 1 0 msb address lsb msb write data lsb rdata hi - z c - bus n - bit register read csn sclk cdata 7 6 5 4 3 2 1 0 msb address lsb rdata hi - z n - 1 n - 2 n - 3 2 1 0 msb read data lsb figure 7 basic c - bus transactions csn sclk cdata 7 6 5 4 3 2 1 0 msb address lsb rdata hi - z
analogue front end (afe) for digital radio CMX983 ? to maximise data bandwidth across the c - bus interface, some read and write registers are capable of data - streaming operation. this allows a single address byte to be followed by the transfer of multiple read or write data words, all within the same c - bus t ransaction. this can significantly increase the transfer rate of large data blocks, as shown in figure 8 . example of c - bus data - streaming (8 - bit writ e register) csn sclk cdata 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 address first byte second byte last byte rdata hi - z example of c - bus data - streaming (8 - bit read register) csn sclk cdata 7 6 5 4 3 2 1 0 address rdata hi - z 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 first byte second byte last byte figure 8 c - bus data - s treaming operation
analogue front end (afe) for digital radio CMX983 ? 6.2 c - bus register details a summary of the c - bus addresses and registers is shown below. after power - up, the CMX983 must be reset using the resetn pin before the c - bus can be used. then, before the internal system clock ( clk ) is running , c - bus accesses are limited to the genr e s e t command, the status register, and the clock control registers clk_con and clkpll_con0/1. after clk is running, indicated by status register bit 7 going high, then the rest of the c - bus registers can be accessed. c - bus address c - bus type no. of data bits register name ? c - bus address c - bus type no. of data bits regis ter name ? $01 cmd - genr e s e t $5c wr 16 pll2_idiv $08 rd 8 status $5d wr 16 pll2_fdiv0 $09 wr 8 int_enab $5e wr 8 pll2_fdiv1 $10 wr 8 vbias_con $5f rd 8 pll2_status $11 wr 16 clk_con $60 cmd - auxadc_start $12 wr 16 clk pll _con 0 $61 cmd - auxadc_abort $13 wr 16 clk pll _con 1 $62 wr 16 auxadc_c lk $14 cmd - clk_off $63 wr 16 auxadc_pwrup $15 cmd - clk_on $64 wr 16 auxadc_con $1d wr 16 rx_input $65 wr 16 auxadc_thr0 $1e wr 16 rx_ovf $66 wr 16 auxadc_thr1 $1f wr 8 rx_con0 $67 wr 16 auxadc_thr2 $20 wr 16 rx_con1 $68 wr 16 auxadc_thr3 $21 wr 16 rx_con2 $69 wr 16 auxadc_thr4 $25 wr 8 rx_con3 $6a wr 16 auxadc_thr5 $26 wr 16 rx_vernier $6b wr 16 auxadc_thr6 $27 wr 16 rx_bitsel1 $6c wr 16 auxadc_thr7 $28 wr 16 rx_bitsel2 $6d rd 8 auxadc_stat $29 wr 16 (ds) rx_coeff0 $6e rd 16 auxadc_data0 $2a wr 16 (ds) rx_coeff1 $6f rd 16 auxadc_data1 $2b wr 16 (ds) rx_coeff2 $70 rd 16 auxadc_data2 $2c wr 16 (ds) rx_coeff3 $71 rd 16 auxadc_data3 $2d wr 8 rx_addr $72 rd 16 auxadc_data4 $2e rd 16 rx_status $73 rd 16 auxadc_data5 $2f wr 16 rx_st_enab $74 rd 16 auxadc_data6 $30 wr 8 tx_con0 $75 rd 16 auxadc_data7 $31 wr 16 tx_con1 $76 wr 8 auxcm p_con0 $34 wr 16 tx_con2 $77 wr 8 auxcmp_con1 $35 wr 16 tx_gain $78 wr 8 auxcmp_con2 $36 wr 16 (ds) tx_coeff0 $79 wr 8 auxcmp_con3 $37 wr 16 (ds) tx_coeff1 $7a wr 8 auxcmp_con4 $38 wr 8 tx_addr $7b rd 8 auxcmp_stat
analogue front end (afe) for digital radio CMX983 ? c - bus address c - bus type no. of data bits register name ? c - bus address c - bus type no. of data bits regis ter name ? $39 rd 8 tx_status $7c wr 8 auxcmp_st_en $3a wr 8 tx_st_enab $82 wr 16 auxdac_clk $40 wr 8 rxport_con0 $83 wr 16 (ds) auxdac_ramd $41 wr 8 rxport_con1 $84 wr 8 auxdac_rama $48 wr 8 txport_con0 $85 cmd - auxdac_up $49 wr 8 txport_con1 $86 cmd - auxdac_down $4e wr 16 pll1_con $87 cmd - auxdac_cycle $4f wr 16 pll1_ lockdet $88 cmd - auxdac_rst $50 wr 16 pll1_flck $89 wr 16 auxdac_data0 $51 w 8 pll1_bleed $8a wr 16 auxdac_data1 $52 wr 8 pll1_rdiv $8b wr 16 auxdac_data2 $53 wr 16 pll1_idiv $8c wr 16 auxdac_data3 $54 wr 16 pll1_fdiv0 $8d wr 16 auxdac_data4 $55 wr 8 pll1_fdiv1 $8e wr 16 auxdac_data5 $56 rd 8 pll1_status $8f wr 16 auxdac_data6 $57 wr 16 pll2_con $90 wr 16 auxdac_data7 $58 wr 16 pll2_ lockdet $91 wr 16 auxdac_data8 $59 wr 16 pll2_flck $ce w 16 pll_cfg $5a w 8 pll2_bleed $5b wr 8 pll2_rdiv (ds) C these registers are capable of data - streaming transactions . note: c - bus locations not defined in the above table are reserved and must not be written to. table 3 c - bus register map 6.3 c - bus general reset the CMX983 can be reset using the c - bus genr e s e t command C this has the same result as resetting the device using the r e s e tn pin. after reset is applied, t he CMX983 will stay in a quiescent state until the system clock generator is programmed (see section 8 ). genr e s e t - $0 1 c - bus command, no data required when the genr e s e t command is sent from the host processor, the internal device reset is applied on the eighth rising edge of the sclk pin and is released on the subsequent rising edge of csn.
analogue front end (afe) for digital radio CMX983 ? 6.4 c - bus status and interrupt figure 9 c - bus status and interrupt the c - bus status register, shown in figure 9 , is a read - only register that contains the status of various circuits wit hin the CMX983 . the status register can be polled by the host processor , or it can be interrupt driven: the interrupt pin irqn will be asserted when any bit of the status register is set to 1 and the associated bit in the int_enab register is also set to 1. enabling an interrupt by setting a n i nt _enab bit (0 1) after the corresponding status register bit has already been set to 1 will also cause the irq n output to be asserted . the irqn pin is an active low open - drain output . status - $08 : 8 - bit read reset value = $00 bit: 7 6 5 4 3 2 1 0 start - up done aux adc end of conv aux adc d igital comp status ana - log ue comp status pll2 lock status pll1 lock status rx chan status tx chan status status b 7 : startup done this status bit gets set to 1 , if enabled, when the startup timer in the system clock generator has reached its endcount value . this indicates that it is safe to access the other c - bus registers within the CMX983 . this bit gets auto matically cleared to 0 when it is read. status b 6 : aux adc end of convert this bit gets set to 1 when an aux ad c convert sequence completes , and automatically gets cleared to 0 when it is read. status b 5 : aux adc digital comparator status this bit gets set to 1 if any of the bits in the auxadc_stat register are set to 1, indicating that one or more adc conversion results were within the programmed threshold range . to clear this status bit, the auxadc_stat register must be read.
analogue front end (afe) for digital radio CMX983 ? status b 4 : a nalogue compa rator status this bit gets set to 1 if any of the bits in the auxcmp_stat register are set to 1 (indicating that an analogue comparator input has crossed its threshold) as long as the associated bit in the auxcmp_st_en register is also set to 1. this statu s bit can be cleared either by reading the auxcmp_stat register or by clearing the associated enable bit(s) in the auxcmp_st_en register. status b 3 : pll2 lock status this bit indicates the pll2 lock status . it can only be cleared by clearing pll2_status bits 1 - 0 (see section 12 for details) . status b 2 : pll 1 lock status this bit indicates the pll1 lock status it can only be cleared by clearing pll1_status bits 1 - 0 (see section 12 for details) . status b1: rx channel status this bit gets set to 1 if any of the bits in the rx_status register are set to 1 and the associated bit in the rx_st_en register is also set to 1. for details about clearing this bit, see section 9.2 . status b0: tx channel status this bit gets set to 1 if any of the bits in the tx_status register are set to 1 and the associated bit in the tx_st_en register is also set to 1. for details about clearing this bit, see section 10 . int_enab - $09 : 8 - bit write reset value = $ 8 0 bit: 7 6 5 4 3 2 1 0 interrupt enable int_enab b 7 - 0 : interrupt enable set ting any of these bits to 1 enable s the corresponding bit in the status register to generate an interrupt. this will cause the active - low open - drain irqn pin to pull down. after a reset, bit 7 of this register will be high which allows a startup done interrupt to be generated.
analogue front end (afe) for digital radio CMX983 ? 7 bias generator figure 10 bias voltage generator the bias generator provides a mid - rail reference voltage ( a v dd /2 ) that is used by the main adcs and dacs. an external decoupling capacitor is required on the vbias pin; no other connections should be made to this pin. a buffered version of the bias voltage, available on the vbbuf pin, can be used to drive external circuitry. vbias_con - $10 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 vbias enab buffer enab vbias_con b7 - 2: reserved, set to 0 vbias_con b1: vbias enable set to 1 to enable the mid - rail vbias generator C this must be done before using the main adc or dac channels. set to 0 to disable and powersave the vbias generator. note that the v bias voltage takes some time to settle, determined by the effective 50k ? source impedance and the value of the external capacitor c ext . vbias_con b0: buffer enable set to 1 to enable the vbias buffer amplifier. set to 0 to disable and power save the vbias buffer. when disabled, the vbbuf pin will go high impedance. b u f f e r e n a b l e + - a v d d a v s s v b i a s e n a b l e c e x t v b i a s _ c o n v b i a s v b b u f t o m a i n a d c / d a c 1 0 0 k 1 0 0 k
analogue front end (afe) for digital radio CMX983 ? 8 system clock generator figure 11 system clock generator the system clock generator buffers the mclk input signal and generates the internal clock s required by the rest of the CMX983 circuitry. the mclk pin can optionally be driven by a full swing logic level , or by the low amplitude sinewave or clipped sinewave that is typically output by a precision oscillator module. in the latter case, a n internal low phase noise amplifier is used to convert the mclk input signal to a full logic level. the buffered mclk signal is used to directly drive the reference dividers in the two fractional - n synthesizers. the main system clock signal clk is generated either by dividing down the mclk signal, or by dividing down an internally generated pll clock signal (if a non - integer related frequency is required). when the CMX983 comes out of reset the clk signal is disabled , which prevents all c - bus accesses except to the three system clock control registers ( clk_con and clkpll_con0 /1 ) , the status register and the genreset command . the clock control registers must be configured directly after the CMX983 comes out of reset in order to start the clk signal . if using the pll, then clk pll_con0 and clk pll _c on1 must be written first. then when clk_con is written , the system clock generator powers up and begins operating . as part of t he power up sequence, a startup delay timer ensures that the internal clk signal is kept inactive until a programmable number of clock pulses hav e been generated by the clock divider C this gives the mclk amplifier bias circui t and the pll time to stabilis e. a startup done status bit can optionally be generated to indicate that the startup delay timer has expired and that the clk signal is active. note that o nce the clk_con register has been written, all further changes to the three clock control register s are disabled until the CMX983 is reset again. clk_con - $1 1 : 16 - bit write reset value = $00 00 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 enab startup done startup delay clock divide e nab mclk amp clk_con b15 - 14 : reserved, set to 0
analogue front end (afe) for digital radio CMX983 ? clk_con b13: enable startup done set this bit to 1 to enable the startup done status bit. this status bit appears in the main status register, and indicates to the host processor that the startup delay counter has timed out and the internal clock clk is running . clk_con b12 - 8: startup delay this value determines how long the system clock generator circuit s are allowed to stabilise before the internal clk signal is enabled . the delay time should be sufficient to allow the bias for th e ac - coupled mclk amplifier to settle and for the clock pll to achieve lock, assuming these circuits are enabled. the startup delay counter is tri ggered immediately when clk_con is written , and counts output clock pulses from the clock divider . when the st artup delay counter reaches its programmed endcount , the clk signal is activated and, if clk_con bit 13 = 1, a startup interrupt is generated. startup delay $00 delay (cycles) = 2 0 (1) $01 delay (cycles) = 2 1 (2) $02 delay (cycles) = 2 2 (4) $03 delay (cycles) = 2 3 (8) 19 (524288) $14 delay (cycles) = 2 20 (1048576) $1 5 - $1f illegal, do not use clk_con b7 - 1: clock divide sets the division ratio between mclk (or pllclk) and the system clock clk. this value can be set to between 1 and 128 (0000000 = 128). clk_con b0: enable mclk amplifier set to 1 to enable the low - noise mclk amplifier, for use when the mclk signal is a low - amplitude sinewave or clipped sinewave. set to 0 to disable the mclk amplifier, for use when mclk is a full swing logic level. c lock pll registers do not write to these registers if the clock pll is not being used. clk pll _con 0 - $1 2 : 16 - bit write bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 clk pll _con 1 - $1 3 : 16 - bit write bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 for assistance in using the clock pll, please contact the technical support t eam at cml .
analogue front end (afe) for digital radio CMX983 ? clk_off - $14 c - bus command, no data required t he clk_off command causes the internal system clock clk to stop, but leaves the mclk amplifier and pll (if either are being used) enabled . this command can be used during periods of device inactivity to save power, but allows clk to be rapidly restarted using the clk_on c ommand. a fter a clk_off command all c - bus accesses are prevented except for the genreset and clk_on command s . clk_on - $15 c - bus command, no data required the clk_on command immediately starts the internal system clock clk running after previously being stopped b y the clk_off command .
analogue front end (afe) for digital radio CMX983 ? 9 receive channel 9.1 rx signal routing and adcs figure 12 rx input switching the i/q inputs connect to the main adcs through a signal switching block and programmable gain amplifiers as shown in figure 12 . the calibration input s can be connected to the programmable gain amplifiers to assist with system setup. each adc is a fourth - order sigma - delta type that outputs a single - bit pulse density modulated bitstream to the following digital channel filters. status bi ts are produced that indicate an input overload ; these can be read from the rx_status register (section 9.2 ). each input require s an external anti - alias filter, although the high oversampling rate typically used by the sigma - delta modulator relaxes the design requirements of these filters. to achieve optimum performance, signals at the sampling frequency (typically around 2.4mhz) s hould be attenuated to - 110db or lower . additionally, in order to reduce the complexity of the digital channel filters, the anti - alias filter may be able to usefully suppress signals at the first decimation rate. the outputs of the rx a and rx b programma ble gain amplifiers are also connected to channels 6 and 7 of the auxiliary adc through differential - to - single - ended converters (see section 13 ). enabling either differential - to - single - ended converter in the auxiliary adc automatically enables the associated rx a or rx b programmable gain amplifier, without also enabling that channels sigma - delta modulator. this feature can be used to implement a low power input s ignal level monitor during periods when the main rx signal path is not active .
analogue front end (afe) for digital radio CMX983 ? the following c - bus register s control the signal routing, gain setting and overflow status of the two rx input circuits: rx_input - $1 d : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cal select rx b enable adc b invert rx b gain ( - 12db 12db, +mute) 0 rx a enable adc a invert rx a gain ( - 12db 12db, +mute) rx_input b15: calibration select when this bit is set to 1 the calibration pin cali is connected to channel a positive input , calq is connected to channel b positive input, and the mid - rail reference voltage v bias is buffered and applied to both the channel a and b negative inputs . also, t he rx a and rx b programmable gain amplifiers are automatically set to 0 db while the calibration select bit is set to 1 . rx_input b14: rx b enable set to 1 to enable channel b gain stage and adc modulator. rx_input b13: adc b invert set to 1 to invert the channel b modulator output. rx_input b12 - 8: rx b gain set channel b input gain to between - 12db and +12db in 1db steps, or mute the output. the gain setting is in 2s complement format: 10000 = mute 10100 = - 12.0db 10101 = - 11.0db ... 11111 = - 1.0db 00000 = 0.0db 00001 = 1.0db ... 01011 = 11.0db 01100 = 12.0db rx_input b7: reserved, set to 0 rx_input b6: rx a enable set to 1 to enable channel a gain stage and adc modulator. rx_input b5: adc a invert set to 1 to invert the channel a modulator output. rx_input 4 - 0: rx a gain set channel a input gain, similar in operation to bits 12 - 8.
analogue front end (afe) for digital radio CMX983 ? rx_ovf - $1 e : 16 - bit wr ite reset value = $00 00 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 filt length b enab i/p b over - flow overflow threshold b 0 filt length a enab i/p a over - flow overflow threshold a the input overflow circuit uses a separate running average filter for each of the modulator output bitstream s ( channels a and b ) using a selectable window width of 32 or 64 bits. the modulator output bits have a weighting of ?, so the maximum theoretical filter output value is 16 (with a window width of 32) or 32 (with a window width of 64) . the average filter output value, for a dc level of 1v pk - pk at the input of the sigma - delta modulator, is approximately 4.82 (window width = 32) or 9.64 (window width = 64). if at any time the filter output for a channel exceeds the specified threshold value (in either the positive or negative direction), and if the overflow flag is enabled, then the associated status bit in the rx_stat us register gets set to 1. rx_ovf b15: reserved, set to 0 rx_ovf b14: filter length b for channel b, s et to 1 for a running average filter length of 64, set to 0 for a filter length of 32. rx_ovf b 1 3 : enable input overflow b for channel b, s et to 1 to enable the filters, set to 0 to disable the filters . rx_ovf b 1 2 - 8 : overflow threshold b if the absolute value of the (enabled) channel b running average filter output is greater than the overflow threshold b value, then an overflow is flagged i n the rx_status register . rx_ovf b7: reserved, set to 0 rx_ovf b 6 : filter length a for channel a, s et to 1 for a running average filter length of 64, set to 0 for a filter length of 32. rx_ovf b 5 : enable input overflow a for channel a, s et to 1 to enable the filters, set to 0 to disable the filters. rx_ovf b 4 - 0: overflow threshold a if the absolute value of the (enabled) channel a running average filter output is greater than the overflow threshold a value, then an overflow is flagged in the rx_status register .
analogue front end (afe) for digital radio CMX983 ? 9.2 receive channel filters figure 13 rx channel filters the CMX983 has two main channel filters ( figure 13 ). within each channel filter, the signal is decimated twice. data from the adc passes into a sinc n filter, a bit selector circuit and a vernier phase adjustment before the first downsampler. the resulting signal then passes into a programmable 128 - tap fir filter, a second bit selector and the second downsampler before being passed to the serial port for transmission to the host processor. the serial port data is formatted as 16 - bit 2s complement values. each stage in the rx channel (sinc filter, bit select, vernier adjust, downsample and fir filter) is programmable. sinc filter the bitstream produced by each sigma - delta modulator has a characteristic high - pass filtered noise profile. the sinc filter attenuates this quantisation noise, along with any other noise or unwanted signals coming from
analogue front end (afe) for digital radio CMX983 ? the de vice inputs, to prevent aliasing problems in the first downsampler. the number of cascaded stages in the sinc filter can be configured to between 3 and 6, with each stage having a length of up to 64. the length of the sinc filter should be set to an intege r multiple (usually 1x) of the first downsample rate m1 so that the zeroes in the filter transfer function appear at multiples of the cr2 clock rate. this minimises the amount of in - band energy in the aliased signals after decimation. note that the sinc fi lter transfer characteristic causes droop in the wanted signal, and this droop increases as the number of sinc stages or the sinc length is increased. however, moderate amounts of droop can be compensated for in the following fir filter. with a nominal pow er supply voltage ( a v dd = 3.3v), the gain of the adc between the input pins and the output of the sinc filter is given by the expression: where l = sinc length, n = number of sinc stages and a = analogue gain (see section 9.1 ). for example, with an analogue gain of 0db, a sinc length of 32 and a sinc number of 5, then a dc input signal of 1v (differential) at the input pins will giv e a nominal output of 5.053x10 6 (~ $4d1b00) into the first bit selector. first bit selector the bit selector at the output of the sinc filter selects which 20 bits of the 37 - bit sinc filter accumulator are passed to the following phase vernier and downsa mpler. phase vernier the phase vernier allows fine adjustment of the signal phase by setting which sinc output sample the first decimator selects. the a and b channel signals can be independently delayed by a programmable number of cycles of the cr1 clock , with the maximum number of delay cycles being one less than the first downsample rate. first downsampler the first downsampler reduces the sample rate of the signal by a factor of m1 = f cr1 /f cr2 . this process causes any residual signal components around multiples of the cr2 clock rate to be aliased, so it is important to make sure that the preceding filters (sinc filter and external anti - alias filter) have adequately attenuated these signal components. fir filter the purpose of the fir filter is to atte nuate out - of band signals and quantisation noise, perform any transfer function shaping that is required by the transmission standard and, if necessary, compensate for the droop caused by the sinc filter. the fir filter acts as an anti - alias filter for the second downsampler (if used) by ensuring that signal components around multiples of the cr3 frequency are adequately attenuated. the filter operates with 20 - bit data samples and 16 - bit coefficients, and can be configured with up to 128 taps. there are fou r banks of programmable coefficients. second bit selector the bit selector at the output of the fir filter selects which 16 bits of the 42 - bit fir filter accumulator are passe d to the following downsampler. second downsampler the second downsampler reduc es the sample rate of the signal by a factor of m2 = f cr2 /f cr3 . this process causes any residual signal components around multiples of the cr3 clock rate to be aliased, so it is important to make sure that the preceding filters have adequately attenuated t hese signal components. n al g 1506 . 0 ?
analogue front end (afe) for digital radio CMX983 ? the following c - bus registers are used to configure the rx channels . the settings in rx_con0/1/2 are applied to both channel filter a and channel filter b : rx_con0 - $ 1f : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 adc clock divide rx_con0 b7: reserved, set to 0 rx_con0 b6 - 0: adc clock divide sets the division ratio between clk and cr1, where cr1 is the clock for the sigma - delta modulator and sinc filter. this value can be set to between 2 and 128 (0000000 = 128). rx_con1 - $2 0 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 sinc number sinc length first downsample rate rx_con1 b15 - 14: reserved, set to 0 rx_con1 b13 - 12: sinc number these bits determine the number of cascade stages in the sinc filter: 00 = 3 stages ( sinc 3 ); 01 = 4 stages ( sinc 4 ); 10 = 5 stages ( sinc 5 ); 11 = 6 stages ( sinc 6 ). rx_con1 b11 - 6: sinc length sets the length of each sinc filter section to between 1 and 64 (000000 = 64) . this is normally set to the same value as the first downsample rate. rx_con1 b5 - 0: first downsample rate sets the division ratio between the cr1 and cr2 clock, which determines the first downsample rate m1. this can be set to between 1 and 64 (000000 = 64). rx_con2 - $2 1 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 fir bypass fir filter length second downsample rate rx_con2 b15 - 14: reserved, set to 0 rx_con2 b1 3 : fir bypass set this bit to 1 to disable and bypass the fir filter. data from the output of the first downsampler will then be sent directly to the input of the second bit selector (in the 20 most - significant bit positions). when the fir bypass bit is changed from 0 to 1, an initialisation sequence is performed which resets
analogue front end (afe) for digital radio CMX983 ? all data samples in fir filter to zero (coefficient rams are not altered). this initialisation takes 128 clk cycles to complete. rx_con2 b12 - 6: fir filter length sets the number of taps in the fir filter to a value between 1 and 128 (0000000 = 128). the filter length is also subject to the following restriction, based on the clk and adc sample frequencies: rx_con2 b5 - 0: second downsample rate sets the division ratio between the cr2 and cr3 clock, which determines the second downsample rate m2. this can be set to between 1 and 64 (000000 = 64). note that the maximum cr3 clock frequency is further restricted to f cr3 f clk /4 , i.e. (n m1 m2) 4, although this limit is unlikely to be approached in a typical receive channel configuration. rx_con3 - $2 5 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 rx b enable fir b coeff select 0 rx a enable fir a coeff select rx_con3 b7: reserved, set to 0 rx_con3 b6: rx b enable set this bit to 1 to enable rx channel b filter logic (sinc filter onwards) and start the transfer of data to the serial port. when this bit is set to 1, the channel b idle bit in rx_status will read as 0. after reset, or when the rx b enable bit is changed from 1 to 0, the channel b logic ceases operating and an initialisation sequence is performed which resets all data samples in the sinc filter and fir filter to zero (coefficient rams are not altered). this initialisation takes 128 clk cycles to complete, after which the channel b idle bit in rx_status will be set to 1. it is recommended that the rx b enable bit should be set to 1 only after the configuration bits in rx_con0/1/2 have b een initialised, and that these registers do not get changed again until the rx b enable bit is cleared to 0 and channel b is idle. rx_con3 b5 - 4: fir b coefficient select selects which bank of coefficients the channel b fir filter uses: 00 = rx_coeff0 01 = rx_coeff1 10 = rx_coeff2 11 = rx_coeff3 rx_con3 b3: reserved, set to 0 rx_con3 b2: rx a enable set this bit to 1 to enable rx channel a filter logic, similar in operation to bit 6. rx_con3 b1 - 0: fir a coefficient select ? ? ? ? ? ? ? ? ? ? ? 1 3 2 cr cr clk f f f th filterleng
analogue front end (afe) for digital radio CMX983 ? selects which bank of coefficients the channel a fir filter uses: 00 = rx_coeff0 01 = rx_coeff1 10 = rx_coeff2 11 = rx_coeff3 rx_vernier - $2 6 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 phase vernier b 0 0 phase vernier a rx_vernier b15 - 14: reserved, set to 0 rx_vernier b13 - 8: phase vernier b allows fine adjustment of the channel b signal phase by setting which sinc output sample the first downsampler selects. setting the phase vernier value to 0 gives an on - time signal; setting the value to n gives a late signal, delayed by n cycles of the cr1 clock. the phase vernier value must be less than the value set for the first downsample rate in the associated decimator control register rx _con1. rx_vernier b7 - 6: reserved, set to 0 rx_vernier b5 - 0: phase vernier a allows fine adjustment of the channel a signal phase (similar in operatio n to bits 13 - 8). rx_bitsel1 - $2 7 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 rx b first bit select 0 0 0 rx a first bit select rx_bitsel1 b15 - 13: reserved, set to 0 rx_bitsel1 b12 - 8: rx b first bit select in rx channel b, selects which 20 bits of the 37 - bit sinc filter accumulator are passed to the following phase vernier and downsample stage. this value determines the number of most - significant bits discarded (valid range = 0 to 17) : a value of 0 selects t he most significant 20 bits of the sinc accumulator, a value of 1 discards the msb of the accumulator and selects the next most significant 20 bits, and so on. convergent rounding is applied to the selected bits and the selector output saturates in the cas e of an overflow (positive saturation = $7ffff, negative saturation = $80000). to assist with setup, an overflow causes a status bit to be set in the rx_status register. rx_bitsel1 b7 - 5: reserved, set to 0 rx_bitsel1 b4 - 0: rx a first bit select rx channe l a first bit select , similar in operation to bits 12 - 8.
analogue front end (afe) for digital radio CMX983 ? rx_bitsel2 - $28 : 16 - bit writ e reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 rx b second bit select 0 0 0 rx a second bit select rx_bitsel2 b15 - 13: reserved, set to 0 rx_bitsel2 b12 - 8: rx b second bit select in rx channel b, selects which 16 bits of the 42 - bit fir filter accumulator are passed to the following downsample stage. this value determines the number of most - significant bits discarded (the valid range = 0 to 2 6): a value of 0 selects the most significant 16 bits of the fir accumulator, a value of 1 discards the msb of the accumulator and selects the next most significant 16 bits, and so on. convergent rounding is applied to the selected bits and the selector ou tput saturates in the case of an overflow (positive saturation = $7fff, negative saturation = $8000). to assist with setup, an overflow causes a status bit to be set in the rx_status register. rx_bitsel2 b7 - 5: reserved, set to 0 rx_bitsel2 b 4 - 0 : rx a sec ond bit select rx channel a second bit select, similar in operation to bits 12 - 8 . rx_coeff0 - $29 : 16 - bit write , data - streaming rx_coeff1 - $2a : 16 - bit writ e, data - streaming rx_coeff2 - $2b : 16 - bit write , data - streaming rx_coeff3 - $2c : 16 - bit write , data - streaming reset value = undefined bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fir coefficient values (2s complement) these four c - bus locations allow the 128 - word fir coefficient rams for the rx channels to be loaded. each coefficient ram can be loaded in ascending order by repeatedly writing data to the same c - bus location (an internal address pointer automatically increments after each write). to increase the loading rate of the coefficients, data - streaming operation is supported for these four c - bus addresses. only as many coefficients as are required (determined by the fir length) need to be loaded into each ram, unused ram locations do not need to be written. before loading each of the four coefficient rams, the internal address pointer needs to be initialised (usually to address 0); this is done by writing to register rx_addr. note that all four rams share this address pointer, so the address needs to be initialised before each coefficient ram is loaded. during operation, with a filter lengt h of n, the fir filter stores the previous n data samples provided by the first downsampler. then, whenever the second downsampler requires a new sample, the fir filter generates this by performing a sequence of n multiply/accumulate operations using the s elected filter coefficients and the stored data samples. the coefficient at ram address 0 is multiplied by the most recent data sample from the first downsampler, the coefficient at address 1 is multiplied by the data delayed by one cycle of cr2, the coeff icient at address 2 is multiplied by the data delayed by two cycles of cr2, and so on. the accumulated total, after scaling/rounding and downsampling, is sent to the serial port for transmission.
analogue front end (afe) for digital radio CMX983 ? rx_addr - $2d : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 rx coefficient address pointer the rx coefficient address pointer determines the address at which data gets written during a c - bus write to any of the four rx coefficient rams. the rx coefficient address pointer automatically increments after each 16 - bit coefficient value is written, so if the coefficients are written in an ascending sequence the pointer only needs to be initialised once before each bank of coefficients is loaded. rx_status - $2e : 16 - bit re ad reset value = $ 0 1 0 1 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ch. b vern. error ch. b fir error ch. b 2 nd bit select over - flow ch. b 1 st bit select over - flow ch. b input over - flow ch. b buffer over - run ch. b idle 0 ch. a vern. error ch. a fir error ch. a 2 nd bit select over - flow ch. a 1 st bit select over - flow ch. a input over - flow ch. a buffer over - run ch. a idle rx_status b15: reserved, set to 0 rx_status b1 4 : channel b vernier error this bit gets set if rx channel b is enabled and the vernier value is incorrect, i.e. it has been set to a value equal to or greater than first downsample rate in channel b . to clear this bit, first correct the error (or disable the channel) then read the rx_status register again. rx_status b1 3 : channel b fir error this bit gets set, if rx channel b is enabled, if a new output value from the fir filter is not ready when the rising edge of the cr3 clock occurs. this happens if the fir filter length is too large for the chosen clock and sample rates. when this happens, data sent from the fir filter to the rx serial port may become lost or corrupted. this bit gets cleared only when rx_status is read. rx_status b 12 : channel b 2 nd bit selector overflow this bi t gets set to 1 when the channel b 2 nd bit selector output value saturates to maximum positive ($7fff) or maximum negative ($8000). this bit gets cleared only when rx_status is read. rx_status b 11 : channel b 1 st bit selector overflow this bit gets set to 1 when the channel b 1 st bit selector output value saturates to maximum positive ($7 f fff) or maximum negative ($80 0 00). this bit gets cleared only when rx_status is read. rx_status b 10 : channel b input overflow this bit gets set to 1 when the channel b in put exceeds a pre - programmed limit (see section 9.1 ). this bit gets cleared only when rx_status is read. rx_status b 9 : channel b buffer overrun this bit gets set to 1 whenever rx channel b generates a data sample before the rx serial port is able to take it, for instance if the rx serial port gets disabled or is configured to run too slowly. when
analogue front end (afe) for digital radio CMX983 ? this happens, the data sample will be lost. the buf fer overrun bit gets cleared only when rx_status is read. rx_status b 8 : channel b idle this bit is a level sensitive signal that is set to 1 whenever channel b is in the idle state. rx_status b7: reserved, set to 0 rx_status b6 - 0: (channel a status bit s) similar in operation to bits 14 - 7. rx_st_enab - $2f : 16 - bit write reset value = $00 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 rx status enable (channel b) 0 rx status enable (channel a) rx_st_enab b15 , b7 : reserved, set to 0 rx_st_enab b14 - 8, b6 - 0 : rx status enable if any of these bits is high while the corresponding bit in the rx_status register is also high, then the rx status bit (in status register bit 1) gets set to 1.
analogue front end (afe) for digital radio CMX983 ? 10 transmit channel figure 14 tx channel a and b the CMX983 has two tx channels ( figure 14 ). within each tx channe l, data can be upsampled twice. d ata from the serial port , formatted as 16 - bit 2s complement values, optionally passes through a first upsampler, a programmable fir interpolation filter and a bit selector . the data then passes through a second upsampler and into a sigma - delta modulator. the resulting signal then passes through a reconstruction filter and variable gain bloc k before being driven onto the tx output pins. first upsampler the first upsampler takes 16 - bit 2s complement values from the serial port at a rate equal to ct1 and outputs them to the interpolation filter at a rate equal to ct2. the upsampler uses zero padding, so for an upsample factor of l1 (= f ct2 /f ct1 ) there are l1 - 1 zero - valued samples inserted between each of the original time samples. this upsampling process results in unwanted spectral images at multiples of the ct1 frequency, but
analogue front end (afe) for digital radio CMX983 ? otherwise the o riginal signal remains undistorted. the first upsample factor can be set to any value up to 8. alternatively, the first upsampler, fir filter and bit selector can be disabled and bypassed. interpolation filter the interpolation filter is a 128 - tap fir typ e that takes the zero padded samples from the first upsampler at a frequency equal to ct2. there are two banks of programmable coefficients. the purpose of the low - pass interpolation filter is to attenuate the unwanted spectral images caused by the first u psampler, perform any transfer function shaping that is required by the transmission standard and, if necessary, provide compensation for the droop caused by the second upsampler or the dac reconstruction filter . bit selector the bit selector at the outpu t of the interpolation filter selects which 16 bits of the 38 - bit fir filter accumulator are passed to the fol lowing upsample and hold stage. second upsample and hold the second upsampler includes a zero - order hold function, so for an upsample factor of l 2 (= f ct3 /f ct2 ) there are l2 - 1 repeated sample values inserted after each sample value from the bit selector. this upsampling process results in unwanted spectral images at multiples of the ct2 frequency, but these lie near the nulls in transfer function of the zero - order hold so they are usefully attenuated . the transfer function of the zero - order hold is h(z)=(1 - z - l 2 )/(z - 1) , where the sample period t=1/f ct2 . this transfer function also causes droop in the wanted signal, but if the ct2 clock rate is high enough this can be made insignificant. if necessary, droop compensation can be performed in the preceding fir interpolation filter. the second upsample factor can be set to any value up to 32. sigma - delta modulator and reconstruction filter the sigma - delt a modulator is a 2 nd - order type whose output has a characteristic high - pass filtered noise profile, with the quantisation noise rising at 12db per octave. the reconstruction filter attenuates this quantisation noise, along with any spectral remnants from t he upsamplers. the reconstruction filter comprises a linear - phase switched capacitor filter (with a selectable bandwidth) followed by a linear - phase continuous time filter . these have the following nominal transfer characteristics , with a sample period t=1 /f ct3 : switched capacitor section: c ontinuous time section : with a sigma - delta clock frequency of 2.4mhz, the switched capacitor section has a - 3db cutoff frequency of approximately 12.2khz (low b/w) or 23.9khz (high b/w). the continuous time filter has a - 3db cutoff frequency of approximately 8 0k hz. output gain stage ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 1 1 1 2 1 1 1 870601 . 0 86233 . 1 1 00826662 . 0 920582 . 0 1 0794179 . 0 ) ( : bandwidth high 935301 . 0 93323 . 1 1 00206664 . 0 958649 . 0 1 0413510 . 0 ) ( : bandwidth low z z z z z h z z z z z h ? ? ? ? ? ? ? filter chip off d recommende 6 6 2 12 1 10 496 . 1 1 1 10 9780 . 1 10 8684 . 1 1 ) ( ? ? ? ? ? ? ? ? ? ? ? ? s s s s h
analogue front end (afe) for digital radio CMX983 ? the final analogue gain stage between the reconstruction filter and the tx output pins can be set to a gain of between - 11db and 11db (in 0.5db steps). a mute setting is also provided. with the gain set to 0db and with a fixed digital input of 32767 , the differential output voltage from the tx dac is approximately 0.75 a v dd . the following c - bus registers are used to config ure the transmit channels: tx_con0 - $30 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 sc high b/w dac clock divide tx_con0 b7: sc high b/w set to 1 to select the high bandwidth cutoff for the reconstruction filter switched capacitor section. set to 0 to select the low bandwidth cutoff. tx_con0 b6 - 0: dac clock divide sets the division ratio between clk and ct3, where ct3 is the clock for the sigma - delta modulator and r econstruction filter. this value can be set to between 2 and 128 (0000000 = 128). tx_con1 - $31 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 nd upsample rate 1 st stage bypass interpolation filter length 1 st upsample rate tx_con1 b15 - 11: second upsample rate sets the division ratio between the ct3 and ct2 clock, which determines the second upsample rate l2. this can be set to between 1 and 32 (00000 = 32). tx_con1 b10: first stage bypass set this bit to 1 to disable the first upsampler, interpolation filter and bit selector, and cause tx data from the serial port to be driven directly into the second upsampler. tx_con1 b9 - 3: interpolation filter length sets the number of taps in the inter polation filter to a value between 1 and 128 (0000000 = 128). this must be set to an integer multiple of the first upsample rate. the filter length is also subject to the following restriction, based on the clk and dac sample frequencies: tx_con1 b2 - 0: first upsample rate the first upsample rate can be set to any value between 1 and 8 (000 = 8). 1 2 ct ct clk f f f th filterleng ? ?
analogue front end (afe) for digital radio CMX983 ? tx_con2 - $34 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx b bit select tx b digital enable tx b analog enable fir b coeff select tx a bit select tx a digital enable tx a analog enable fir a coeff select tx_con2 b1 5 - 11: tx b bit select in tx channel b, selects which 16 bits of the 38 - bit fir filter accumulator are passed to the following upsample stage. this value determines the number of most - significant bits discarded (valid range = 0 to 22) : a value of 0 selects the most significant 16 bit s of the fir accumulator, a value of 1 discards the msb of the accumulator and selects the next most significant 16 bits, and so on. convergent rounding and saturation are applied to the selected bits. to assist with setup, an overflow causes a status bit to be set in the tx_status register. tx_con2 b10: tx b digital enable set this bit to 1 to enable the tx channel b logic, from the first upsampl er to the sigma - delta modulator, and start the transfer of data from the serial port. the channel idle status i n the tx_status register immediately goes low when the tx channel b logic is enabled . the tx b digital enable bit should be set after all other tx channel b configuration bits have been initialised. w hen the tx b digital enable bit changes from 1 to 0, the tx channel stops requesting data from the tx serial port but continues processing the buffered data (up to 2 words) until an underrun occurs. t he interpolation filter data ram is then cleared immediately ( all data samples reset to zero ) in readiness fo r the next time the channel is enabled ; the coeffici ent rams are not altered. clearing t he data samples takes 128 clk cycles , after which the channel idle status gets set to 1 . i f the tx b digital enable bit goes high while the associated tx serial port remains disabled, default data values of $0000 will be fed into the tx channel. this continues until the tx serial port becomes enabled, at which point normal data transfers through the tx serial port will commence. if the tx serial port is subsequently di sabled while the tx b digital enable bit remains high, then the tx channel will repeatedly transmit the final 16 - bit data value o btained from the tx serial port, and a buffer underrun will be flagged in tx_status . tx_con2 b9: tx b analogue enable set this bit to 1 to enable the tx channel b reconstruction filter and output gain stage. normally the analogue enable would be activated in advance of the digital enable and deactivated after all data in a transmission has been processed. tx_con2 b8: fir b coeff icient select selects which coefficients the channel b interpolation filter uses: 0 = tx_coeff0 1 = tx_coeff1 tx_con2 b 7 - 3: tx a bit select similar in operation to bits 15 - 11 . tx_con2 b2: tx a digital enable set this bit to 1 to enable the tx channel a logic, similar in operation to bit 10. tx_con2 b1: tx a analogue enable
analogue front end (afe) for digital radio CMX983 ? set this bit to 1 to enable the tx channel a reconstruction filter and output gain stage , similar in operation to bit 9 . tx_con2 b0: fir a coefficient select selects which coefficients the channel a interpolation filter uses: 0 = tx_coeff0 1 = tx_coeff1 tx_gain - $35 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 tx b clamp tx b gain 0 tx a clamp tx a gain tx_gain b15: reserved, set to 0 tx_gain b14: tx b clamp when the tx analog is disabled (tx_con2 bit 9 = 0), this bit controls what happens to the dac output pins q txp and q txn: when the tx b clamp bit is set to 1 the n q txp and q txn get clamped to a mid - rail reference voltage a v dd /2; otherwise, qtxp and qtxn will become high impedance (greater than 1 00k ? ). tx_gain b13 - 8: tx b gain set channel b output gain to between - 11db and +11db in 0.5db steps, or mute the output. the gain setting is in 2s complement format with an implicit binary point between bit 9 and 8: 100000 = mute 101010 = - 11.0db 101011 = - 10.5db 101100 = - 10.0db ... 111110 = - 1.0db 111111 = - 0.5db 000000 = 0.0db 000001 = 0.5db 000010 = 1.0db ... 010100 = 10.0db 010101 = 10.5db 010110 = 11.0db tx_gain b7: reserved, set to 0 tx_gain b 6 : tx a clamp controls itxp and itxn clamp level, similar in operation to bit 14. tx_gain b5 - 0: tx a gain set channel a output gain, similar in operation to bits 13 - 8.
analogue front end (afe) for digital radio CMX983 ? tx_coeff0 - $36 : 16 - bit write, data - streaming tx_coeff1 - $37 : 16 - bit write, data - streaming reset value = undefined bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fir coefficient values (2s complement) these two c - bus locations allow the 128 - word fir coefficient rams for tx channel a and b to be loaded. each coefficient ram can be loaded in ascending order by repeatedly writing data to the same c - bus location (an internal address pointer automatically in crements after each write). to increase the loading rate of the coefficients, data - streaming operation is supported for these two c - bus addresses. only as many coefficients as are required (determined by the fir length) need to be loaded into each ram, unu sed ram locations do not need to be written. the length of the interpolation filter, set in tx _con2, must be an integer multiple of the first upsample rate l1. because of the way the interpolation filter is implemented, the coefficients must be scrambled before loading as demonstrated in the following code example: // initialise array of coefficients int coefficient[filter_length] = {0x0002, 0x0031, 0xffa3, ...}; // initialise pointer cbus_write_8bits( tx_addr, 0x00); // load coefficients into CMX983 for (i = 0; i < upsample_rate1; i++) for (j = 0; j < filter_length; j += upsample_rate1) cbus_write_16bits( tx_coeff 0 , coefficient[i + j]); for instance, if the first upsample ratio is set to 5 and the filter length is set to 60, the coefficients c0..c59 would be loaded in the following sequence. note that c0 is the coefficient that is multiplied by the most recent data sample from the first upsampler: c0, c5, c10, c50, c55, c1, c6, c11, c51, c56, c2, c7, c12, c52, c 57, c3, c8, c13, c53, c58, c4, c9, c14, c54, c59 before loading either of the two coefficient rams, the internal address pointer needs to be initialised (usually to address 0); this is done by writing to register tx_addr. note that both coefficient r ams share this address pointer, so the address needs to be initialised before each coefficient ram is loaded. tx_addr - $38 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 tx coefficient address pointer the tx coefficient address pointer determines the address at which data gets written during a c - bus write to either of the tx coefficient rams. the tx coefficient address pointer automatically increments
analogue front end (afe) for digital radio CMX983 ? after each 16 - bit coefficient value is written, so if the coefficients are written in an ascending sequence the pointer only needs to be initialised once before each coefficient ram is loaded. tx_status - $3 9 : 8 - bit read reset value = $ 11 bit: 7 6 5 4 3 2 1 0 0 ch. b bitsel over - flow ch. b buffer under - run ch. b idle 0 ch. a bitsel over - flow ch. a buffer under - run ch. a idle tx_status b7: reserved, set to 0 tx_status b 6 : channel b bit selector overflow this bit gets set to 1 when the channel b bit selector output value saturates to maximum positive ($7fff) or maximum negative ($8000). this bit gets cleared only when tx_status is read. tx_status b 5 : channel b buffer underrun this bit gets set to 1 whenever tx channel b runs out of data from the serial port, for instance if the tx serial port gets dis abled or is configured to run too slowly. when this happens, the tx channel will retransmit the previous data sample. the buffer underrun bit gets cleared only when tx_status is read. tx_status b 4 : channel b idle this bit is a level sensitive signal that is set to 1 whenever channel b is in the idle state. tx_status b3: reserved, set to 0 tx_status b 2 - 0: ( channel a status bits) similar in operation to bits 6 - 4. tx_st_enab - $3a : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 tx status enable (channel b) 0 tx status enable (channel a) tx_st_enab b7, b3 : reserved, set to 0 tx_st_enab b6 - 4, b2 - 0: tx status enable if any of these bits is high while the corresponding bit in the tx_status register is also high, then the tx status bit (in status register bit 0) gets set to 1 .
analogue front end (afe) for digital radio CMX983 ? 11 serial ports 11.1 rx serial port figure 15 rx serial port data fro m rx channel a and b are output from the CMX983 through a pcm serial port ( figure 15 ). pcm data is sent in short frame sync mode with the CMX983 acting as a master. the pcm clock rxclk is divided down from the system clock clk, and data transmission is most significant bit first. if both rx channel a and b are selected, the two 16 - bit data words are multiplexed t hrough a single output data pin rxd as shown in figure 16 . if only one of the two rx channels is selected, then the 16 - bit serial port shift register for the disabled channel is bypassed and only the data for the selected channel is shifted out (example shown in figure 17 ) . figure 16 rx port timing (channel a and b both selected ) r x d r x f s r x c l k 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 0 5 4 3 2 1 c h a n n e l a d a t a 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 0 5 4 3 2 1 c h a n n e l b d a t a 1 5 1 4 1 3 t c y c _ r x f s t c y c _ r x c l k
analogue front end (afe) for digital radio CMX983 ? figure 17 rx port timing (channel b only selected) r x d r x f s r x c l k 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 0 5 4 3 2 1 c h a n n e l b d a t a 1 5 1 4 1 3 t c y c _ r x f s t c y c _ r x c l k
analogue front end (afe) for digital radio CMX983 ? the following c - bus registers are used to configure the rx serial port: rxport_con0 - $40 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 rxclk divide value rxport_con0 b7 - 0: rxclk divide value sets the division ratio between clk and rxclk. this value can be set to between 2 and 256 (00000000 = 256). rxclk has a nominal 50:50 duty cycle, and its frequency must be at least 32 times greater than f cr3 (the frequency of the rx channel second downsample clock, section 9.2 ); back - to - back data frames are allowed. note: to avoid jitter on the rxfs signal, the frequency ratio f rxclk / f cr3 must be an integer. rxport_con1 - $41 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 0 0 chan. b data select chan. a data select rxd hi - z rx port enable invert rx - clk rxport_con1 b7 - 5: reserved, set to 0 rxport_con1 b4: channel b data select set to 1 to cause the 16 - bit channel b data to be output on the rxd pin. set to 0 to prevent channel b data from being output on the rxd pin (this bypasses the 16 - bit channel b shift register). rxport_con1 b3: channel a data select set to 1 to cause the 16 - bit channel a data to be output on the rxd pin. set to 0 to preven t channel a data from being output on the rxd pin (this bypasses the 16 - bit channel a shift register). rxport_con1 b2: rxd hi - z set to 1 to cause the rxd pin to go high impedance between data packets. set to 0 to cause the rxd pin to be driven low between data packets. rxport_con1 b1: rx port enable set to 1 to enable the rx serial port and start the rxclk pin oscillating. the frame sync pulse rxfs will only be generated when the rx serial port is enabled, and the rx channel(s) are enabled. set to 0 to d isable the rx serial port and drive rxclk low. when the rx serial port is disabled, data samples generated by the rx channels will be discarded. if the rx port enable bit changes from 1 to 0 during a data frame, the frame will complete before the rxclk pin stops oscillating. rxport_con1 b0: invert rxclk set this bit to 1 to invert the rxclk signal. this bit should not be changed if the rx port enable bit has already been set to 1.
analogue front end (afe) for digital radio CMX983 ? 11.2 tx serial port figure 18 tx serial port dat a for tx channel a and b are input to the CMX983 through a pcm serial port ( figure 18 ). pcm data is sent in short frame sync mode with th e CMX983 acting as a master. the pcm clock txclk is divided down from the system clock clk, and data transmission is most significant bit first. if both tx channel a and b are selected, the two 16 - bit data words are multiplexed through a single input data pin txd as shown in figure 19 . if only one of the two tx channels is selected, then the 16 - bit serial port shift register for the disabled channel is bypassed and only the dat a for the selected channel is shifted in (example shown in figure 20 ) . figure 19 tx port timing (channel a and b both selected) t x d t x f s t x c l k 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 0 5 4 3 2 1 c h a n n e l a d a t a 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 0 5 4 3 2 1 c h a n n e l b d a t a 1 5 1 4 1 3 t c y c _ t x f s t c y c _ t x c l k t x d t x f s t x c l k 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 0 5 4 3 2 1 c h a n n e l b d a t a 1 5 1 4 1 3 t c y c _ t x f s t c y c _ t x c l k
analogue front end (afe) for digital radio CMX983 ? figure 20 tx port timing (channel b only selected) the following c - bus registers are used to configure the tx serial port: txport_con0 - $4 8 : 8 - bit write - only reset value = $00 bit: 7 6 5 4 3 2 1 0 txclk divide value txport_con0 b7 - 0: txclk divide value sets the division ratio between clk and txclk. this value can be set to between 2 and 256 (00000000 = 256). txclk has a nominal 50:50 duty cycle, and its frequency must be at least 32 times greater than f ct1 (the frequ ency of the tx channel first upsample clock, section 10 ); back - to - back data frames are allowed. note: to avoid jitter on the txfs signal, the frequency ratio f txcl k / f ct1 must be an integer. txport_con1 - $49 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 0 0 0 chan. b data select chan. a data select tx port enable invert tx - clk txport_con1 b7 - 4: reserved, set to 0 txport_con1 b3: channel b data select set to 1 to cause the 16 - bit channel b data to be input on the txd pin. set to 0 to prevent channel b data from being input on the txd pin (this bypasses the 16 - bit channel b shift register). txport_con1 b2: channel a data select set to 1 to cause the 16 - bit channel a data to be input on the txd pin. set to 0 to prevent channel a data from being input on the txd pin (this bypasses the 16 - bit channel a shift register). txport_con1 b1: tx port enable set to 1 to enable the tx serial port and start the txclk pin oscillating. the frame sync pulse txfs will only be generated when the tx serial port is enabled, and the tx channel(s) are enabled. set to 0 to disable the tx serial port and drive txclk low. if the tx port enab le bit changes from 1 to 0 during a data frame, the frame will complete before the txclk pin stops oscillating. txport_con1 b0: invert txclk set this bit to 1 to invert the txclk signal. this bit should not be changed if the tx port enable bit has already been set to 1.
analogue front end (afe) for digital radio CMX983 ? 12 fractional - n frequency synthesizers figure 21 fractional - n frequency synthesizer the CMX983 has two identical, independently programmable, 2.1 ghz fractional - n frequency synthesizers; a block diagram of one of the synthesizers is shown in figure 21 . n ote that a single ended vco signal can be used; if so, it should be ac - coupled to rf1p and the capacitor connected to rf1n should be grounded. the synthesizers use a sigma - delta modulation technique that allows use of a high reference frequency, thus providing rapid frequency switching and low phase noise performance. the 24 - bit fractional divider resolution provides an ultra - fine step size for narrowband applications, and can be used to co mpensate for crystal oscillator frequency drift or doppler shift. a fast locking mechanism is provided that increases the transition rate when changing to a new operating frequency. this is done by temporarily modifying the loop filter characteristics and charge pump gain whenever the main divider settings are updated, allowing the responsiveness of the closed loop system to be increased without compromising the loop stability. the fast lock mode automatically turns off after a predetermined delay, thus re verting the pll to its standard, low noise mode of operation. each synthesizer has a programmable lock detector circuit that indicates when the loop is in lock. the lock detector s can be configured for analogue or digital operation, and no external compon ents are required . m c l k p h a s e d e t e c t o r c h a r g e p u m p m u l t i - m o d u l u s d i v i d e r ( 3 2 2 0 4 7 ) - m o d 1 6 / 2 4 b i t p r b s p l l 1 _ f d i v 0 p l l 1 _ i d i v p l l 1 _ r d i v r e f d i v i d e r ( 1 1 2 8 ) p l l 1 _ l o c k d e t v c o p l l 1 _ f l c k f a s t l o c k t i m e r c l k f a s t l o c k c o n t r o l d i v i d e r u p d a t e f l c k 1 r f 1 n r f 1 p c p 1 c p 1 v d d d i t h e r p l l 1 _ s t a t u s l o c k d e t e c t o r p l l 1 l o c k s t a t u s p l l 1 _ c o n p l l 1 _ f d i v 1 p l l 1 _ b l e e d b l e e d c u r r e n t r 2 r 3 c 2 c 3 c 1 r 1 g r o u n d c a p a c i t o r o n r f 1 n i f v c o o u t p u t i s s i n g l e - e n d e d p l l 1 _ c f g
analogue front end (afe) for digital radio CMX983 ? the pll synthesizer s are configured through a number of c - bus registers. the registers for pll1 and p ll2 operate in an identical way: pll1_con - $ 4e ; 16 - bit write pll2_con - $ 57 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 resol - ution mode select enab dither 0 enab pll inv. cp in - lock status enab out - of - lock status enab lock status edge trigger charge pump current pll1[2]_con b15: reserved, set to 0 pll1[2]_con b14: resolution set this bit to 0 to select a 24 - bit fractional value for the main divider (using registers pll1[2]_fdiv1 and pll1[2]_fdiv0). set this bit to 1 to select a 16 - bit fractional value for the main divider (using register pll1[2]_fdiv0 only). pll1[2]_con b13 - 1 1: mode select sets the main divider operating mode: 000 integer mode (sigma - delta disabled) 001 fractional - n divider with 3 rd order modulator 110 fractional - n divider with alternative 3 rd order modulator other values should not be used. the two types of fractional - n modulator offer different noise characteristics. the type 110 generally has the best close - in noise (characterised by 1 hz normalised phase noise), whereas the type 001 has lower sigma - delta noise at offset around 1 mhz. note: the exact c haracteristics of the pll noise will depend on the overall pll design including the vco gain and loop filter. pll1[2]_con b10: enable dither set this bit to 1 to a dd a dither to the lsb of the fractional divide value. this helps to suppress idle tones f rom the sigma - delta modulator output. set this bit to 0 to disable the dither. pll1[2]_con b8: enable pll set to 1 to enable the pll circuit ( sigma - delta modulator, multi - modulus divider, reference divider, phase detector and charge pump). set to 0 to disable and powersave the pll circuit. pll1[2]_con b7: invert charge pump with this bit set to 0 the charge pump will sink current when the main divider out put frequency f main is a higher frequency than the reference clock f ref . set this bit to 1 to invert the charge pump output, so that it sources current when f main > f ref . pll1[2]_con b6: in - l ock status enable set to 1 to allow the in - lock status bit in th e pll1[2]_status register to be set when lock is detected . the i n - lock status bit can either be edge - triggered or level - triggered, depending on the state of pll1[2]_con bit 4. pll1[2]_con b5: out - of - lock status enable
analogue front end (afe) for digital radio CMX983 ? set to 1 to allow the out - of - lock status bit in the pll1[2]_status register to be set when lock is lost . the out - of - lock status bit can either be edge - triggered or level - triggered, depending on the state of pll1[2]_con bit 4. pll1[2]_con b4: lock status edge trigger when this bit is set to 1, the in - lock status bit and out - of - lock status bit ( pll1[2]_status bits 1 - 0) will be edge triggered. this means that the in - lock status bit gets set each time the lock signal transitions from 0 to 1, and the out - of - lock status bit gets set each time the lock signal transitions from 1 to 0. when this bit is set to 0, the in - lock status bit and out - of - lock status bit ( pll1[2]_status bits 1 - 0) will be level triggered. this means that t he in - lock status bit will be continuously set hi gh as lo ng as lock = 1 and pll1[2]_con bit 6 = 1, and the out - of - lock status bit will be continuously set high as long as lock = 0 and pll1[2]_con bit 5 = 1. pll1[2]_con b3 - 0: charge pump current sets the value of the charge pump output current pulses. the value can be set in increments of 25a , from 25a (0000) to 400a (1111). pll_cfg - $ce: 16 - bit write reset value = $2000 all bits in this register should be cleared to zero for optimum performance. pll1_ lockdet - $ 4f : 16 - bit write pll2_ lockdet - $5 8 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lock detect enab lock mode reset lock analogue configuration bits: 0 0 0 0 0 lock discharge rate lock charge rate d igital configuration bits: loss - of - lock window lock window loss - of - lock threshold lock threshold pll1[2]_ lockdet b15: lock detect enable set this bit to 1 to enable the lock detector circuit. set this bit to 0 to disable and powersave the lock detector circuit. pll1[2]_ lockdet b14: lock mode set this bit to 1 to use the analogue lock detector. set this bit to 0 to use the digital lock detector. pll1[2]_ lockdet b13: reset lock writing a 1 to this bit generates a short pulse that resets the lock detector (either an alogue or digital) to an out - of - lock conditi on and clears pll1[2]_status bits 1 - 0. immediately after writing a 1 to the reset lock bit, it is cleared back to 0 and the lock detector and lock status bits resume normal operation. analogue configuration bits
analogue front end (afe) for digital radio CMX983 ? these bits are active wh en pll1[2]_ lockdet bit 14 = 1: pll1[2]_ lockdet b12 - 8: reserved, set to 0 pll1[2]_ lockdet b7 - 4 : lock discharge rate these bits control the discharge rate of the analogue lock detector capacitor , which determine s the time taken for the lock signal to go inactive when lock is lost. the discharge rate is specified as a multiple of the selected charge rate (see bits 3 - 0) . pll1[2]_ lockdet bits 7 - 4 discharge rate pll1[2]_ lockdet bits 7 - 4 discharge rate $0 5 x charge rate $8 100 x charge rate $1 7 x charge rate $9 150 x charge rate $2 10 x charge rate $a 200 x charge rate $3 15 x charge rate $b 300 x charge rate $4 20 x charge rate $c 500 x charge rate $5 30 x charge rate $d - $f d o not use $6 50 x charge rate $7 70 x charge rate pll1[2]_ lockdet b3 - 0: lock charge rate these bits control the charge rate of the analogue lock - detector capacitor, and so determine the time taken for the lock signal to become active when the phase detector inputs are in phase. the nominal time taken for the capacitor to fully charge from a reset state, assuming no discharge pulses occur, is shown below: pll1[2]_ lockdet bits 3 - 0 charge time pll1[2]_ lockdet bits 3 - 0 charge time $0 5 s $8 100 s $1 7 s $9 150 s $2 10 s $a 200 s $3 15 s $b 300 s $4 20 s $c 500 s $5 30 s $d 700 s $6 50 s $e 1 ms $7 70 s $f d o not use digital configuration bits these bits are active when pll1[2]_ lockdet bit 14 = 0: pll1[2]_ lockdet b12 - 1 1 : loss - of - lock window while the loss - of - lock counter is active (i.e. lock = 1), these bits determine the phase detector error window: if the difference in arrival time of the phase detector inputs is outside this window, they are deemed to be out of phase. when enough consecu tive out of phase pulses occur (determined by pll1[2]_ lockdet bits 7 - 5 ) then the lock signal gets set to 0 . the loss - of - lock window is specified as a multiple of the lock window value, which in turn is determined by pll1[2]_ lockdet bits 10 - 8. pll1[2]_ lockdet bits 12 - 11 loss - of - lock window
analogue front end (afe) for digital radio CMX983 ? 00 1 .0 lock window 01 1.5 lock window 10 2 .0 lock window 11 illegal, do not use pll1[2]_ lockdet b 10 - 8 : lock window while the lock counter is active (i.e. lock = 0) , these bits determine the phase detector error window : if the difference in arrival time of the phase detector inputs is within this window, they are deemed to be in phase. when sufficient consecutive in phase pulses occur (determined by pll1[2]_ lockdet bits 4 - 0) then the lock signal gets se t to 1. the nominal value of the error window is shown in the following table: pll1[2]_ lockdet bits 10 - 8 lock window pll1[2]_ lockdet bits 10 - 8 lock window $0 7 ns $4 30 ns $1 10 ns $5 50 ns $2 15 ns $6 70 ns $3 20 ns $7 100 ns pll1[2] _lockdet b 7 - 5 : loss - of - lock threshold while the lock indicator is active (lock = 1), these bits determine how many consecutive out of phase signals must occur at the phase detector before loss - of - lock is detected, causing the lock indicator to go inactive (lock = 0). the loss - of - lock threshold can be set to between 1 and 8 (000 = 8). pll1[2] _lockdet b 4 - 0 : lock threshold while the lock indicator is inactive (lock = 0), these bits determine how many consecutive in phase signals must occur at the phase detector before lock is detected, causing the lock indicator to go active (lock = 1). the lock threshold can be set to between 1 and 32 (00000 = 32). pll1_flck - $5 0 : 16 - bit writ e pll2_flck - $59 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 enab fastlck fastlock timer coarse divide fastlock timer fine divide fastlock current pll1[2]_flck b15 - 13 : reserved, set to 0 pll1[2]_flck b1 2 : enable fastlock set to 1 to enable fastlock. then each time the main divider registers are updated , the associated fastlock pin (flck1 or flck2) is pulled to ground, the charge pump current changes to the value set by pll1[2]_flck bits 1 - 0, and the fastlock timer is started. the fastlock state continues until the timer exp ires, at which point the fastlock pin returns to a high impedance state and the charge pump current reverts to the value determined by pll1[2]_con bits 3 - 0. pll1[2]_flck b1 1 - 9 : fastlock timer coarse divide pll1[2]_flck b 8 - 2 : fastlock timer fine divide
analogue front end (afe) for digital radio CMX983 ? these bits control the duration of the fastlock mode. the coarse divide can be set to a value between 0 and 7, and the fine divide can be set to between 1 and 128 (0000000 = 128). the fastlock timer is clocked by the internal system clock clk, and its peri od is given by the following expression: pll1[2]_ flck b1 - 0: fastlock current sets the value of the charge pump output current pulses in fastlock mode. the value is set as a multiple of the nominal charge pump current: pll1[2]_flck bits 1 - 0 charge pump current multiplier m 00 4x 01 8x 10 12x 11 16x to maintain loop stability with fastlock active the resistor r1 shown in figure 21 will typically need to be set to the following value: ? 1 ? 2 ? ? 1 with fastlock active, the pll lock time is decreased by a factor of approximately ? . in practice, an even greater reduction is often achieved because fastlock can reduce or eliminate cycle slipping in the phase detector. pll1_bleed - $51: 8 - bit write pll2_bleed - $5a: 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 0 enab bleed bleed coarse bleed fine these registers can be used to add a bleed current to the charge pump output of the plls. the bleed current adds a phase shift to the pll loop and can help reduce spurious products associated with the sigma - delta modulator by oper ating the charge pump in a more linear region. excessive bleed current should be avoided because it can increase the pll reference spurs and phase noise. a good initial compromise is to set the phase shift to about four vco cycles: ? ????? 4 ? ???? ? ?? ? ???? ? ??? where r div is the reference divider value and i cp is the charge pump current setting. this bleed current value can then be adjusted to optimise performance. any leakage current from external components on the cp1 or cp2 pins must als o be considered as this will alter the effective bleed current. pll1[2]_bleed b7 - 6: reserved, set to 0 pll1[2]_bleed b5: enable bleed set to 1 to enable a constant bleed current to be sourced into the associated charge pump output pin. clk de coarsedivi fastlock f finedivide t ? ? 4
analogue front end (afe) for digital radio CMX983 ? pll1[2]_bleed b4 - 2: bleed current (coarse) pll1[2]_bleed b1 - 0: bleed current (fine) these bits control the nominal bleed current sourced into the charge pump output pin, according to the following formula: the bleed current can therefore be set to a value within the range 0.5 a 112 a. for instance, if pll1[2]_bleed bits 4 - 2 = 101 2 and pll1[2]_bleed bits 1 - 0 = 11 2 , the resulting nominal bleed current will be 0.5 a 2 5 1.75 = 28 a. note that during fastlock, the bleed current is scaled up in the same proportion as the main charge pump current, as determined by pll1[2]_flck bits 1 - 0. pll1_rdiv - $52 : 8 - bit write pll2_rdiv - $5 b : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 reference divider pll1[2]_rdiv b7: reserved, set to 0 pll1[2]_rdiv b6 - 0: sets the division ratio between the master clock mclk and the pll reference clock. this value can be set to between 1 and 128 (00 00000 = 128). pll1_idiv - $53 : 16 - bit write pll2_idiv - $5 c : 16 - bit write reset value = $0020 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 main divider integer value pll1[2]_idiv b15 - 11: reserved, set to 0 pll1[2]_idiv b10 - 0: main divider integer value these bits represent the integer portion closest to the desired fractional - n divider value. the integer value is combined with the fractional value from registers pll1[2]_fdiv1 and pll1[2]_fdiv0 (which represent a fractional offset of between approximately +0.5 and C 0.5) to allow selection of the desired vco frequency. the valid range for the main divider integer value is from 32 to 2047 (in integer - n mode), or from 36 to 2043 (in fractional - n mode). pll1_fdiv0 - $54 : 16 - bit write pll2_fdiv0 - $5 d : 16 - bi t write reset value = $0000 ? ? ? ? ? ? ? ? ? ? 4 _ 1 2 5 . 0 _ fine bleed a i coarse bleed bleed ?
analogue front end (afe) for digital radio CMX983 ? bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 main divider fractional value (lsb) pll1_fdiv1 - $55 : 8 - bit write pll2_fdiv1 - $5 e : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 main divider fractional value (msb) pll1[ 2]_fdiv0 b15 - 0: main divider fractional value (lsb) pll1[2]_fdiv1 b7 - 0: main divider fractional value (msb) in fractional - n mode, the fractional divide value ranges between approximately C 0.5 and +0.5 as determined by the pll1[2]_fdiv1 and pll1[2]_fdiv0 re gisters: with fractional resolution set to 24 bits, the registers are concatenated to form a 24 - bit 2s complement number fdiv . the resulting fractional divide value is equal to (fdiv ? 2 24 ), which is in the range C 0.5 to +0.49999994 with fractional resolution set to 16 bits, the pll1[2]_fdiv1 register is ignored and the value in the pll1[2]_fdiv0 register is treated as a 16 - bit 2s complement number fdiv . the fractional divide value is equal to (fdiv ? 2 16 ), which is in the range C 0.5 to +0.49998474 in integer - n mode, both the pll1[2]_fdiv1 and pll1[2]_fdiv0 registers are ignored. pll1_status - $5 6 : 8 - bit read pll2_status - $5f : 8 - bit read reset value = $00 bit: 7 6 5 4 3 2 1 0 lock 0 0 0 0 0 in - lock status out - of - lock status pll1[2]_status b7: lock this bit shows the current state of the lock detector output: lock = 1 indicates in lock, and lock = 0 indicates out of lock. this bit can be polled by the host processor. pll1[2]_status b6 - 2: reserved, set to 0 pll1[2]_status b1: in - lock status to enable this status bit, the in - lock status enable bit (pll1[2] _con bit 6) must be set to 1. the in - lock status bit can be either edge triggered or level triggered, depending on the state of pll1[2] _con bit 4. when configured as edge triggered, the in - lock status bit gets set high after each 0 to 1 transition of the lock signal, and gets cleared when the pll1[2]_status register is read. when configured as level triggered, the in - lock status bit gets continuously set high as long as lock = 1 and pll1[2] _con bit 6 = 1 , and gets cleared when the pll1[2]_status register is read and either lock = 0 or pll1[2] _con bit 6 = 0 . note: the i n - lock status bit is also cleared to 0 when a reset lock operation is performed (see d escription of pll1[2]_lockdet bit 13).
analogue front end (afe) for digital radio CMX983 ? pll1[2]_status b 0 : out - of - lock status to enable this status bit, the out - of - lock status enable bit (pll1[2] _con bit 5 ) must be set to 1. the out - of - lock status bit can be either edge triggered or level triggered, dep ending on the state of pll1[2] _con bit 4. when configured as edge triggered, the out - of - lock status bit gets set high after each 1 to 0 transition of the lock signal, and gets cleared when the pll1[2]_status register is read. when configured as level trigg ered, the out - of - lock status bit gets continuously set high as long as lock = 0 and pll1[2] _con bit 5 = 1 , and gets cleared when the pll1[2]_status register is read and either lock = 1 or pll1[2] _con bit 5 = 0 . note: the out - of - lock status bit is also clea red to 0 when a reset lock operation is performed (see description of pll1[2]_lockdet bit 13). the in - lock status (bit 1) and the out - of - lock status ( bit 0) are ored to gether and the resulting signal is passed to the main status register (section 6.4 ). this can be used to generate an interrupt signal. 12.1 register loading order to use the pll1 synthesiser, the registers must be loaded in the order specified b elow. similar rules apply to pll2. registers pll1_con, pll1_lockdet, pll1_flck and pll1_rdiv should be initialised before the main divider registers are loaded for the first time. the pll enable bit (pll1_con bit 8) should be set during this process to po wer up the synthesizer circuit, but the charge pump output will remain in a high impedance state until the main divider registers are loaded. after the main divider registers are loaded in the correct order (which depends on the operating mode), the pll s ynthesizer begins operating. the main divider registers can be changed at any subsequent time, but must always be updated in the specified order: integer - n mode: load pll1_idiv with the desired value, at which point the new divide ratio will take effect. fractional - n mode, 16 - bit fractional resolution: load pll1_idiv (if necessary), then load pll1_fdiv0. the new divide ratio only takes effect when pll1_fdiv0 is loaded. fractional - n mode, 24 - bit fractional resolution: load pll1_idiv and pll1_fdiv1 (if nec essary), then load pll1_fdiv0. the new divide ratio only takes effect when pll1_fdiv0 is loaded. each time the main divide registers are updated, at the point when the new divide ratio takes effect, a fastlock sequence in the associated pll is triggered (if enabled). 12.2 fractional - n programming examples e xample 1: to operate pll1 in 16 - bit fractional mode (modulator type 001) with a vco frequency f vco = 803.125mhz, a master clock frequency f mclk = 19.2mhz, and a pll comparison frequency f ref = 2.4mhz. rd iv = f mclk f ref = 19.2mhz 2.4mhz = 8 ndiv = f vco f ref = 803.125mhz 2.4mhz = 334.6354167
analogue front end (afe) for digital radio CMX983 ? split the n divider value into integer and fractional parts: idiv = round(334.6354167) = 335 (decimal) = 0x014f (hex) fdiv (16 - bit mode) = round(2 16 ( ndiv C idiv)) = - 23893 (decimal) = 0xa2ab (hex) load c - bus registers: pll1_con bit 14 = 1 (16 - bit), bit 13 - 11 = 00 1 , bit 8 = 1 (enable), set other bits as desired set pll1_lockdet and pll1_flck as desired pll1_rdiv = 0x08 pll1_idiv = 0x014f pll1_fdi v0 = 0xa2ab at this point, the charge pump is enabled and pll1 begins to acquire lock. there is no need to load pll1_fdiv1 in 16 - bit mode. the frequency step size in this example is 2.4mhz 2 16 36.621hz. e xample 2: to operate pll2 in 24 - bit fractiona l mode (modulator type 110) with a vco frequency f vco = 1721.386mhz, a master clock frequency f mclk = 20.736mhz, and a pll comparison frequency f ref = 1.728mhz. rdiv = f mclk f ref = 20.736mhz 1.728mhz = 12 (decimal) = 0x0c (hex) ndiv = f vco f ref = 1721.386mhz 1.728mhz = 996.1724537 split the n divider value into integer and fractional parts: idiv = round(996.1724537) = 996 (decimal) = 0x03e4 (hex) fdiv (24 - bit mode) = round(2 24 ( ndiv C idiv)) = 2893293 (decimal) = 0x2c25ed (hex) load c - bus registers: pll2_con bit 14 = 0 (24 - bit), bit 13 - 11 = 1 10 , bit 8 = 1 (enable), set other bits as desired set pll2_lockdet and pll2_flck as desired pll2_rdiv = 0x0c pll2_idiv = 0x03e4 pll2_fdiv1 = 0x2c pll2_fdiv0 = 0x25ed at this point, the cha rge pump is enabled and pll 2 begins to acquire lock. the frequency step size in this example is 1.728mhz 2 24 0.103hz. note: if the calculated fractional part of ndiv is exactly equal to 0.5 then the idiv value should be rounded up. for example, if ndi v = 312.5000 then idiv = round(ndiv) = 313. 12.3 lock detector configuration guidelines the CMX983 fractional - n pll synthesizers each contain an analogue lock detector and a digital lock detector. both types of lock detector use th e phase error in the pll loop to determine whether the pll is in
analogue front end (afe) for digital radio CMX983 ? lock. the user can select the type of lock detector that works best in their particular application. the following guidelines describe how the lock detectors in pll1 operate; the lock detecto rs in pll2 are identical. 12.3.1 digital lock detector digital lock detector mode is selected when pll1_lockdet bit 14 = 0. the digital lock detector is connected to the r - divider and n - divider output clocks as shown in figure 22 . the pll phase error is measured as the time difference between the positive edges of those clock signals. if the phase error is within the specified error window then an in_phase pulse is generated, otherwise an out_of_phase pulse is generated. the number of consecutive in_phase and out_of_phase pulses is accumulated and is used to determine the state of the lock output. figure 22 digital lock detector typical r - divider and n - divider output waveforms are shown in figure 23 , along with the state transition diagram of the lock detector. the lo ck signal goes active after a number of consecutive in_phase pulses are received by the control logic, defined by the lock threshold (pll1_lockdet bits 4 - 0); the lock signal subsequently goes inactive after a number of consecutive out_of_phase pulses a re received, defined by the loss - of - lock threshold (pll1_lockdet bits 7 - 5). note that when the pll is out of lock (lock = 0), the error window width is set by the lock window value in pll1_lockdet bits 10 - 8; when the pll is in lock (lock = 1), the error window width is increased by the loss - of - lock multiplier in pll1_lockdet bits 12 - 11.the lock status is communicated to the host c through the pll1_status register. d i g i t a l l o c k d e t e c t o r m e a s u r e p h a s e e r r o r p l l 1 _ l o c k d e t c o n t r o l c o u n t e r i n c r s t o u t _ o f _ p h a s e i n _ p h a s e l o c k c o u n t u p d o w n c h a r g e p u m p c p 1 p l l 1 _ b l e e d p h a s e d e t e c t o r p l l 1 _ i d i v p l l 1 _ r d i v r - d i v i d e r n - d i v i d e r m c l k v c o _ c l k - m o d + p l l 1 _ f d i v 1 / 0 r d q 1 r d q 1 d e l a y p d c l k _ r p d c l k _ n
analogue front end (afe) for digital radio CMX983 ? figure 23 digital lock detector s tate transitions in fractional - n mode the position of the n - divider edge varies by up to 4 cycles of the vco clock due to the action of the sigma - delta modulator, and has an extra offset of up to 0.5 cycles depending on the fractional division value in pll1_fdiv1/0. the effect of applying a bleed current is also shown in figure 23 ; this increases the phase error as the pll feedback loop compensates for the extra char ge added on each phase detector cycle. any leakage current on the cp1 pin adds a further shift C the source of this leakage current may be the on - chip current sources in the charge pump, or the off - chip loop filter or vco components. the total amount of sh ift caused by the bleed and leakage current is given by ? ?????? ? ? ??? ( ? ????? + ? ??????? ) ? ???? ? ?? 1 (units are amps, hertz, seconds) where r div is the mclk division value set by pll1_rdiv, i leakage is the leakage current being sourced into the cp1 pin and i cp1 is the charge pump current setting. when configuring the digital lock detector the selected lock window width must be large enough to encompass the maximum expected phase error, with sufficien t margin to give reliable lock detector operation in the presence of noise. a good starting point is to set the lock window approximately 50% larger than the maximum expected phase error: ???? ??????? 1 . 5 ( 4 . 5 ? ??? + | ? ?????? | ) the digital lo ck detector performance can be further optimised by adjusting the lock threshold and loss - of - lock threshold in pll1_lockdet bits 7 - 0. setting these thresholds to larger values makes the lock signal less liable to glitch as the pll acquires lock and less se nsitive to noise when in lock, but less responsive if the pll loses lock. 12.3.2 analogue lock detector analogue lock detector mode is selected when pll1_lockdet bit 14 = 1. the analogue lock detector is connected to the phase detector outputs as shown in figure 24 . l o c k w i n d o w ( p l l 1 _ l o c k d e t b i t s 1 0 - 8 ) l o s s - o f - l o c k w i n d o w ( p l l 1 _ l o c k d e t b i t s 1 2 - 1 1 ) v c o c y c l e p d c l k _ r p d c l k _ n l o c k = 0 i n _ p h a s e c o u n t + + c o u n t = 0 o u t _ o f _ p h a s e c o u n t = 0 c o u n t = = l o s s - o f - l o c k t h r e s h o l d ? c o u n t = = l o c k t h r e s h o l d ? n y l o c k = 1 i n _ p h a s e o u t _ o f _ p h a s e c o u n t + + n y r e s e t s t a t e t r a n s i t i o n d i a g r a m p d c l k _ n ( n o b l e e d ) ( w i t h b l e e d ) n o m i n a l i n - l o c k p h a s e d e t e c t o r s i g n a l s t o f f s e t
analogue front end (afe) for digital radio CMX983 ? figure 24 analogue lock detector the output of the exclusive - or gate in the analogue lock detector pulses every phase detector cycle, going high on the first rising edge of the two phase detector inputs and going low on the rising edge of the other input. the duration of this pulse is a measure of the phase error of the pll loop, with a longer pulse represent ing a larger phase error. the pulse is used to control the charging and discharging of a capacitor. when the phase error signal is low the capacitor charges up, and when the phase error signal is high the capacitor discharges. when the average pll phase e rror is small enough, an overall positive current is supplied to the capacitor and its voltage increases. when the capacitor voltage eventually exceeds the upper threshold in the comparator circuit the lock output goes high, indicating that the pll is in l ock. if the pll phase error subsequently increases so that the overall current supplied to the capacitor is negative, the capacitor voltage decreases. when the capacitor voltage falls below the lower threshold in the comparator circuit the lock output goes low, indicating that lock has been lost. pll1_lockdet bits 3 - 0 control the time taken for the capacitor voltage to increase from 0v to the upper comparator threshold voltage v h , in the absence of any phase error in the pll loop. this value should be set to some multiple of the phase detector cycle time ? ? ? ???? ? ( ? ???? ? ???? ) where l is approximately the number of in phase cycles that must occur before the lock signal goes high. typically, the value of l will be set to greater than 30 in ord er to achieve reliable lock detector operation. pll1_lockdet bits 6 - 4 set the discharge rate of the capacitor, which is defined as a multiple of the charge rate. note that the discharge current is always higher than the charge current. to configure the di scharge rate the average in - lock phase error must be calculated. in the absence of any bleed or leakage current the phase error varies from cycle to cycle (in fractional - n mode) by an average of approximately 2 vco cycles. p h a s e d e t e c t o r a n a l o g u e l o c k d e t e c t o r p l l 1 _ i d i v p l l 1 _ r d i v r - d i v i d e r n - d i v i d e r m c l k v c o _ c l k - m o d + p l l 1 _ l o c k d e t l o c k u p d o w n c h a r g e p u m p c p 1 p l l 1 _ f d i v 1 / 0 r d q 1 r d q 1 d e l a y + - + - r 1 r 1 r 2 r e s e t _ l o c k c d i s c h a r g e r a t e c h a r g e r a t e 0 1 p h a s e e r r o r p d c l k _ r p d c l k _ n v h v l p l l 1 _ b l e e d p h a s e d e t e c t o r p l l 1 _ i d i v p l l 1 _ r d i v r - d i v i d e r n - d i v i d e r m c l k v c o _ c l k - m o d + p l l 1 _ f d i v 1 / 0 r d q 1 r d q 1 d e l a y p d c l k _ r p d c l k _ n
analogue front end (afe) for digital radio CMX983 ? adding bleed or leakage current will increase the average phase error because it shifts the position of the n - divider output with respect to the r - divider output. the amount of this shift, as described in section 12.3.1 , is ? ?????? ? ? ???? ( ? ????? + ? ??????? ) ? ???? ? ?? 1 for the purpose of calculations the average in - lock phase error is approximately ? ? ? ??? _ ??? ? ? ?????? 2 + ( 2 ? ??? ) 2 in order for the lock detector capacitor voltage to increase when the pll is in lock, the average charge supplied to the capacitor on each cycle must be greater than the charge removed. to achieve this, the discharge factor set by pll1_lockdet bits 6 - 4 sho uld set to: ????? ? ???? _ ???? 1 ? ( ? ???? ? ???? ? ? ? ??? _ ??? ? 1 ) where m is the ratio (when in lock) of the charge added to the capacitor to the charge removed on each phase detector cycle. a good rule is to make m=4, although this value ca n be adjusted to achieve reliable lock detector operation.
analogue front end (afe) for digital radio CMX983 ? 13 auxiliary adc and comparators figure 25 auxiliary adc and comparators the auxiliary adc and comparator s circuit is shown in figure 25 . the auxiliary analogue to digital converter is a 10 - bit successive approximation adc with eight multiplexed inputs . six of the adc inputs connect to dedicated input pins and the remaining two inputs can be individually configured to connect to either the main rx channel i/q gain stages, or to the auxdac7/8 pins. if using either of the auxdac7/8 pins as an adc input, the associated auxiliary dac cannot be used and must be d isabled. each auxiliary adc channel includes a digital threshold comparator that can assert a status flag when any of the programmed threshold levels have been exceeded. there are five analogue comparators that share five of the adc input signals. each of these five inputs is compared against an internal voltage threshold, and a separate flag is set when any of the programmed threshold levels have been crossed. a n a l o g u e c o m p a r a t o r s c l o c k d i v a u x a d c _ d a t a 7 1 0 a u x a d c _ d a t a 6 a u x a d c _ d a t a 5 a u x a d c _ d a t a 4 a u x a d c _ d a t a 3 a u x a d c _ d a t a 2 a u x a d c _ d a t a 1 a u x a d c _ d a t a 0 a u x a d c _ t h r 0 a u x a d c _ t h r 1 s a m p l e / h o l d 1 s a m p l e / h o l d 2 t h r e s h o l d c o m p a r a t o r s m u x d e m u x a u x a d c 0 a u x a d c 1 a u x a d c 2 a u x a d c 3 a u x a d c 4 f r o m i n p u t g a i n s t a g e i a u x a d c _ c o n a u x a d c _ p w r u p a u x a d c _ c l k a u x a d c _ a b o r t a d c c o n t r o l l o g i c e n d o f c o n v e r t s t a t u s c l k a u x a d c c l k 8 1 0 - b i t a d c 4 m n 4 m n 2 p t i m e r p w r u p a u x a d c _ t h r 2 a u x a d c _ t h r 3 a u x a d c _ t h r 4 a u x a d c _ t h r 5 a u x a d c _ t h r 6 a u x a d c _ t h r 7 a u x a d c _ s t a t a u x a d c 5 + - + - + - + - + - 2 . 5 v a v d d t h r e s h o l d a d j u s t o u t p u t i n v e r t / l a t c h a u x c m p _ s t _ e n 5 a n a l o g u e c o m p a r a t o r s t a t u s d i g i t a l c o m p a r a t o r s t a t u s a u x c m p _ c o n 1 0 1 2 3 4 a u x c m p _ c o n 2 a u x c m p _ c o n 3 a u x c m p _ c o n 0 a u x c m p _ c o n 4 a u x c m p _ s t a t a u x a d c _ s t a r t q a u x d a c 7 ( a u x a d c 6 ) a u x d a c 8 ( a u x a d c 7 ) a l t e r n a t e r o u t i n g f o r a u x a d c c h a n n e l s 6 a n d 7
analogue front end (afe) for digital radio CMX983 ? 13.1 auxiliary adc each of the eight auxiliary adc inputs can be disabled if required. two sample - and - hold (s/h) circuits are used so that while one channel is being converted, the next channel is charging the opposite s/h. the adc uses the analogue supply a v dd as a reference C an input value of 0v gives a nominal digital output of 0, and an input value equal to a v dd gives a nominal output of 1023 ($3ff). the adc can be configured into one of two conversion modes: 1. single shot convert C when the host processor i ssues an auxadc_start command through the c - bus, a convert sequence (an a/d conversion on each enabled input in ascending order) is performed. 2. continuous convert C convert sequences are performed repeatedly, under control of an internal timer. in both conv ersion modes a status bit is generated at the end of each convert sequence. a separate status bit is generated when the converted data values of selected channels cross a high or low preset threshold value. these status bits appear in the main status regis ter (section 6.4 ) and can either be polled by the host c, or used to generate an interrupt signal. note that although the end of convert indication occurs when all selected channels have completed conversion, each individual result register is updated when the respective channel finishes a conversion. therefore, in continuous convert mode, there is a limited time after the end of convert is asserted before the next convert sequence overwrites the first enabled channels data register. the host c must read the result within this time otherwise the data will be lost. to save power, the aux adc can be configured to automatically power down parts of its analogue c ircuitry when no channels are selected for conversion, or after a convert sequence (in either single shot or continuous convert mode) has completed on all enabled channels. when this power down mode is selected, a programmable delay must be added at the st art of each new convert sequence before the adc starts doing its first conversion. this delay, controlled by the auxadc_pwrup register, allows time for circuits to power up and stabilise and adds directly to the time taken to complete a convert sequence. the following c - bus registers are used to configure the auxiliary adcs: auxadc_start - $60 c - bus command, no data required when the aux adc is configured in single shot convert mode, a convert sequence is initiated when the host c issues an auxadc_start command. this command is ignored it the adc is configured in continuous convert mode, or in single shot mode if a convert sequence is already in progress. auxadc_abort - $61 c - bus command, no data required issuing this command immediately terminates an a ctive single shot or continuous convert sequence, without generating an end of convert status bit. the auxadc_abort command also resets the convert mode to single shot (auxadc_con bit 8 = 0), but leaves all other configuration bits unaltered.
analogue front end (afe) for digital radio CMX983 ? auxadc_c lk - $62 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aux adc clock divide timer coarse divide timer fine divide auxadc_clk b15 - 10: aux adc clock divide these bits hold the prescaler value p that determines the frequency of the auxiliary adc clock auxadcclk. the value p can be set to between 1 and 64 (000000 = 64); the frequency of auxadcclk is given by: auxadcclk should be set to a frequency of between 1mhz and 2mhz. each individual adc conversi on takes 11 periods of auxadcclk to perform, plus one extra cycle of clk to store the result in the associated data register. if there are n channels enabled, then a convert sequence will be completed in a time given by: if the auxadc_pwrup register is loaded with a value greater than 0, the convert sequence will be lengthened by that number of auxadcclk cycles. auxadc_clk b9 - 7: timer coarse divide auxadc_clk b6 - 0: timer fine divide the aux adc timer determines the rate at which convert sequences are started in continuous convert mode. the coarse divide can be set to a value between 0 and 7, and the fine divide can be set to between 1 and 128 (0000000 = 128). the timer interval is given by this expression: for instance, if the coarse divide is set to 2 (010) and the fine divide is set to 125 (1111101) then the timer interval will equal 4 2 x125 = 2000 cycles of clk. the timer period t t imer should be set to a value greater than the convert sequence time t con vert , unless b ack - to - back convert sequences are required in which case set the coarse divide to 000 and the fine divide to 0000001 . auxadc_pwrup - $63 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwrup enab 0 0 0 0 power up coarse divide power up fine divide auxadc_pwrup b15: power - up enable p f f clk auxadcclk ? ? 2 ? ? ? ? ? ? ? ? ? ? clk auxadcclk convert f f n t 1 11 clk de coarsedivi timer f finedivide t ? ? 4
analogue front end (afe) for digital radio CMX983 ? set to 1 to enable the power - up delay timer. set to 0 to disable the delay timer C this should only be done if the sample/hold circuits remain powered up between convert sequences (see register auxadc_con). auxadc_pwrup b14 - 11: reserved, set to 0 auxadc_pwrup b10 - 8: timer coarse divide auxadc_pwrup b7 - 0: timer fine divide the power - up divider determines how many cycles of auxadcclk will occur after a convert sequence is initiated before the conversion actually begins. the coarse divide can be set to a value between 0 and 7, and the fine divide can be set to between 1 and 256 (00000000 = 256). the delay is given by: with the aux adc configured to power down t he sample/hold circuits between convert sequences, this delay allows the circuits time to power back up and stabilise when a new convert sequence begins. the required delay time is defined in section 14.3 (operating characteristics) . auxadc_con - $64 : 16 - bit write reset value = $0 2 00 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 adc7 alt input adc6 alt input q single ended enable i single ended enable s/h auto - power conv. mode channel enable auxadc_con register b15 - 1 4 : reserved, set to 0 auxadc_con register b13: adc7 alternative input set to 1 to connect pin auxdac8 to adc input 7, set to 0 to connect the q channel differential to single - ended converter to adc input 7. when using pin auxdac8 as an input to the aux adc, the pin must be put into a high impedance state by disabling a ux dac8 (clear auxdac_data 8 r egister b15 ). auxadc_con register b12: adc6 alternative input set to 1 to connect pin auxdac7 to adc input 6, set to 0 to connect the i channel differential to single - ended converter t o adc input 6. when using pin auxdac7 as an input to the aux adc, the pin must be put into a hig h impedance state by disabling aux dac7 (clear auxdac_data 7 r egister b15 ). auxadc_con register b11: q - channel single - ended converter enable set to 1 to enable the differential to single - ended converter on adc input 7, and enable the associated input gain stage in rx channel b (i f not already enabled). set this bit to 0 to power down the converter. the converter cannot automatically power down between convert seq uences. auxadc_con register b10: i - channel single - ended converter enable set to 1 to enable the differential to single - ended converter on adc input 6, and enable the associated input gain stage in rx channel a (if not already enabled). set this bit to 0 t o power down the converter. the converter cannot automatically power down between convert sequences. clk de coarsedivi powerup f finedivide t ? ? 4
analogue front end (afe) for digital radio CMX983 ? auxadc_con register b9: sample/hold auto - power set this bit to 1 to automatically power down the sample/hold circuits between conversion sequences. set th is bit to 0 to keep the sample/hold circuits powered up between conversion sequences. auxadc_con register b8: convert mode set to 0 for single shot convert mode. issuing a c - bus auxadc_start command then starts a single conversion on each of the enabled adc inputs from lowest to highest . set to 1 for continuous convert mode. convert sequences ( a/d conversions on each enabled input from lowest to highest ) are then automatically performed at regular intervals, as determined by the timer divide value in the auxadc_clk register. this bit is automatically cleared to 0 by an auxadc_abort command. auxadc_con register b7 - 0: channel enable when any of the channel enable bits is set to 1 it causes the corresponding input to be selected for analogue to digital conversion. during a convert sequence each enabled channel, from the lowest to the highest, is converted in turn. the channel enable bits should not be modifi ed while a convert sequence is underway. channel select analogue input channel select analogue input 7 q input 3 auxadc3 6 i input 2 auxadc2 5 auxadc5 1 auxadc1 4 auxadc4 0 auxadc0 aux adc inputs 0 to 5 (pins auxadc0 to auxadc5) are direct inputs to the adc multiplexer. inputs 6 and 7 connect to the main adc channel a and b signal inputs through differential to single - ended converters. these have good common mode rejection and a differential gain of 0.5, so that an input signal of, say, 5v pk - pk dif ferential will give a 2.5v pk - pk output, centred on a v dd /2. auxadc_thr0 - $65 16 - bit wri te auxadc_thr1 - $66 16 - bit write auxadc_thr2 - $67 16 - bit write auxadc_thr3 - $68 16 - bit write auxadc_thr4 - $69 16 - bit write auxadc_thr5 - $6a 16 - bit write auxadc_thr6 - $6b 16 - bit write auxadc_thr7 - $6c 16 - bit write reset value = $00ff bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aux adc threshold value b aux adc threshold value a at the end of a convert sequence the result for each enabled adc channel is compared against the two threshold values in the associated threshold register, and a bit in the auxadc_stat register is set accordingly (this may also set a bit in the main status register). only the most significant 8 bits of the aux adc values are used for the comparison. using aux adc channel 0 as an example, the
analogue front end (afe) for digital radio CMX983 ? associated adc status bit (auxadc_stat bit 0) is set as shown below. the other seven channels operate in a similar wa y. (a) if threshold value a (auxadc_thr0 b7 - 0) ? threshold value b (auxadc_thr0 b15 - 8), then the status bit (auxadc_stat b0) is set if: adc result (auxa d c_data0 b9 - 2) > threshold value a (auxadc_thr0 b7 - 0), or adc result (auxa d c_data0 b9 - 2) < threshold value b (auxadc_thr0 b15 - 8) (b) if threshold value a (auxadc_thr0 b7 - 0) < threshold value b (auxadc_thr0 b15 - 8), then the status bit (auxadc_stat b0) is set if: adc result (auxa d c_data0 b9 - 2) > threshold value a (auxadc_thr0 b7 - 0), and adc result (auxa d c_data0 b9 - 2 ) < threshold value b (auxadc_thr0 b15 - 8) setting the threshold values according to (a) is useful for testing if the adc value has exceeded a particular range, and (b) is useful for testing if the adc value has entered a particular range, as shown in figure 26 . note that the threshold comparison for a particular channel can be disabled by setting threshold value a = $ff and threshold value b = $00. case (a): case (b): $3ff threshold status bit set if adc result enters this range $3ff threshold a threshold b threshold status bit set if adc result enters this range. threshold b or if adc result enter this range threshold a $000 $000 figure 26 auxiliary adc threshold trigger range auxadc_stat - $6d : 8 - bit read reset value = $00 bit: 7 6 5 4 3 2 1 0 adc thresh flag 7 adc thresh flag 6 adc thresh flag 5 adc thresh flag 4 adc thresh flag 3 adc thresh flag 2 adc thresh flag 1 adc thresh flag 0 auxadc_stat register b7 - 0: adc threshold flag 7..0 each adc threshold flag gets set to 1 at the end of a convert sequence if the associated adc channel is enabled and the corresponding adc result is within the programmed threshold range (see description of auxadc_thr7..0 registers). the threshold flags in auxadc_stat are sticky: once they are set to 1 they remain in that state until a c - bus read of auxadc_stat is performed, after which they are automatically cleared to 0. the eight threshold flags in the auxadc_stat register are ored together and the resulting digital comparator status bit is passed to the CMX983 status register (section 6.4 ).
analogue front end (afe) for digital radio CMX983 ? auxadc_data0 - $6e : 16 - bit read auxadc_data1 - $6f ; 16 - bit read auxadc_data2 - $70 : 16 - bit read auxadc_data3 - $71 : 16 - bit read auxadc_data4 - $72 ; 16 - bit read auxadc_data5 - $73 : 16 - bit read auxadc_data6 - $74 : 16 - bit read auxadc_data7 - $75 : 16 - bit read reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 aux adc data each of the eight registers auxadc_data0 to auxadc_data7 holds the 10 - bit result of the last conversion performed on the associated channel. the data is updated immediately that the respective channel has been converted during a convert sequence, the regis ters are not updated simultaneously when the convert sequence has completed.
analogue front end (afe) for digital radio CMX983 ? 13.2 auxiliary comparators each of the five analogue comparator channels can be individually enabled. the positive inputs of the comparators are connected to the auxadc4..0 input pins , and the negative inputs of the comparators are connected to a set of five programmable threshold voltages. the threshold voltages can be individually set in nominal 100mv increments, and can use either the analogue supply or an on - chip bandgap voltage as a reference. each comparator output can be optionally inverted so that a status flag is generated either when the input pin is above or below the associated threshold voltage. the following c - bus registers are used to configure the auxiliary adcs: auxcm p_con0 - $76 : 8 - bit write auxcmp_con1 - $77 : 8 - bit write auxcmp_con2 - $78 ; 8 - bit write auxcmp_con3 - $79 : 8 - bit write auxcmp_con4 - $7a : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 con0: enab cmp 0 invert cmp 0 vref sel 0 comparator 0 threshold voltage con1: enab cmp 1 invert cmp 1 vref sel 1 comparator 1 threshold voltage con2: enab cmp 2 invert cmp 2 vref sel 2 comparator 2 threshold voltage con3: enab cmp 3 invert cmp 3 vref sel 3 comparator 3 threshold voltage con4: enab cmp 4 invert cmp 4 vref sel 4 comparator 4 threshold voltage each of these five registers controls one of the analogue comparators: auxcmp_con0 - 4 register b7: enable comparator set to 1 to enable the associated channel (comparator + threshold voltage generator), or set to 0 to disable and powersave the channel. the comparators are prevented from setting their associated flag bit in the auxcmp_stat register when they are disabled, or for 256 clk cycles after the enable bit changes from 0 to 1 (to allow time for the intern al threshold voltage to settle). auxcmp_con0 - 4 register b6: invert comparator set to 1 to invert the comparator output, causing the comparator flag to be set when the input voltage goes below the comparator threshold voltage. set to 0 to cause the compara tor flag to be set when the input voltage goes above the comparator threshold voltage. auxcmp_con0 - 4 register b5: voltage reference select set to 1 to use the internally generated voltage (2.5v) as the reference for the comparator threshold. set to 0 to u se the analogue supply voltage ( a v dd ) as the reference for the comparator threshold. auxcmp_con0 - 4 register b4 - 0: comparator threshold voltage set the comparator threshold voltage from 0.0v (00000 2 ) to 3.1v (11111 2 ) in 100mv (nominal) steps. note: if usin g the internally generated voltage as a reference, then the maximum voltage that can be set is 2.5v (11001 2 ).
analogue front end (afe) for digital radio CMX983 ? auxcmp_stat - $7b : 8 - bit read reset value = $00 bit: 7 6 5 4 3 2 1 0 0 0 0 cmp thresh flag 4 cmp thresh flag 3 cmp thresh flag 2 cmp thresh flag 1 cmp thresh flag 0 auxcmp_stat register b7 - 5: reserved, set to 0 auxcmp_stat register b4 - 0: comparator threshold flag 4..0 each comparator threshold flag gets set to 1 if the associated comparator is enabled and the corresponding input pin voltage is greater than the programmed threshold voltage (or less than, if the comparator output is inverted). the threshold flags in auxcmp_stat are sticky: once they are set to 1 they remain in that state until a c - bus read of auxcmp_stat is performed, after which they are automatically cleared to 0. when auxcmp_stat is read, if the comparator input is still greater than the programmed threshold voltage then the flag will stay high. disabling a comparator channel does not automatically clear the associated flag bit. the five threshold flags in the auxcmp_stat register are gated with the enable bits in the auxcmp_stat_en register and are then ored together. the resulting analogue comparator status bit is passed to the CMX983 status register (section 6.4 ), as shown in figure 27 . this can be used t o generate an interrupt signal. figure 27 comparator and threshold status flag auxcmp_st_en - $7c : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 0 0 enab stat 4 enab stat 3 enab stat 2 enab stat 1 enab stat 0 auxcmp_st_en register b7 - 5: reserved, set to 0 auxcmp_st_en register b4 - 0: enable status 4..0 setting any of the enable status bits to 1 allows the associated comparator threshold flag in the auxcmp_stat register to drive the analogue comparator status bi t to 1. + - a u x c m p _ c o n 0 b i t 7 ( e n a b c m p ) a u x c m p _ c o n 0 b i t 6 ( i n v e r t c m p ) a u x c m p _ s t _ e n b i t 0 ( e n a b s t a t 0 ) r e a d a u x c m p _ s t a t a u x c m p _ s t a t b i t 0 1 2 3 4 a n a l o g u e c o m p a r a t o r s t a t u s [ c o m p a r a t o r / l a t c h c h a n n e l 0 s h o w n ] f r o m c h a n n e l s 1 . . . 4 s e t r s t q c l k
analogue front end (afe) for digital radio CMX983 ? 14 auxiliary dacs figure 28 auxiliary dacs the CMX983 has nine general - purpose 10 - bit d/a converters (pins auxdac0 C auxdac8) to assist in a variety of control functions ( figure 28 ). these aux dacs operate independently, and can be individually enabled or powered down. the aux dacs are designed to provide an output as a proportion of th e analogue supply voltage, depending on the aux dacs data register setting: a value of 0 drives that aux dacs output to a v ss ; a value of 1023 ($3ff) drives the output to a v dd . dac0 has an additional ramping feature where the contents of an internal 64 wor d 10 bit dac ram can be transferred in ascending order to dac0 (ramp up), in descending order (ramp down) or repeatedly up and down (cyclical ramping) at a programmable rate. the dac0 ramp up and ramp down facility is particularly useful for controlling the power of an rf transmitter at the beginning and end of a transmit slot, in order to minimise adjacent - channel splatter. the following c - bus registers are used to configure the auxiliary dacs: auxdac_clk - $82 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 ramp coarse divide ramp fine divide auxdac_clk register b15 - 11: reserved, set to 0
analogue front end (afe) for digital radio CMX983 ? auxdac_clk register b10 - 8: ramp coarse divide auxdac_clk register b7 - 0: ramp fine divide the ramp clock divider determines the rate at which the 64 - word dac ram is read during a ramp sequence C a total of 63 reads are performed during a ramp up or ramp down. the coarse divide can be set to a value between 0 and 7, and the fine divide can be set to between 1 and 256 (00000000 = 256). the total time taken to ramp up or down is given by the following expression: for instance, if the coarse divide is set to 2 (010) and the fine divide is set to 15 (00001111) then the ramp time will equal 63x4 2 x15 = 15120 cy cles of clk. during cyclical ramping, the period of a single output cycle will equal 2xt ramp . auxdac_ramd - $83 : 16 - bit write, data - streaming reset value = undefined bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 aux dac ram values the 64 - word dac ram can be loaded in ascending order by repeatedly writing data to this c - bus location (the internal address pointer automatically increments after each write). to increase the loading rate of the coefficients, data - streaming operation is suppo rted for this c - bus address. before loading the dac ram, the internal address pointer needs to be initialised (usually to address 0); this is done by writing to register auxdac_rama. note that writes to the dac ram are disabled if the dac0 select bit (auxd ac_ data0 bit 12 ) is set to 1. auxdac_rama - $84 : 8 - bit write reset value = $00 bit: 7 6 5 4 3 2 1 0 0 0 dac ram address pointer the dac ram address pointer determines the address at which data gets written during a c - bus write to the auxiliary dac ram. the address pointer automatically increments after each 16 - bit value is written, so if the ram is written in an ascending sequence the pointer only needs to be initialised once before the ram is loaded. auxdac_up - $85 c - bus command, no data required when the auxdac_ up command is issued, the dac ram contents are read out in an ascending sequence and applied to dac0 (through the multiplexer) until the final locati on at address 63 has been read. auxdac_down - $86 c - bus command, no data require d ? ? ? ? ? ? ? ? ? ? ? clk de coarsedivi ramp f finedivide t 4 63
analogue front end (afe) for digital radio CMX983 ? when the auxdac_down command is issued, the dac ram contents are read out in a descendin g sequence and applied to dac0 ( through the multiplexer ) until the final location at address 0 has been read. auxdac_cycle - $87 c - bus command, no data required when the auxdac_ cycle command is issued, the dac ram will cycle continuously between ramp up and ramp down operations. the rate at which data is read from the ram is determined by the auxdac_clk register, and it takes a total of 2x63 = 126 reads to complete one up + one down cycle. this mode of operation can be terminated by issuing an auxdac_up, auxdac_down or auxdac_rst command, or by setting auxdac_ data0 bit 12 to 0. auxdac_rst - $88 c - bus command, no data required when the auxdac_rst command is issued, any active ramp operation is immediately terminated and the dac ram pointer is reset to 0. auxdac_data0 - $89 : 16 - bit write auxdac_data1 - $8a : 16 - bit write auxdac_data2 - $8b : 16 - bit write auxdac_data3 - $8c : 16 - bit write auxdac_data4 - $8d : 16 - bit writ e auxdac_data5 - $8e : 16 - bit write auxdac_data6 - $8f : 16 - bit write auxdac_data7 - $90 : 16 - bit write auxdac_data8 - $91 : 16 - bit write reset value = $0000 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dac0: enab ramp revrse ramp hold dac0 select 0 0 aux dac0 data dac1: enab 0 0 0 0 0 aux dac1 data dac2: enab 0 0 0 0 0 aux dac2 data dac3: enab 0 0 0 0 0 aux dac3 data dac4: enab 0 0 0 0 0 aux dac4 data dac5: enab 0 0 0 0 0 aux dac5 data dac6: enab 0 0 0 0 0 aux dac6 data dac7: enab 0 0 0 0 0 aux dac7 data dac8: enab 0 0 0 0 0 aux dac8 data auxdac_data0 - 8 register b15: dac 0 C dac 8 enable setting any of these bits to 1 enables the corresponding aux dac circuit and causes a voltage to be driven onto its output pin. when a dac is disabled it goes into a zero - power state and its output pin goes high impedance. auxdac_ data0 register b 14 : ramp reverse mode
analogue front end (afe) for digital radio CMX983 ? this bit determines the behaviour of dac0 during a ramp operation when a c - bus command is issued that reverses the direction of the ramp, i.e. issuing a n auxdac_up command while the dac is ramping down, or issuing an auxdac_down command while the dac is ramping up. when this bit is set to 0, the ramp direction reverses immediately. when this bit is set to 1, the ramp direction reverses only when the curre ntly active ramp operation completes. auxdac_data0 register b1 3 : ramp hold set this bit to 1 to pause a ramp up, ramp down or ramp cycle operation; this freezes the dac0 output. setting this bit to 0 allows the ramp function to continue. auxdac_data0 register b 12 : dac0 select this bit controls the multiplexer at the input to dac0. when this bit is set to 1, the dac ram output register is connected to dac0 and c - bus writes to the dac ram are disabled. when this bit is set to 0, the auxdac_data0 register is connected to dac0 and any active ramp operation is immediately terminated. auxdac_data1 - 8 register b14 - 1 2 : reserved, set to 0 auxdac_data0 - 8 register b11 - 10: reserved, set to 0 auxdac_data0 - 8 register b9 - 0: dac0 C dac8 data the least significant 10 - bit values in registers auxdac_data1 C auxdac_data8 are driven directly into the corresponding auxiliary dacs. the least significant 10 - bit value in register auxdac_data0 is multiplexed with the output of the ramp circuit before being driven into dac0; this multiplexer is controlled by auxdac_ data0 bit 12 . an example of the aux dac ram contents for a raised cosine ramp profile is shown in figure 29 . aux dac ram con tents (hexadecimal) 0 000 1 001 2 003 3 006 4 00a 5 010 6 017 7 01f 8 028 9 033 10 03e 11 04b 12 059 13 068 14 078 15 089 16 09a 17 0ad 18 0c1 19 0d5 20 0ea 21 100 22 116 23 12d 24 145 25 15d 26 175 27 18e 28 1a7 29 1c0 30 1d9 31 1f3 32 20c 33 226 34 23f 35 258 36 271 37 28a 38 2a2 39 2ba 40 2d2 41 2e9 42 2ff 43 315 44 32a 45 33e 46 352 47 365 48 376 49 387 50 397 51 3a6 52 3b4 53 3c1 54 3cc 55 3d7 56 3e0 57 3e8 58 3ef 59 3f5 60 3f9 61 3fc 62 3fe 63 3ff figure 29 aux dac ram contents example
analogue front end (afe) for digital radio CMX983 ? 15 performance specification 15.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units power supplies io v dd - io v ss - 0.3 4.0 v d v dd - d v ss - 0.3 2.16 v a v dd - a v ss - 0.3 4.0 v rf1 v dd - a v ss - 0.3 2.16 v rf2 v dd - a v ss - 0.3 2.16 v cp1 v dd - a v ss - 0.3 6.0 v cp2 v dd - a v ss - 0.3 6.0 v voltage differential between power supplies: iov ss , dv ss and av ss 0 C ss - 0.3 io v dd + 0.3 v current into or out of any pin, except power supply pins - 20 +20 ma q1 package (64 - pin vqfn) min. max. units total allowable power dissipation at t amb = 25 c 3500 mw ... derating 35.0 mw/ c storage temperature - 55 +125 c operating temperature - 40 +85 c 15.2 operating limits correct operation outside these limits is not implied. min typ max. units iov dd - iov ss 3.0 3.3 3.6 v dv dd - dv ss 1.7 1.8 1.9 v av dd - av ss 3.0 3.3 3.6 v rf1v dd - av ss 1.7 1.8 1.9 v rf2v dd - av ss 1.7 1.8 1.9 v cp1v dd - av ss 3.0 5.0 5.25 v cp2v dd - av ss 3.0 5.0 5.25 v voltage differential between power supplies: iov ss , dv ss and av ss 0 C C C C dd , rf1v dd and rf2v dd ) be brought up and the resetn pin driven low before the analogue supply ( av dd ) is brought up. the charge pump supplies ( cp1v dd , cp2v dd ) can be brought up either before or after the other supplies. if this sequence is not followed then the analogue circuits may power up in an indeterminate or active state, and this state may persist until the 1.8v supplies are brought up and the res etn pin is driven low. the CMX983 will not suffer physical damage or reliability degradation if the recommended power up sequence is not followed.
analogue front end (afe) for digital radio CMX983 ? 15.3 operating characteristics for the conditions in table 4 below unless otherwise specified: table 4 operational characteristics - test conditions power supplies general av dd , iov dd 3.3 v f mclk , f clk 19.2 mhz cp1v dd , cp2v dd 5.0 v t amb 25 c dv dd , rf1v dd , rf2v dd 1.8 v main adc and rx channel configuration main dac and tx channel configuration signal tone 1010 hz signal tone 1010 hz signal amplitude, peak 1.98 v input code level, peak 30178 rx input gain 0 db input sample rate (ct1) 150 khz - clock rate (cr1) 2.4 mhz upsampler 1 rate bypass sinc filter length 16 fir filter bypass sinc filter no. 5 bit selector bypass bit selector 1 17 upsampler 2 rate 16 decimator 1 rate 16 - clock rate (ct3) 2.4 mhz fir filter bypass sc filter bandwidth low bit selector 2 1 tx output gain 0 db decimator 2 rate 1 external rc filter - 3db 100 khz output sample rate (cr3) 150 khz measurement bandwidth 9 khz measurement bandwidth 9 khz dc parameters notes min. typ. max. unit supply current C powersave 1 ioi dd C C dd C C dd C C dd or rf2i dd C C dd or cp2i dd C C supply current C idle (clk running ) di dd C C dd 6 C C supply current C i and q tx channels active ioi dd 1, 2 C C dd 1, 2 C C dd 1, 5 C C dd 1, 2 C C supply current C i and q rx channels active ioi dd 1, 2 C C dd 1, 2 C C dd 1, 5 C C dd 1, 2 C C
analogue front end (afe) for digital radio CMX983 ? additional currents from idle mode one rf synthesiser active: di dd C 0.09 C ma ai dd C 1.2 C ma rf1i dd or rf2i dd 3 C 9.2 C ma cp1i dd or cp2i dd 4 C 0.75 C ma digital pll active: di dd C 0.47 C ma one auxadc input active: di dd C 0.06 C ma ai dd C 0.45 C ma one auxdac output active: di dd C 0.02 C ma ai dd C 0.26 C ma v bias buffer active: ai dd C 0.11 C ma
analogue front end (afe) for digital radio CMX983 ? dc parameters notes min. typ. max. unit digital interfaces input logic 1 70% C C iov dd input logic 0 C C 30% iov dd input leakage current (logic 1 or 0) - 1.0 C 1.0 a input capacitance C C 7.5 pf output logic 1 (i = 2ma) 90% C C iov dd output logic 0 (i = - 5ma) C C 10% iov dd off state leakage current - 1.0 C 1.0 a v bias output voltage offset wrt av dd /2 (i ol < 1 ? a) C 2% C av dd output impedance C 50 C k ? start - up time 7 C 10.5 C ms v b buf ( v bias buffer ) output load current C C 50 a notes: 1. t amb = 25c, not including any current drawn from the device pins by external circuitry. 2. includes 2 x rf synthesisers, digital pll, auxadc and auxdac. 3. lock detect active. 4. per charge pump, with an output current of 100a. 5. no digital pll, rf synthesisers or auxiliary circuits. 6. mclk amplifier active. 7 . with 100nf load.
analogue front end (afe) for digital radio CMX983 ? operating characteristics (continued) ac parameters notes min. typ. max. unit clocks mclk frequency (f mclk ) 5 C 30 mhz mclk sensitivity (ac - coupled) 0.2 C 0.8 vpk - pk mclk slew rate (ac - coupled) 10 C C v/ s mclk amplifier phase noise 10 C - 83 C dbc/hz clk frequency (f clk ) 5 C 50 mhz synthesiser 1 and 2 rf input frequency (f rf1,2 ) 100 C 2100 mhz rf input sensitivity 12 50 C 500 mvpk rf input slew rate 150 C C v/ s charge pump sink/source (programmable) C 25 - 400 C a charge pump absolute accuracy - 20 C 20 % charge pump matching - 4 C 4 % charge pump compliance range 0.5 C cp1/2 v dd - 0.5 v pd comparison frequency (f comp ) C C 30 mhz n - divider range (integer mode) 32 C 2047 n - divider range (fractional mode) 36 C 2043 1hz normalised phase noise floor 11 C - 205 C dbc/hz main adcs g ain stage error - 0.3 0 0.3 db sigma - delta clock rate (cr1) C 2.4 2.6 mhz sinad 87 88 C db input voltage (after gain stage) C C 20 to 80 %av dd sfdr - 95 - db zero error (offset) - 5.5 10 mv main dacs g ain stage error - 0.3 0 0.3 db sigma - delta clock rate (ct3) C 2.4 2.6 mhz o utput voltage C C 10 to 90 %av dd r esolution (gain = 0db) C 75.5 C v/bit o utput load (per output, to av dd /2) 20 C C k ? sinad 72 76 C db sfdr C 85 C db zero error (offset) C 3.0 10 mv notes: 10. mclk = 19.2mhz sinewave, 400mvpk - pk, measured at 1khz offset. 11. 1hz normalised phase noise floor (pn1hz) can be used to calculate the phase noise within the pll loop bandwidth by: measured phase noise (in 1hz) = - pn1hz - 20log 10 (n) - 10log 10 (f comparison ); f comparison = frequency at the output of the reference divider; n = main divider ratio. measured with f comparison = 2.4mhz, charge pump current = 400ua, modulator setting = 001. value will vary depending on pll settings. 12. an input sinewave below 477mhz requires an amplitude greater than 50mvpk in order to meet the minimum slew rate specification .
analogue front end (afe) for digital radio CMX983 ? operating characteristics (continued) ac parameters notes min. typ. max. unit aux adc sample/hold startup time 30 C C s resolution C 10 C bits aux adc clock period 500 C 1000 ns integral non - linearity 20 C C 2 bits differential non - linearity 20, 21 C C 1 bits zero error (offset) C C 10 mv input capacitance C C 5 pf aux comparators internal 2.5v reference voltage 2.3 2.5 2.7 v comparator offset voltage C 6.5 10 mv aux dacs capacitive load on aux dac output C C 100 pf resolution C 10 C bits settling time to 0.5 lsb 22 C C 10 s integral non - linearity C C 4 bits differential non - linearity 24 C C 1 bits zero error (offset) C 5.5 10 mv output current (individual aux dac output) 23 C C 2.3 ma total output current (sum of all aux dacs) C C 10 ma output noise voltage (100 hz C 30khz) C 30 C v rms notes: 20. non - linearity is specified between 0.5% and 99.5% of full scale. 21. guaranteed monotonic (no missing codes). 22. worst case large signal transition. 23. dac output voltage in the range 0.2v to av dd C 0.2v at maximum output current 24. not applicable in alternate routi ng mode
analogue front end (afe) for digital radio CMX983 ? operating characteristics (continued) ac parameters notes min. typ. max. unit c - bus timing input pin rise/fall time (10% - 90% of iov dd ) C C 3 ns capacitive load on rdata and irqn C C 30 pf t cse csn enable to sclk high time 40 C C ns t csh last sclk high to csn high time 40 C C ns t loz sclk low to rdata output enable time 30 0 C C ns t hiz csn high to rdata high impedance 30 C C 30 ns t csoff csn high time between transactions 40 C C ns t ck sclk cycle time 100 C C ns t c h sclk high time 40 C C ns t c l sclk low time 40 C C ns t cds cdata setup time 25 C C ns t cdh cdata hold time 25 C C ns t rd v sclk low to rdata valid time 31 0 C 35 ns serial port timing input pin rise/fall time (10% - 90% of iov dd ) C C 3 ns capacitive load on rx and tx port output pins C C 30 pf t rck rxclk cycle time 100 C C ns t rck h rxclk high time 40 C C ns t rck l rxclk low time 40 C C ns t rc hd rxclk high to rxd or rxfs delay 31 - 20 C 20 ns t rc loz rxclk high to rxd output enable time 30 0 C C ns t rxds rxd or rxfs setup time to rxclk low 20 C C ns t rxdh rxd or rxfs hold time from rxclk low 20 C C ns t t ck txclk cycle time 100 C C ns t t ck h txclk high time 40 C C ns t t ck l txclk low time 40 C C 0 ns t t c hd txclk high to txfs delay 31 - 20 C 20 ns t t xds txd or txfs setup time to txclk low 20 C C ns t t xdh txd or txfs hold time from txclk low 20 C C ns notes: 30. measured with test load b on output pin 31. measured with test load a on output pin
analogue front end (afe) for digital radio CMX983 ? 15.4 timing diagrams figure 30 ac test load for digital outputs figure 31 c - bus timings d v d d d v s s c 2 r 1 r 2 d e v i c e u n d e r t e s t t e s t l o a d b r 1 = 1 . 2 k r 2 = 1 k c 1 = 5 p f ( m i n ) , 3 0 p f ( m a x ) c 2 = 5 p f c 1 , c 2 i n c l u d e j i g c 1 d e v i c e u n d e r t e s t t e s t l o a d a d v s s d v s s 7 6 5 4 3 2 1 0 3 2 1 0 7 6 5 c s n s c l k c d a t a r d a t a h i - z 3 2 1 0 = l e v e l u n d e f i n e d o r n o t i m p o r t a n t t c s e t c k t c h t c l 3 0 % i o v d d 7 0 % i o v d d c d a t a s c l k c s n r d a t a t l o z t c s h t r d v t r d v t c d s t c d h t c s o f f t h i z a d d r e s s w r i t e d a t a r e a d d a t a 1 5 7 1 4 6 1 5 7 1 4 6
analogue front end (afe) for digital radio CMX983 ? figure 32 serial port timings r x c l k r x f s t r c k r x d t r c k h t r c h d t r c l o z t r x d s t r c h d t r x d s t r x d h t r x d h d a t a 1 5 d a t a 1 4 d a t a 1 3 7 0 % i o v d d 3 0 % i o v d d t x c l k t x f s t x d t t c h d t t x d s t t x d s t t x d h d a t a 1 5 d a t a 1 4 d a t a 1 3 7 0 % i o v d d 3 0 % i o v d d t t x d h t r c k l t t c k t t c k h t t c k l
analogue front end (afe) for digital radio CMX983 ? 15.5 typical performance characteristics refer to table 4 for details of the test conditions that apply to the following graphs . figure 33 adc sinad vs. input level figure 34 adc sfdr vs. input level 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 db v pk - pk differential 0 20 40 60 80 100 120 0.01 0.1 1 db v pk - pk differential
analogue front end (afe) for digital radio CMX983 ? figure 35 adc two tone test note: for the graph shown in figure 35 , input level was 1.5v pk - pk for each of the two tones.
analogue front end (afe) for digital radio CMX983 ? figure 36 dac sinad vs. input code level figure 37 dac sfdr vs. input code lev el 0 10 20 30 40 50 60 70 80 90 10 100 1000 10000 100000 db input code level, peak 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 100000 db input code level, peak
analogue front end (afe) for digital radio CMX983 ? figure 38 pll1 output spectra note: the graph shown in figure 38 shows the output spectra for f comp = 4.8mhz (rdiv = $4) and 250 ? a charge pump current. without fast lock: loop filter (reference design as shown in figure 21 ) c1 = 6n8f / c2 = 27nf / r2 = 1k5ohms / r3 = 470ohms / c3 = 470pf
analogue front end (afe) for digital radio CMX983 ? figure 39 pll1 lock time note: the graph shown in figure 39 shows the lock times for a change in f vco from 875mhz (idiv = 182, fdiv = $4aaaaa) to 965mhz (idiv = 201, fdiv = $0aaaaa) for f comp = 4.8mhz (rdiv = $4) and 250 ? a charge pump current. without fast lock: loop f ilter (reference design as shown in figure 21 ) c1 = 6n8f / c2 = 27nf / r2 = 1k5ohms / r3 = 470ohms / c3 = 470pf figure 40 pll1 indicated lock time vs. fast lock current (965 to 875.525 mhz) note: fast lock timer, coarse = 4, fine = 80, giving 1.067ms 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 2 4 6 8 10 12 14 16 18 ms fast lock current (x charge pump current)
analogue front end (afe) for digital radio CMX983 ? figure 41 pll2 output spectra note: the above graph shows the output spectra for f comp = 4.8mhz (rdiv = $4) and 250 ? a charge pump current. without fast lock: loop filter (reference design as shown in figure 21 ) c1 = 1n5f / c2 = 9n4f (4n7f//4n7f) / r2 = 4k7ohms / r3 = 1k2ohms / c3 = 180pf
analogue front end (afe) for digital radio CMX983 ? figure 42 pll2 lock time note: the above graph shows the lock times for a change in f vco from 2044mhz (idiv = 426, fdiv = $d55555) to 2125mhz (idiv = 443, fdiv = $b55555) for f comp = 4.8mhz (rdiv = $4) and 250 ? a charge pump current. without fast lock: loop filter (reference design as shown in figure 21 ) c1 = 1n5f / c2 = 9n4f (4n7f//4n7f) / r2 = 4k7ohms / r3 = 1k2ohms / c3 = 180pf figure 43 pll2 indicated loc k time vs. fast lock current (2125 to 2043 mhz) note: fast lock timer, coarse = 6, fine = 1, giving 213 s 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 2 4 6 8 10 12 14 16 18 ms fast lock current (x charge pump current)
analogue front end (afe) for digital radio CMX983 ? figure 44 relative performance of pll options -105 -103 -101 -99 -97 -95 -93 -91 -89 -87 -85 100000 1000000 dbc offset frequency hz type '110' type '001'
analogue front end (afe) for digital radio CMX983 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circui try described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipmen t to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed. 16 packaging figure 45 64 - lead vqfn mechanical outline: order as part no. CMX983q1

▲Up To Search▲

Price & Availability of CMX983

	To Download CMX983 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .