quadrature clock converter features: ?x1, x2 and x4 mode selection ?up to 16mhz output clock frequency ?index input and output ?up/down indicator output ?programmable output clock pulse width ?on-chip filtering of inputs for optical or magnetic encoder applications. ?ttl and cmos compatible i/os ?+4.5v to +10v operation (v dd - v ss ) ?LS7082N (dip); LS7082N-s (soic ) - see figure 1 input/output description: v dd (pin 1) supply voltage positive terminal. indx (pin 2) encoder index pulses are applied to this input. rbias (pin 3) input for external component connection. a resistor con- nected between this input and v ss adjusts the output clock pulse width (tow). for proper operation, the output clock pulse width must be less than or equal to the a, b pulse separation (t ow t ps) . v ss (pin 4 ) supply voltage negative terminal. a (pin 5) quadrature clock input a. this input has a filter circuit to validate input logic level and eliminate encoder dither. x2 (pin 8) a low level applied to this input selects x2 mode of opera- tion. see table 1 for mode selection truth table and figure 2 for input/output timing relationship. b (pin 9) quadrature clock input b. this input has a filter circuit identical to input a. x4/x1 (pin 10) this input selects between x1 and x4 modes of operation. see table 1 for mode selection truth table and figure 2 for input/output timing relationship. up/dn (pin 11) the count direction at any instant is indicated at this output. an up count direction is indicated by a high, and a down count direction is indicated by a low (see figure 2). dnck (pin 12) this down clock output consists of low-going pulses gen- erated when a input lags the b input (see figure 2). upck (pin 13) this up clock output consists of low-going pulses gener- ated when a input leads the b input (see figure 2). indx (pin 14) this output consists of low-going pulses generated by a positive clock transition at the a input when indx input is high and b input is low and a negative clock transition at the b input when indx input is high and a input is high. (see figure 2). note : all unused input pins must be tied to v dd or v ss . description: the LS7082N is a cmos quadrature clock converter. quad- rature clocks derived from optical or magnetic encoders, when applied to the a and b inputs of the ls7082, are converted to strings of up clocks and down clocks. pulses derived from the index track of an encoder, when applied to the indx input, produce absolute position reference pulses which are syn- chronized to the up clocks and down clocks. these outputs can be interfaced directly with standard up/down counters for direction and position sensing of the encoder. april 2006 7082n-041906-1 table 1. mode selection truth table x2 input x4/x1 input mode 0 don? care x2 1 0 x1 1 1 x4 lsi/csi lsi computer sy stems, inc. 1235 walt whitman road, melville, ny 11747 (631) 271-0400 fax (631) 271-0405 LS7082N u l a3800 1 2 3 4 5 6 7 LS7082N upck dnck up/dn x4/x1 b x2 v dd (+v) indx rbias v ss (-v) a nc nc 14 13 12 11 8 9 10 figure 1 pin assignment - top view lsi indx discontinued
absolute maximum ratings : parameter symbol value units dc supply voltage v dd - v ss 11.0 v voltage at any input v in v ss - 0.3 to v dd + 0.3 v operating temperature t a 0 to + 70 ? storage temperature t stg -55 to + 150 ? dc electrical characteristics: (all voltages referenced to v ss , t a = 0 c to 70 c.) parameter symbol min max units condition supply voltage v dd 4.5 10.0 v - supply current i dd - 6.0 ? v dd = 10.0v, all input frequencies = 0hz rbias = 2m w x4/x1, x2, indx logic low v il - 0.3v dd v - a, b logic low v il - 0.6 v v dd = 4.5v - 1.0 v v dd = 9v - 1.1 v v dd = 10v x4/x1, x2, indx logic high v ih 0.7v dd - v - a, b logic high v ih 3.1 - v v dd = 4.5v 5.0 - v v dd = 9v 5.6 - v v dd = 10v all outputs: sink current i ol 1.75 - ma v dd = 4.5v v ol = 0.4v 5.0 - ma v dd = 9v 5.7 - ma v dd = 10v source current i oh 1.0 - ma v dd = 4.5v v oh = v dd - 0.5v 2.5 - ma v dd = 9v 3.0 - ma v dd = 10v transient characteristics: (t a = 0 c to 70 c) parameter symbol min max units condition a, b inputs: validation delay tv d - 85 ns v dd = 10v - 100 ns v dd = 9v - 160 ns v dd = 4.5v a, b inputs: pulse width t pw t vd + t ow infinite ns - a to b or b to a phase delay t ps t ow infinite ns - 1 a, b frequency f a, b - 2t pw hz - input to output delay t ds - 120 ns v dd = 10v - 150 ns v dd = 9v - 235 ns v dd = 4.5v includes input validation delay output clock pulse width t ow 50 - ns see fig. 4 & 5 7082n-012703-2 discontinued
7082n-041906-3 upck (x2) a b indx upck (x1) dnck (x1) dnck (x2) upck (x4) indx up/dn t pw t ds t ps tow t ds figure 2. LS7082N input/output timing diagram dnck (x4) mux clock and direction decode dual one-shot dual one-shot current mirror v dd figure 3. LS7082N block diagram x2 clock 14 11 13 12 3 5 9 10 8 1 4 2 indx a b x2 indx v ss filter rbias +v -v x4/x1 filter up/dn discontinued
figure 4. tow vs r bias , k v dd =5v v dd =9v v dd =10.0v 100 200 300 400 500 250 500 750 1000 1250 1500 note : vertical axis is output clock pulse width, tow, ns encoder a clock b clock index 5 9 2 13 12 14 8 10 1 3 4 r b upck dnck reset x2 x4/x1 v dd a b rbias v ss upck dnck indx figure 6. a typical application in x4 mode v ss v dd LS7082N 5 4 14 16 8 +v 40193 +v indx v dd =5v v dd =9v v dd =10.0v 25 30 20 15 10 5 2 4 6 8 10 12 figure 5. tow vs r bias , m note : vertical axis is output clock pulse width, tow, ? the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7082n-012703-4 discontinued
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