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this is information on a product in full production. september 2014 docid026724 rev 1 1/35 RL9958 low r dson spi controlled h-bridge datasheet - production data features ? programmable current regulation peak threshold by spi up to 8.6 a typ. ? operating battery supply voltage 4.0 v to 28 v ? operating v dd supply voltage 4.5 v to 5.5 v ? all pins withstand 19 v, vs and output pins withstand 40 v ? full path r on from 100 m (at t j = -40 c) to 300 m (at t j =150 c) ? logic inputs ttl/cmos-compatible ? operating frequency up to 20 khz ? 16-bit spi interface for configuration/diagnostics, daisy chain capability ? over temperature and short circuit protection ? v s undervoltage disable function ? v dd undervoltage and overvoltage protection ? v dd overvoltage detection ? open-load detection in on condition ? full diagnostics in off state ? enable and disable input ? low stand by current (<10 a) ? voltage and current slew-rate control for low emi, programmable through spi ? aerospace and defense features ? dedicated traceability and part marking ? production parts approval documents available ? adapted extended life time and obsolescence management ? extended product change notification process ? designed and manufactured to meet sub ppm quality goals ? advanced mold and frame designs for superior resilience to harsh environment (acceleration, emi, thermal, humidity) ? single fabrication, assembly and test site ? dual internal production source capability application all types of resistive, inductive and capacitive loads in aerospace and defense applications. description the RL9958 is an spi controlled h-bridge, designed for the control of dc and stepper motors in safety critical applications and under extreme environmental conditions. the h-bridge is protected against over temperature, short circuits and has an undervoltage lockout for all the supply voltages v s and v dd , and for overvoltage on v dd . all malfunctions cause the output stages to go tristate. detailed failure diagnostics on each channel is provided via spi: short circuit to battery, short circuit to ground, short circuit overload, over temperature. open-load can be detected in on condition, for the widest application ranges. current regulation threshold can be set by spi from 2.5 a to 8.6 a (typ.), in 4 steps. guaranteed accuracy is 10 % on all temp range, using an external reference resistor with 1% accuracy over all temp range. current limitation threshold is linearly reduced by temperature over 165 c.and a thermal warning bit is set by spi. the h-bridge contains integrated free-wheel diodes. in case of free-wheeling condition, the low side transistor is switched on in parallel of its diode to reduce power dissipation. a multiple wire bonding technique, as well as st proprietary package design is making RL9958 compatible with several power packages, for maximum flexibility: powerso-20 package (medium power, jedec standard mo166. powerso-20 '!0'03 www.st.com
contents RL9958 2/35 docid026724 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pins function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.1 di and en inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.2 dir and pwm inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.1 daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 spi communication failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 5 v and 3.3 v output compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 temperature-dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 current regulation with low-inductive loads . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 slew rate control in case of current limitation on low-side . . . . . . . . . . . . 15 5 diagnostics and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 reset requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 diagnosis reset bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 protection and on state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 over-current on high-side - short to ground . . . . . . . . . . . . . . . . . . . . . . 18 5.2.2 over-current on low-side - short to vs . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.3 short circuit over-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.4 open load in on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.5 over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.6 vs under-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.7 vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid026724 rev 1 3/35 RL9958 contents 3 5.2.8 vdd under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.9 output short protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 off-state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.1 off-state detection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.2 open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 h-bridge functional status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.1 device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.2 device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.3 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.4 digital inputs: ttl // 3.3v / 5v cmos compatible . . . . . . . . . . . . . . . . . 27 6.4.5 bridge output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.6 over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.7 current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . . 28 6.4.8 diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.9 off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.10 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables RL9958 4/35 docid026724 rev 1 list of tables table 1. powerso-20 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. control pins en, di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. control pins dir, pwm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. configuration protocol (cfg_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. diagnosis protocol (dia_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. current limitation programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 7. slew rate control on low side mos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 8. diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. vs under-voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. digital inputs: ttl // 3.3v / 5v cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. bridge output drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20. over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 21. current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 22. diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 23. off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 24. timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 26. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid026724 rev 1 5/35 RL9958 list of figures 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. h-bridge configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. spi protocol structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. fsi bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. daisy chain topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. spi zero clock communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9. current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. temperature dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. current regulation with different loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 12. slew rate switching strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. diagnostics for scb / scol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. open load in on state - low-side current recirculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. off-state detection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. off-state diagnostic principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. thermal impedance (junction-ambient) of power packages . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20. application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. powerso-20 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
block diagram RL9958 6/35 docid026724 rev 1 1 block diagram figure 1. block diagram /54 /54 96 '.$ '!4% $2)6%2 #harge0ump 63 5ndervoltage 6$$ 5nder /vervoltage #ontrol,ogic 30) 2eference currentgenerator 3/ 3) #3 3#+ 6$$)/ %. $) 07- $)2 6$$ 2%84 /vertemperature #urrent,imitation #urrent -onitor &3 $iagnostic /ver #urrent $etection /ver #urrent $etection 4o#ontrol,ogic"lock 4o#ontrol,ogic"lock 4o#ontrol,ogic"lock '!0'03
docid026724 rev 1 7/35 RL9958 pins description 34 2 pins description 2.1 pins function the exposed slug must be soldered on the pcb and connected to gnd. figure 2. pin connection (top view) table 1. powerso-20 pin function pin n name description 1 gnd ground 2 so serial out 3 vddio supply voltage for spi 4 cs chip select 5 cp charge pump 6 vs supply voltage 7 dir direction input 8 out1 output 1 9 di disable 10 gnd ground 11 gnd ground 12 en enable 13 out2 output 2 14 pwm pwm input 15 rext external reference resistor 16 si serial in 17 sck spi clock 18 vdd supply voltage 19 n.c. not connected (to be connected to gnd on the pcb) 20 gnd ground '.$ $) %. 6$$)/ #3 63 #0 $)2 /54 3/ '.$ '.$ /54 07- 3) 2%84 3#+ 6$$ .# '.$ '!0'03
device description RL9958 8/35 docid026724 rev 1 3 device description 3.1 supply range the RL9958 has an operating supply range from "vs_uv" (battery monitoring) up to 28 v. however, the device is tested until 16 v; the functionality of the device is guaranteed until 28 v. the absolute maximum rating is defined to 40 v dc. 3.2 control inputs the bridge is controlled by the inputs pwm, dir, en and di. all the digital inputs and outputs of the RL9958 are compatible with 3.3 v and 5 v cmos. the power stages output out1 and out2 are controlled by the direct inputs dir and pwm as given in table 2 . the dir input gives the direction of output current, while the pwm input controls whether the current is increased or reduced. 3.2.1 di and en inputs the pin di is internally pulled-up and high active. when di is active (set to high), the bridge is set to tristate, whatever the state of the dir and pwm inputs. all the data stored in spi registers are not reset and spi communication with the mcu is still possible. when di is inactive (set to low), the bridge is controlled by the dir and pwm inputs. the pin en is internally pulled down and high active. when en is inactive (set to low), the bridge is set to tri-state, whatever the state of the dir and pwm inputs. all the data stored in spi registers are not reset and spi communication with the mcu is still possible. when en is active (set to high), the bridge is controlled by the dir and pwm inputs. the coding is performed as shown in the next table. the state of the bridge is transferred in the diagnostic register in a bit called "act". table 2. control pins en, di en di bit ?act? bridge status 0 0 0 tri-state 0 1 0 tri-state 1 0 1 on-state 1 1 0 tri-state
docid026724 rev 1 9/35 RL9958 device description 34 3.2.2 dir and pwm inputs the pins dir and pwm are internally pulled down. the bridge is controlled by these two inputs according to the table below. figure 3. h-bridge configurations the outputs can be disabled (set to tri-state) by the disable and enable inputs di and en. input di has an internal pull-up. input en has an internal pull-down. during freewheeling phase, an active freewheeling on the low-side mos is automatically set, switching on the power transistor in parallel to the internal freewheeling diode. table 3. control pins dir, pwm dir pwm out1 out2 bridge status h h h l forward l l l l freewheeling low l h l h reverse h l l l freewheeling low '!0'03 /54 /54 ) , $)2 07-&orward /54 /54 ) , $)2 07-2everse 6 6 /54 /54 ) , $)2 07-&reewheeling ,3 /54 /54 ) , $)2 07-&reewheeling ,3 6 6
device description RL9958 10/35 docid026724 rev 1 3.3 serial peripheral interface (spi) the spi is used for bidirectional communication with a control unit, allowing ic configuration, diagnosis and identification. RL9958 can also be used in daisy-chain configuration (number of device in the daisy chain is not limited). the spi interface of RL9958 is a slave spi interface: the master is the c which provides cs and sck to RL9958. transfer format uses 16 bits word in case of single device configuration and multiple of 16 bits word in case of daisy chain configuration. the first answer after power-on-reset is the ic identifier. a command sent by the c during transfer n is answered during transfer n+1. so is clocked on sck rising edge. si is sampled on falling edge. when cs = '1' and during power- on reset, so is in tri-state. otherwise, the spi interface is always active. settings made by the spi control word become active at the end of the spi transmission and remain valid until a different control word is transmitted or a power on reset occurs. at each spi transmission, the diagnosis bits as currently valid in the error logic are transmitted. details on diagnosis are described in section 5 . figure 4. spi protocol structure between cs falling edge and sck rising edge, an internal signal called "fsi bit" is set asynchronously on so output. this can be useful to have internal information on the device without stimulating the sck clock. the definition of the fsi bit is presented in the diagnostics chapter. figure 5. fsi bit except the enable / disable bit (?act? pin), all the bits of diagnosis register are latched and can be released by: ? diagnosis register read by spi ? power-on-reset condition. the coding for the configuration and diagnosis registers is reported in the table below. '!0'03 #3 #ommand. !nswertocmd. !nswertocmd. #ommand. 3) 3/ '!0'03 #3 3#+ &3)bit 3/ ,3" -3"
docid026724 rev 1 11/35 RL9958 device description 34 table 4. configuration protocol (cfg_reg) bit name description config. value after reset 0 - lsb res reserved ? 1 dr diagnostic reset bit 0 2 cl_1 bit1 for regulation current level 0 3 cl_2 bit2 for regulation current level 1 4 res reserved ? 5 res reserved ? 6 res reserved ? 7 res reserved ? 8 vsr voltage slew rate control value 0 9 isr current slew rate control value 0 10 isr_dis current slew rate control disable 0 11 ol_on open load in on state enable 0 12 res reserved ? 13 res reserved ? 14 0 ?0? to be written ? 15-msb 0 ?0? to be written ? table 5. diagnosis protocol (dia_reg) bit name description status after reset bit state dr impact h-bridge status 0-lsb ol_off open load in off condition 0 latched ? ? 1 ol_on open load in on condition 0 latched ? ? 2 vs_uv vs undervoltage 0 not latched ? hi-z if ?1? 3 vdd_ov vdd overvoltage 0 latched x hi-z if ?1? 4 ilim current limitation reached 0 latched ? ? 5 twarn temperature warning 0 latched ? ? 6 tsd over-temperature shutdown 0 latched x hi-z if ?1? 7 act bridge enable 1 not latched ? hi-z if ?0? 8 oc_ls1 over-current on low side 1 0 latched x hi-z if ?1? 9 oc_ls2 over-current on low side 2 0 latched x hi-z if ?1? 10 oc_hs1 over-current on high side 1 0 latched x hi-z if ?1? 11 oc_hs2 over-current on high side 2 0 latched x hi-z if ?1? 12 null not used ? ? ? ? 13 null not used ? ? ? ? 14 sgnd_off short to gnd in off condition 0 latched ? ? 15-msb sbat_off short to battery in off condition 0 latched ? ?
device description RL9958 12/35 docid026724 rev 1 3.3.1 daisy chain operation several RL9958 can be connected to one spi connection in daisy chain operation to save c interface pins. the number of devices connected in daisy chain is unlimited. figure 6. daisy chain topology 3.4 spi timing figure 7. spi timing '!0'03 singlechain 4wodevisesinonedaisychain 4hreedevisesinonedaisychain shiftregister ?# 3#+ #3 3#+ 3#+ #3 #3 3#+ #3 3#+ #3 3#+ #3 3#+ #3 #3 #3 )## )#" )#! #3lowforclocks3#+ #3lowforclocks3#+ #3lowforclocks3#+ readsfrom)#! # readsfrom)#$ % readsfrom)#& writesfrom)#$ % writesfrom)#& writesinto)#! # )#$ )#% )#& 3/ 3) 3) 3/ 3) 3/ 3) $/ 3) 3/ 3) 3/ 3) 3/ shiftregister shiftregister shiftregister shiftregister shiftregister shiftregister '!0'03 t #..#3 t hclch t sclcl t cll t clh t hclcl t sclch t csdv t pcld t scld t hcld t pchdz -3" -3" ,3" ,3" &3) 3/ 3) 3#+ #3
docid026724 rev 1 13/35 RL9958 device description 34 3.5 spi communication failure in case of "no sck edge" when cs = '0', the transfer is considered as valid: no error is returned to the c. the answer of last command is sent during next transfer. when the number of sck period is different from 0 or multiple of 16, next spi answer is all zero. figure 8. spi zero clock communication 3.6 5 v and 3.3 v output compatibility in order to ensure a full compatibility with 5 v and 3.3 v mcu peripherals, the pin vddio is dedicated to supply the output buffer of so. the overall current consumption on vddio is "ivddio". a parasitic current from the pin so could flow through the pin vddio in case of over-voltage on so pin vs. vddio pin. '!0'03 #3 3) &3)bit 3/ #ommand. #ommand. !nswertocmd. !nswertocmd.
current regulation RL9958 14/35 docid026724 rev 1 4 current regulation to protect the actuator and limit power dissipation, a two-level chopper current limitation is integrated as shown in figure below. the current is measured by sense cells integrated in the low-side switches. as soon the upper current limit ?ih? is reached, both low-side drivers are switched on to allow free-wheeling recirculation, until the lower current limit ?il? is reached. during the current regulation, all the slew rate controls are disabled in order to minimize the power dissipation. four current limit levels can be set by the spi control bits 0 and 1. in order to achieve very precise current threshold and ripple, an external resistance is required (1 % accuracy on all temp range/lifetime) to generate a current reference. detailed values for current thresholds and ripple are reported in table 6 . figure 9. current limitation 4.1 temperature-dependent current regulation in order to reduce power dissipation and thus the junction temperature, above a temperature twarn = 160 c, current regulation high limit linearly decreases with temperature, to reach about 2.5 a at tsd = 175 c (shutdown temperature). when this thermal threshold is reached during a current limitation phase, the information is stored and latched in a coding of bits called " twarn ". this bit can be reset only if the settings conditions (t j > twarn and i lim = 0) are not present anymore. this feature is mainly used to reduce the power dissipation and thus the junction temperature. table 6. current limitation programmability cl_2 cl_1 current limit (typical values) 0 0 2.5 a 0 1 4 a 1 0 6.6 a (default value) 1 1 8.6 a '!0'03 time ,imitation#urrent tb"lankingtime tb"lankingtime #urrent )( ),
docid026724 rev 1 15/35 RL9958 current regulation 34 figure 10. temperature dependent current regulation 4.2 current regulation with low-inductive loads each time output stages are turned off, an internal timing starts for duration toff-min . whenever turn-on is reached in a time toff that is shorter than toff-min , output stages are kept off, until toff-min is reached. in such case the ripple control could be not so precise as specified. figure 11. current regulation with different loads 4.3 slew rate control in case of current limitation on low-side the slew rate control can be done on voltage and current or only on voltage. this can be selected by spi through the bit isr_dis. the slew rate of each high-side power transistor of the bridge is controlled either during turn-on and turn-off (current and voltage slew rate). the same setting is applied for both switching. moreover, this slew rate is configurable by spi in order to get the best trade-off between conducted/radiated emi and power dissipation during switching. the slew rate '!0'03 ) 4war n 4sd 4j '!0'03 tb #urrent )( ), tb time tb 4off 4off 4off min 4off min /54 (igh)nductive,oad ,ow)nductive,oad
current regulation RL9958 16/35 docid026724 rev 1 selection can be done "on the fly" by spi. the corresponding bits are called " vsr " and " isr ". no external component is needed to select the slew rate range. only the power transistors not used for freewheeling can be adjusted, the two others can be controlled with a preset slew rate. the couples of value defined to fulfill most of the application requirements are described in the table below. the required accuracy is 50 % for an output current from 1a to 8a and with output voltage up to 19 v. the overall delay implemented between high-side and low- side transistor switching must be adjusted automatically to avoid any cross-conduction through one half-bridge in all conditions. in case of current limitation and any detection that put the bridge in tri-state, the slew rate is not related anymore to the preset bits " vsr "; " isr " but to a dedicated faster slew rate control named "super fast" mode. the automatic change from spi selectable to super fast slew rate is described hereafter. figure 12. slew rate switching strategy table 7. slew rate control on low side mos range vsr isr dv/dt (v/ s) di/dt (a/ s) 1 ( default value )0 0 4 3 2 0 1 4 0.3 3102 3 4 1 1 2 0.3 no sr control not selectable 14 14 t off min timeisstartedateach(3switched /&&whilein3&23mode endofblanking/207-fallingedge t off min t b t b t off min t off min 7hen)), andaftert off min andi?pwmgg 2,gobackto.32 otherwise2,remains in3&32mode )( ) ,3 t .32
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docid026724 rev 1 17/35 RL9958 diagnostics and protections 34 5 diagnostics and protections a detailed diagnostic of the h-bridge is available through spi communication. the 16 bits diagnostic word is sent back to the mcu in return of a command word. the diagnostic word is used to report two kinds of information: ? h-bridge failures: ? over-current on each transistor in on-state, ? vps under-voltage, ? vdd over-voltage, ? over-temperature, ? open-load in on-state, ? off-state diagnostic. ? h-bridge functional status: ? current limitation condition, ? current limitation decreasing condition, ? disable / enable status. 5.1 diagnosis reset strategy 5.1.1 reset requests except "act" and "vs_uv" bits, all the others are latched and can only be released by: ? transition from "disable" to "enable" on di / en pins, ? diagnostic register read by spi (see details on each failure release) depending on bit "dr", ? power-on-reset condition. when the diagnostic register is reset, the bridge is switched back to normal mode driven by dir and pwm. all the settings are kept as before the failure. in case of spi read, no additional action on di / en is needed. 5.1.2 diagnosis reset bit in case of "dr" set to low (default value), all the bits of the diagnostic register can be reset by the three possibilities described in previous section. in case of "dr" set to high, the over-current, vdd over-voltage and over-temperature diagnostic bits can not be reset by spi read and therefore, the bridge is kept in tri-state until a transition from "disable" to "enable" on di/en pins or power-on-reset condition. table 8. diagnosis reset strategy dr diagnosis reset strategy 0 all diagnostic bits reset at each spi reading (default) 1 over current bits (8..11) + temp. shutdown tsd bit (6) + vdd over voltage bit (3) not reset by spi
diagnostics and protections RL9958 18/35 docid026724 rev 1 5.2 protection and on state diagnostics RL9958 is protected against short circuits, overload and invalid supply voltage by the following measures. 5.2.1 over-current on high-side - short to ground the high-side switches are protected against a short of the output to ground by an over- current shutdown. if a high-side switch is turned on and the current rises above the short circuit detection current ioc all output transistors are turned off after a filter time toc_ls and the error bits "overcurrent on high side 1 (2)", oc_hs1 ( oc_hs2 ) are stored in the internal status register. 5.2.2 over-current on low-side - short to vs due to the chopper current regulation, the low-side switches are already protected against a short to the supply voltage. to be able to distinguish a short circuit from normal current limit operation, the current limitation is deactivated for the blanking time t b after the current has exceeded the current limit threshold ih. if the short circuit detection current i oc is reached within this blanking time, a short circuit is detected. all output transistors are turned off and the according error bit ?over-current on low side 1 (2)?, oc_ls1 ( oc_ls2 ) is set. 5.2.3 short circuit over-load if, during the blanking time ( t b ) of the current regulation mode, the current reaches the i oc threshold; after a filtering time, the output mos are switched off and the ?short circuit over load? can be checked by the reading of the overcurrent bits of the dia_reg (please refer to table 5 bit 8, 9,10 and 11). figure 13. diagnostics for scb / scol 5.2.4 open load in on state to perform the open load diagnosis in on state, the flag ol_on has to be set high through spi. after every open load diagnosis in on state, the ol_on flag is resetted, to perform a new open load diagnosis in on state the ol_on flag has to be set again. '!0'03 time tb"lankingtime #urre /vercurrent faultdetected 4racking nt )( ), )oc tb"lankingtime /. /utput stage /&&
docid026724 rev 1 19/35 RL9958 diagnostics and protections 34 this disable the turning on of the low-side drivers during current recirculation. the current flows through the body diode of the low-side mos for a fixed time. at the end of this fixed time the vout voltage is sampled and the possible open load condition detected (see figure 14 ). figure 14. open load in on state - low-side current recirculation 5.2.5 over-temperature when twarn is reached, thermal current reduction is activated, and the information is stored and latched. when tsd is reached, the ? tsd ? bit is set and all output transistors are put in tri-state conditions as long as a reset is applied. 5.2.6 vs under-voltage shutdown if the supply-voltage at the v s pins falls below the under-voltage detection threshold vs_uv_off , the outputs are set to tri-state and the error bit "undervoltage at v s " is set. a filtering time " tuv_vs " is implemented to avoid unwanted detection due to parasitic glitches. the information is transferred into the spi register in a bit called " vs_uv ". this bit is not latched. as soon as the voltage rises again above the vs under-voltage threshold (hysteresis implemented), the bridge is switched back to normal mode driven by dir and pwm. all the settings are kept as before the under-voltage event. '!0'03 07- /,?/. &!5,4 6 '.$ ,/73)$% 2%#)2#5,!4)/. $iangonsis /&& $iangonsis /. reset set reset ,3 -/3/. ,3 -/3 /. 4u c 4u c ,3-/3 /&& ,3-/3 /&& 6/54x set /0%.,/!$$%4%#4%$ /0%.,/!$/##522%$ 30) activity towrite/,?/."it table 9. over-temperature tsd comments bridge state fsi 1 tj > tsd tri-state- 1 0 (default) tj < tsd - 0
diagnostics and protections RL9958 20/35 docid026724 rev 1 figure 15. battery voltage monitoring 5.2.7 vdd over-voltage detection although the vdd input pin and all i/o's are able to withstand up to 19 v, an over-voltage circuitry is implemented to ensure that the bridge is kept in tri-state when the vdd voltage is higher than the vdd overvoltage threshold " vdd_ov_off " for duration longer than " tov_vdd ". the information is detected and stored into the spi register in a bit called " vdd_ov ". the bridge is kept in tri-state as long as an appropriate reset is not requested (see section 5.1 ). 5.2.8 vdd under-voltage detection when the vdd voltage falls below the under-voltage detection threshold " vdd_uv_off " for duration longer than " tuv_vdd ", the bridge is switched to tri-state. in such a condition, the RL9958 is going in sleep mode. when the voltage increases above the threshold (hysteresis implemented), the RL9958 starts with all the settings reset to their default values (power on reset). 5.2.9 output short protection the RL9958 can sustain short on the outputs. in case of short to gnd, short to battery or short between outputs the battery voltage cannot exceed 18 v. the connection of a 100 f plus a 1 f decoupling capacitors as close as possible to v s pin and the gnd connection of the slug or of the exposed pad is mandatory to improve the robustness. table 10. vs under-voltage vs_uv comments bridge state fsi 1 vs < vs_uv_off hi z 1 (not latched) 0 (default) vs > vs_uv_on - 0 '!0'03 6s 6s?uv 63?56 4uv?vs t4uv?vs "ridge 3tate /. 34!4% 42) 34!4% /. 34!4% table 11. vdd over-voltage detection vdd_ov comments bridge state fsi 1 vdd > vdd_ov_off hi-z 1 (latched) 0 (default) vdd < vdd_ov_on - 0
docid026724 rev 1 21/35 RL9958 diagnostics and protections 34 5.3 off-state diagnosis this diagnostic is performed in any off-state condition, just after ignition key-on or during an off-state phase occurring after an on-state phase of the bridge. 5.3.1 off-state detection scheme in order to avoid any wrong diagnostic, a filtering time " tdiag_off " is applied before performing the detection if the bridge was in on-state before. this filtering time is not applied in case of detection after key on. figure 16. off-state detection scheme 5.3.2 open load detection an equivalent resistor of 100 k (typ.) is targeted for open-load detection. in order to avoid any unwanted supply of the bridge through the high-side transistor body diode during off-state measurement, the current source is connected only if vs is higher than the vs under-voltage threshold. figure 17. open load detection the diagnostic is based on a closed loop voltage control on out1 and associated current measurement. a voltage amplifier forces a constant voltage on out1 through two current sources (high- side source and low-side current sink). the out2 is pulled-down through a constant current sink. based on the current flowing out of the amplifier (ip ? in) compared to several current thresholds, open-load as well as short-circuit to ground and battery can be detected. '!0'03 0/2 $) /&& /&& /&& /&& 3,%%0 /. /. /. %. $)!' 30) 4 diag?off 4 diag?off $iag $one $iag $one $iag $one .o $iag .o $iag .o $iag .o $iag .o $iag .o $iag .o $iag .o $iag $iag $one .o $iag .o $iag .o $iag .o $iag .o $iag .o $iag '!0'03 k k k ,/!$#/..%#4%$ /0%.,/!$ 4ypicalvalue fordetection
diagnostics and protections RL9958 22/35 docid026724 rev 1 figure 18. off-state diagnostic principle 5.4 h-bridge functional status three bits in the diagnosis register are used to give a feedback about the state of the h- bridge. status are current limitation (bit 4 "c_lim"), temperature warning (bit 5 "t_wrn") and bridge enable status (bit 7 "act"). those bits do not report a failure but only a functional state of the h-bridge that could be useful to change the control strategy mainly in term of power dissipation. )pl )n )n 6dd 6?")!3 )ph #urrent-irror and#omparator #urrent-irror and#omparator 6dd cmd?diag cmd?diag )?diag 6dd 37)4#(! ,/!$ 37)4#(" #522%.43).+ 6ps 6ps '!0'03
docid026724 rev 1 23/35 RL9958 electrical specifications 34 6 electrical specifications 6.1 absolute maximum ratings the component must withstand the overall following stimulus without any damage or latch- up. beyond these values, damage to the component may occur. note: in case of load dump condition, status of device outputs is kept unchanged. 6.2 thermal data table 12. absolute maximum ratings symbol parameter test condition min. max. unit v ps supply voltage continuous transient (0.5 s; i ? 10 a) -1 -2 40 40 v v dd logic supply voltage 0 v < v ps < 40 v -0.3 19 v v ddio sdo supply voltage 0 v < v ps < 40 v -0.3 19 v v i logic input voltage 0 v < v ps < 40 v 0 v < v dd < 19 v -0.3 19 v v o logic output voltage 0 v < v ps < 40 v 0 v < v dd < 18.7v -0.3 vddio+0.3 v output pins (outx, vps) esd compliance eia/jesd22-a114-b 4 - kv input pins 2 - - iso 7637 pulses cf. standards - - - - latch-up immunity jedec standard -100 +100 ma table 13. thermal data symbol parameter test condition min. max. unit t j junction temperature failure condition -40 otsd c lifetime -40 150 t stg storage temperature - -55 150 c t amb ambient temperature 0 v < v ps < 40 v -40 125 c r thj-case thermal resistance junction to case (1) - - 1 c/w 1. guaranteed by design and package characterization.
electrical specifications RL9958 24/35 docid026724 rev 1 figure 19. thermal impedance (junction-ambient) of power packages 6.3 range of functionality within the range of functionality, all RL9958 functionalities have to be guaranteed. all voltages refers to gnd. currents are positive into and negative out of the specified pin. '!0'03 4imes :4(?#7 0w33/onsp 0w33/onspthenh 0w3/onsp 0w3/onspthenh 4imes :4(?#7 0w33/onsp 0w33/onspthenh 0w3/onsp 0w3/onspthenh table 14. range of functionality pos. symbol parameter test condition min. typ. max. unit fr1 v ps supply voltage - vps_uv_off 14 28 (1) v fr2 dv ps /d t supply voltage slew rate - -20 - 20 v/ s fr3 v dd logic supply voltage - vdd_uv_off 5 vdd_ov_off v fr4 dv dd /d t logic supply voltage slew rate - - - 0.025 (2) v/ s fr5 v i logic input voltage (sdi, sclk, ncs, di, en, dir, pwm) see also table 12: absolute maximum ratings . -0.3 - vdd_ov_off v fr6 v ddio sdo output voltage - 3 - 5.5 v fr7 f spi spi clock frequency - - - 5 mhz 1. in load dump conditions v ps ranges between 28v and 40v. during load dump, status of device outputs is kept unchanged, 2. to vdd pin are connected 10 f and 10nf (close to the pin) capacitors.
docid026724 rev 1 25/35 RL9958 electrical specifications 34 6.4 electrical characteristics t case = -40 c to 125 c unless otherwise specified, v dd = 4.5 v to 5.5 v unless otherwise specified v ps = 4 v to 28 v unless otherwise specified all voltages refer to gnd. currents are positive into and negative out of the specified pin. 6.4.1 device supply 6.4.2 device supply monitoring table 15. device supply pos. symbol parameter test condition min. typ. max. unit 1.1 i ps power supply current v dd < 0.7 v; v ps = 16 v from -40 c to 25 c --20 a v dd < 0.7 v; v ps = 16 v at 125 c --35 a f pwm = 0, i out = 0 - - 20 ma 1.2 i out leakage current on output bridge in tri-state - - 100 a 1.3 i cc logic-supply current v dd >v dd_uv_on f pwm = 0 --5ma f pwm = 20 khz (average value) --5ma table 16. device supply monitoring pos. symbol parameter test condition min. typ. max. unit 2.1 v ps_uv_off v ps under-voltage threshold v ps decreasing - - 4 v 2.2 v ps_uv_on v ps under-voltage threshold v ps increasing - - 4.5 v 2.3 v ps_uv_hyst v ps under-voltage hysteresis - 0.1 - - v 2.4 t uv_vps v ps under-voltage filtering time v ps decreasing 1 - 3 s 2.5 v dd_uv_off v dd under-voltage threshold v dd decreasing 3 - 3.7 v 2.6 v dd_uv_on v dd under-voltage threshold v dd increasing 3.3 - 4 v 2.7 v dd_uv_hyst v dd under-voltage hysteresis - 0.1 - - v 2.8 t uv_vdd v dd under-voltage filtering time v dd decreasing 1 - 4 s 2.9 v dd_ov_off v dd over-voltage threshold v dd increasing 5.8 - 6.8 v 2.10 v dd-ov_on v dd over-voltage threshold v dd decreasing 5.5 - 6.5 v 2.11 v dd_ov_hyst v dd over-voltage hysteresis - 0.1 - - v 2.12 t ov_vdd v dd over-voltage filtering time v dd increasing 60 100 140 s
electrical specifications RL9958 26/35 docid026724 rev 1 6.4.3 spi table 17. spi pos. symbol parameter test condition min. typ. max. unit 3.1 f spi clock frequency (50 % duty cycle) - - - 5 mhz 3.2 t sdo_trans sdo transition speed, 20-80 % v sdo = 5v, c load = 50 pf (1) 5 - 30 ns v sdo = 5 v, c load = 150 pf 5 - 50 ns 3.3 t clh minimum time sclk = high - 75 - ns 3.4 t cll minimum time sclk = low - 75 - ns 3.5 t pcld propagation delay (sclk to data at 10% of sdo rising edge) ---40ns 3.6 t csdv ncs = low to data at sdo active ---85ns 3.7 t sclch sclk low before ncs low (setup time sclk to ncs change h/l) -75--ns 3.8 t hclcl sclk change l/h after ncs = low -75--ns 3.9 t scld sdi input setup time (sclk change h/l after sdi data valid) -40--ns 3.10 t hcld sdi input hold time (sdi data hold after sclk change h/l) -40--ns 3.11 t sclcl sclk low before ncs high - 100 - - ns 3.12 t hclch sclk high after ncs high - 100 - - ns 3.13 t pchdz ncs l/h to sdo @ high impedance ---75ns 3.14 t onncs ncs min. high time - 300 - ns 3.15 - capacitance at sdi, sclk; ncs - - - 14 pf - capacitance at sdo - - - 19 pf 3.16 t fncs ncs filter time will be ignored) guaranteed by design (pulses = tfncs guaranteed by design 10 - 40 ns 3.17 v ddio supply voltage for sdo output buffer - 3 - 5.5 v 3.18 sdo_h high output level on sdo i sdo = 1.5 ma v ddio - 0.4 --v 3.19 sdo_l low output level on sdo i sdo = 2 ma - - 0.4 v 3.20 i sdo tri state leakage current ncs = high v ddio = 5 v -5 - 5 a 1. not tested ? guaranteed by c load = 150 pf measurement
docid026724 rev 1 27/35 RL9958 electrical specifications 34 6.4.4 digital inputs: ttl // 3.3v / 5v cmos compatible 6.4.5 bridge output drivers table 18. digital inputs: ttl // 3.3v / 5v cmos compatible pos. symbol parameter test condition min. typ. max. unit 4.1 v ih input voltage high - 2 - vdd+0.3 v 4.2 v il input voltage low - -0.3 - 0.8 v 4.3 hysteresis of input voltage - 200 - - mv 4.4 i inl input current source for: di / ncs / sclk / sdi v in = 0 v -100 - -30 a v in = 5 v no back supply allowed -- 5 4.5 i inh input current sink for: en / dir / pwm v in = 5 v 30 - 100 a v in = 0 v -5 - - 4.6 v rext external resistor - - 1.24 - v r ext --10-k overall tolerance can be taken as 3.5 % -1 -% table 19. bridge output drivers pos. symbol parameter test condition min. typ. max. unit 5.1 r dson_h high-side transistor r dson t j = 150 c, i out = 3 a 4 v < v ps < 5 v - - 300 m t j = 150 c, i out = 3 a v ps > 5 v - - 150 5.2 r dson_l low-side transistor r dson t j = 150 c, i out = 3 a 4 v < v ps < 5 v - - 300 m t j = 150 c, i out = 3 a v ps > 5 v - - 150 5.3 v bd_h body diode forward voltage drop high-side transistor i diode = 3 a - 1.2 2 v 5.4 v bd_l body diode forward voltage drop low-side transistor i diode = 3 a - 1.2 2 v
electrical specifications RL9958 28/35 docid026724 rev 1 6.4.6 over-temperature monitoring 6.4.7 current limitation and over-current detection table 20. over-temperature monitoring pos. symbol parameter test condition min. typ. max. unit 6.1 otwarn over-temperature warning - 150 - 170 c 6.2 otsd over-temperature shut-down - 170 - 200 c 6.3 othyst over-temperature hysteresis - 10 - - c 6.4 t tsd over-temperature filtering time guaranteed by clock measurement -36- s table 21. current limitation and over-current detection pos. symbol parameter test condition min. typ. max. unit 7.1 i lim_h current limitation high threshold cl1:0 = 00; -40 c t j 150 c 2 2.5 3.1 a cl1:0 = 01; -40 c t j 150 c 3.5 4 4.85 cl1:0 = 10; -40 c t j < 25 c 5.5 6.75 8 cl1:0 = 10; 25 c t j 150 c 5.5 6.6 7.7 cl1:0 = 11; -40 c t j < 25 c 7.8 9.1 10.4 cl1:0 = 11; 25 c t j 150c 7.6 8.6 9.6 cl1:0 = xx, t j = otsd 2 2.5 3 7.2 i lim_l current limitation low threshold cl1:0 = 0x; -40 c t j 150 c i lim_h ?0.2 i lim_h - 0.5 i lim_h - 0.8 a cl1:0 = 10; -40c t j < 25 c i lim_h ? 0.35 i lim_h - 0.65 i lim_h - 0.95 cl1:0 = 10; 25 c t j 150c i lim_h ? 0.35 i lim_h - 0.55 i lim_h - 0.85 cl1:0 = 11; -40c t j < 25c i lim_h ?0.4 i lim_h - 0.7 i lim_h -1 cl1:0 = 11; 25 c t j 150c i lim_h ?0.4 i lim_h - 0.55 i lim_h - 0.95 7.3 t limh high current limitation threshold filtering time can be included in t blanck 0.1 - 1 s 7.4 t liml low current limitation threshold filtering time -1-3 s 7.5 t offmin current limitation delay time -30-45 s 7.6 t b blanking time - 4.9 - 8.7 s
docid026724 rev 1 29/35 RL9958 electrical specifications 34 6.4.8 diagnostic of open-load in on-state 6.4.9 off-state diagnostic 7.7 ioc_ls ioc-hs low-side over-current threshold high-side over-current threshold cl1:0 = 0x; -40 c t j 150 c 5.5 7.7 11 a cl1:0 = 1x; -40c t j < 25 c 9.3 12 16.5 cl1:0 = 1x; 25 c t j 150c 9.3 11.5 14 tracking cl1:0 = 0x; cl1:0 = 10; -40 c t j 150 c i lim_h +2 - - cl1:0 = 11; -40 c t j 150 c i lim_h +1.3 - - 7.8 toc_ls toc_hs low-side & high-side over-current detection filtering time - 0.8 - 2.5 s table 21. current limitation and over-current detection (continued) pos. symbol parameter test condition min. typ. max. unit table 22. diagnostic of open-load in on-state pos. symbol parameter test condition min. typ. max. unit 8.1 is_ol-on current source t j = -40 c (go-no-go functional test) 50 - 120 a t j = 25 c to 150 c (go-no-go functional test) 50 - 100 8.2 tmeas_on detection time (settling time) - - 3 5 s table 23. off-state diagnostic pos. symbol parameter test condition min. typ. max. unit 9.1 r ol load detection threshold 10 60 200 k 9.2 tdiag_off delay time before enabling off- state diagnostic structure diag after on-state guaranteed through scan 100 125 150 ms 9.3 t diag-off_1 off-state diag filtering time when out 1 and/or 2 decrease from v ps used each time out pins are released from vps (after release of scb, after tdiag_off) guaranteed through scan 2.4 3 3.6 ms 9.4 t diag_off_2 off-state diagnostic filtering time on failure detection one symmetric filter for each failure type (ol, scg, scb) guaranteed through scan 200 250 300 s 9.5 t clock oscillator frequency - 4 - 6 mhz
electrical specifications RL9958 30/35 docid026724 rev 1 6.4.10 timing characteristics table 24. timing characteristics pos. symbol parameter test condition min. typ. max. unit 10.1 f pwm pwm frequency - - - 20 khz 10.2 t don delay time for switch-on r load @ i out = 3 a pwm 90% v out (or 10 % i out ) --10 s t doff delay time for switch-off r load @ i out = 3 a pwm 10 % v out (or 90% iout) --10 s ? t d delay time: symmetry pwm accuracy = 1% @ 2khz --5 s 10.3 t d_dis disable delay time di / en 90% outx @ i out = 3 a --6 s 10.4 t d_en enable delay time di / en 10 % out - - 6 s 10.5 t d_pow power-on delay time dir= pwm=en=1 / di=0 no load / v ps = v dd increasing v ps = v dd 10 % v out1 (= v ps ) - - 200 s 10.6 t d_filter di / en digital filter time - 1 - 3 s 10.7 t rise_h low-side transistor rise time non selectable by spi 0.04 - 0.2 s 10.8 t fall_h low-side transistor fall time non selectable by spi 1 - 3 s 10.9 dv out/ d t voltage slew rate for high-side transistors (measurement is performed between 30 % and 70 % of the slope) super fast mode 7 14 24 v/ s vsr = 0 2 4 6 vsr = 1 1 2 3 10.10 di out /d t current slew rate for high-side transistors (measurement is performed between 40 % and 60 % of the slope) isr=0 1.5 3 4.5 a/ s isr=1 0.15 0.3 0.45 10.11 t diag timing for reliable diagnostic guaranteed through scan pattern 35 - 55 s
docid026724 rev 1 31/35 RL9958 application circuit 34 7 application circuit figure 20. application circuit 1. the above application diagram shows all the suggested components for a proper device operation. '!0'03 /54 /54 63 #0 "!44%29 )# ?& 6 6 66 $# '.$s 6$$ 3/ 3) 3#+ .#3 $)2 07- %. $) 2%84 ?# 0ower3upply 6$$)/ /54 63 #0 "!44%29 ?& '.$s 6$$ 3/ 3) 3#+ .#3 $)2 07- %. $) 2%84 6$$)/ n& n& ?& n& n& k 7 k 7 k 7 n&
order codes RL9958 32/35 docid026724 rev 1 8 order codes table 25. ordering information order code package packing RL9958 powerso-20 tube RL9958tr tape & reel
docid026724 rev 1 33/35 RL9958 package information 34 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 21. powerso-20 mechanical data and package dimensions /54,).%!.$ -%#(!.)#!,$!4! e a ! % a 03/-%# $%4!),! 4 $ % % hx? $%4!),! lead slug a 3 'age0lane , $%4!)," 2 $%4!)," #/0,!.!2)49 '# # 3%!4).'0,!.% e b c . . ( "/44/-6)%7 % $ $)- mm inch -). 490 -!8 -). 490 -!8 ! a a a b c $ $ % e e % % % ' ( h , . ?typ 3 ?max 4 h$and%vdonotincludemoldflashorprotusions -oldflashorprotusionsshallnotexceedmmv #riticaldimensionsh%vh'vandhav &orsubcontractorsthelimitistheonequotedinjedec-/ 0ower3/ ) *%$%#-/ 7eight gr '!0'03
revision history RL9958 34/35 docid026724 rev 1 10 revision history table 26. document revision history date revision changes 16-sep-2014 1 initial release.
docid026724 rev 1 35/35 RL9958 35 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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