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november 2011 doc id 13675 rev 7 1/28 AN2586 application note getting started with stm32f 10xxx hardware development introduction this application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. it shows how to use the low-density value line, low-density, medium-density value line, medium-density, high-density, xl-density and connectivity line stm32f10xxx product families and describes the minimum hardwar e resources required to develop an stm32f10xxx application. detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. glossary low-density value line devices are stm32f100xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. medium-density value line devices are stm32f100xx microcontrollers where the flash memory density ranges between 64 and 128 kbytes. medium-density devices are stm32f100xx, stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 64 and 128 kbytes. high-density value line devices are stm32f100xx microcontrollers where the flash memory density ranges between 256 and 512 kbytes. high-density devices are stm32f101xx and stm32f103xx microcontrollers where the flash memory density ranges between 256 and 512 kbytes. xl-density devices are stm32f101xx and stm32f103xx microcontrollers where the flash memory density ranges between 768 kbytes and 1 mbyte. connectivity line devices are stm32f105xx and stm32f107xx microcontrollers. www.st.com
contents AN2586 2/28 doc id 13675 rev 7 contents 1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 independent a/d converter supply and reference voltage . . . . . . . . . . . . 6 1.1.2 battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 power on reset (por) / power down reset (pdr) . . . . . . . . . . . . . . . . . . 8 1.3.2 programmable voltage detector (pvd) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.3 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 hse osc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 external source (hse bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.2 external crystal/ceramic resonator (hse crystal) . . . . . . . . . . . . . . . . . 12 2.2 lse osc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 external source (lse bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 external crystal/ceramic resonator (lse crystal) . . . . . . . . . . . . . . . . . . 13 2.3 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 swj debug port (serial wire and jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.1 swj debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.2 flexible swj-dp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.3 internal pull-up and pull-down resistors on jtag pins . . . . . . . . . . . . . . 19 4.3.4 swj debug port connection with standard jtag connector . . . . . . . . . 19
AN2586 contents doc id 13675 rev 7 3/28 5 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 ground and power supply (v ss , v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5 other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6 unused i/os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.3 boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.4 swj interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
list of tables AN2586 4/28 doc id 13675 rev 7 list of tables table 1. boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2. debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. swj i/o pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AN2586 list of figures doc id 13675 rev 7 5/28 list of figures figure 1. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. pvd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. jtag connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. typical layout for v dd /v ss pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14. stm32f103ze(t6) microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 24
power supplies AN2586 6/28 doc id 13675 rev 7 1 power supplies 1.1 introduction the device requires a 2.0 v to 3.6 v operating voltage supply (v dd ). an embedded regulator is used to supply the internal 1.8 v digital power. the real-time clock (rtc) and backup registers can be powered from the v bat voltage when the main v dd supply is powered off. figure 1. power supply overview note: v dda and v ssa must be connected to v dd and v ss , respectively. 1.1.1 independent a/d converter supply and reference voltage to improve conversion accuracy, the adc has an independent power supply that can be filtered separately, and shielded from noise on the pcb. the adc voltage supply input is available on a separate v dda pin an isolated supply ground connection is provided on the v ssa pin when available (depending on package), v ref? must be tied to v ssa . on 100-pin and 144-pin packages to ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage adc input on v ref+ . the voltage on v ref+ may range from 2.4 v to v dda . a/d converter v dd v ss i/o ring bkp registers temp. sensor reset block standby circuitry pll (wakeup logic, iwdg) rtc voltage regulator core memories' digital peripherals low voltage detector (v ssa ) v ref? v dda domain v dd domain 1.8 v domain backup domain lse crystal 32 khz oscillator rcc bdcr register ai14863 (from 2.4 v up to v dda ) v ref+ (v dd ) v dda (v ss ) v ssa (v dd ) v bat
AN2586 power supplies doc id 13675 rev 7 7/28 on packages with 64 pins or less the v ref+ and v ref- pins are not available, they are internally connected to the adc voltage supply (v dda ) and ground (v ssa ). 1.1.2 battery backup to retain the content of the backup registers when v dd is turned off, the v bat pin can be connected to an optional standby voltage supplied by a battery or another source. the v bat pin also powers the rtc unit, allowing the rtc to operate even when the main digital supply (v dd ) is turned off. the switch to the v bat supply is controlled by the power down reset (pdr) circuitry embedded in the reset block. if no external battery is used in the application, it is highly recommended to connect v bat externally to v dd . 1.1.3 voltage regulator the voltage regulator is always enabled after reset. it works in three different modes depending on the application modes. in run mode, the regulator supplies full power to the 1.8 v domain (core, memories and digital peripherals) in stop mode, the regulator supplies low power to the 1.8 v domain, preserving the contents of the registers and sram in standby mode, the regulator is powered off. the contents of the registers and sram are lost except for those concerned with th e standby circuitry and the backup domain. 1.2 power supply schemes the circuit is powered by a stabilized power supply, v dd . caution: ? if the adc is used, the v dd range is limited to 2.4 v to 3.6 v ? if the adc is not used, the v dd range is 2.0 v to 3.6 v the v dd pins must be connected to v dd with external decoupling capacitors (one 100 nf ceramic capacitor for each v dd pin + one tantalum or ceramic capacitor (min. 4.7 f typ.10 f). the v bat pin can be connected to the external battery (1.8 v < v bat < 3.6 v). if no external battery is used, it is recommended to connect this pin to v dd with a 100 nf external ceramic de coupling capacitor. the v dda pin must be connected to two external decoupling capacitors (100 nf ceramic + 1 f tantalum or ceramic). the v ref+ pin can be connected to the v dda external power supply. if a separate, external reference voltage is applied on v ref+ , a 100 nf and a 1 f capacitors must be connected on this pin. in all cases, v ref+ must be kept between 2.4 v and v dda . additional precautions can be taken to filter analog noise: ?v dda can be connected to v dd through a ferrite bead. ?the v ref+ pin can be connected to v dda through a resistor (typ. 47 ).
power supplies AN2586 8/28 doc id 13675 rev 7 figure 2. power supply scheme 1. optional. if a separate, external reference voltage is connected on v ref+ , the two capacitors (100 nf and 1 f) must be connected. 2. v ref + is either connected to v dda or to v ref . 3. n is the number of v dd and v ss inputs. 1.3 reset and power supply supervisor 1.3.1 power on reset (por) / power down reset (pdr) the device has an integrated por/pdr circuitry that allows proper operation starting from 2v. the device remains in the reset mode as long as v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. for more details concerning the power on/power down reset threshold, refer to the electrical characteristics in the low- density, medium-density, high-density, xl-d ensity, and connectivity line stm32f10xxx datasheets. figure 3. power on reset/power down reset waveform v bat stm32f10xxx n 100 nf v dd + 1 10 f 100 nf + 1 f 100 nf + 1 f (note 1) battery v bat v ref+ v dda v ssa v ref? v dd 1/2/3/.../n v ss 1/2/3/.../n v ref v dd ai14865b v dd por pdr 40 mv hysteresis temporization t rsttempo reset ai14364
AN2586 power supplies doc id 13675 rev 7 9/28 1.3.2 programmable vo ltage detector (pvd) you can use the pvd to monitor the v dd power supply by comparing it to a threshold selected by the pls[2:0] bits in the power control register (pwr_cr). the pvd is enabled by setting the pvde bit. a pvdo flag is available, in the power control/status register (pwr_csr), to indicate whether v dd is higher or lower than the pvd threshold. this event is internally connected to exti line16 and can generate an interrupt if enabled through the exti registers. the pvd output interrupt can be generated when v dd drops below the pvd threshold and/or when v dd rises above the pvd threshold dependi ng on the exti line16 rising/falling edge configuration. as an example the service routine can perform emergency shutdown tasks. figure 4. pvd thresholds 1.3.3 system reset a system reset sets all register s to their reset values except for the reset flags in the clock controller csr register and the registers in the backup domain (see figure 1 ). a system reset is generated when one of the following events occurs: 1. a low level on the nrst pin (external reset) 2. window watchdog end-of-count condition (wwdg reset) 3. independent watchdog end-of-count condition (iwdg reset) 4. a software reset (sw reset) 5. low-power management reset the reset source can be identified by checking the reset flags in the control/status register, rcc_csr. v dd 100 mv hysteresis pvd threshold pvd output ai14365
power supplies AN2586 10/28 doc id 13675 rev 7 the stm32f1xx does not require an external rese t circuit to power-up correctly. only a pull- down capacitor is recommended to improve ems performance by protecting the device against parasitic resets. see figure 5 . charging and discharging a pull-down capacitor through an internal resistor increases the device power consumption. the capacitor recommended value (100 nf) can be reduced to 10 nf to limit this power consumption; figure 5. reset circuit 2 05 6 $$ 6 $$! 77$'reset )7$'reset 0ulse generator 0owerreset min?s 3ystemreset &ilter 3oftwarereset ,ow powermanagementreset ?& %xternal resetcircuit .234 aic
AN2586 clocks doc id 13675 rev 7 11/28 2 clocks three different clock sources can be us ed to drive the system clock (sysclk): hsi oscillator clock (high-speed internal clock signal) hse oscillator cloc k (high-speed external clock signal) pll clock the devices have two secondary clock sources: 40 khz low-speed internal rc (lsi rc) that drives the independent watchdog and, optionally, the rtc used for auto-wakeup from the stop/standby modes. 32.768 khz low-speed external crystal (lse crystal) that optionally drives the real-time clock (rtcclk) each clock source can be switched on or off independently when it is not used, to optimize the power consumption. refer to the stm32f10xxx or stm32f100xx reference manual (rm0008 or rm0041, respectively) for a description of the clock tree: rm0008 for stm32f101xx, stm32f102xx, stm32f103xx and stm32f105xx/107xx microcontrollers rm0041 for stm32f100xx value line microcontrollers 2.1 hse osc clock the high-speed external clock signal (hse) can be generated from two possible clock sources: hse external crystal/ceramic resonator (see figure 7 ) hse user external clock (see figure 6 ) 1. the value of r ext depends on the crystal characteristics. typi cal value is in the range of 5 to 6 r s (resonator series resistance). 2. load capacitance c l has the following formula: c l = c l1 x c l2 / (c l1 + c l2 ) + c stray where: c stray is the pin capacitance and board or trace pcb-re lated capacitance. typically, it is between 2 pf and 7 pf. please refer to section 5: recommendations on page 20 to minimize its value. figure 6. external clock figure 7. crystal/ceramic resonators osc_out osc_in external source (hi-z) ai14369 hardware configuration osc_out osc_in ai14370 stm32f10xxx r ext (1) c l1 c l2 hardware configuration
clocks AN2586 12/28 doc id 13675 rev 7 2.1.1 external source (hse bypass) in this mode, an external clock source must be provided. it can have a frequency of up to: 24 mhz for stm32f100xx value line devices 25 mhz for stm32f101xx, stm32f102xx and stm32f103xx devices 50 mhz for connectivity line devices the external clock signal (square, sine or tr iangle) with a duty cycle of about 50%, has to drive the osc_in pin while the osc_out pin must be left in the high impedance state (see figure 7 and figure 6 ). 2.1.2 external crystal/ceram ic resonator (hse crystal) the external oscillator frequency ranges from: 4 to 16 mhz on stm32f101xx, stm32f102xx and stm32f103xx devices 4 to 24 mhz for stm32f100xx value line devices 3 to 25 mhz on connectivity line devices the external oscillator has the advantage of producing a very accurate rate on the main clock. the associated hardware configuration is shown in figure 7 . the resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output dist ortion and startup stabilization time. the load capacitance values must be adjusted according to the selected oscillator. for c l1 and c l2 it is recommended to use high-quality ceramic capacitors in the 5 pf-to- 25 pf range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. c l1 and c l2, are usually the same value. the crystal manufacturer typically specifies a load capacitance that is the series combination of c l1 and c l2 . the pcb and mcu pin capacitances must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). refer to the electrical characteristics sections in the datasheet of your product for more details.
AN2586 clocks doc id 13675 rev 7 13/28 2.2 lse osc clock the low-speed external clock signal (lse) can be generated from two possible clock sources: lse external crystal/ce ramic resonator (see figure 9 ) lse user external clock (see figure 8 ) note: 1 ?external clock? figure: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf 2 ?external clock? and ?crystal/ceramic resonators? figures: osc32_in and osc_out pins can be used also as gpio, but it is recommended not to use them as both rtc and gpio pins in the same application 3? crystal/ceramic re sonators? figure: the value of r ext depends on the crystal characteristics. a 0 resistor would work but would not be optimal. typical value is in the range of 5 to 6 r s (resonator series resistance). to fine tune r s value refer to an2867 - oscillator de sign guide for st microcontrollers. 2.2.1 external source (lse bypass) in this mode, an external clock source must be provided. it can have a frequency of up to 1 mhz. the external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the osc32_in pin while the osc32_out pin must be left high impedance (see figure 9 and figure 8 ). 2.2.2 external crystal/ceram ic resonator (lse crystal) the lse crystal is a 32.768 khz low-speed external crystal or ceramic resonator. it has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (rtc) for clock/calendar or other timing functions. the resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output dist ortion and startup stabilization time. the load capacitance values must be adjusted according to the selected oscillator. figure 8. external clock figure 9. crystal/ceramic resonators osc32_out osc32_in external source (hi-z) ai14371 hardware configuration osc32_out osc32_in ai14372c stm32f10xxx c l1 c l2 hardware configuration r ext (3)
clocks AN2586 14/28 doc id 13675 rev 7 2.3 clock security system (css) the clock security system can be activated by software. in this case, the clock detector is enabled after the hse oscillator startup delay, and disabled when this oscillator is stopped. if a failure is detected on the hse oscilla tor clock, the oscillator is automatically disabled. a clock failure event is sent to the break input of the tim1 advanced control timer and an interrupt is generated to inform the software about the failure (clock security system interrupt cssi), allowing the mcu to perform rescue operations. the cssi is linked to the cortex?-m3 nmi (n on-maskable interrupt) exception vector. if the hse oscillator is used directly or indi rectly as the system clock (indirectly means that it is used as the pll input clock, and the pll clock is used as the system clock), a detected failure causes a switch of the system clock to the hsi oscillator and the disabling of the external hse oscillator. if th e hse oscillator clock (div ided or not) is the clock entry of the pll used as system cl ock when the failure occurs, the pll is disabled too. for details, see the stm32f10xxx (rm0008) and stm32f100xx (rm0041) reference manuals available from the stmicroelectronics website www.st.com .
AN2586 boot configuration doc id 13675 rev 7 15/28 3 boot configuration 3.1 boot mode selection in the stm32f10xxx, three different boot modes can be selected by means of the boot[1:0] pins as shown in ta b l e 1 . the values on the boot pins are latched on the 4 th rising edge of sysclk after a reset. it is up to the user to set the boot1 and boot0 pins after reset to select the required boot mode. the boot pins are also resampled when exiting the standby mode. consequently, they must be kept in the required boot mode configuration in the standby mode. after this startup delay has elapsed, the cpu fetches the top-of-stack value from address 0x0000 0000, and starts code execution from the boot memory starting from 0x0000 0004. 3.2 boot pin connection figure 10 shows the external connection required to select the boot memory of the stm32f10xxx. figure 10. boot mode selection implementation example 1. resistor values are giv en only as a typical example. table 1. boot modes boot mode selection pins boot mode aliasing boot1 boot0 x 0 main flash memory main flash memory is selected as boot space 0 1 system memory system memory is selected as boot space 1 1 embedded sram embedded sram is selected as boot space ai14373 v dd stm32f10xxx boot0 boot1 v dd 10 k 10 k
boot configuration AN2586 16/28 doc id 13675 rev 7 3.3 embedded boot loader mode the embedded boot loader mode is used to r eprogram the flash memory using one of the available serial interfaces: in low-density, low-density value line, medium-density, medium-density value line, and high-density devices, the boot loader is activated through the usart1 interface. for further details please refer to an2606. in xl-density devices, the boot loader is activated through the usart1 or usart2 (remapped) interface. for further details please refer to an2606. in connectivity line devices the boot loader can be activated through one of the following interfaces: usart1, usart2 (remapped), can2 (remapped) or usb otg fs in device mode (dfu: device firmware upgrade). the usart peripheral operates with the inte rnal 8 mhz oscillator (hsi). the can and usb otg fs, however, can only function if an external 8 mhz, 14.7456 mhz or 25 mhz clock (hse) is present. for further details, please refer to an2662. this embedded boot loader is located in the system memory and is programmed by st during production.
AN2586 debug management doc id 13675 rev 7 17/28 4 debug management 4.1 introduction the host/target interface is the hardware equipment that connects the host to the application board. this interface is made of three components: a hardware debug tool, a jtag or sw connector and a cable connecting the host to the debug tool. figure 11 shows the connection of the host to the evaluation board (stm3210b-eval, stm3210c-eval, stm32100b-eval or stm3210e-eval). the value line evaluation board (stm32100b-eval or stm32100e-eval) embeds the debug tools (st-link). consequently, it can be directly connected to the pc through a usb cable. figure 11. host-to-board connection 4.2 swj debug port (serial wire and jtag) the stm32f10xxx core integrates the serial wire / jtag debug port (swj-dp). it is an arm? standard coresight? debug port that combines a jtag-dp (5-pin) interface and a sw-dp (2-pin) interface. the jtag debug port (jtag-dp) provides a 5-pin standard jtag interface to the ahp- ap port the serial wire debug port (sw-dp) provides a 2-pin (clock + data) interface to the ahp-ap port in the swj-dp, the two jtag pins of the sw-dp are multiplexed with some of the five jtag pins of the jtag-dp. 4.3 pinout and debug port pins the stm32f10xxx mcu is offered in various packages with different numbers of available pins. as a result, some functi onality related to the pin ava ilability may differ from one package to another. 4.3.1 swj debug port pins five pins are used as outputs for the swj-dp as alternate functions of general-purpose i/os (gpios). these pins, shown in ta b l e 2 , are available on all packages. %valuationboard (ost0# 0owersupply *4!'37connector $ebugtool aib
debug management AN2586 18/28 doc id 13675 rev 7 4.3.2 flexible swj-dp pin assignment after reset (sysresetn or poreset n), all five pins used for the swj-dp are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). however, the stm32f10xxx mcu implements a register to disable some part or all of the swj-dp port, and so releases the associated pins for general-purpose i/os usage. this register is mapped on an apb bridge connected to the cortex?-m3 system bus. this register is programmed by the user software program and not by the debugger host. ta bl e 3 shows the different possibilit ies to release some pins. for more details, see the stm32f10xxx (rm0008) and stm32f100xx (rm0041) reference manuals, available from the stmicroelectronics website www.st.com . table 2. debug port pin assignment swj-dp pin name jtag debug port sw debug port pin assignment type description type debug assignment jtms/swdio i jtag test mode selection i/o serial wire data input/output pa 1 3 jtck/swclk i jtag test clock i serial wire clock pa14 jtdi i jtag test data input - - pa15 jtdo/traceswo o jtag test data output - traceswo if async trace is enabled pb3 jntrst i jtag test nreset - - pb4 table 3. swj i/o pin availability available debug ports swj i/o pin assigned pa13 / jtms/ swdio pa1 4 / jtck/ swclk pa15 / jtdi pb3 / jtdo pb4/ jntrst full swj (jtag-dp + sw-dp) - reset state x x x x x full swj (jtag-dp + sw-dp) but without jntrst xxxx jtag-dp disabled and sw-dp enabled x x jtag-dp disabled and sw-dp disabled released
AN2586 debug management doc id 13675 rev 7 19/28 4.3.3 internal pull-up and pu ll-down resistors on jtag pins the jtag input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. special care must be taken with the swclk/tck pin that is directly connected to the clock of some of these flip-flops. to avoid any uncontrolled i/o levels, the stm32f10xxx embeds internal pull-up and pull- down resistors on jtag input pins: jntrst: internal pull-up jtdi: internal pull-up jtms/swdio: internal pull-up tck/swclk: internal pull-down once a jtag i/o is released by the user software, the gpio controller takes control again. the reset states of the gpio control registers put the i/os in the equivalent state: jntrst: input pull-up jtdi: input pull-up jtms/swdio: input pull-up jtck/swclk: input pull-down jtdo: input floating the software can then use these i/os as standard gpios. note: the jtag ieee standard recommends to ad d pull-up resistors on tdi, tms and ntrst but there is no special recommendation for tck. however, for the stm32f10xxx , an integrated pull-down resistor is used for jtck. having embedded pull-up and pull-down resistors removes the need to add external resistors. 4.3.4 swj debug port connecti on with standard jtag connector figure 12 shows the connection between the stm32f10xxx and a standard jtag connector. figure 12. jtag connector implementation ai14376 v dd v dd stm32f10xxx njtrst jtdi jstm/swdio jtck/swclk jtdo nrstin (1) vtref (3) ntrst (5) tdi (7) tms (9) tck (11) rtck (13)tdo (15) nsrst (17) dbgrq (19) dbgack 10 k 10 k 10 k v ss (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) connector 2 10 jtag connector cn9
recommendations AN2586 20/28 doc id 13675 rev 7 5 recommendations 5.1 printed circuit board for technical reasons, it is best to use a multilayer printed circuit board (pcb) with a separate layer dedicated to ground (v ss ) and another dedicated to the v dd supply. this provides good decoupling and a good shielding effect. for many applications, economical reasons prohibit the use of this type of board. in this case, the major requirement is to ensure a good structure for ground and for the power supply. 5.2 component position a preliminary layout of the pcb must separate the different circuits according to their emi contribution in order to reduce cross-coupling on the pcb, that is noisy, high-current circuits, low-voltage circuits, and digital components. 5.3 ground and power supply (v ss , v dd ) every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all ground returns should be to a single point. loops must be avoided or have a minimum area. the power supply should be implemented close to the ground line to minimize the area of the supply loop. this is due to the fact that the supply loop acts as an antenna, and is therefore the main transmitter and receiver of emi. all component-free pcb areas must be filled with additional grounding to create a ki nd of shielding (especia lly when using single- layer pcbs). 5.4 decoupling all power supply and ground pins must be properly connected to the power supplies. these connections, including pads, tracks and vias should have as low an impedance as possible. this is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer pcbs. in addition, each power supply pair should be decoupled with filtering ceramic capacitors c (100 nf) and a chemical capacitor c of about 10 f connected in parallel on the stm32f10xxx device. these capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the pcb. typical values are 10 nf to 100 nf, but exact values depend on the application needs. figure 13 shows the typical layout of such a v dd /v ss pair.
AN2586 recommendations doc id 13675 rev 7 21/28 figure 13. typical layout for v dd /v ss pair 5.5 other signals when designing an application, the emc performance can be improved by closely studying: signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for led commands). for these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve emc performance. for digital signals, the best possible electrical margin must be reached for the two logical states and slow schmitt triggers ar e recommended to eliminate parasitic states. noisy signals (clock, etc.) sensitive signals (high impedance, etc.) 5.6 unused i/os and features all microcontrollers are designed for a vari ety of applications and often a particular application does not use 100% of the mcu resources. to increase emc performance, unused clocks, counters or i/os, should not be left free, e.g. i/os should be set to ?0? or ?1?(pull-up or pull-down to the unused i/o pins.) and unused features should be ?frozen? or disabled. via to v ss via to v dd cap. v dd v ss stm32f10xxx
reference design AN2586 22/28 doc id 13675 rev 7 6 reference design 6.1 description the reference design shown in figure 14 , is based on the stm32f103ze(t6), a highly integrated microcontroller running at 72 mhz, that combines the new cortex ? -m3 32-bit risc cpu core with 512 kbytes of embedded flash memory and up to 64 kbytes of high- speed sram . this reference design can be tailored to any other stm32f10xxx device with different package, using the pins correspondence given in table 6: reference connection for all packages . 6.1.1 clock two clock sources are used for the microcontroller: lse: x1? 32.768 khz crystal for the embedded rtc hse: x2? 8 mhz crystal for the stm32f10xxx microcontroller refer to section 2: clocks on page 11 . 6.1.2 reset the reset signal in figure 14 is active low. the reset sources include: reset button (b1) debugging tools via the connector cn1 refer to section 1.3: reset and power supply supervisor on page 8 . 6.1.3 boot mode the boot option is configured by setting switches sw2 (boot 0) and sw1 (boot 1). refer to section 3: boot configuration on page 15 . note: in low-power mode (more specially in standby mode) the boot mode is mandatory to be able to connect to tools (the device should boot from the sram). 6.1.4 swj interface the reference design shows the connection between the stm32f10xxx and a standard jtag connector. refer to section 4: debug management on page 17 . note: it is recommended to connect the reset pins so as to be able to reset the application from the tools. 6.1.5 power supply refer to section 1: power supplies on page 6 .
AN2586 reference design doc id 13675 rev 7 23/28 6.2 component references table 4. mandatory components id components name reference quantity comments 1 microcontroller stm32f103ze(t6) 1 144-pin package 2 capacitors 100 nf 11 ceramic capacitors (decoupling capacitors) 3 capacitor 10 f 1 ceramic capacitor (decoupling capacitor) table 5. optional components id components name reference quantity comments 1resistor 10 k 5 pull-up and pull-down for jtag and boot mode. 2resistor 390 1 used for hse: the value depends on the crystal characteristics. this resistor value is given only as a typical example. 3resistor 0 1 used for lse: the value depends on the crystal characteristics. this resistor value is given only as a typical example. 4 capacitor 100 nf 3 ceramic capacitor 5 capacitor 1f 2 used for vdda and vref. 6 capacitor 10 pf 2 used for lse: the value depends on the crystal characteristics. 7 capacitor 20 pf 2 used for hse: the value depends on the crystal characteristics. 8 quartz 8 mhz 1 used for hse 9 quartz 32 khz 1 used for lse 10 jtag connector he10 1 11 battery 3v3 1 if no external battery is used in the application, it is recommended to connect v bat externally to v dd 12 switch 3v3 2 used to select the correct boot mode. 13 push-button b1 1
reference design AN2586 24/28 doc id 13675 rev 7 figure 14. stm32f103ze(t6) microcontroller reference schematic 1. if no external battery is used in the application, it is recommended to connect v bat externally to v dd . 2. to be able to reset the device from t he tools this resistor has to be kept. mcu 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 cn1 jtag vdd r2 10k r 3 10k r1 10k jtag connector deco u pling c a p a citor 1 4 3 2 b1 c5 100nf c4 20pf c 3 20pf x2 8 mhz r6 3 90 r7 10k vdd 2 3 1 s w2 re s et# o s c_in o s c_out c 8 100nf c9 100nf c10 100nf c7 100nf vdd c11 100nf 4 1 3 2 x1 3 2k c2 10pf c1 10pf bt1 cr1220 holder v bat 3 2 1 jp1 vdd mcu su pply r4 10k vdd 2 3 1 s w1 c12 100nf r9 0 pe2 1 pf2 12 o s c_in 2 3 pa0-wkup 3 4 pc 5 45 pg 0 56 pe10 6 3 pe11 64 pe 3 2 pe4 3 pe5 4 pe6 5 pc1 3 -anti _tamp 7 pc14-o s c 3 2_i n 8 pc15-o s c 3 2_out 9 pf0 10 pf1 11 pf 3 1 3 pf4 14 pf5 15 pf6 1 8 pf7 19 pf 8 20 pf9 21 pf10 22 o s c_out 24 nr s t 25 pc 0 26 pc 1 27 pc 2 2 8 pc 3 29 pa 1 3 5 pa 2 3 6 pa 3 3 7 pa 4 40 pa 5 41 pa 6 42 pa 7 4 3 pc 4 44 pb 0 46 pb 1 47 pb2-boot1 4 8 pf11 49 pf12 50 pf1 3 5 3 pf14 54 pf15 55 pg 1 57 pe7 5 8 pe 8 59 pe9 60 pe12 65 pb15 76 pg 2 8 7 pc 8 9 8 pa14 109 pg11 126 pg12 127 pg 1 3 12 8 pe1 3 66 pe14 67 pe15 6 8 pb10 69 pb11 70 pb12 7 3 pb1 3 74 pb14 75 pd 8 77 pd 9 7 8 pd10 79 pd11 8 0 pd12 8 1 pd 1 3 8 2 pd14 8 5 pd15 8 6 pg 3 88 pg 4 8 9 pg 5 90 pg 6 91 pg 7 92 pg 8 9 3 pc 6 96 pc 7 97 pc 9 99 pa 8 100 pa 9 101 pa10 102 pa11 10 3 pa12 104 pa 1 3 105 nc 106 pa15 110 pc10 111 pc11 112 pc12 11 3 pd 0 114 pd 1 115 pd 2 116 pd 3 117 pd 4 11 8 pd 5 119 pd 6 122 pd 7 12 3 pg 9 124 pg10 125 pg14 129 pb 7 1 3 7 boot0 1 38 pb 8 1 3 9 pb 9 140 pe0 141 pe1 142 pg15 1 3 2 pb 3 1 33 pb 4 1 3 4 pb 5 1 3 5 pb 6 1 3 6 u1a s tm 3 2f10 3 zet6 vdd_7 62 vbat 6 v ss _5 16 vdd_5 17 v ss a 3 0 vref- 3 1 vref+ 3 2 vdda 33 v ss _4 38 vdd_4 3 9 v ss _6 51 vdd_6 52 v ss _7 61 v ss _10 120 v ss _1 71 vdd_1 72 v ss _ 8 83 vdd_ 8 8 4 v ss _9 94 vdd_9 95 v ss _2 107 vdd_2 10 8 vdd_10 121 v ss _ 3 14 3 vdd_ 3 144 v ss _11 1 3 0 vdd_11 1 3 1 u1b s tm 3 2f10 3 zet6 vdd def au lt s etting: 2<- > 3 c1 3 100nf c14 100nf c15 100nf c16 100nf c17 10 f c6 100nf mcu boot mode l s e h s e boot mode o s c_in o s c_out boot 0 boot 1 re s et r 8 0 1) 2) 100nf 1 f ai14 8 767c vdd 100nf 1 f vdd
AN2586 reference design doc id 13675 rev 7 25/28 table 6. reference connection for all packages pin name pin numbers for lqfp packages pin numbers for bga packages pin numbers for vfqfpn package 144 pins 100 pins 64 pins 48 pins 144 pins 100 pins 36 pins osc_in 23 12 5 5 d1 c1 2 osc_out 24 13 6 6 e1 d1 3 pc15- osc32_out 9944c1b1 - pc14- osc32_in 8 8 3 3 b1 a1 - boot0 138 94 60 44 d5 d5 35 pb2-boot1 48 37 28 20 j5 g5 17 nrst 25 14 7 7 f1 e1 4 pa13 105 72 46 34 a12 a10 25 pa14 109 76 49 37 a11 a9 28 pa15 110 77 50 38 a10 a8 29 pb4 134 90 56 40 a6 a6 31 pb3 133 89 55 39 a7 a7 30 v ss_1 71 49 31 23 h7 e7 18 v ss_2 107 74 47 35 g9 e6 26 v ss_3 143 99 63 47 e5 e5 36 v ss_4 38 27 18 - g4 e4 - v ss_5 16 10 - - d2 c2 - v ss_6 51 - - - h5 - - v ss_7 61 - - - h6 - - v ss_8 83 - - - g8 - - v ss_9 94 - - - g10 - - v ss_10 120 - - - e7 - - v ss_11 130 - - - e6 - v dd_1 72 50 32 24 g7 f7 19 v dd_2 108 75 48 36 f9 27 v dd_3 144 100 64 48 f5 f5 1 v dd_4 39 28 19 - f4 f4 - v dd_5 17 11 - - d3 d2 - v dd_6 52 - - - g5 - - v dd_7 62 - - - g6 - - v dd_8 84 - - - f8 - -
reference design AN2586 26/28 doc id 13675 rev 7 v dd_9 95 - - - f10 - - v dd_10 121 - - - f7 - - v dd_11 131 - - - f6 - - v ref+ 32 21 - - l1 j1 - v ref- 31 20 - - k1 h1 - v ssa 30 19 12 8 j1 g1 - v dda 33 22 13 9 m1 k1 - v bat 6611c2b2 - table 6. reference connection for all packages (continued) pin name pin numbers for lqfp packages pin numbers for bga packages pin numbers for vfqfpn package 144 pins 100 pins 64 pins 48 pins 144 pins 100 pins 36 pins
AN2586 revision history doc id 13675 rev 7 27/28 7 revision history table 7. document revision history date revision changes 12-jul-2007 1 initial release. 23-may-2008 2 application note also applicable to high-density devices. figure 1: power supply overview , figure 2: power supply scheme and figure 6: clock overview updated. low-speed internal rc frequency modified in section 2: clocks on page 11 . v ref+ voltage range modified. table 6: reference connection for all packages on page 25 added. small text changes. 23-jun-2009 3 connectivity line stm32f10xxx and section : glossary added. section 1.2: power supply schemes and figure 2: power supply scheme updated. figure 5: reset circuit updated. figure 6 clock overview removed in section 2: clocks . note 1 added note 3 updated below figure 8: external clock . section 2.1.1: external source (hse bypass) and section 2.1.2: external crystal/c eramic resonator (hse crystal) updated. section 2.3 clock-out capability section removed. section 3.1: boot mode selection and section 3.3: embedded boot loader mode updated. when no external battery is used, it is recommended to externally connect the v bat pin to v dd . pa14 updated in table 7: document revision history . small text changes. stm3210c-eval evaluation board added in section 4 . 01-mar-2010 4 this application note also applies to stm32f100xx low- and medium-density value line products: ? low- and medium-density value line devices added to introduction on page 1 ? section 2.1.1: external source (hse bypass) and section 2.1.2: external crystal/ceramic resonator (hse crystal) updated ? reference to value line?s evaluation board added to section 4.1: introduction table 5: reset circuit updated. 19-oct-2010 5 modified section 2.2.1: external source (lse bypass) updated for high-density value line devices. 14-apr-2011 6 updated vdda and vref schematics in figure 14: stm32f103ze(t6) microcontroller reference schematic on page 24 and table 5: optional components . 18-nov-2011 7 updated to include xl-density devices.
AN2586 28/28 doc id 13675 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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