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? 2015 microchip technology inc. ds20005418b-page 1 hv5122 / hv5222 features processed with high voltage cmos technology output voltages to 225v using a ramped supply voltage sink current minimum 100ma shift register speed 8.0mhz strobe and enable inputs cmos compatible inputs forward and reverse shifting options description hv5122 / hv5222 are low-voltage serial to high-volt- age parallel converters with open-drain outputs. these devices are primarily designed for use as a driver for ac electroluminescent displays. hv5122 / hv5222 can also be used in any application requiring multiple high- voltage, current-sinking output capabilities such as driving inkjet and electrostatic print heads, plasma pan- els, vacuum fluorescent, or large matrix lcd displays. these devices consist of a 32-bit shift register and con- trol logic to perform the output enable and all-on func- tions. data is shifted through the shift register on the high-to-low transition of the clock. hv5122 shifts in the counter-clockwise direction when viewed from the top of the package and hv5222 shifts in the clockwise direction. for cascading devices, hv5122 / hv5222 provides a data output buffer that reflects he current status of the last bit of the shift register . operation of the shift regis- ter is not affected by the oe (output enable) or the str (strobe) inputs. hv5122 / hv5222 are designed to be used in systems which either switch off the high voltage supply before changing the state of the high voltage outputs or which limit the current through each output. 32-channel, serial-to-parallel converter with open-drain outputs downloaded from: http:///
hv5122 / hv5222 ds20005418b-page 2 ? 2015 microchip technology inc. package type functional block diagram 44-lead plcc see ta b l e 2 - 1 for pin information 44-lead pqfp 1 44 1 44 6 40 hv out 2 ?? ? 28 additional outputs ?? ? hv out 31 oe data input clk data out str hv out 1 hv out 32 32 bit static shift register downloaded from: http:/// ? 2015 microchip technology inc. ds20005418b-page 3 hv5122 / hv5222 1.0 electrical characteristics absolute maximum ratings ? supply voltage, v dd ............................................................................................................................... ....-0.5v to +15v supply voltage, v pp ............................................................................................................................... ..-0.5v to +250v logic input levels ............................................................................................................. .................. -0.5v to v dd +0.5v ground current 1 ............................................................................................................................... ........................ 1.5a continuous total power dissipation 2 .................................................................................................................. 1200mw operating temperature range.................................................................................................... .............. -40c to +85c storage temperature range ...................................................................................................... ............. -65c to +150c 1: duty cycle is limited by the tota l power dissipated in the package. 2: for operation above 25c ambient derate linearly to maximum operating temperature at 20mw/c. ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended perio ds may affect devi ce reliability. table 1-1: electrical characteristics electrical specifications: over recommended conditions unless otherwise specified symbol parameter min max units conditions dc characteristics i dd v dd supply current - 15 ma f clk = 8.0mhz, f data = 4.0mhz i ddq quiescent v dd supply current - 100 a d in = 0v, all input logic pins = 0v, all outputs off i o(off) off-state output current - 10 a all outputs high, all switches parallel i ih high level logic input current - 1.0 a v in = v dd i il low level logic input current - -1.0 a v il = 0 v oh high level output data out v dd - 1.0v -v i dout = -100a v ol low level output voltage hv out -1 5 v i hvout = +100ma data out - 1.0 i dout = +100a v oc hv out clamp voltage - -1.5 v i ol = -100ma ac characteristics (v dd = 12v, t a =25c) f clk clock frequency - 8.0 mhz t w clock width, high or low 62 - ns t su data setup time before clk falls 25 - ns t h data hold time after clk falls 10 - ns t on turn-on time, hv out from strobe - 500 ns r l = 2.0k ? to 200v t dhl data output delay after h to l clk - 100 ns c l = 15pf t dlh data output delay after l to h clk - 100 ns c l = 15pf table 1-2: typical thermal resistance package ja 44-lead pqfp 51c/w 44-lead plcc 37c/w downloaded from: http:/// hv5122 / hv5222 ds20005418b-page 4 ? 2015 microchip technology inc. 2.0 pin description the locations of the pins are listed in package type . table 2-1: pin description pqfp pin # hv5122 hv5222 description 1h v out 11 hv out 22 high voltage outputs. 2h v out 12 hv out 21 3h v out 13 hv out 20 4h v out 14 hv out 19 5h v out 15 hv out 18 6h v out 16 hv out 17 7h v out 17 hv out 16 8h v out 18 hv out 15 9h v out 19 hv out 14 10 hv out 20 hv out 13 11 hv out 21 hv out 12 12 hv out 22 hv out 11 13 hv out 23 hv out 10 14 hv out 24 hv out 9 15 hv out 25 hv out 8 16 hv out 26 hv out 7 17 hv out 27 hv out 6 18 hv out 28 hv out 5 19 hv out 29 hv out 4 20 hv out 30 hv out 3 21 hv out 31 hv out 2 22 hv out 32 hv out 1 23 data out data out data output for cascading to the data input of the next device. 24 n/c n/c no connect. 2526 27 28 oe oe output enable input. when oe is low, all hv outputs are forced into a low state, regardless of data in each channel. when oe is high, all hv outputs reflect data latched. 29 clk clk data shift register clock. input are shifted into the shift register on the positive edge of the clock. 30 gnd gnd logic and high voltage ground. 31 vdd vdd low voltage logic power rail. 32 str str strobe. 33 data in data in serial data input. data needs to be present before each rising edge of the clock. 34 n/c n/c no connect. downloaded from: http:/// ? 2015 microchip technology inc. ds20005418b-page 5 hv5122 / hv5222 35 hv out 1h v out 32 high voltage outputs. 36 hv out 2h v out 31 37 hv out 3h v out 30 38 hv out 4h v out 29 39 hv out 5h v out 28 40 hv out 6h v out 27 41 hv out 7h v out 26 42 hv out 8h v out 25 43 hv out 9h v out 24 44 hv out 10 hv out 23 table 2-1: pin descript ion pqfp (continued) pin # hv5122 hv5222 description table 2-2: pin description plcc pin # hv5122 hv5222 description 1h v out 16 hv out 17 high voltage outputs 2h v out 17 hv out 16 3h v out 18 hv out 15 4h v out 19 hv out 14 5h v out 20 hv out 13 6h v out 21 hv out 12 7h v out 22 hv out 11 8h v out 23 hv out 10 9h v out 24 hv out 9 10 hv out 25 hv out 8 11 hv out 26 hv out 7 12 hv out 27 hv out 6 13 hv out 28 hv out 5 14 hv out 29 hv out 4 15 hv out 30 hv out 3 16 hv out 31 hv out 2 17 hv out 32 hv out 1 18 data out data out data output for cascading to the data input of the next device. 19 n/c n/c no connect. 2021 22 23 oe oe output enable input. when oe is low, all hv outputs are forced into a low state, regardless of data in each channel. when oe is high, all hv outputs reflect data latched. 24 clk clk data shift register clock. input are shifted into the shift register on the positive edge of the clock. 25 gnd gnd logic and high voltage ground. 26 vdd vdd low voltage logic power rail. 27 str str strobe. downloaded from: http:/// hv5122 / hv5222 ds20005418b-page 6 ? 2015 microchip technology inc. 28 data in data in serial data input. data needs to be present before each rising edge of the clock. 29 n/c n/c no connect. 30 hv out 1h v out 32 high voltage outputs. 31 hv out 2h v out 31 32 hv out 3h v out 30 33 hv out 4h v out 29 34 hv out 5h v out 28 35 hv out 6h v out 27 36 hv out 7h v out 26 37 hv out 8h v out 25 38 hv out 9h v out 24 39 hv out 10 hv out 23 40 hv out 11 hv out 22 41 hv out 12 hv out 21 42 hv out 13 hv out 20 43 hv out 14 hv out 19 44 hv out 15 hv out 18 table 2-2: pin descript ion plcc (continued) pin # hv5122 hv5222 description downloaded from: http:/// ? 2015 microchip technology inc. ds20005418b-page 7 hv5122 / hv5222 3.0 functional description table 3-1 provides functional information about hv5122 / hv5222. note 1: h = high level, l = low level, x = irrelevant, = high-to-low transition 2: = dependent on previous stages state bef ore the last clk high-to-low transition 3.1 power-up and recommended operating conditions to power-up hv5122 / hv5222, perform the following power-up sequence: 1. connect ground 2. apply v dd 3. set all inputs to a known state to power-down the device, reverse the steps above. figure 3-1: input and output equivalent circuits table 3-1: functional table function inputs outputs data in clk oe str shift reg hv outputs data out 1 2...32 1 2...32 all on x x x l ... on on...on all off x x l h ... off off...off load s/r h/l l h h/l q1...q31 off off...off q32 output enable x h/l h h h/l ... on/off ... table 3-2: recommended operating conditions symbol parameter min typ max units v dd logic voltage supply 10.8 12 13.2 v hv out high voltage output -0.3 - 225 v v ih high-level input voltage v dd -2.0 - v dd v v il low-level input voltage 0 - 2.0 v f clk clock frequency - - 8.0 mhz t a operating free-air temperature -40 - +85 c vdd input gnd hv out logic inputs gnd dataout logic data output high voltage outputs vdd hv in gnd downloaded from: http:/// hv5122 / hv5222 ds20005418b-page 8 ? 2015 microchip technology inc. figure 3-2: switching waveforms data in data valid 1 clk data out data out str t dlh t su t h t wl t wh t dhl hv out 50% 50% 50% 50% 50% 15v t on 12v 0v 12v 0v downloaded from: http:/// ? 2015 microchip technology inc. ds20005418b-page 9 hv5122 / hv5222 4.0 packaging information 4.1 package marking information legend: xx...x product code or customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or custom er-specific information. package may or not include the corporate logo. 3 e 3 e 44-lead plcc example xxxxxxxxx xxxxxxxxxxxyywwnnn xxxxxxxxxxx e 3 hv5122pj 1526343 e 3 44-lead pqfp example xxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn e 3 hv5122pg 1526343 e 3 downloaded from: http:/// hv5122 / hv5222 ds20005418b-page 10 ? 2015 microchip technology inc. 44-lead pqfp package outline (pg) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* 0.80 bsc 0.73 1.95 ref 0.25 bsc 0 o nom - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5 o max 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7 o jedec registration mo-112, variation aa-2, issue b, sep.1995. 7 k l v g l p h q v l r q l v q r w v s h f l ? h g l q w k h - ( ' ( & |