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1/15 may 2002 M68Z512 4 mbit (512 kbit x 8) low power sram with output enable features summary n ultra low data retention current C 100na (typical) C 10a (max) n operation voltage: 5.0v 10% n 512 kbit x 8 sram with output enable n equal cycle and access times: 70ns n low v cc data retention: 2.0v n tri-state common i/o n cmos for optimum speed/power n automatic power-down when deselected n intended for use with st zeropower ? and timekeeper ? controllers figure 1. package tsop ii 32 (nc) 10 x 20mm 32 1
M68Z512 2/15 table of contents description ....................................................................3 logicdiagram(figure2.).........................................................3 signalnames(table1.)..........................................................3 tsop connections (figure 3.) . . . ..................................................3 blockdiagram(figure4.).........................................................4 maximumrating.................................................................4 absolutemaximumratings(table2.) ...............................................4 dc and ac parameters. . ........................................................5 dc and ac measurement conditions (table 3.) . . . .....................................5 ac testing load circuit (figure 5.) ..................................................5 capacitance (table 4.) . . . ........................................................5 dccharacteristics(table5.) ......................................................6 operation......................................................................6 operating modes (table 6.) ........................................................6 readmode....................................................................7 addresscontrolled,readmodeacwaveforms(figure6.)..............................7 chip enable or output enable controlled, read mode ac waveforms (figure 7.). . ...........7 standby mode ac waveforms (figure 8.). . ...........................................7 read and standby modes ac characteristics (table 7.) . . ..............................8 writemode...................................................................9 write enable controlled, write mode ac waveforms (figure 9.) ........................9 chipenablecontrolled,writemodeacwaveforms(figure10.)........................10 writemodeaccharacteristics(table8.) ..........................................10 lowvccdataretentionacwaveforms(figure11.)..................................11 lowvccdataretentioncharacteristics(table9.)....................................11 partnumbering ...............................................................12 package mechanical information . . . ..........................................13 revisionhistory...............................................................14
3/15 M68Z512 description the M68Z512 is a 4 mbit (4,194,304 bit) cmos sram, organized as 524,288 words by 8 bits. the device features fully static operation requiring no external clocks or timing strobes, with equal ad- dress access and cycle times. it requires a single 5v 10% supply, and all inputs and outputs are ttl compatible. this device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. the M68Z512 is available in a 32-lead tsop ii (10 x 20mm) package. figure 2. logic diagram table 1. signal names figure 3. tsop connections ai03030 19 a0-a18 w dq0-dq7 v cc M68Z512 g v ss 8 e a0-a18 address inputs dq0-dq7 data input/output e chip enable g output enable w write enable v cc supply voltage v ss ground dq5 dq6 dq7 dq0 v ss dq3 dq4 dq1 dq2 a12 a15 a14 a16 a6 a17 g w a8 a10 a11 a9 a13 a5 a7 a2 a0 a3 a4 a1 ai03031 M68Z512 8 1 9 16 17 24 25 32 v cc a18 e
M68Z512 4/15 figure 4. block diagram maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). 2. up to a maximum operating v cc of 5.5v only. 3. one output at a time, not to exceed 1 second duration. ai03033 row decoder a a (10) chip enable. input data ctrl dq dq (8) column decoder i/o circuits (9) a a chip enable. w g memory array v cc v ss e symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg (1) storage temperature C65 to 150 c v io (2) input or output voltage C0.3 to v cc + 0.3 v v cc supply voltage C0.3 to 7.0 v i o (3) output current 20 ma p d power dissipation 1 w
5/15 M68Z512 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. dc and ac measurement conditions note: output high z is defined as the point where data is no longer driven (see table 3, page 5). figure 5. ac testing load circuit table 4. capacitance note: 1. sampled only, not 100% tested. 2. outputs deselected. 3. at 25c. parameter M68Z512 v cc supply voltage 4.5 to 5.5v ambient operating temperature 0 to 70c load capacitance (c l ) 100pf input rise and fall times 5ns input pulse voltages 0to3v input and output timing ref. voltages 1.5v ai03032 5.0v out c l = 100pf or 5pf c l includes jig capacitance 1838 w device under test 994 w symbol parameter (1,2) min max unit c in input capacitance on all pins (except dq) 6 pf c out (3) output capacitance 8 pf
M68Z512 6/15 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. average ac current, outputs open, cycling at t avav minimum. 3. all other inputs at v il 0.8v or v ih 3 2.2v. 4. all other inputs at v il 0.3v or v ih 3 v cc C0.3v. operation the M68Z512 has a chip enable power down fea- ture which invokes an automatic standby mode whenever chip enable is de-asserted (e =high). an output enable (g ) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. operational modes are determined by device control inputs w and e as summarized in the op- erating modes table (see table 6). table 6. operating modes note: x = v ih or v il . symbol parameter test condition (1) min typ max unit i li input leakage current 0v vin v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 (2) supply current v cc =3.6v 90 ma i cc2 (3) supply current (standby) ttl v cc =3.6v,e =v ih 15 ma i cc3 (4) supply current (standby) cmos v cc =3.6v,e 3 v cc C 0.3v, f = 0 1.6 20 a v il input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v operation e w g dq0-dq7 power read v il v ih v ih hi-z active read v il v ih v il data output active write v il v il x data input active deselect v ih x x hi-z standby
7/15 M68Z512 read mode the M68Z512 is in the read mode whenever write enable (w ) is high with output enable (g ) low, and chip enable (e ) is asserted. this pro- vides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. valid data will be available at the eight output pins within t avqv after the last stable address, providing g is low and e is low. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t elqv or t glqv )ratherthanthe address. data out may be indeterminate at t elqx and t glqx , but data lines will always be valid at t avqv . figure 6. address controlled, read mode ac waveforms note: e = low, e2 = high, +g =low,w =high. figure 7. chip enable or output enable controlled, read mode ac waveforms note: write enable (w )=high. figure 8. standby mode ac waveforms ai03034 tavav tavqv taxqx a0-a18 dq0-dq7 valid data valid ai03035 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a18 e g dq0-dq7 valid ai03036 tpd i cc1 tpu i cc2 50% e
M68Z512 8/15 table 7. read and standby modes ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. c l = 100pf. 3. c l = 5pf. 4. at any given temperature and voltage condition, t ehqz is less than t elqx and t ghqz is less than t glqx for any given device. symbol parameter (1) M68Z512 unit C70 min max t avav read cycle time 70 ns t avqv (2) address valid to output valid 70 ns t elqv (2) chip enable low to output valid 70 ns t glqv (2) output enable low to output valid 35 ns t elqx (4) chip enable low to output transition 10 ns t glqx (4) output enable low to output transition 5 ns t ehqz (3,4) chip enable high to output hi-z 25 ns t ghqz (3) output enable high to output hi-z 25 ns t axqx (2) address transition to output transition 10 ns t pu chip enable low to power up 0 ns t pd chip enable high to power down 70 ns
9/15 M68Z512 write mode the M68Z512 is in the write mode whenever the w and e pins are low. either the chip enable in- put (e ) or the write enable input (w ) must be de- asserted during address transitions for subse- quent write cycles. write begins with the con- currence of chip enable being active with w low. therefore, address setup time is referenced to write enable and chip enable as t avwl and t aveh respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the earlier rising edge of e ,orw . if the output is enabled (e =lowandg =low), then w will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the ris- ing edge of write enable, or for t dveh before the rising edge of e , whichever occurs first, and re- main valid for t whdx or t ehdx . figure 9. write enable controlled, write mode ac waveforms note: output enable (g )=low. ai03037 tavav twhax tdvwh data input a0-a18 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx
M68Z512 10/15 figure 10. chip enable controlled, write mode ac waveforms note: output enable (g )=high. if e goes high with w high, the output remains in a high-impedance state. table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. c l = 5pf 3. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. symbol parameter (1) M68Z512 unit C70 min max t avav write cycle time 70 ns t avw l address valid to write enable low 0 ns t avwh address valid to write enable high 60 ns t aveh address valid to chip enable high 60 ns t wlwh write enable pulse width 55 ns t whax write enable high to address transition 0 ns t whdx write enable high to input transition 0 ns t whqx (3) write enable high to output transition 5 ns t wlqz (2,3) write enable low to output hi-z 25 ns t ave l address valid to chip enable low 0 ns t eleh chip enable low to chip enable high 45 ns t ehax chip enable high to address transition 0 ns t dvwh input valid to write enable high 25 ns t dveh input valid to chip enable high 25 ns ai03038 tavav tehax tdveh a0-a18 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
11/15 M68Z512 figure 11. low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. typical condition: t a =25c. 3. see figure 11 for measurement points. guaranteed but not tested. t avav is read cycle time. symbol parameter (1) test condition min typ max unit i ccdr (2) supply current (data retention) v cc =3v,e 3 v cc C 0.3v 0.4 10 a v dr supply voltage (data retention) e 3 v cc C 0.3v, f = 0 2v t cdr chip disable to power down e 3 v cc C 0.3v, f = 0 0ns t er (3) operation recovery time t avav ns ai03039 data retention mode ter 5v tcdr v cc 3v v dr > 2.0v e 2.2v e 3 v dr C 0.3v
M68Z512 12/15 part numbering table 10. ordering information example for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m68z 512 w C70 nc 1 tr device type m68z device function 512 = 4 mbit (512kb x8) operating voltage blank = 4.5 to 5.5v speed C70 = 70ns package nc = tsop ii 32-lead (10 x 20mm) temperature range 1 = 0 to 70c shipping method for soic blank = tubes tr = tape & reel
13/15 M68Z512 package mechanical information figure 12. tsop ii 32 C 32-lead plastic thin small outline ii, 10 x 20 mm, package outline note: drawing is not to scale. table 11. tsop ii 32 C 32-lead plastic thin small outline ii, 10 x 20 mm, package mechanical data symb mm inches min typ max min typ max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.30 0.52 0.012 0.020 c 0.12 0.21 0.005 0.008 cp 0.10 0.004 d 20.82 21.08 0.820 0.830 e 1.27 C C 0.050 C C e 11.56 11.96 0.455 0.471 e1 10.03 10.29 0.395 0.405 l 0.40 0.60 0.016 0.024 a 0 5 0 5 n32 32 tsop-d 16 17 cp a 1 l a1 a 32 d e b e1 e c a2
M68Z512 14/15 revision history table 12. document revision history date revision details may 1999 first issue 03/14/00 tsop32 ii package dimension changed (table 11) from preliminary data to data sheet 07/26/00 ordering information scheme changed (table 10) 09/21/00 i ccdr supply current changed (table 9) 03/30/01 reformatted; temp./voltage info. added to tables (table 4, 5, 7, 8, 9) 05/13/02 add reflow time and temperature footnote (table 2)
15/15 M68Z512 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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