integrated circuit systems, inc. general description features ics9169c-40 block diagram system clock chip 9169c-40reva072897p pin configuration 34-pin ssop functionality 3.3v10%, 0-70 c crystal (x1, x2) = 14.31818 mhz pentium is a trademark on intel corporation. ? 8 selectable cpu clocks up to 75mhz ? six synchronous pci clocks ? one referance clock at 14.318mhz ? power-up stabilization time = 2ms on all cpu and pci clocks, which meets intel pentiumpro power-up ? low cpu and pci clock jitter <500ps ? low skew output ? improved output drivers are designed for low emi ? test mode ? optional common or mixed supply mode: (vdd = vddl1 =vddl2 = 3.3v) (vdd = 3.3v, vddl1=vddl2 = 2.5) (vdd = 3.3v, vddl1 = 3.3v, vddl2 = 2.5v) ? space saving and low cost 34-pin ssop package the ics9169c-40 is a clock synthesizer chip for pentium or cyrix cpu based motherboards using pci. features include eight cpu clocks and six pci clocks. a reference output is available equal to the crystal frequency. the device meets the pentium power-up stabilization, which requires that cpu and pci clocks be stable within 2ms after power-up. the ics9169c-40 clock output are designed for low emi emissions. controlled rise and fall times, unique output driver circuits and innovative circuit layout techniques enable the ics9169c-40 to have lower emi than other clock devices. the ics9169c-40 accepts a 14.318mhz reference crystal or clock as its input and runs from a 3.3v supply. fs2 fs1 fs0 cpu pci 0 0 0 50mhz 33.3mhz 0 0 1 55mhz 36.67mhz 0 1 0 ref/2 ref/4 0 1 1 75mhz 37.5mhz 1 0 0 50mhz 25mhz 1 0 1 55mhz 27.6mhz 1 1 0 60mhz 30mhz 1 1 1 66.6mhz 33.3mhz ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics169c-40 pin descriptions pin number pin name type description 1, 9 vdd pwr power supply 2 ref out buffered output reference. 3.3v 3, 5, 18, 26, 32 gnd pwr digital ground. 4 n/c - not connected. 6, 7, 8, 10, 11, 12 pci (1:6) out clock outputs - controlled by 3.3v v dd 13, 19, 20 fs (0:2) in frequency select inputs, these inputs have internal pull-ups. 14 pd# in input for tristate. if pd# = 0, then all outputs are tristated and the device is in shutdown mode (vco's off, crystal oscillator is off and all logic is reset) when pd# = 1, the device is in normal operating mode. has internal pull-up 15 agnd pwr analog ground 16 n/c - not connected 17 avdd pwr analog power supply 21 vddl1 pwr 3.3/2.5v power supply for cpu (1:4) 22, 23, 24, 25, 27, 28, 29, 30 cpu (1:8) out clock outputs. 31 vddl2 pwr 3.3/2.5v power supply for cpu (5:8) 33 x2 out reference oscillator 34 x1 in reference oscillator
3 ics169c-40 absolute maximum ratings electrical characteristics at 3.3v supply v oltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il - - 0.2v dd v input high voltage v ih 0.7v dd --v input low current i il vin=0v -50.0 25.0 50 a input high current i ih vin=v dd -5.0 - 5.0 a output low voltage 1 v ol iol=12ma; for cpu, pci - 0.3 0.4 v output high voltage 1 v oh ioh=-12ma; for cpu, pci 2.4 2.8 - v output low voltage 1 v ol iol=7.5ma; for ref clk - 0.3 0.4 v output high voltage 1 v oh ioh=-15ma; for ref clk 2.4 2.8 - v output low voltage 1 v ol iol=7.5ma: cpu only; vddl (1:2) = 2.5v -0.30.4v output high voltage 1 v oh ioh=-13ma; cpu only; vddl (1:2) = 2.5v 2.0 2.2 - v supply current i dd @66.6 mhz; all outputs unloaded - 35 65 ma power down current i dd (pd) pd#=0 all logic inputs to vdd -244500a other all logic inputs to gnd -371700a
4 ics169c-40 electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 tr1 15pf load, 0.4 to 2.0v; vdd=vddl for all outputs -0.91.4ns fall time 1 tf1 15pf load, 2.0 to 0.4v; vdd=vddl for all outputs - 0.8 1.2 ns rise time 1 tr2 15pf load, 0.4 to 2.0v; vddl=2.5v & vdd = 2.3v; cpu -1.52.0ns fall time 1 tf2 15pf load, 2.0 to 0.4v; vddl=2.5v & vdd = 3.3v; cpu - 1.4 2.0 ns duty cycle 1 dt 15pf load cpu, pci, ref @ vout=1.5v 45 50 55 % duty cycle 1 dt 15pf load; vddl (1:2)=2.5v vth=1.25v 45 49 55 % jitter, one sigma 1 tj1s1 cpu & pci clocks; load=15pf, vdd=vddl - 50 150 ps jitter, absolute 1 tjab1 cpu & pci clocks; load=15pf, vdd=vddl -220 - 220 ps jitter, one sigma 1 tj1s2 ref; load=15pf - 200 300 ps jitter, absolute 1 tjab2 ref load=15pf -500 - 500 ps jitter, cycle to cycle (for cpu only) t cc vdd=vddl; @ 60mhz -400 - +400 ps vdd=vddl; @ 66mhz -350 - 350 ps vdd=vddl; @ 75mhz -250 - 250 ps vdd=3.3v; vddl=2.5; for all frequencies 400 - 400 ps input frequency 1 fi 12.0 14.318 16.0 mhz logic input capacitance 1 cin logic input pins - 5 - pf crystal oscillator capacitance 1 cinx x1, x2 pins - 18 - pf power-on time 1 ton from vdd=1.6v to 1st crossing of 66.6 mhz vdd supply ramp < 40ms -2.54.5 ms frequency settling time 1 ts from 1st crossing of acquisition to < 1% settling -1.82.0ms clock skew window 1 tsk1 cpu to cpu & pci to pci; load=15pf; @1.5v -250 14.5 250 ps clock skew 1 tsk2 cpu to pci; load=15pf; @1.5v; vdd=vddl; cpu is early 1.0 2.0 4.0 ns clock skew 1 tsk3 cpu to pci; load=15pf; (cpu is early) vddl=2.5v, vth=1.25v; vdd=3.3v, vth=1.5v 0.50 1.5 3.0 ns
5 ics169c-40 technical pin function descriptions vdd/avdd this is the power supply to the internal logic of the device as well as the following clock output buffers: ? pci (1:6) ? ref this pin may be operated at any voltage between 3.0 and 5.5 volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the ac parameter table in this data sheet. gnd/agnd this is the power supply ground return pin for the chip. xin this pin serves one of two functions. when the device is used with a crystal, xin acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, xin is the device? input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. xout this pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, xout is an output signal that drives (or excites) the discrete crystal. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. cpu (1:8) these pins are the clock outputs that drive processor and other cpu related circuitry that require clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks is controlled by that which is applied to the vddl (1:2) pin of the device. see the functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. pci (1:6) outputs for pci bus with a skew 250ps. a high current rate of 60ma is available at 3.3v. these outputs are supplied from vdd. fs0, fs1, fs2 these pins control the frequency of the clocks at the cpu, pci pins. see the funtionality table at the beginning of this data sheet for a list of the specific frequencies, and the selection codes that are necessary to produce these frequencies. the device reads these pins at power-up. if a "1" value is desired for a specific frequency selection bit,a 10k ohm restor must be connected from the apporapriate fs pin to the vdd supply. if a "0" value is desired, then the 10k resistor must be connected to ground. ref this is a fixed frequency clock that runs at the same frequency as the input reference clock (typically 14.31818 mhz) is and typically used to drive video and isa bus requirements. vddl (1:2) this is the power supply to the cpu clock drivers. this pin may be operated "at any voltage" between 2.5 and 3.3 volts. clocks from the buffers that it supplies will have a voltage swing form ground to this level. for the actual guaranteed high and low voltage levels of these clocks. please consult the ac parameter table in this data sheet.
6 ics169c-40 ordering information ics9169cf-40 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp ssop package symbol common dimensions variations d n min. nom. max. min. nom. max. a .097 .101 .104 aa .701 .706 .711 34 a1 .005 .009 .0115 a2 .090 .092 .094 b .014 .016 .019 c .0091 .010 .0125 d see variations e .292 .296 .299 e .040 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 dimensions are in inches ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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