integrated circuit systems, inc. general description features ics9169c-26 block diagram frequency generator and integrated buffers 9169c-26revb091997p pin configuration ? twelve selectable cpu clocks operate up to 83.3 mhz ? eight selectable cpu clocks operate up to100 mhz ? maximum cpu jitter of 200ps ? seven bus clocks support sync or async bus operation ? 500ps skew window for all synchronous clock edges cpu clocks to bus clocks in sync mode skew 1-4ns (cpu early) ? integrated buffer outputs drive up to 30pf loads ? 3.0v - 3.7v supply range ? 36-pin ssop package ? 48 mhz clock for usb support and 24 mhz clock for fd 36-pin ssop functionality 3.3v10%, 0-70 c crystal (x1, x2) = 14.31818 mhz pentium is a trademark on intel corporation. the ics9169c-26 is a low-cost frequency generator designe specifically for pentium?-based chip set systems. the integrated buffer minimizes skew and provides all the clocks required. a 14.318 mhz xtal oscillator provides the reference clock to generate standard pentium frequencies. the cpu clock makes gradual frequency transitions without violating the pll timing of internal microprocessor clock multipliers. either synchronous (cpu/2) or asynchronous (32 mhz) pci bus operation can be selected. bsel fs2 fs1 fs0 cpu (1:8) mhz bus (0:7) mhz 48 mhz 24 mhz ref (1:3) 0 0 0 0 55 27.5 48 24 14.318 0 0 0 1 80 40 48 24 14.318 0 0 1 0 100 50 48 24 14.318 0 0 1 1 75 37.5 48 24 14.318 0 1 0 0 50 25 48 24 14.318 0 1 0 1 66.6 33.3 48 24 14.318 0 1 1 0 60 30.0 48 24 14.318 0 1 1 1 tristate tristate tristate tristate tristate 1 select select select tristate 32.0 48 24 14.318 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. preliminary product preview
2 ics169c-26 preliminary product preview pin descriptions pin number pin name type description 1, 7, 13, 27, 33 vdd pwr power for control logic, pll and output buffers. 2x1in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 12 - 16 mhz crystal, nominally 14.31818 mhz. 3 x2 out xtal output which includes xtal load capacitance. 4, 10, 16, 23, 30 gnd pwr ground for logic, pll and output buffers. 5, 6, 8, 9, 11, 12, 14, 15 cpu(1:8) out processor clock outputs which are a multiple of the input reference frequency as shown in the table above. 17, 18, 19 fs(1:2) in frequency multiplier select pins. see table above. these inputs have internal pull-up devices. 20 bsel in selector for synchronous or asynchronous bus operation. 21, 22, 24, 25, 26, 28, 29 bus(1:7) out bus clock outputs. 31 48mhz out fixed 48 mhz clock (with 14.318 mhz input). 32 24mhz out fixed 24 mhz clock (with 14.318 mhz input). 34, 35, 36 ref(1:3) out ref is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 mhz.
3 ics169c-26 preliminary product preview absolute maximum ratings electrical characteristics at 3.3v supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il --0.2v dd v input high voltage v ih 0.7v dd --v input low current i il v in =0v -28.0 -10.5 - a input high current i ih v in =v dd -5.0 - 5.0 a output low current1 i ol v ol =0.8v; for cpus & buses 30.0 47.0 - ma output high current1 i oh v ol =2.0v; for cpus & buses - -66.0 -42.0 ma output low current1 i ol v ol =0.8v; for fixed clks 25.0 38.0 - ma output high current1 i oh v ol =2.0v; for fixed clks - -47.0 -30.0 ma output low voltage1 v ol i ol =15ma; for cpus & buses - 0.3 0.4 v output high voltage1 v oh i oh =-30ma; for cpus & buses 2.4 2.8 - v output low voltage1 v ol i ol =12.5ma; for fixed clks - 0.3 0.4 v output high voltage1 v oh i oh =-20ma; for fixed clks 2.4 2.8 - v supply current i dd @66.6 mhz; all outputs unloaded - 55 110 ma
4 ics169c-26 preliminary product preview electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v cpu & bus -0.91.5ns fall time 1 t f1 20pf load, 2.0 to 0.8v cpu & bus -0.81.4 ns rise time 1 t r2 20pf load, 20% to 80% cpu & bus -1.52.5ns fall time 1 t f2 20pf load, 80% to 20% cpu & bus -1.42.4 ns duty cycle 1 d t 20pf load @ vout=1.4v 45 50 55 % jitter, one sigma 1 t j1s1 cpu & bus clocks; load=20pf, >25 mhz -50150 ps jitter, absolute 1 t jab1 pclk & bclk clocks; load=20pf, fout>25 mhz -200 - 200 ps jitter, one sigma 1 t j1s2 fixed clk; load=20pf - 1 3 % jitter, absolute 1 t jab2 fixed clk; load=20pf -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator capacitance 1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1st crossing of 66.6 mhz v dd supply ramp < 40ms - 2.5 4.5 ms frequency settling time 1 t s from 1st crossing of acquisition to < 1% settling -2.04.0ms clock skew 1 t sk1 cpu to cpu; load=20pf; @1.4v - 150 250 ps clock skew 1 t sk2 bus to bus; load=20pf; @1.4v - 300 500 ps clock skew 1 t sk3 cpu & bus; load=20pf; @1.4v 1 2.6 4 ns
5 ics169c-26 preliminary product preview ordering information ics9169cf-26 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp this table in inches ssop package symbol common dimensions variations d n min. nom. max. min. nom. max. a .097 .101 .110 aa .602 .607 612 36 a1 .008 .010 .0116 ab .701 .706 .711 44 a2 .090 .092 .094 ac .620 .625 .630 48 b .0091 .014 .017 ad .720 .725 .730 56 c .0091 .010 .0125 d see variations e .292 .296 .299 e .0315 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice.
|
