1. general description the 74aup2g79-q100 provides the dual pos itive-edge triggere d d-type flip-flop. information on the data input (nd) is transferred to the nq output on the low-to-high transition of the clock pulse (ncp). the nd inpu t must be stable one set-up time prior to the low-to-high clock transition for predictable operation. schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire v cc range from 0.8 v to 3.6 v. this device ensures a very low static and dynamic power consumption across the entire v cc range from 0.8 v to 3.6 v. this device is fully specified for pa rtial power-down ap plications using i off . the i off circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 0.8 v to 3.6 v ? high noise immunity ? complies with jedec standards: ? jesd8-12 (0.8 v to 1.3 v) ? jesd8-11 (0.9 v to 1.65 v) ? jesd8-7 (1.2 v to 1.95 v) ? jesd8-5 (1.8 v to 2.7 v) ? jesd8-b (2.7 v to 3.6 v) ? esd protection: ? mil-std-883, method 3015 class 3a. exceeds 5000 v ? hbm jesd22-a114f class 3a. exceeds 5000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? low static power consumption; i cc = 0.9 ? a (maximum) ? latch-up performance exceeds 100 ma per jesd78 class ii ? inputs accept voltages up to 3.6 v ? low noise overshoot and undershoot < 10 % of v cc ? i off circuitry provides partial power-down mode operation 74aup2g79-q100 low-power dual d-type flip-fl op; positive-edge trigger rev. 1 ? 11 june 2013 product data sheet
74aup2g79_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 11 june 2013 2 of 18 nxp semiconductors 74aup2g79-q100 low-power dual d-type flip-flop; positive-edge trigger 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram table 1. ordering information type number package temperature range name description version 74AUP2G79DC-Q100 ? 40 ? c to +125 ? c vssop8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm sot765-1 table 2. marking codes type number marking code [1] 74AUP2G79DC-Q100 p79 fig 1. logic symbol fig 2. iec logic symbol 001aah811 1d 1cp 2d 2cp 1q 2q 001aah812 d cp d cp fig 3. logic diagram (one flip-flop) mna442 cp d c c c c c c c c c tg tg tg tg q c
74aup2g79_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 11 june 2013 3 of 18 nxp semiconductors 74aup2g79-q100 low-power dual d-type flip-flop; positive-edge trigger 6. pinning information 6.1 pinning 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level; ? = low-to-high cp transition; x = don?t care; q = lower case letter indicates the state of referenced inpu t, one set-up time prior to the low-to-high cp transition. fig 4. pin configuration sot765-1 $ 8 3 * 4 & |