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february 2015 docid027443 rev 1 1 / 12 this is information on a product in full production. www.st.com STW40N65M2 n - channel 650 v, 0.087 typ., 32 a mdmesh? m2 power mosfet in a to - 247 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STW40N65M2 650 v 0.099 32 a ? extremely low gate charge ? excellent output capacitance (c oss ) profile ? 100% avalanche tested ? zener - protected applications ? switching applications description this device is an n - channel power mosfet developed using mdmesh? m2 technology. thanks to its strip layout and an improved vertical structure, the device exhibits low on - resistance and optimized switching cha racteristics, rendering it suitable for the most demanding high efficiency converters. table 1: device summary order code marking package packaging STW40N65M2 40n65m2 to -2 47 tube t o-247 1 2 3
contents STW40N65M2 2 / 12 docid027443 rev 1 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.2 electrical characteri stics (curves) ...................................................... 6 3 test circuits ..................................................................................... 8 4 package information ....................................................................... 9 4.1 to - 247 package information ............................................................. 9 5 revision history ............................................................................ 11
STW40N65M2 electrical ratings doci d027443 rev 1 3 / 12 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d drain current (continuous) at t c = 25 c 32 a i d drain current (continuous) at t c = 100 c 20 a i dm ( 1 ) drain current (pulsed) 128 a p tot total dissipation at t c = 25 c 250 w dv/dt ( 2 ) peak diode recovery voltage slope 15 v/ns dv/dt ( 3 ) mosfet dv/dt ruggedness 50 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature 150 notes: ( 1 ) pulse width limited by safe operating area. ( 2 ) i sd 32 a, di/dt 400 a/s; v ds peak < v (br)dss , v dd = 400 v ( 3 ) v ds 520 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max 0.5 c/w r thj - amb thermal resistance junction - ambient max 50 c/w table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repet i tive or not repet i tive (pulse width limited by t jmax ) 3 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 820 mj
electrical characteristics STW40N65M2 4 / 12 docid027443 rev 1 2 electrical characteristics (t c = 25 c unless otherwise specified) table 5: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 650 v i dss zero gate voltage drain current v gs = 0 v, v ds = 650 v 1 a v gs = 0 v, v ds = 650 v, t c = 125 c 100 a i gss gate - body leakage current v ds = 0 v, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 16 a 0.087 0.099 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 2355 - pf c oss output capacitance - 102 - pf c rss reverse transfer capacitance - 2.7 - pf c oss eq. (1) equivalent output capacitance v ds = 0 v to 520 v, v gs = 0 v - 380 - pf r g intrinsic gate resistance f = 1 mhz open drain - 4.5 - q g total gate charge v dd = 520 v, i d = 32 a, v gs = 10 v (see figure 15: "gate charge test circuit" ) - 56.5 - nc q gs gate - source charge - 8 - nc q gd gate - drain charge - 24 - nc notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 325 v, i d = 16 a r g = 4.7 , v gs = 10 v (see figure 14: "switching times test circuit for resistive load" and figure 19: "switching time waveform" ) - 15 - ns t r rise time - 10 - ns t d(off) turn - off- delay time - 96.5 - ns t f fall time - 12 - ns
STW40N65M2 electrical characteristics doci d027443 rev 1 5 / 12 table 8: source drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 32 a i sdm (1) source - drain current (pulsed) - 128 a v sd (2) forward on voltage v gs = 0 v, i sd = 32 a - 1.6 v t rr reverse recovery time i sd = 32 a, di/dt = 100 a/s, v dd = 60 v (see figure 16: " test circuit for inductive load switching and diode recovery times" ) - 468 ns q rr reverse recovery charge - 8.7 c i rrm reverse recovery current - 37.5 a t rr reverse recovery time i sd = 32 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 16: " test circuit for inductive load switching and diode recovery times" ) - 610 ns q rr reverse recovery charge - 11.7 c i rrm reverse recovery current - 39 a notes: (1) pulse width is limited by safe operating area (2) pulse test: pulse duration = 300 s, duty cycle 1.5%
electrical characteristics STW40N65M2 6 / 12 docid027443 rev 1 2.2 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : normalized gate threshold voltage vs temperature figure 7 : normalized v (br)dss vs temperature i d 10 1 0.1 0.1 1 100 10 (a) 100s 1ms 10ms 100 10s operation in this area is limited by max r ds(on) v ds (v) t j = 150 c t c = 25 c single pulse gipd030220151540als k t p ? z th = k*r thj-c = t p / ? single pulse 0.01 =0.5 10 -1 10 -2 10 -3 10 -4 10 -5 10 -3 10 -2 10 -1 0.2 0.1 0.05 0.02 t p (s) gc18460 ds gipg300120151500als v gs = 6,7,8,9,10 v v 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 i d (a) v (v) gs = 5 v v gs = 4 v gipg300120151715als 0 2 4 6 8 70 60 50 40 30 20 10 0 i d (a) v gs (v) v gs = 20 v
STW40N65M2 electrical characteristics doci d027443 rev 1 7 / 12 figure 8 : static drain - source on - resistance figure 9 : normalized on - resistance vs. temperature figure 10 : gate charge vs. gate - source voltage figure 11 : capacitance variations figure 12 : output capacitance stored energy figure 13 : source - drain diode forward characteristics
test circuits STW40N65M2 8 / 12 docid027443 rev 1 3 test circuits figure 14 : switching times test circuit for resistive load figure 15 : gate charge test circuit figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform am01469v1 v dd 47 k 1 k 47 k 2.7 k 1 k 12 v v i v gs 2200 f p w i g = const 100 100 nf d.u.t. v g am01470v1 a d d.u. t . s b g 25 a a b b r g g f ast diode d s l=100 h f 3.3 1000 f v dd d.u. t . v (b r )d s s v dd v dd v d i dm i d am01472v1 am01473v1 0 v gs 90% v ds t on 90% 10% 90% 10% t d(on) t r t t d(off) t f 10% 0 off
STW40N65M2 package information doci d027443 rev 1 9 / 12 4 package information in order to meet environmental requirements, st offers these d evices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 to - 247 package information figure 20 : to - 247 drawing 0075325_h
package information STW40N65M2 10 / 12 docid027443 rev 1 table 9: to - 247 mechanical data dim. mm. min. typ. max. a 4.85 5.15 a1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 d 19.85 20.15 e 15.45 15.75 e 5.30 5.45 5.60 l 14.20 14.80 l1 3.70 4.30 l2 18.50 ?p 3.55 3.65 ?r 4.50 5.50 s 5.30 5.50 5.70
STW40N65M2 revision history doci d027443 rev 1 11 / 12 5 revision history table 10: document revision history date revision changes 0 9 - feb - 2014 1 first release.
STW40N65M2 12 / 12 docid027443 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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