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integrated circuit systems, inc. ics9248-153 third party brands and names are the property of their respective owners. block diagram 9248-153 rev b 5/10/01 functionality pin configuration 48-pin 300mil ssop recommended application: amd-k7 (amd 750, irongate chipset) output features: ? 3 differential pair open drain cpu clocks (1.5v external pull-up; up to 150mhz achieviable through i 2 c) 2 - agpclk @ 3.3v 8 - pci @3.3v, including 1 free running 1 - 48mhz @ 3.3v 1 - 24/48mhz @ 3.3v 2- ref @3.3v, 14.318mhz. features: up to 150mhz frequency support support power management: cpu, pci, stop and power down mode from i 2 c programming. spread spectrum for emi control +/-0.25% center spread uses external 14.318mhz crystal fs pins for frequency select key specifications: cpu ? cpu: <200ps agp-agp: <250ps pci ? pci: <500ps cpu - sdram_out: |250ps| cpu-agp: |250ps| amd-k7 tm system clock chip * internal 120k pullup resistor on indicated inputs ** internal 240k pullup resistor on indicated inputs **fs0/ref0 **fs1/ref1 gndref x1 x2 gndpci pciclk_f pciclk0 vddpci pciclk1 pciclk2 gndpci pciclk3 pciclk4 vddpci pciclk5 pciclk6 vddagp agp0 agp1 gndagp vdd48 48mhz sel24_48#/24-48mhz vddref gndsd sdram_out vddsd reserved cpuclkc2 cpuclkt2 gndcpu cpuclkc1 cpuclkt1 gnd cpuclkc0 cpuclkt0 reserved vdd gnd pci_stop# cpu_stop# pd# spread# fs2* s data sclk gnd48 ics9248-153 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 fs (2:0) spread# cpu_stop# x1 x2 osc pll cpu stop pll2 ref(1:0) cpuclkc(2:0) cpuclkt(2:0) sdram_out 48mhz pciclk (6:0) 24_48mhz pciclk_f pci_stop# sel24_48# pd# / 2 / 3 pci stop x 2 / 2 agp (1:0) power groups vdd48, gnd48 = 48mhz, pll2 vddref, gndref= ref, x1, x2 vdd, gnd = pll core 0 0 0 133.33 33.33 66.67 0 0 1 95 31.67 63.33 0 1 0 100.99 33.66 67.33 0 1 1 115 38.33 76.67 1 0 0 100.7 33.57 67.13 1 0 1 103 34.33 68.67 1 1 0 105 35.00 70.00 1 1 1 110 36 . 6 77 3 . 33 pci agp fs2 fs1 fs0 cpu , sdram ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9248-153 third party brands and names are the property of their respective owners. pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1 , 2 ) 0 : 1 ( s fn id d v o t p u - l l u p s a h , s n i p t c e l e s y c n e u q e r f ) 0 : 1 ( f e rt u ot u p t u o k c o l c z h m 8 1 3 . 4 1 , 5 2 , 1 2 , 6 , 3 7 4 , 1 4 , 8 3 , 3 3 d n gr w pd n u o r g 41 xn i d a o l f p 3 3 l a n r e t n i s a h , t u p n i l a t s y r c z h m 8 1 3 . 4 1 n i _ l a t x 2 x m o r f r o t s i s e r k c a b d e e f d n a p a c 52 xt u of p 3 3 p a c d a o l l a n r e t n i s a h , t u p t u o l a t s y r c t u o _ l a t x 7f _ k l c i c pt u o # p o t s _ i c p e h t y b d e t c e f f a t o n . t u p t u o i c p g n i n n u r e e r f . t u p n i 8 , 0 1 , 1 1 , 3 1 , 4 1 , 6 1 , 7 1) 0 : 6 ( k l c i c pt u ov 3 . 3 e l b i t a p m o c l t t . s t u p t u o k c o l c i c p 5 1 , 9i c p d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o k l c i c p r o f r e w o p 8 1p g a d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o p g a r o f r e w o p 9 1 , 0 2) 0 : 1 ( p g at u o. d e p p o t s e b t o n y a m e s e h t . i c p x 2 s a d e n i f e d s t u p t u o p g a 4 3d d vr w pv 3 . 3 y l l a n i m o n , e r o c r o f r e w o p d e t a l o s i 2 28 4 d d vr w pv 3 . 3 y l l a n i m o n s t u p t u o z h m 4 2 d n a z h m 8 4 r o f r e w o p 3 2z h m 8 4t u ot u p t u o z h m 8 4 4 2 # 8 4 - 4 2 l e sn i 4 2 n i p r o f t u p t u o z h m 8 4 r o 4 2 s t c e l e s z h m 4 2 = h g i h z h m 8 4 = w o l z h m 8 4 - 4 2t u o# 8 4 - 4 2 l e s h g u o r h t e l b a t c e l e s t u o k c o l c d e x i f 6 2k l c sn ii f o n i p k c o l c 2 t n a r e l o t v 5 y r t i u c r i c c 7 2a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 8 22 s fn id d v o t p u - l l u p s a h , n i p t c e l e s y c n e u q e r f 9 2# d a e r p sn i f o d a e r p s r e t n e c . w o l n e h w e r u t a e f m u r t c e p s d a e r p s s e l b a n e . % 5 2 . 0 - / + 0 3# d pn i s t u p t u o l l a & l l p l a n r e t n i . w o l e v i t c a , p i h c n w o d s r e w o p . d e l b a s i d e r a 1 3# p o t s _ u p cn i s a r e h w w o l n e v i r d s i t k l c u p c . s k l c u p c s t l a h d e t r e s s a s i n i p s i h t n e h w h g i h n e v i r d s i c k l c u p c . ) w o l e v i t c a ( 2 3# p o t s _ i c pn i f _ k l c i c p . w o l n e v i r d n e h w l e v e l " 0 " c i g o l t a s u b i c p s t l a h n i p s i h t y b d e t c e f f a t o n s i 6 4t u o _ m a r d st u or e f f u b y a l e d o r e z m a r d s r o f k c o l c e c n e r e f e r 4 4 , 5 3d e v r e s e rc / nl i a r r e w o p u p c e r u t u f 6 3 , 9 3 , 2 4) 0 : 2 ( t k l c u p ct u o n e p o e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . p u - l l u p v 5 . 1 l a n r e t x e n a d e e n s t u p t u o n i a r d 7 3 , 0 4 , 3 4) 0 : 2 ( c k l c u p ct u o e s e h t . t u p t u o u p c r i a p l a t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c " . p u _ l l u p v 5 . 1 l a n r e t x e n a d e e n s t u p t u o n i a r d n e p o 5 4d s d d vr w pv 3 . 3 y l l a n i m r o n . n i p t u o _ m a r d s r o f r e w o p 8 4f e r d d vr w pv 3 . 3 y l l a n i m o n , 2 x , 1 x , f e r r o f r e w o p
3 ics9248-153 third party brands and names are the property of their respective owners. notes: 1. default at power-up will be latched logic inputs to define frequency, as displayed by bit 1. 2. pwd = power-up default byte 6: sdram clock & generator mode control register i 2 c command bitmaps bit pwd 7 0 00 0 0 0 133.33 33.33 66.67 00 0 0 1 95 31.67 63.33 00 0 1 0 100.99 33.66 67.33 00 0 1 1 115 38.33 76.67 00 1 0 0 100.7 33.57 67.13 00 1 0 1 103 34.33 68.67 00 1 1 0 105 35.00 70.00 00 1 1 1 110 36.67 73.33 01 0 0 0 102 34.00 68.00 01 0 0 1 104 34.67 69.33 01 0 1 0 106 35.33 70.67 01 0 1 1 107 35.67 71.33 01 1 0 0 108 36.00 72.00 01 1 0 1 109 36.33 72.67 01 1 1 0 90 30.00 60.00 01 1 1 1 111 37.00 74.00 10 0 0 0 112 37.33 74.67 10 0 0 1 113 37.67 75.33 10 0 1 0 114 38.00 76.00 10 0 1 1 116 38.67 77.33 10 1 0 0 117 39.00 78.00 10 1 0 1 118 39.33 78.67 10 1 1 0 119 39.67 79.33 10 1 1 1 120 30.00 60.00 11 0 0 0 142 35.50 71.00 11 0 0 1 144 36.00 72.00 11 0 1 0 146 36.50 73.00 11 0 1 1 138 34.50 69.00 11 1 0 0 136 34.00 68.00 11 1 0 1 135 33.75 67.50 11 1 1 0 140 35.00 70.00 11 1 1 1 150 37.50 75.00 0 0 - sdram_out disable 1 - sdram _ out enable 1 agp 01000 note1 1 0 - frequency is selected by hardware select, latched input; spread controlled by pin 29 1 - frequency is selected by bit (6:2); spread controlled by bit 7 0 description spread spectrum enable (+/- 0.25% center spread) 0=off 1=on 6:2 bit 3 bit 2 fs2 bit 6 fs1 bit 5 fs0 bit 4 cpu, sdram pci
4 ics9248-153 third party brands and names are the property of their respective owners. i 2 c command bitmaps byte 4: clock control register notes: a value of '1' is enable, '0' is disable t i b# n i pt l u a f e dn o i t p i r c s e d 71 1 e l b a n e 0 f e r 64 21 e l b a n e z h m 8 4 / z h m 4 2 53 21 e l b a n e z h m 8 4 40 21 e l b a n e 1 p g a 39 11 e l b a n e 0 p g a 23 4 , 2 41 " y r a t n e m i l p m o c " d n a " e u r t , r i a p l a i t n e r e f f i d f o h t o b ( e l b a n e 2 k l c u p c 10 4 , 9 31 " y r a t n e m i l p m o c " d n a " e u r t , r i a p l a i t n e r e f f i d f o h t o b ( e l b a n e 1 k l c u p c 07 3 , 6 31 " y r a t n e m i l p m o c " d n a " e u r t , r i a p l a i t n e r e f f i d f o h t o b ( e l b a n e 0 k l c u p c byte 5: pci clock control register notes: a value of '1' is enable, '0' is disable t i b# n i pt l u a f e dn o i t p i r c s e d 72 1 e l b a n e 1 f e r 67 11 e l b a n e 6 k l c i c p 56 11 e l b a n e 5 k l c i c p 44 11 e l b a n e 4 k l c i c p 33 11 e l b a n e 3 k l c i c p 21 11 e l b a n e 2 k l c i c p 10 11 e l b a n e 1 k l c i c p 08 1 e l b a n e 0 k l c i c p
5 ics9248-153 third party brands and names are the property of their respective owners. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5 a input low current i il1 v in = 0v; inputs with no pull-up resistors -5 a input low current i il2 v in = 0v; inputs with pull-up resistors -200 a i dd3.3op100 c l = 0 pf; select @ 100 mhz 180 ma i dd3.3op133 c l = 0 pf; select @ 133 mhz 180 ma powerdown current i dd3.3pd c l = 0 pf; input address to vdd or gnd 600 a input frequency f i v dd = 3.3 v 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms t cpu-sdram v t = 50%, cpu=100mhz -250 -210 ps t cpu-agp v t = 50%, cpu=100mhz -250 0 ps 1 guaranteed by design, not 100% tested in production. input capacitance 1 operating supply current skew 1
6 ics9248-153 third party brands and names are the property of their respective owners. electrical characteristics - cpuclk (open drain) t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% ; c l = 20 pf ( un l ess ot h erw i se state d) . p a r a meter s ymb o l co nditi o n s min typ m a x unit s output impedance z o 1 v o = v x 60 ? output high voltage v oh2b termination to v pull-up (external) 11.2v output low voltage v ol2b termination to v pull-up (external) 0.4 v output low current i ol2b v ol = 0.3 v 18 ma rise time t r2b 1 v ol = 20%, v oh = 80% 2.4 2.6 ns fall time t f2b 1 v oh = 80%, v ol = 20% 1.2 2.6 ns duty cycle d t2b 1 v t = 50% 42 45.4 52 % differential voltage-ac v dif 1 note 2 0.4 1.03 v pull-up (external) + 0.6 v differential voltage-dc v dif 1 note 2 0.2 v pull-up (external) + 0.6 v differential crossover voltage v x 1 note 3 400 412 950 mv skew t sk2b 1 v t = 50% 55 200 ps jitter, absolute t jabs2b 1 v t = 50% -250 120 +250 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = v x 99 250 ps notes: 1 - guaranteed by design, not 100% tested in production. 2 - v dif specifies the minimum input differential voltages (v tr -v cp ) required for switching, where v tr is the "true" input level and vcp is the "complement" input level. 3 - vpull-up(external) = 1.5v, min = (v pull-up(external) /2) - 150mv; max = (v pull-up(external) /2) + 150mv electrical characteristics - usb, ref t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , c l = 20 pf ( un l ess ot h erw i se state d) . parameter s ymb o l co nditi o n s min typ max unit s output high voltage v oh5 i oh = -12 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 2.28 4 ns fall time t f5 1 v oh = 2.4v, v ol = 0.4 v 2.28 4 ns duty cycle d t5 1 v t = 50% 45 52.5 55 % jitter, cycle-to-cycle, ref t jcyc-cyc5, ref 1 v t = 50% 402 1000 ps jitter, cycle-to-cycle, fixed clock t jcyc-cyc5, fixed 1 v t = 50% 248 500 ps 1 guaranteed by design, not 100% tested in production.
7 ics9248-153 third party brands and names are the property of their respective owners. electrical characteristics - pciclk_f t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , c l = 30 pf ( un l ess ot h erw i se state d) . p a r a meter s ymb o l co nditi o n s min typ m a xunit s output high voltage v oh1 i oh = -11 ma 2.6 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -12 ma output low current i ol1 v ol = 0.8 v 12 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.56 2 ns fall time t f1 1 v oh = 2.4v, v ol = 0.4 v 1.56 2 ns duty cycle d t1 1 v t = 50% 45 51.3 55 % jitter, cycle-to-cycle t jcyc-cyc 1 v t = 50% 88 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk t a = 0 - 70 o c; v dd = 3.3 v +/- 5 %, c l = 30 pf (un l ess ot h erw i se state d ). parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.6 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -16 ma output low current i ol1 v ol = 0.8 v 19 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.56 2 ns fall time t f1 1 v oh = 2.4v, v ol = 0.4 v 1.56 2 ns duty cycle d t1 1 v t = 50% 45 51.3 55 % skew (window) t sk1 1 v t = 50% 320 500 ps jitter, cycle-to-cycle t jcyc-cyc 1 v t = 50% 88 500 ps 1 guaranteed by design, not 100% tested in production.
8 ics9248-153 third party brands and names are the property of their respective owners. electrical characteristics - agp t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , c l = 20 pf ( un l ess ot h erw i se state d) . parameter s ymb o l co nditi o n s min typ max unit s output high voltage v oh4b i oh = -18 ma 2 v output low voltage v ol4b i ol = 18 ma 0.4 v output high current i oh4b v oh = 2.0 v -19 ma output low current i ol4b v ol = 0.8 v 19 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.4 v 1.27 2 ns fall time t f4b 1 v oh = 2.4v, v ol = 0.4 v 1.10 2 ns duty cycle d t4b 1 v t = 50% 45 50.6 55 % skew (window) t sk4b 1 v t = 50% 30 250 ps jitter, cycle-to-cycle t jcyc-cyc4b 1 v t = 50% 272 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram_out t a = 0 - 70 o c; v dd = 3.3 v +/- 5 %, c l = 30 pf (un l ess ot h erw i se state d ). parameter symbol conditions min typ max units output high voltage v oh3 i oh = -11 ma 2 v output low voltage v ol3 i ol = 11 ma 0.4 v output high current i oh3 v oh = 2.0 v -12 ma output low current i ol3 v ol = 0.8 v 12 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.90 2.2 ns fall time t f3 1 v oh = 2.4v, v ol = 0.4 v 0.77 2.2 ns duty cycle d t3 1 v t = 50% 455255% jitter, cycle-to-cycle t jcyc-cyc3 1 v t = 50% 89 250 ps 1 guaranteed by design, not 100% tested in production.
9 ics9248-153 third party brands and names are the property of their respective owners. 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 ack byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
10 ics9248-153 third party brands and names are the property of their respective owners. fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9248- 153 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
11 ics9248-153 third party brands and names are the property of their respective owners. general description the ics9248-153 is a main clock synthesizer chip for amd-k7 based systems. this provides all clocks required for such a system when used with a zero delay buffer chip such as the ics9179-06. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248-153 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-153 . all other clocks will continue to run while the cpuclks clocks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9248-153 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state. pciclk cpuclkt cpuclkc pd# (high) cpu_stop# internal cpuclk
12 ics9248-153 third party brands and names are the property of their respective owners. pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-153 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ics9248-153 internally. pciclk (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state. cpuclk (internal) pciclk (internal) pciclk (free-runningl) cpu_stop# pwr_dwn# pciclk (external) pci_stop#
13 ics9248-153 third party brands and names are the property of their respective owners. pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248-153 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclkt cpuclkc pciclk vco crystal pd#
14 ics9248-153 third party brands and names are the property of their respective owners. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2 . 41 2 . 80 . 095 . 110 a1 0 . 20 0 . 40 . 008 . 016 b 0 . 20 0 . 34 . 008 . 0135 c 0 . 13 0 . 25 . 005 . 010 d e 10 . 03 10 . 68 . 39 5. 420 e1 7 . 40 7 . 60 . 291 . 299 e h 0 . 38 0 . 64 . 015 . 025 l 0 .5 0 1 . 02 . 020 . 040 n ordering information ics9248 y f-153-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device example: ics xxxx y f - ppp - t

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