integrated circuit systems, inc. general description features ics9248-55 block diagram pentium/pro/ ii tm system clock chip 9248-55 rev b 12/04/98 pin configuration 48-pin ssop pentium is a trademark on intel corporation. ? generates system clocks for cpu, ioapic, pci, plus 14.314 mhz ref (0:2), usb, and super i/o ? supports single or dual processor systems ? supports spread spectrum modulation for cpu & pci clocks, down spread -0.5% ? skew from cpu (earlier) to pci clock (rising edges for 100/33.3mhz) 1.5 to 4ns ? two fixed outputs at 48mhz. ? separate 2.5v and 3.3v supply pins ? 2.5v or 3.3v output: cpu, ioapic ? 3.3v outputs: pci, ref, 48mhz ? no power supply sequence requirements ? uses external 14.318mhz crystal, no external load cap required for c l =18pf crystal ? 48 pin 300 mil ssop the ics9248-55 is a clock synthesizer chip for pentium and pentiumpro cpu based desktop/notebook systems that will provide all necessary clock timing. features include four cpu and eight pci clocks. three reference outputs are available equal to the crystal frequency. additionally, the device meets the pentium power-up stabilization requirement, assuring that cpu and pci clocks are stable within 2ms after power-up. pd# pin enables low power mode by stopping crystal osc and pll stages. other power management features include cpu_stop#, which stops cpu (0:3) clocks, and pci_stop#, which stops pciclk (0:6) clocks. high drive cpuclk outputs typically provide greater than 1 v/ns slew rate into 20pf loads. pciclk outputs typically provide better than 1v/ns slew rate into 30pf loads while maintaining 505% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. the ics9248-55 accepts a 14.318mhz reference crystal or clock as its input and runs on a 3.3v core supply. power groups vdd = supply for pll core vdd1 = ref (0:2), x1, x2 vdd2 = pciclk_f, pciclk (0:6) vdd3 = 48mhz0, 48mhz1 vddl1 = ioapic (0:1) vddl2 = cpuclk (0:3) ground groups gnd = ground for pll core gnd1 = ref (0:2), x1, x2 gnd2 = pciclk_f, pciclk (0:6) gnd3 = 48mhz0, 48mhz1 gndl1 = ioapic (0:1) gndl2 = cpuclk (0:3) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. * internal pull-down resistor of 240k to gnd. on indicated inputs
2 ics9248-55 pin descriptions select functions functionality cpu pci, pci_f ref ioapic 48 mhz selection tristate hi - z hi - z hi - z hi - z hi - z testmode tclk/2 1 tclk/6 1 tclk 1 tclk 1 tclk/2 1 spread spectrum modulated 2 modulated 2 14.318mhz 14.318mhz 48.0mhz pin number pin name type description 1, 2 ref0, ref1 out 14.318mhz clock output 3 gnd1 pwr ground for ref outputs 4x1in xtal_in 14.318mhz crystal input, has internal 33pf load cap and feed back resistor from x2 5 x2 out xtal_out crystal output, has internal load cap 33pf 6, 12, 18 gnd2 pwr ground for pci outputs 7 pciclk_f out free running pci output 8, 10, 11, 13, 14, 16, 17 pciclk (0:6) out pci clock outputs. ttl compatible 3.3v 9, 15 vdd2 pwr power for pciclk outputs, nominally 3.3v 19, 33 vdd pwr isolated power for core, nominally 3.3v 20, 32 gnd pwr isolated ground for core 21 vdd3 pwr power for 48mhz outputs, nominally 3.3v 22, 23 48mhz (0:1) out 48mhz outputs 24 gnd3 pwr ground for 48mhz outputs 25, 26, 27 fs (0:2) in frequency select pins 28 spread# in enables spread spectrum feature when low 29 pd# in powers down chip, active low 30 cpu_stop# in halts cpu clocks at logic "0" level when low 31 pci_stop# in halts pci bus at logic "0" level when low 37, 41 vddl2 pwr power for cpu outputs, nominally 2.5v 34, 38 gndl2 pwr ground for cpu outputs. 35, 36, 39, 40 cpuclk (3:0) out cpu and host clock outputs @ 2.5v 42 n/c - not internally connected 43 gndl1 pwr ground for ioapic outputs 44, 45 ioapic (0:1) out ioapic outputs (14.318mhz) @ 2.5v 46 vddl1 pwr power for ioapic outputs, nominally 2.5v 47 ss_sel in .25% spread spectrum selector at power up. logic 0 for downspread logic 1 for centerspread ref2 out 14.318mhz clock output 48 vdd1 pwr supply for ref (0:2), x1, x2, nominal 3.3v fs2 fs1 fs0 cpu mhz pci mhz 0 0 0 133 33.25 0 0 1 83.3 41.65 010 75 37.5 0 1 1 66.6 33.3 1 0 0 124 41.33 1 0 1 133 44.3 1 1 0 112 37.3 1 1 1 100 33.3
3 ics9248-55 power management ics9248-55 power management requirements clock enable configuration full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. during power up and power down operations using the pd# select pin will not cause clocks of a shorter or longer pulse than that of the running clock. the first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. board routing and signal loading may have a large impact on the initial clock distortion also. notes. 1. clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device . 3. power up latency is when pd# goes inactive (high) to when the first valid clocks are output by the device. 4. power down has controlled clock counts applicable to cpuclk, pciclk only. the ref and ioapic will be stopped independent of these. signal signal state latency no. of rising edges of free running pciclk cpu_ stop# 0 (disabled) 2 1 1 (enabled) 1 1 pci_stop# 0 (disabled) 2 1 1 (enabled) 1 1 pd# 1 (normal operation) 3 3ms 0 (power down) 4 2max cpu_stop# pci_stop# pwr_dwn# cpuclk pciclk other clocks, ref, ioapics, 48 mhz 0 48 mhz 1 crystal vcos x x 0 low low stopped off off 0 0 1 low low running running running 0 1 1 low running running running running 1 0 1 running low running running running 1 1 1 running running running running running
4 ics9248-55 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-55 . it is used to turn off the pciclk (0:6) clocks for low power operation. pci_stop# is synchronized by the ics9248-55 internally. the minimum that the pciclk (0:6) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:6) clocks. pciclk (0:6) clocks are stopped in a low state and started with a full high pul se width guaranteed. pciclk (0:6) clock on latency cycles are only one rising pciclk. clock off latency is one pciclk clock. cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-55 . the minimum that the cpuclk is enabled (cpu_stop# high pulse) is 100 cpuclks. all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9248-55 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248-55. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state.
5 ics9248-55 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal is synchronized internally by the ics9248-55 prior to its control action of powering down the clock synthesizer. internal clocks will not be running after the device is put in power down state. when pd# is active (low) all clocks are driven to a low state and held prior to turning off the vcos and the crystal oscillator. the pow er on latency is guaranteed to be less than 3ms. the power down latency is less than three cpuclk cycles. pci_stop# and cpu_stop# are don?t care signals during the power down operations. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device). 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside the ics9248. 3. the shaded sections on the vco and the crystal signals indicate an active clock is being generated.
6 ics9248-55 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a operating i dd3 .3 op6 6 c l = 0 pf; select @ 66mhz 60 170 ma supply current i dd3.3op100 c l = 0 pf; select @ 100mhz 66 170 ma power down supply current i dd3 .3 pd c l = 0 pf; with input address to vdd or gnd 70 600 a input frequency f i v dd = 3.3 v; 11 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cpu-pci1 v t = 1.5 v; 1.5 3 4 ns 1 guaranteed by design, not 100% tested in production. input capacitance 1 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op66 c l = 0 pf; select @ 66.8 mhz 16 72 ma supply current i dd2.5op100 c l = 0 pf; select @ 100 mhz 23 100 ma skew 1 t cpu-pci2 v t = 1.5 v; v tl = 1.25 v 1.5 3 4 ns 1 guaranteed by design, not 100% tested in production.
7 ics9248-55 electrical characteristics - cpuclk t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.3 v output low voltage v ol2 b i ol = 12 ma 0.2 0.4 v output high current i oh2 b v oh = 1.7 v -41 -19 ma output low current i ol2 b v ol = 0.7 v 19 37 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.25 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v 454855% skew t sk2b 1 v t = 1.25 v 30 175 ps jitter, cycle-to-cycle t j cyc-cyc2b 1 v t = 1.25 v 150 200 ps jitter, one sigma t j 1s2b 1 v t = 1.25 v 40 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 140 +250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output high voltage v oh4 b i oh = -18 ma 2 2.2 v output low voltage v ol4 b i ol = 18 ma 0.33 0.4 v output high current i oh4 b v oh = 1.7 v -41 -28 ma output low current i ol4 b v ol = 0.7 v 29 37 ma rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 1.5 2 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 1.3 2 ns duty cycle 1 d t4b v t = 1.25 v 455455% skew 1 t sk4b 1 v t = 1.25 v 60 250 ps jitter, one sigma 1 t j1s4b v t = 1.25 v 1 3 % jitter, absolute 1 t jabs4b v t = 1.25 v -5 5 % 1 guaranteed by design, not 100% tested in production.
8 ics9248-55 electrical characteristics - pciclk t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.1 0.4 v output high current i oh1 v oh = 2.0 v -62 -22 ma output low current i ol1 v ol = 0.8 v 16 57 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t1 v t = 1.5 v 455055% skew 1 t sk1 v t = 1.5 v 140 500 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 17 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -500 70 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 3.1 v output low voltage v ol5 i ol = 9 ma 0.17 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 29 42 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t5 v t = 1.5 v 455355% jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 35% 1 guaranteed by design, not 100% tested in production.
9 ics9248-55 electrical characteristics - 48 mhz t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units frequency accuracy 1 f acc4 8 m 167 ppm output high voltage v oh5 i oh = -12 ma 2.6 3 v output low voltage v ol5 i ol = 9 ma 0.14 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 16 42 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.2 4 ns duty cycle 1 d t5 v t = 1.5 v 455255% jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 35% 1 guaranteed by design, not 100% tested in production.
10 ics9248-55 ordering information ics9248bf-55 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp this table in inches ssop package symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 ad .720 .725 .730 56 a2 .088 .090 .092 b .008 .010 .0135 c .005 .006 .0085 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
|
