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coolset?-f3 ICE3A1065LJ off-line smps current mode controller with integrated 650v startup cell/depletion coolmos? ( latched and frequency jitter mode ) never stop thinking. power management & supply version 2.4, 19 nov 2012
edition 2012-11-19 published by infineon technologies ag, 81726 munich, germany, ? 2012 infineon technologies ag. all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical valu es stated herein and/or any information regarding the application of the device, infineon technologies her eby disclaims any and all warranties and liabilities of any kind, including wi thout limitation, warranties of non-infrin gement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices, please contact your nearest infineon technologies office (www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact your neare st infineon technologies office. infineon technologies components may be used in life-s upport devices or systems onl y with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representat ives worldwide: see our webpage at http:// www.infineon.com coolmos?, coolset? are trademarks of infineon technologies ag. coolset?-f3 ICE3A1065LJ revision history: 2012-11-19 datasheet previous version: 2.3 page subjects (major changes since last revision) 22 revised outline dimension for pg-dip-8 package
type package marking v ds f osc r dson 1) 1) typ @ t=25c 230vac 15% 2) 2) calculated maximum input power rating at t a =75c, t j =125c and without copper area as heat sink. 85-265 vac 2) ICE3A1065LJ pg-dip-8 ICE3A1065LJ 650v 100khz 2.95 32w 16w version 2.4 3 19 nov 2012 coolset? -f3 ICE3A1065LJ off-line smps current mode controller with integrated 650v startup ce ll/depletion coolmos? ( latched and frequency jitter mode ) test pg-dip-8 description the coolset?-f3 meets the requirements for off-line battery adapters and low cost smps for the lower power range. adopting the bicmos technology, the ic can provide a wider vcc range up to 26v. furthermore the active burst mode is integrated to achieve the lowest standby power requirements <100mw at no load and v in = 270vac. as the controller is always active during the active burst mode, it is an immediate response on load jumps. and it leads to <1% ripple of the output voltage. in case of overtemperature, ov ervoltage or short winding, it enters into latched off mode, which can be reset by re- cycling the ac main line. when there are open loop and overload conditions, it would enter auto restart mode. in addition, an external latch enable function is provided for extra flexibility in protection. wi th the built-in soft start, the component count can be further reduced. the internal precise peak current limitation can effectively optimize the dimension of the transformer and the output diode. the built-in and extendable blanki ng window can prevent the mis-triggering of auto restart mode. the frequency jitter mode can effectively reduce the emi noise and further reduce the components in input filter. product highlights ? active burst mode to reach the lowest standby power requirements < 100mw ? built-in latched off mode and external latch enable function to increase robustness of the system ? built-in and extendable blanking window for high load jumps to increase system reliability ? built-in soft start ? frequency jitter for low emi ? pb-free lead plating; rohs compilant features ? 650v avalanche rugged coolmos? with built-in startup cell ? active burst mode for lowest standby power ? fast load jump response in active burst mode ? 100khz internally fixed switching frequency ? built-in latched off mode for overtemperature, overvoltage & short winding detection ? auto restart mode for overload, open loop & vcc undervoltage ? built-in soft start ? built-in and extendable blanking window for short duration high current ? external latch enable function ? max duty cycle 75% ? overall tolerance of current limiting < 5% ? internal pwm leading edge blanking ? bicmos technology provide wide vcc range ? frequency jitter and soft driving for low emi c vcc c bulk converter dc output + snubber power management pwm controller current mode 85 ... 270 vac typical application r sense bl fb gnd active burst mode latched off mode auto restart mode control unit - cs vcc startup cell precise low tolerance peak current limitation drain coolset?-f3 ( latch & jitter ) depl. coolmos?
coolset?-f3 ICE3A1065LJ table of contents page version 2.4 4 19 nov 2012 1 pin configurati on and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin configuration with pg-dip-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 representative blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.2 pwm-latch ff1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5.1 leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5.2 propagation delay com pensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.6 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6.1 basic and extendable blankin g mode . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6.2 active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.2.1 entering active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.2.2 working in active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.2.3 leaving active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.3 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.3.1 latched off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.3.2 auto restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.1 absolute maximum rating s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3.4 soft start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3.5 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3.6 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.3.7 coolmos? section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5 temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 7 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 8 schematic for recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . .24
version 2.4 5 19 nov 2012 coolset?-f3 ICE3A1065LJ pin configurati on and functionality 1 pin configuration and functionality 1.1 pin configuration with pg-dip-8 figure 1 pin configuration pg-dip-8(top view) note: pin 4 and 5 are shorted within the dip 8 package. 1.2 pin functionality bl (blanking and latch) the bl pin combines the functions of extendable blanking time for entering the auto restart mode and the external latch enable. the extendable blanking time function is to extend the built -in 20ms blanking time by adding an external capacitor at bl to ground. the external latch enable function is an external access to latch off the ic. it is triggered by pulling down the bl pin to less than 0.1v. fb (feedback) the information about the re gulation is provided by the fb pin to the internal protec tion unit and to the internal pwm-comparator to control the duty cycle. the fb- signal controls in case of light load the active burst mode of the controller. cs (current sense) the current sense pin senses the voltage developed on the series resistor inserted in the source of the integrated depl. coolmos?. if cs reaches the internal threshold of the current limit comparator, the driver output is immediately switched off. furthermore the current information is provided for the pwm- comparator to realize the current mode. drain (drain of integr ated depl. coolmos?) pin drain is the connection to the drain of the internal depl. coolmos tm . vcc (power supply) the vcc pin is the positive supply of the ic. the operating range is between 10.5v and 26v. gnd (ground) the gnd pin is the ground of the controller. pin symbol function 1 bl blanking and latch 2 fb feedback 3 cs current sense/ 650v 1) depl. coolmos? source 1) at t j = 110c 4 drain 650v 1) depl. coolmos? drain 5 drain 650v 1) depl. coolmos? drain 6 n.c. not connected 7 vcc controller supply voltage 8 gnd controller ground package pg-dip-8 1 6 7 8 4 3 2 5 gnd bl fb cs vcc n.c. drain drain
version 2.4 6 19 nov 2012 coolset?-f3 ICE3A1065LJ representative blockdiagram 2 representative blockdiagram figure 2 representative blockdiagram internal bias voltage reference oscillator duty cycle max c11 x3.2 current limiting pwm op current mode soft start c2 c1 24v 0.1v r fb power management c bk c vcc 85 ... 270 vac c bulk + conver t dc out p v out spike blanking 8.0us pwm comparator c3 4.0v c4 4.5v gate driver 0.72 clock r sense 10k d1 c6a 3.0v c5 1.35v c10 1.66v r s q auto restart mode & g7 & g5 & g9 1 g8 & g1 1 g3 thermal shutdown t j >140c 0.9v s1 1 power-down reset latched off mode reset v vcc < 6.23v latched off mode cs bl gnd vcc c7 c8 fb pwm section control unit ff1 c12 & 0.31v leading edge blanking 220ns 25k 2pf 5.0v g10 spike blanking 190 ns 1pf propagation-delay compensation 5.0v undervoltage lockout v csth g2 - ice3xxxxxlj / coolset?-f3 ( latch & jitter mode ) snubber vcc drain depl. coolmos? startup cell c6b & g6 3.61v & g11 active burst mode 0.6v 10.5v 18v latch enable signal t le #1 #2 # : optional external components; #1 : c bk is used to extand the blanking time #2 : t le is used to enable the external latch function freq. jitter 20ms blanking time 20ms blanking time 8us blanking time 1 ms counter soft start block soft-start comparator spike blanking 8.0us t2 3.25k 5.0v t1 t3 0.6v i bk
version 2.4 7 19 nov 2012 coolset?-f3 ICE3A1065LJ functional description 3 functional description all values which are used in the functional description are typical values. for calculating the worst cases the min/max values which can be found in section 4 electrical characteristics have to be considered. 3.1 introduction coolset?-f3 is the further development of the coolset?-f2 to meet the requirements for the lowest standby power at minimum load and no load conditions. a new fully integrated standby power concept is implemented into the ic in order to keep the application design easy. compared to coolset?-f2 no further external parts are needed to achieve the lowest standby power. an intelligent active burst mode is used for this standby mode. after entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal pwm control. the response on load jumps is optimized. the voltage ripple on v out is minimized. v out is on well controlled in this mode. the usually external connected rc-filter in the feedback line after the optocoupler is integrated in the ic to reduce the external part count. furthermore a high voltage startup cell is integrated into the ic which is switched off once the undervoltage lockout on-threshold of 18v is exceeded. this startup cell is part of the integrated depl. coolmos?. the external startup resistor is no longer necessary as this startup cell is connected to the drain. power losses are therefore reduced. this increases the efficiency under light load conditions drastically. this version is adopting the bicmos technology and it can increase design flexibility as the vcc voltage range is increased to 26v. for this lj version, the soft start is a built-in function. it is set at 20ms. then it can save external component counts. there are 2 modes of blanki ng time for high load jumps; the basic mode and the extendable mode. the blanking time for the basic mode is pre-set at 20ms while the extendable mode will increase the blanking time at basic mode by adding external capacitor at the bl pin. during this time wi ndow the overload detection is disabled. with this concept no further external components are necessary to adjust the blanking window. in order to increase the robustness and safety of the system, the ic provides 2 levels of protection modes: latched off mode and auto restart mode. the latched off mode is only entered under dangerous conditions which can damage the smps if not switched off immediately. a restart of the system can only be done by recycling the ac line. in addition, for this lj version, there is an external latch enable function provided to increase the flexibility in protection. when the bl pin is pulled down to less than 0.1v, the latch off mode is triggered. the auto restart mode reduces the average power conversion to a minimum under unsafe operating conditions. this is necessary for a prolonged fault condition which could otherwise lead to a destruction of the smps over time. once the malfunction is removed, normal operation is automatically retained after the next start up phase. the internal precise peak current limitation reduces the costs for the transformer and the secondary diode. the influence of the change in the input voltage on the power limitation can be av oided together with the integrated propagation delay compensation. therefore the maximum power is nearly independent on the input voltage which is required for wide range smps. there is no need for an extra over-sizing of the smps, e.g. the transformer or the secondary diode. furthermore, this lj version implements the frequency jitter mode to the switching clock such that the emi noise will be effectively reduced. 3.2 power management figure 3 power management the undervoltage lockout monitors the external supply voltage v vcc . when the smps is plugged to the main line the internal startu p cell is biased and starts internal bias voltage reference power management latched off mode reset v vcc < 6.23v 5.0v latched off mode undervoltage lockout 18v 10.5v power-down reset active burst mode auto restart mode startup cell vcc drain depl. coolmos? soft start block
coolset?-f3 ICE3A1065LJ functional description version 2.4 8 19 nov 2012 to charge the external capacitor c vcc which is connected to the vcc pin. this vcc charge current is controlled to 0.9ma by the startup cell. when the v vcc exceeds the on-threshold v ccon =18v, the bias circuit are switched on. then the startup cell is switched off by the undervoltage lockout and therefore no power losses present due to the connection of the startup cell to the drain voltage. to av oid uncontrolled ringing at switch-on a hysteresis start up voltage is implemented. the switch-off of the controller can only take place after active mode was entered and v vcc falls below 10.5v. the maximum current consumption before the controller is activated is about 250 a. when v vcc falls below the off-threshold v ccoff =10.5v, the bias circuit switched off and the soft start counter is reset. thus it is ensured that at every startup cycle the soft start starts at zero. the internal bias circuit is switched off if latched off mode or auto restart mode is entered. the current consumption is then reduced to 250 a. once the malfunction condition is removed, this block will then turn back on. the recovery from auto restart mode does not require re-cycling the ac line. in case latched off mode is entered, vcc needs to be lowered below 6.23v to reset the latched off mode. this is done usually by re-cycling the ac line. when active burst mode is entered, the internal bias is switched off most of the time but the voltage reference is kept alive in order to reduce the current consumption below 450 a. 3.3 startup phase figure 4 soft start in the startup phase, the ic provides a soft start period to control the maxi mum primary current by means of a duty cycle limitatio n. the soft start function is a built-in function and it is controlled by an internal counter. when the v vcc exceeds the on-threshold voltage, the ic starts the soft start mode. the function is realized by an internal soft start re sistor, a current sink and a counter. and the amplitude of the current sink is controlled by the counter. figure 5 soft start phase figure 6 soft start circuit soft-start comparator soft start & g7 c7 g ate d river 0.6v x3.2 pwm op cs soft start counter soft start soft start finish softs v softs v softs2 v softs1 5v r softs soft start counter i 2i 4i softs 8i 32i
coolset?-f3 ICE3A1065LJ functional description version 2.4 9 19 nov 2012 after the ic is sw itched on, the v softs voltage is controlled such that the vo ltage is increased step- wisely (32 steps) with the increase of the counts. the soft start counter would send a signal to the current sink control in every 600us such that the current sink decrease gradually and the duty ratio of the gate drive increase gradually. the so ft start will be finished in 20ms after the ic is switched on. at the end of the soft start period, the current sink is switched off. 3.4 pwm section figure 7 pwm section block 3.4.1 oscillator the oscillator generates a fixed frequency of 100khz with frequency jittering of 4% (which is 4khz) at a jittering period of 4ms. a capacitor, a current source and a current sink which determine the frequency are integrated. the charging and discharging current of the implemented oscillator capacitor are internally tri mmed, in order to achieve a very accurate switching frequency. the ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of d max =0.75. once the soft start period is over and when the ic goes into normal operating mode, the switching frequency of the clock is varied by the control signal from the soft start block. then the switching frequency is varied in range of 100khz 4khz at period of 4ms. 3.4.2 pwm-latch ff1 the output of the oscillator block provides continuous pulse to the pwm-latch which turns on/off the internal depl. coolmos tm . after the pwm-latch is set, it is reset by the pwm comparator, the soft start comparator or the current -lim it comparator. when it is in reset mode, the output of the driver is shut down immediately. 3.4.3 gate driver figure 8 gate driver the driver-stage is optimized to minimize emi and to provide high circuit efficiency. this is done by reducing the switch on slope when exceeding the internal coolmos? threshold. this is achieved by a slope control of the rising edge at the driver?s output (see figure 9). figure 9 gate rising slope thus the leading switch on spike is minimized. furthermore the driver circuit is designed to eliminate cross conduction of the output stage. oscillator duty cycle max gate driver 0.75 clock & g9 1 g8 pwm section ff1 r s q soft start comparator pwm comparator current limiting depl. coolmos? gate frequency jitter soft start block vcc 1 pwm-latch depl. coolmos? gate driver gate t (internal) v gate 5v ca. t = 130ns
coolset?-f3 ICE3A1065LJ functional description version 2.4 10 19 nov 2012 during power up, when vcc is below the undervoltage lockout threshold v vccoff , the output of the gate driver is set to low in order to disable power transfer to the secondary side. 3.5 current limiting figure 10 current limiting block there is a cycle by cycle peak current limiting operation realized by the current-limit comparator c10. the source current of the integrated depl. coolmos? is sensed via an external sense resistor r sense . by means of r sense the source current is transformed to a sense voltage v sense which is fed into the pin cs. if the voltage v sense exceeds the internal threshold voltage v csth, the comparator c10 immediately turns off the gate drive by resetting the pwm latch ff1. a propagation delay compensation is added to support the immediate shut down of the integrated depl. coolmos? with very short propagation delay. thus the influence of the ac input voltage on the maximum output power can be reduced to minimal. in order to prevent the current limit from distortions caused by leading edge spikes, a leading edge blanking is integrated in the current sense path for the comparators c10, c12 and the pwm-op. the output of comparator c12 is activated by the gate g10 if active burst mode is entered. when it is activated, the current limiting is reduced to 0.31v. this voltage level determines the maximum power level in active burst mode. furthermore, the comparator c11 is implemented to detect dangerous current levels which could occur if there is a short winding in the transformer or the secondary diode is shorten. to ensure that there is no accidentally entering of the latched mode by the comparator c11, a 190ns spike blanking time is integrated in the output pa th of comparator c11. 3.5.1 leading edge blanking figure 11 leading edge blanking whenever the internal depl. coolmos? is switched on, a leading edge spike is generated due to the primary-side capacitances and reverse recovery time of the secondary-side rectifier. this spike can cause the gate drive to switch off unintentionally. in order to avoid a premature terminatio n of the switching pulse, this spike is blanked out with a time constant of t leb = 220ns. 3.5.2 propagation delay compensation in case of overcurrent detection, there is always propagation delay to switch off the internal depl. coolmos?. an overshoot of the peak current i peak is induced to the delay, which depends on the ratio of di/ dt of the peak current (see figure 12). figure 12 current limiting c11 current limiting c10 1.66v c12 & 0.31v leading edge blanking 220ns g10 spike blanking 190 ns propagation-delay compensation v csth active burst mode pwm latch ff1 10k d1 1pf pwm-op cs latched off mode t v sense v csth t leb = 220ns t i sense i limit t propagation delay i overshoot1 i peak1 signal1 signal2 i overshoot2 i peak2
coolset?-f3 ICE3A1065LJ functional description version 2.4 11 19 nov 2012 the overshoot of signal2 is larger than of signal1 due to the steeper rising waveform. this change in the slope is depending on the ac input voltage. propagation delay compensation is integrated to reduce the overshoot due to di/dt of the rising primary current. thus the propagation delay time between exceeding the current sense threshold v csth and the switching off of the integrated internal depl. coolmos? is compensated over temperature within a wide range. current limiting is then very accurate. for example, i peak = 0.5a with r sense = 2. the current sense threshold is set to a static voltage level v csth =1v without propagation delay compensation. a current ramp of di/dt = 0.4a/s, or dv sense /dt = 0.8v/s, and a propagation delay time of t propagation delay =180ns leads to an i peak overshoot of 14.4%. with the propagation delay compensation, the ov ershoot is only around 2% (see figure 13). figure 13 overcurrent shutdown the propagation delay compensation is realized by means of a dynamic threshold voltage v csth (seefigure.14). in case of a steeper slope the switch off of the driver is earlier to compensate the delay. figure 14 dynamic voltage threshold v csth 3.6 control unit the control unit contains the functions for active burst mode, auto restart mode and latched off mode. the active burst mode and the auto restart mode both have 20ms internal blanking time. for the auto restart mode, a further extendable blanking time is achieved by adding external capacitor at bl pin. by means of this blanking time, the ic avoids entering into these two modes accidentally. furthermore those buffer time for the overload detection is very useful for the application that works in low current but requires a short duration of high current occasionally. 3.6.1 basic and extendable blanking mode figure 15 basic and extendable blanking mode there are 2 kinds of blanking mode; basic mode and the extendable mode. the basic mode has an internal pre-set 20ms blanking time while the extendable mode has extended blanking time to basic mode by connecting an external capacitor to the bl pin. for the extendable mode, the gate g5 is blocked even though the 20ms blanking time is reached if an external capacitor c bk is added to bl pin. while the 20ms blanking time is passed, the switch s1 is opened by g2. then the 0.9v clamped voltage at bl pin is charged to 4.0v through the internal i bk constant current. then g5 is enabled by comparator c3. after 0,9 0,95 1 1,05 1,1 1,15 1,2 1,25 1,3 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 with compensation without compensation dt dv sense s v sense v v t v csth v osc signal1 signal2 v sense propagation delay max. duty cycle off time t c3 4.0v c4 4.5v c5 1.35v & g5 & g6 0.9v s1 1 g2 control unit active burst mode auto restart mode 5.0v bl fb c bk 20ms blanking time 20ms blanking time spike blanking 8.0us # i bk soft start block
coolset?-f3 ICE3A1065LJ functional description version 2.4 12 19 nov 2012 the 8.0us spike blanking time, the auto restart mode is activated. for example, if c bk = 0.22uf, i bk = 8.4ua blanking time = 20ms + c bk x (4.0 - 0.9) / i bk = 100ms the 20ms blanking time circuit after c4 is disabled by the soft stat block such that the controller can start up properly. the active burst mode has basic blanking mode only while the auto restart mode has both the basic and the extendable blanking mode. 3.6.2 active burst mode the ic enters active burst mode under low load conditions. with the active burst mode, the efficiency increases significantly at li ght load conditions while still maintaining a low ripple on v out and a fast response on load jumps. during active burst mode, the ic is controlled by the fb signal. since the ic is always active, it can be a very fa st response to the quick change at the fb signal. the start up cell is kept off in order to minimize the power loss. figure 16 active burst mode the active burst mode is located in the control unit. figure 16 shows the related components. 3.6.2.1 entering active burst mode the fb signal is kept monito ring by the comparator c4. during normal operation, the internal blanking time counter is reset to 0. when fb signal falls below 1.35v, it starts to count. when the counter reach 20ms and fb signal is still below 1.35v, the system enters the active burst mode. this time window prevents a sudden entering into the active burst mode due to large load jumps. after entering active burst mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the ic to approx. 450ua. it needs the application to enforce the vcc voltage above the undervoltage lockout level of 10.5v such that the startup cell will not be switched on accidentally. or otherwise the power loss will increase drastically. the minimum vcc level during active burst mode depends on the load condition and the application. the lowest vcc level is reached at no load condition. 3.6.2.2 working in active burst mode after entering the active burst mode, the fb voltage rises as v out starts to decrease, which is due to the inactive pwm section. the comparator c6a monitors the fb signal. if the voltage level is larger than 3.61v, the internal circuit will be activated; the internal bias circuit resumes and starts to provide switching pulse. in active burst mode the gate g10 is released and the current limit is reduced to 0.31v. in one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. if the load at v out is still kept unchanged, the fb signal will drop to 3.0v. at this level the c6b deactivates the internal circuit again by switching off the internal bi as. the gate g11 is active again as the burst flag is set after entering active burst mode. in active burst mode, the fb voltage is changing like a saw tooth between 3.0v and 3.61v (see figure 17). 3.6.2.3 leaving active burst mode the fb voltage will increase immediately if there is a high load jump. this is observed by the comparator c4. as the current limit is ca. 31% during active burst mode, a certain load jump is needed so that the fb signal can exceed 4.5v. at th at time the comparator c4 resets the active burst mode control which in turn blocks the comparator c 12 by the gate g10. the maximum current can then be resumed to stabilize v out. c4 4.5v c6a 3.61v 1.35v fb control unit active burst mode internal bias & g10 current limiting & g6 c6b 3.0v & g11 20 ms blanking time c5
coolset?-f3 ICE3A1065LJ functional description version 2.4 13 19 nov 2012 figure 17 signals in active burst mode 3.6.3 protection modes the ic provides several protection features which are separated into two categories. some enter latched off mode and the others enter auto restart mode. besides the pre-defined protection feature for the latch off mode, there is also an external latch off enable pin for customer defined latch off protection features. the latched off mode can only be reset if vcc falls below 6.23v. both modes prevent the smps from destructive states.the following table shows the relationship between possible system failures and the chosen protection modes. 3.6.3.1 latched off mode figure 18 latched off mode 1.35v 3.61v 4.5v v fb t t 0.31v 1.06v v cs 10.5v v vcc t t 450ua i vcc t 2.5ma v out t 20ms blanking time current limit level during active burst mode 3.0v entering active burst mode leaving active burst mode blanking timer vcc overvoltage latched off mode overtemperature latched off mode short winding/short diode latched off mode bl pin < 0.1v latched off mode overload auto restart mode open loop auto restart mode vcc undervoltage auto restart mode short optocoupler auto restart mode c1 24v spike blanking 8.0us & g1 1 g3 thermal shutdown t j >140c latched off mode vcc c4 4.5v c11 1.66v spike blanking 190 ns cs voltage reference control unit latched off mode reset v vcc < 6.23v fb t le bl c2 latch enable signal 8us blanking time 0.1v 1ms counter uvlo #
coolset?-f3 ICE3A1065LJ functional description version 2.4 14 19 nov 2012 the vcc voltage is observed by comparator c1 while the fb voltage is monitored by the comparator c4. if the vcc voltage is > 24v and the fb is > 4.5v, the overvoltage detection is activated. that means the overvoltage detection is only activated if the fb signal is outside the operating range > 4.5v, e.g. when open loop happens. the logic can eliminate the possible of entering latch off mode if there is a small voltage overshoots of v vcc during normal operating. the internal voltage reference is switched off most of the time once latched off mode is entered in order to minimize the current consumption of the ic. this latched off mode can only be reset if the v vcc < 6.23v. in this mode, only the uvlo is working which controls the startup cell by sw itching on/off at v vccon /v vccoff . during this phase, the aver age current consumption is only 250 a. as there is no longer a self-supply by the auxiliary winding, the vcc drops. the undervoltage lockout switches on the in tegrated startup cell when vcc falls below 10.5v. the startup cell is switched off again when vcc has exceeded 18v. once the latched off mode was entered, there is no start up phase whenever the vcc exceeds the switch-on level of the undervoltage lockout. therefore the vcc voltage changes between the switch-on and switch-off levels of the undervoltage lockout with a saw tooth shape (see figure 19). figure 19 signals in latched off mode the thermal shutdown block monitors the junction temperature of the ic. after detecting a junction temperature higher than latched thermal shutdown temperature; t jsd , the latched off mode is entered. the signals coming from the temperature detection and vcc overvoltage detection are fed into a spike blanking with a time constant of 8.0 s in order to ensure the system reliability. furthermore, a short winding or short diode on the secondary side can be detected by the comparator c11 which is in parallel to the propagation delay compensated current limit comparator c10. in normal operating mode, comparator c10 controls the maximum level of the cs signal at 1.06v. if there is a failure such as short winding or short diode, c10 is no longer able to limit the cs signal at 1.06v. instead the comparator c11 detects the peak current voltage > 1.66v and enters the latched off mode immediately in order to keep the smps in a safe stage. in case the pre-defined latch off features are not sufficient, there is a customer defined external latch enable feature. the latch off mode can be triggered by pulling down the bl pin to < 0.1v. it can simply add a trigger signal to the base of the externally added transistor, t le at the bl pin. to ensure this latch function will not be mis-trig gered during start up, a 1ms delay time is implemented to blank the unstable signal. 3.6.3.2 auto restart mode figure 20 auto restart mode in case of overload or open loop, the fb exceeds 4.5v which will be observed by comparator c4. then the internal blanking counter starts to count. when it reaches 20ms, the switch s1 is released. then the clamped voltage 0.9v at v bl can increase. when there is no external capacitor c bk connected, the v bl will reach 4.0v immediately. when both the input signals at and gate g5 is positive, the auto-restart mode will be activated after the extra spike blanking time of 8.0us is elapsed. however, when an extra blanking time is needed, it can be achieved by adding an external capacitor, c bk . a constant current source of i bk will start 10.5v t i vccstart t 0.9ma v out v vcc 18v c3 4.0v c4 4.5v & g5 0.9v s1 1 g2 control unit auto restart mode 5.0v bl fb c bk 20ms blanking time spike blanking 8.0us # i bk
coolset?-f3 ICE3A1065LJ functional description version 2.4 15 19 nov 2012 to charge the capacitor c bk from 0.9v to 4.0v after the switch s1 is released. the charging time from 0.9v to 4.0v are the extendable blanking time. if c bk is 0.22uf and i bk is 8.4ua, the extendable blanking time is around 80ms and the total blanking time is 100ms. in combining the fb and blanking time, there is a blanking window generated which prev ents the system to enter auto restart mode due to large load jumps. in case of vcc undervoltage, the ic enters into the auto restart mode and star ts a new startup cycle. short optocoupler also leads to vcc undervoltage as there is no self supply after activating the internal reference and bias. in contrast to the latched off mode, there is always a startup phase with switchi ng cycles in auto restart mode. after this start up phase, the conditions are again checked whether the fa ilure mode is still present. normal operation is resumed once the failure mode is removed that had caused the auto restart mode.
version 2.4 16 19 nov 2012 coolset?-f3 ICE3A1065LJ electrical characteristics 4 electrical characteristics note: all voltages are measured with respect to ground (p in 8). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make su re, that any capacitor that will be connected to pin 7 ( v cc) is discharged before assembling the application circuit. 4.2 operating range note: within the operati ng range the ic operates as described in the functional description. parameter symbol limit values unit remarks min. max. drain source voltage v ds - 650 v t j =110c pulse drain current, t p limited by max. t j =150c i d_puls - 3.4 a avalanche energy, repetitive t ar limited by max. t j =150c 1) 1) repetitive avalanche causes additional po wer losses that can be calculated as p av = e ar * f e ar - 0.07 mj avalanche current, repetitive t ar limited by max. t j =150c i ar - 1.0 a vcc supply voltage v vcc -0.3 27 v fb voltage v fb -0.3 5.0 v cs voltage v cs -0.3 5.0 v junction temperature t j -40 150 c controller & coolmos tm storage temperature t s -55 150 c thermal resistance junction -ambient r thja1 - 90 k/w pg-dip-8 esd capability (incl. drain pin) v esd - 2 kv human body model 2) 2) according to eia/jesd22-a114-b (dischar ging a 100pf capacitor through a 1.5k series resistor) parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccoff 26 v junction temperature of controller t jcon -25 130 c max value limited due to thermal shut down of controller junction temperature of coolmos? t jcoolmos -25 150 c
coolset?-f3 ICE3A1065LJ electrical characteristics version 2.4 17 19 nov 2012 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range t j from ? 25 c to 130 c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc = 18 v is assumed. 4.3.2 internal voltage reference parameter symbol limit values unit test condition min. typ. max. start up current i vccstart - 150 250 a v vcc =17v vcc charge current i vcccharge1 - - 5.0 ma v vcc = 0v i vcccharge2 0.55 0.90 1.60 ma v vcc = 1v i vcccharge3 - 0.7 - ma v vcc =17v leakage current of start up cell and coolmos? i startleak - 0.2 50 a v drain = 450v at t j =100c supply current with inactive gate i vccsup1 - 1.5 2.5 ma supply current with active gate i vccsup2 - 2.5 4.2 ma i fb = 0a supply current in latched off mode i vcclatch - 250 - a i fb = 0a supply current in auto restart mode with inactive gate i vccrestart - 250 - a i fb = 0a supply current in active burst mode with inactive gate i vccburst1 - 450 950 a v fb = 2.5v i vccburst2 - 450 950 a v vcc = 11.5v, v fb = 2.5v vcc turn-on threshold vcc turn-off threshold vcc turn-on/off hysteresis v vccon v vccoff v vcchys 17.0 9.8 - 18.0 10.5 7.5 19.0 11.2 - v v v parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v ref 4.90 5.00 5.10 v measured at pin fb i fb = 0
version 2.4 18 19 nov 2012 coolset?-f3 ICE3A1065LJ electrical characteristics 4.3.3 pwm section 4.3.4 soft start time 4.3.5 control unit parameter symbol limit values unit test condition min. typ. max. fixed oscillator frequency f osc1 87 100 113 khz f osc2 92 100 108 khz t j = 25c frequency jittering range f jitter - 4.0 - khz t j = 25c max. duty cycle d max 0.70 0.75 0.80 min. duty cycle d min 0 - - v fb < 0.3v pwm-op gain a v 3.0 3.2 3.4 voltage ramp offset v offset-ramp - 0.6 - v v fb operating range min level v fbmin - 0.5 - v v fb operating range max level v fbmax - - 4.3 v cs=1v, limited by comparator c4 1) 1) the parameter is not subjected to production test - verified by de sign/characterization fb pull-up resistor r fb 9 15.4 22 k parameter symbol limit values unit test condition min. typ. max. soft start time t ss - 20.0 - ms parameter symbol limit values unit test condition min. typ. max. clamped v bl voltage during normal operating mode v blclmp 0.85 0.90 0.95 v v fb = 4v blanking time voltage limit for comparator c3 v bkc3 3.85 4.00 4.15 v over load & open loop detection limit for comparator c4 v fbc4 4.28 4.50 4.72 v active burst mode level for comparator c5 v fbc5 1.23 1.35 1.43 v active burst mode level for comparator c6a v fbc6a 3.48 3.61 3.76 v after active burst mode is entered
coolset?-f3 ICE3A1065LJ electrical characteristics version 2.4 19 19 nov 2012 note: the trend of all the voltage levels in the cont rol unit is the same regarding the deviation except v vccovp and v vccpd 4.3.6 current limiting active burst mode level for comparator c6b v fbc6b 2.88 3.00 3.12 v after active burst mode is entered overvoltage detection limit v vccovp 23 24 25 v v fb = 5v latch enable level at bl pin v le 0.07 0.1 0.2 v > 30 s charging current at bl pin i bk 5.8 8.4 10.9 a charge starts after the built-in 20ms blanking time elapsed latched thermal shutdown 1) t jsd 130 140 150 c built-in blanking time for overload protection or enter active burst mode t bk - 20 - ms without external capacitor at bl pin inhibit time for latch enable function during start up t ihle - 1.0 - ms count when vcc > 18v spike blanking time before latch off or auto restart protection t spike - 8.0 - s power down reset for latched mode v vccpd 5.2 6.23 7.8 v after latched off mode is entered 1) the parameter is not subjected to production test - ve rified by design/characterization. the thermal shut down temperature refers to the junction temperature of the controller. parameter symbol limit values unit test condition min. typ. max. peak current limitation (incl. propagation delay) v csth 0.99 1.06 1.09 v d v sense / d t = 0.6v/ s (see figure 13) peak current limitation during active burst mode v cs2 0.27 0.31 0.37 v leading edge blanking t leb - 220 - ns cs input bias current i csbias -1.5 -0.2 - a v cs =0v over current detection for latched off mode v cs1 1.570 1.66 1.764 v cs spike blanking for comparator c11 t csspike - 190 - ns parameter symbol limit values unit test condition min. typ. max.
version 2.4 20 19 nov 2012 coolset?-f3 ICE3A1065LJ electrical characteristics 4.3.7 coolmos? section parameter symbol limit values unit test condition min. typ. max. drain source breakdown voltage v (br)dss 600 650 - - - - v v t j = 25c t j = 110c drain source on-resistance r dson - - 2.95 6.60 3.42 7.56 t j = 25c t j =125c 1) at i d = 1.0a 1) the parameter is not subjected to production test - verified by de sign/characterization effective output capacitance, energy related c o(er) - 7.0 - pf v ds = 0v to 480v rise time t rise - 30 2) 2) measured in a typical flyback converter application - ns fall time t fall - 30 2) - ns
coolset?-f3 ICE3A1065LJ temperature derating curve version 2.4 21 19 nov 2012 5 temperature derating curve figure 21 safe operati ng area ( soa ) curve figure 22 soa temperature derating coefficient curve safe operating area for ice3a(b)1065 (lj) i d = f ( v ds ) parameter : d = 0, t c = 25deg.c 0.001 0.01 0.1 1 10 1 10 100 1000 v ds [v] i d [a] dc tp = 100ms t p = 0.1ms tp = 1ms tp = 10ms tp = 1000ms soa temperature derating coefficient curve ( package dissipation ) for f3 & f2 coolset 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 ambient/case temperature ta/tc [deg.c] ta : dip, tc : to220 soa temperature derating coefficient [%]
version 2.4 22 19 nov 2012 coolset?-f3 ICE3A1065LJ outline dimension 6 outline dimension figure 23 pg-dip-8 (pb-free plat ing plastic dual in-line outline) pg-dip-8 (plastic dual in-line package)
coolset?-f3 ICE3A1065LJ marking version 2.4 23 19 nov 2012 7marking figure 24 marking marking
version 2.4 24 19 nov 2012 coolset?-f3 ICE3A1065LJ schematic for recommended pcb layout 8 schematic for recommended pcb layout figure 25 schematic for recommended pcb layout general guideline for pcb layout design using f3 coolset (refer to figure 25): 1. ?star ground ?at bulk capacitor ground, c11: ?star ground ?means all primary dc grounds should be connected to the ground of bulk capacitor c11 separately in one point. it can reduce the switching noi se going into the sensitive pins of the coolset device effectively. the primary dc gr ounds include the followings. a. dc ground of the primary auxiliary winding in power transformer, tr1, and ground of c16 and z11. b. dc ground of the curr ent sense resistor, r12 c. dc ground of the coolset device, g nd pin of ic11; the signal grounds from c13, c14, c15 and collector of ic12 should be connected to the gnd pin of ic11 and then ?star ?connect to the bulk capacitor ground. d. dc ground from bridge rectifier, br1 e. dc ground from the br idging y-capacitor, c4 2. high voltage traces clearance: high voltage traces should keep enough spacing to the nearby traces. otherwise, arcing would incur. a. 400v traces (positive rail of bulk capacitor c11) to nearby trace: > 2.0mm b. 600v traces (drain voltage of co olset ic11) to nearby trace: > 2.5mm 3. filter capacitor close to the controller ground: filter capacitors, c13, c14 and c15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. guideline for pcb layout design when >3kv lightni ng surge test applied (refer to figure 25): 1. add spark gap spark gap is a pair of saw-tooth like copper plate fa cing each other which can discharge the accumulated charge during surge test through the sharp point of th e saw-tooth plate. a. spark gap 3 and spark gap 4, input common mode choke, l1: gap separation is around 1.5mm (no safety concern) c11 bulk cap r11 d11 c12 ic12 r12 c13 c16 c15 c14 d13 r14 r23 r22 ic21 c23 r24 c22 r21 r25 gnd vo d21 c21 f3 coolset schematic for recommended pcb layout r13 z11 tr1 n l br1 c2 y-cap c3 y-cap c1 x-cap l1 fuse1 c4 y-cap gnd spark gap 3 spark gap 4 d11 spark gap 1 spark gap 2 fb cs gnd nc softs vcc f3 drain coolset ic11
coolset?-f3 ICE3A1065LJ schematic for recommended pcb layout version 2.4 25 19 nov 2012 b. spark gap 1 and spark gap 2, live / neutral to ground: these 2 spark gaps can be used when the lightning surge requirement is >6kv. 230vac input voltage application, the gap separation is around 5.5mm 115vac input voltage application, the gap separation is around 3mm 2. add y-capacitor (c2 and c3) in the live and neutral to ground even though it is a 2-pin input 3. add negative pulse clamping diode, d11 to the current sense resistor, r12: the negative pulse clamping diode can reduce the negati ve pulse going into the cs pin of the coolset and reduce the abnormal behavior of the coolset. the di ode can be a fast speed diode such as in4148. the principle behind is to drain the high surge voltage from live/neut ral to ground without passing through the sensitive components such as the primary controller, ic11.
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