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june 2013 docid17496 rev 7 1/33 AN3216 application note getting started with stm3 2l1xxx hardware development introduction this application note is intended for system designers who require a hardware implementation overview of the development b oard features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. it shows how to use stm32l1xxx product families and describ es the minimu m hardware resources required to develop an stm32l1xxx application. detailed reference design schematics are also co ntained in this document with descriptions of the main components, interfaces and modes. table 1. applicable products type product categories microcontrollers stm32l1 series www.st.com
contents AN3216 2/33 docid17496 rev 7 contents 1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 independent a/d converter supply and reference voltage . . . . . . . . . . . . 8 2.1.2 independent lcd supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.3.1 power-on reset (por)/power-down reset (pdr), brownout reset (bor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.2 programmable voltage detector (pvd) . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.3 brownout reset (bor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.4 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 msi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 hse osc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 external source (hse bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.2 external crystal/ceramic resonator (hse cr ystal) . . . . . . . . . . . . . . . . . 17 3.3 lse osc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 external source (lse bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 external crystal/ceramic re sonator (lse crystal) . . . . . . . . . . . . . . . . . . 18 3.4 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 swj debug port (serial wire and jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid17496 rev 7 3/33 AN3216 contents 3 5.3 pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.1 swj debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.2 flexible swj-dp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.3 internal pull-up and pull-down resistors on jtag pins . . . . . . . . . . . . . . 24 5.3.4 swj debug port connection with standard jtag connector . . . . . . . . . 24 6 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 ground and power supply (v ss , v dd , v ssa , v dda ) . . . . . . . . . . . . . . . . . 25 6.4 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6 unused i/os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.3 boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.4 swj interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of tables AN3216 4/33 docid17496 rev 7 list of tables table 1. applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3. debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4. swj i/o pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid17496 rev 7 5/33 AN3216 list of figures 5 list of figures figure 1. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. optional lcd power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. power on reset/power down rese t waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. pvd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. crystal/ceramic resona tors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. external clock (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. crystal/ceramic resonators (1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. host-to-board connectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. jtag connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. typical layout for v dd /v ss pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. stm32l152vb(t6) microcontroller reference schemati c . . . . . . . . . . . . . . . . . . . . . . . . . . 29
glossary AN3216 6/33 docid17496 rev 7 1 glossary ? medium-density devices are microcontrollers where the flash memory ranges between 32 and 128 kbytes. ? medium-density + devices are microcontrollers where the flash memory is 256 kbytes. ? high-density devices are microcontrollers where the flash memory is 384 kbytes.
docid17496 rev 7 7/33 AN3216 power supplies 32 2 power supplies 2.1 introduction digital power voltage (v core ) is provided with an embedded linear voltage regulator with three different programmable ranges from 1.2 to 1.8 v. to be fully functional at full speed, the device requires a 2.0 to 3.6 v operating voltage supply (v dd ), making possible to reach the digital power voltage v core of 1.8 v (product voltage range 1). product voltage range 2 (v core = 1.5 v) and 3 (v core = 1.2 v) can be selected when the v dd operates from 1.65 to 3.6 v. therefore, frequency is limited to 16 mhz and 4 mhz respectively. when the adc and brownout reset (bor) are not used, the device can operate at power voltages below 1.8 v down to 1.65 v. figure 1. power supply overview note: v dda and v ssa must be connected to v dd and v ss , respectively. v dd v ss ai17469 (v dd ) v dda (v ss ) v ssa adc dac reset block pll (from 1.8 v up to v dda ) v ref+ (must be tied to v ssa ) v ref- v lcd i/o supply v dda domain v dd domain standby circuitry (wakeup logic, iwdg, rtc, lse crystal 32 kbyte osc rcc csr) voltage regulator dynamic voltage scaling lcd v core domain core memories digital peripherals temp. sensor step-up converter v sel
power supplies AN3216 8/33 docid17496 rev 7 2.1.1 independent a/d converter supply and reference voltage to improve conversion accuracy, the adc and the dac have an independent power supply that can be filtered separately, and shielded from noise on the pcb. ? the adc voltage supply input is available on a separate v dda pin ? an isolated supply ground conn ection is provided on the v ssa pin v dda and v ref require a stable voltage. the consumption on v dda can reach several ma (see i dd (adcx), i dd (dac), i dd (compx), i vdda , and i vref in the product datasheets for further information). when available (depending on the package), v ref must be tied to v ssa . on bga 64-pin and all 100-pin or more packages to ensure a better accuracy on low-voltage inputs and outputs, the user can connect to v ref+ , a separate external reference voltage wh ich is lower than v dd . v ref+ is the highest voltage, represented by the full scale value, for an analog input (adc) or output (dac) signal. ? for adc ? 2.4 v v ref+ = v dda for full speed (adcclk = 16 mhz, 1 msps) ? 1.8 v v ref+ = v dda for medium speed (adcclk = 8 mhz, 500 ksps) ? 2.4 v v ref+ v dda for medium speed (adcclk = 8 mhz, 500 ksps) ? 1.8 v v ref+ < v dda for low speed (adcclk = 4 mhz, 250 ksps) ? when product voltage range 3 is selected (v core = 1.2 v), the adc is low speed (adcclk = 4 mhz, 250 ksps) ? for dac ? 1.8 v v ref+ < v dda on packages with 64 pins or less (except bga package) v ref+ and v ref- pins are not available. they are internally connected to the adc voltage supply (v dda ) and ground (v ssa ).
docid17496 rev 7 9/33 AN3216 power supplies 32 2.1.2 independent lcd supply the v lcd pin is provided to control the contrast of the glass lcd. this pin can be used in two ways: ? it can receive, from an external circuitry, the desired maximum voltage that is provided on the segment and common lines to the glass lcd by the microcontroller. ? it can also be used to connect an external capacitor that is used by the microcontroller for its voltage step-up converter. this step-up converter is controlled by software to provide the desired voltage to the segment and common lines of the glass lcd. refer to the specific product datasheet for the capacitor value. the voltage provided to the segment and common lines defines the contrast of the glass lcd pixels. this contrast can be reduced when the dead time between frames is configured. 2.1.3 voltage regulator the internal voltage regulator is always enabled after reset. it can be configured to provide the core with three different voltage ranges. choosing a range with low v core reduces the consumption but lowers the maximum acceptable core speed. consumption ranges in decreasing consumption order are as follows: ? range 1, available only for v dd above 2.0 v, allows maximum speed ? range 2 allows cpu frequency up to 16 mhz ? range 3 allows cpu frequency up to 4 mhz voltage regulator works in three different modes depending on the application modes. ? in run mode, the regulator supplies full power to the v core domain (core, memories and digital peripherals). ? in stop mode, low power run and low power wait modes, the regulator supplies low power to the v core domain, preserving the contents of the registers and sram. ? in standby mode, the regulator is powered of f. the contents of the registers and sram are lost except for those concer ned with the standby circuitry.
power supplies AN3216 10/33 docid17496 rev 7 2.2 power supply schemes the circuit is powered by a stabilized power supply, v dd . ? the v dd pins must be connected to v dd with external decoupling capacitors; one single tantalum or ceramic capacitor (minimum 4.7 f typical 10 f) for the package + one 100 nf ceramic capacitor for each v dd pin). ? the v dda pin must be connected to two external decoupling capacitors (100 nf ceramic capacitor + 1 f tantalum or ceramic capacitor). ? the v ref+ pin can be connected to the v dda external power supp ly. if a separate, external reference voltage is applied on v ref+ , a 100 nf and a 1 f capacitor must be connected on this pin. to compensate peak consumption on vref, the 1 f capacitor may be increased up to 10 f when the sampling speed is high. when adc or dac is used, v ref+ must remain between 1.8 v and v dda . v ref+ can be grounded when adc and dac are not active; this enables the user to power down an external voltage reference. ? additional precautions can be ta ken to filter analog noise: v dda can be connected to v dd through a ferrite bead. figure 2. power supply scheme 1. v ref + is either connected to v dda or to v ref . 2. n is the number of v dd and v ss inputs. msv18291v2 vdd1/2/.../n analog: rcs, pll,... gpios out in kernel logic (cpu, digital & memories) standby-power circuitry (osc32k,rtc,wake-up logic, rtc backup registers n 100 nf + 1 10 f regulator vss1/2/.../n vdda vref+ vref- vssa adc level shifter io logic vdd 100 nf + 1 f vref 100 nf + 1 f vdda
docid17496 rev 7 11/33 AN3216 power supplies 32 figure 3. optional lcd power supply scheme ? option 1 : lcd power supply is provided by a dedicated vlcd su pply source, vsel switch is open. ? option 2 : lcd power supply is provided by the in ternal step-up conv erter, vsel switch is closed, an external capacitance is neede d for correct behavior of this converter. note: the availa bility of the v lcd rails depend on the device; please refer to your product datasheet for more details. 2.3 reset and power supply supervisor the input supply to the main and low power regulators is monitored by a power-on/power- down/brownout reset circuit. power-on/power-down reset are a null power monitoring with fixed threshold voltages, whereas brownout reset gives the choice between several thresholds with a very low, but not null, power consumption. in addition, the stm32l1xxx embeds a progra mmable voltage detector that compares the power supply with the programmable threshold. an interrupt can be generated when the power supply drops below the v pvd threshold and/or when the power supply is higher than the v pvd threshold. the interrupt service routine then generates a warning message and/or puts the mcu into a safe state. msv32511v1 v dd1/2/.../n n x 100 nf + 1 x 10 f step-up converter v ss1/2/.../n v dd 100 nf v lcd v lcdrail1 v lcdrail2 v lcdrail3 v lcd pb0 or pe12 pb2 pb12 or pe11 c ext c rail3 lcd vsel c rail2 c rail1 option 1 option 2
power supplies AN3216 12/33 docid17496 rev 7 figure 4. power supply supervisors 1. the pvd is available on al l stm32l devices and it is enab led or disabled by software. 2. the bor is available only on devices operating from 1. 8 to 3.6 v, and unless disabled by option byte it masks the por/pdr threshold. 3. when the bor is disabled by option byte, the reset is asserted when v dd goes below pdr level. 4. for devices operating from 1.65 to 3.6 v, there is no bor and the reset is released when v dd goes above por level and asserted when v dd goes below pdr level. v dd /v dda pvd output 100 mv hysteresis v pvd v bor hysteresis 100 mv it enabled bor reset (n rst) por/pdr reset (nr st) pvd bor always active por/pdr (bor not available) ai17211b por v / pdr v bor/pdr reset (nrst) bor disabled by option byte (note 1) (note 2) (note 3) (note 4)
docid17496 rev 7 13/33 AN3216 power supplies 32 2.3.1 power-on reset (por )/power-down reset (pdr), brownout reset (bor) the monitoring voltage begins at 0.7 v. during power-on, for devices operating betwee n 1.8 and 3.6 v, the bor keeps the device under reset until the supply voltages (v dd and v ddio ) come close to the lowest acceptable voltage (1.8 v). at power-up th is internal reset is maintained during ~1 ms to wait for the supply to reach its final value and stabilize. at power-down the reset is acti vated as soon as the power drops below the lowest limit (1.65 v). at power-on, a defined reset should be maintained below 0.7 v. the upper threshold for a reset release is defined in the electrical char acteristics section of the product datasheets. figure 5. power on reset/power down reset waveform if you want to run the cpu at full speed the threshold should be raised to 2.0 v. for a programmable threshold above the chip lowest lim it, a brownout reset can be configured to the desired value. the bor can also be used to detect a power voltage drop earlier. the threshold values of the bor can be configured through the flash_obr option byte. 2.3.2 programmable volt age detector (pvd) the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. seven different pvd levels can be selected by software between 1.85 v and 3.05 v, with a 200 mv step. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine then generates a warning message and/or puts the mcu into a safe state. the pvd is enabled by software configuration. as an example, the servic e routine can perform emergency shutdown tasks. v dd /v dda re s et por pdr temporiz a tion t r s ttempo
power supplies AN3216 14/33 docid17496 rev 7 figure 6. pvd thresholds 2.3.3 brownout reset (bor) during power on, the brownout reset (bor) keeps the device under reset until the supply voltage reaches the specified v bor threshold. for devices operating from 1.65 to 3.6 v, the bor option is not available and the power supply is monitored by the por/pdr. as th e por/pdr thresholds are at 1.5 v, a ?grey zone? exists between the v por /v pdr thresholds and the minimum product operating voltage 1.65 v. for devices operating from 1.8 to 3.6 v, th e bor is always active at power on and its threshold is 1.8 v. when the system reset is released, the bor leve l can be reconfigured or disabled by option byte loading. if the bor level is kept at the lowest level, 1.8 v at power-on and 1.65 v at power down, the system reset is fully managed by the bor and the product operating voltages are within safe ranges. when the bor option is disabled by option byte, the power down reset is controlled by the pdr and a ?grey zone? exists between the 1.65 v and v pdr . v bor is configured through device option bytes. by default, level 4 threshold is activated. five programmable v bor thresholds can be selected (see product datasheets for actual v bor0 to v bor4 thresholds). when the supply voltage (v dd ) drops below the selected v bor threshold, a device reset is generated. when the v dd is above the v bor upper limit the device reset is released and the system can start. bor can be disabled by programming the device option bytes. to disable the bor function, v dd must have been higher than v bor0 to start the device option byte programming sequence. the power-on and power-down is then monitored by the por and pdr (see power-on reset (por)/power-down reset (pdr) section in the product datasheets). the bor threshold hysteresis is ~100 mv (between the risi ng and the fallin g edge of the supply voltage). v dd /v dda pvd o u tp u t 100 mv hy s tere s i s pvd thre s hold
docid17496 rev 7 15/33 AN3216 power supplies 32 2.3.4 system reset a system reset sets all registers to their rese t values except for the rtc, backup registers and rcc control/status register, rcc_csr. a system reset is generated when one of the following events occurs: 1. a low level on the nrst pin (external reset) 2. window watchdog end-of-count condition (wwdg reset) 3. independent watchdog end-of -count condition (iwdg reset) 4. a reset bit set by software (swreset) 5. entering standby or stop mode configured to generate a reset (low-power management reset) 6. option byte loader reset 7. exiting standby mode the reset source can be identified by checking the reset flags in the control/status register, rcc_csr. figure 7. reset circuit the stm32l does not require an external rese t circuit to power-up correctly. only a pull- down capacitor is recommended to improve ems performance by pr otecting the device against parasitic resets (see figure 7 ). charging/discharging the pull-down capacitor thru the internal resistor adds to the device power consumption. the recommended value of 100 nf for the capacitor can be reduced to 10 nf to limit this power consumption. r pu v dd /v dda pulse generator (min 20 s) system reset filter 0.1 f external reset circuit nrst ai14366d 88%(sftfu *8%(sftfu 1pxfssftfu 4pguxbsfsftfu -pxqpxfsnbobhfnfousftfu 0qujpoczufmpbefssftfu &yjujoh4uboecznpef
clocks AN3216 16/33 docid17496 rev 7 3 clocks four different clock sources can be used to drive the system clock (sysclk). they are: ? hsi ((high-speed inte rnal) oscillator clock ? hse (high-spee d external) oscillator clock ? pll clock ? msi (multispeed internal) oscillator clock the msi is used as a system clock source after startup from reset, wake-up from stop or standby low power modes. the devices have the following two secondary clock sources: ? 37 khz low speed internal rc (lsi rc) wh ich drives the independent watchdog and optionally the rtc used for auto-wakeup from stop/standby mode. ? 32.768 khz low speed external crystal (l se crystal) which optionally drives the real-time clock (rtcclk) each clock source can be switched on or off independently when it is not used, to optimize power consumption. refer to the stm32l1 xxx reference manual (rm0038) for a description of the clock tree. 3.1 msi clock the msi clock signal is generated from an internal rc oscillato r. its frequency range can be adjusted by software through the rcc_ics cr register. seven frequency ranges are available: 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.1 mhz (default value) and 4.2 mhz. those frequencies are multiple values of 32.768 khz. the msi clock is used as a system clock after a rest art from reset. the msi rc oscillator has the advantage of prov iding a low-cost (no external components) low-power clock source. it is used as a wake up clock in low power modes to reduce power consumption and wakeup time. the msirdy flag in the rcc_cr register indica tes wether the msi rc is stable or not. at startup, the msi rc output clock is not rele ased until this bit is set by hardware. the msi rc can be switched on and off through the rcc_cr register (default is on). if the application is subject to voltage or temperature variations, this may affect the rc oscillator speed. you can trim the msi frequency in the application through the rcc_icscr register. typically, this uses the hse as reference (see rm0038 for details on clock measurement with tim9/tim10/tim11). for more information refer to an3300 ?how to calibrate an stm32l1xx internal rc oscillator? .
docid17496 rev 7 17/33 AN3216 clocks 32 3.2 hse osc clock the high-speed external clock signal (hse) can be generated from two possible clock sources: ? hse user external clock (see figure 8 ) ? hse external crystal/ceramic resonator (see figure 9 ) 1. the value of r ext depends on the crystal characteristics. a typi cal value is in the range of 5 to 6 r s (resonator series resistance). 2. load capacitance, c l , has the following formula: c l = c l1 x c l2 / (c l1 + c l2 ) + c stray where: c stray is the pin capacitance and board or trace pcb-related capacit ance. typically, it is between 2 pf and 7 pf. please refer to section 6: recommendations on page 25 to minimize its value. 3.2.1 external sour ce (hse bypass) in this mode, an external clock source must be provided. it can have a frequency of up to 32 mhz. the external clock signal (square, sine or tr iangle) with a duty cycle of about 50%, has to drive the osc_in pin while the osc_out pin must be left in the high impedance state (see figure 8 and figure 9 ). 3.2.2 external crystal/ceram ic resonator (hse crystal) the external oscillator frequen cy ranges from 1 to 24 mhz. the external oscillator has th e advantage of producing a very accurate rate on the main clock. the associated hardware configuration is shown in figure 9 . the resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output di stortion and startup stab ilization time. the load capacitance values must be adjusted ac cording to the se lected oscillator. for c l1 and c l2 it is recommended to use high-quality ceramic capacitors in the 5 pf to 25 pf range (typical), designed for high-frequ ency applications and selected to meet the requirements of the crystal or resonator. c l1 and c l2, are usually the same value. the crystal manufacturer typically specifies a load ca pacitance that is the series combination of c l1 and c l2 . the pcb and mcu pin capacitances must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). refer to the electrical characte ristics sections in the datash eet of your product for more details. figure 8. external clock figure 9. crystal/ceramic resonators osc_out osc_in external source (hi-z) ai14369 hardware configuration osc_out osc_in ai14370b stm32l1xxx r ext (1) c l1 c l2 hardware configuration
clocks AN3216 18/33 docid17496 rev 7 3.3 lse osc clock the low-speed external clock signal (lse) can be generated from two possible clock sources: ? lse user external clock (see figure 10 ) ? lse external crystal/ceramic resonator (see figure 11 ) 1. osc32_in and osc_out pins can be also used as gp ios, but it is recommended not to use them as both rtc and gpio pins in the same application. 2. to avoid exceeding the maximum value of cl1 and cl2 (15 pf), it is strongly recommended to use a resonator with a load capacitance cl 7 pf. never use a resonator with a load capacitance of 12.5 pf. 3. the value of rext depends on the crystal characterist ics. a 0 w resistor works but, is not optimal. a typical value is in the range of 5 to 6 rs (resonator se ries resistance). to fine tune the rs value refer to an2867 (oscillator design guide for st microcontrollers). 3.3.1 external source (lse bypass) in this mode, an external cl ock source must be provided. it must have a frequency of 32.768 khz. the external clock signal (square, sine or tria ngle) with a duty cycle of about 50% has to drive the osc32_in pin while the osc32_out pin must be left high impedance (see figure 10 ). 3.3.2 external crystal/ceramic resonator (lse crystal) the lse crystal is a 32.768 khz low-speed extern al crystal or ceramic resonator. it has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (rtc) for clock/calendar or other timing functions. the oscillator can be switched on and off by soft ware (default is off). when switched on, the oscillator is not stable immediately. a bit is set in the rcc_csr register when the oscillator becomes stable and an interrupt can be gene rated if enabled in the rcc_cir register. the resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output di stortion and startup stab ilization time. the load capacitance values must be adjusted acco rding to the selected oscillator (see figure 11 ). figure 10. external clock (1) figure 11. crystal/ ceramic resonators (1)(2) osc32_out osc32_in external source (hi-z) ai14371 hardware configuration osc32_out osc32_in ai14372d stm32l1xxx c l1 c l2 hardware configuration r ext (3)
docid17496 rev 7 19/33 AN3216 clocks 32 3.4 clock securi ty system (css) the clock security system can be activated by software. in this case, the clock detector is enabled after the hse oscillator startup delay, a nd disabled when this oscillator is stopped. if a failure is detected on the h se oscillator clock, this oscilla tor is automatically disabled and an interrupt is generated to inform the soft ware about the failure (clock security system interrupt, cssi), allowing the mcu to perform rescue operations. the cssi is linked to the cortex?-m3 nmi (non-maskable interrupt) exception vector. if the hse oscillator is used directly or indirectly as the system clock (indirectly means: it is used as the pll input clock, and the pll cl ock is used as the system clock), a detected failure causes the system clock to switch to the msi oscillator and the external hse oscillator to be disabled. if th e hse oscillator clock is the clo ck entry of the pll used as the system clock when the failure occu rs, the pll is also disabled. for details, see the stm32l1xxx reference manual (rm0038).
boot configuration AN3216 20/33 docid17496 rev 7 4 boot configuration 4.1 boot mode selection in the stm32l1xxx, three different boot modes can be selected by means of the boot[1:0] pins as shown in table 2 . the values on the boot pins are latched on the 4 th rising edge of sysclk after a reset. it is up to the user to set the boot1 and boot0 pi ns after reset to select the required boot mode. boot0 is a dedicated pin while boot1 is shared with a gpio pin. once boot1 has been sampled, the corresponding gpio pin is free and can be used by the application. the boot pins are also resampled when exiting standby mode. consequently, they must be kept in the required boot mode configurat ion in standby mode. after this startup delay has elapsed, the cpu fetches the top-of-stack value from address 0x0000 0000, and starts code execution from the boot me mory starting from 0x0000 0004. 4.2 boot pin connection figure 12 shows the external connection required to select the boot memory of the stm32l1xxx. figure 12. boot mode selection implementation example 1. resistor values are giv en only as a typical example. table 2. boot modes boot mode selection pins boot mode aliasing boot1 boot0 x 0 main flash memory main flash memory is selected as boot space 0 1 system memory system memory is selected as boot space 1 1 embedded sram embedded sram is selected as boot space ai14373b v dd stm32l1xxx boot0 boot1 v dd 10 k 10 k
docid17496 rev 7 21/33 AN3216 boot configuration 32 4.3 embedded boot loader mode the embedded boot loader is used to reprogram the flash memory through one of the following interfaces: usart1 , usart2 or usb for medium+ and high density devices. this program is located in the system memory and is programmed by st during production (see the stm32l flash programming manual for further details).
debug management AN3216 22/33 docid17496 rev 7 5 debug management 5.1 introduction the host/target interface is the hardware equipm ent that connects the host to the application board. this interface is made of three components: a hardware debug tool, a jtag or sw connector and a cable connecting the host to the debug tool. figure 13 shows the connection of the host to a development board. the evaluation board (stm32l152-eval and stm32l152d-eval) embeds the debug tools (st-link) so it can be directly connected to the pc through an usb cable. figure 13. host-to-board connection 5.2 swj debug port ( serial wire and jtag) the stm32l1xxx core integrates the serial wire/jtag debug port (swj-dp). it is an arm? standard coresight? debug port that combines a jtag-dp (5-pin) in terface and a sw-dp (2-pin) interface. ? the jtag debug port (jtag-dp) provides a 5-pin standard jtag interface to the ahp- ap port ? the serial wire debug port (sw-dp) provides a 2-pin (clock + data) interface to the ahp-ap port in the swj-dp, the two jtag pins of the sw-dp are multiplexed with some of the five jtag pins of the jtag-dp. development board host pc power supply jtag/sw connector debug tool ai14866c
docid17496 rev 7 23/33 AN3216 debug management 32 5.3 pinout and debug port pins the stm32l1xxx mcu is offered in various packages with different numbers of available pins. as a result, some functi onality related to the pin ava ilability may differ from one package to another. 5.3.1 swj debug port pins five pins are used as outputs for the swj-dp as alternate functions of general-purpose i/os (gpios). these pins, shown in table 3 , are available on all packages. 5.3.2 flexible swj-dp pin assignment after reset (sysresetn or por esetn), all five pins used fo r the swj-dp are assigned as dedicated pins which are immediately usable by the debugger host (note that the trace outputs are not assigned except if exp licitly programmed by the debugger host). however, the stm32l1xxx mcu implements a regi ster to disable all or part of the swj-dp port, and so releases the associated pins for general-purpose i/o usage. this register is mapped on an apb bridge co nnected to the cortex ?-m3 system bus. it is programmed by the user software program and not by the debugger host. table 4 shows the different possibilit ies for releasing some pins . for more details, see the stm32l1xxx reference manual (rm0038). table 3. debug port pin assignment swj-dp pin name jtag debug port sw debug port pin assignmen t type description type debug assignment jtms/swdio i jtag test mode selection i/o serial wire data input/output pa13 jtck/swclk i jtag test clock i serial wire clock pa14 jtdi i jtag test data input - - pa15 jtdo/traceswo o jtag test data output - traceswo if async trace is enabled pb3 jntrst i jtag test nreset - - pb4 table 4. swj i/o pin availability available debug ports swj i/o pin assigned pa13 / jtms/ swdio pa14 / jtck/ swclk pa15 / jtdi pb3 / jtdo pb4/ jntrst full swj (jtag-dp + sw-dp) - reset state x x x x x full swj (jtag-dp + sw-dp) but without jntrst xxxx jtag-dp disabled and sw-dp enabled x x jtag-dp disabled and sw-dp disabled released
debug management AN3216 24/33 docid17496 rev 7 5.3.3 internal pull-up and pu ll-down resistors on jtag pins the jtag input pins must not be floating since they are direct ly connected to flip-flops which control the debug mode features. special care must be taken with the swclk/tck pin that is directly connected to the cloc k of some of these flip-flops. to avoid any uncontrolled i/o levels, the stm32l1xxx embeds internal pull-up and pull- down resistors on the jtag input pins: ? jntrst: internal pull-up ? jtdi: internal pull-up ? jtms/swdio: internal pull-up ? tck/swclk: internal pull-down once a jtag i/o is released by the user soft ware, the gpio controller takes control again. the reset states of the gpio control registers put the i/os in the following equivalent states: ? jntrst: input pull-up ? jtdi: input pull-up ? jtms/swdio: input pull-up ? jtck/swclk: input pull-down ? jtdo: input floating the software can then use these i/os as standard gpios. note: the jtag ieee standard recommends to ad d pull-up resistors on tdi, tms and ntrst but, there is no special recommendation for tck. however, for the stm32l1xxx , an integrated pull-down resistor is used for jtck. having embedded pull-up and pull-down resistors removes the need to add external resistors. 5.3.4 swj debug port connection wi th standard jtag connector figure 14 shows the connection between the stm32l1xxx and a standard jtag connector. figure 14. jtag connector implementation ai14376b v dd v dd stm32l1xxx njtrst jtdi jstm/swdio jtck/swclk jtdo nrstin (1) vtref (3) ntrst (5) tdi (7) tms (9) tck (11) rtck (13)tdo (15) nsrst (17) dbgrq (19) dbgack 10 k 10 k 10 k v ss (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) connector 2 10 jtag connector
docid17496 rev 7 25/33 AN3216 recommendations 32 6 recommendations 6.1 printed circuit board for technical reasons, it is best to use a multilayer printed circuit board (pcb) with a separate layer dedicated to ground (v ss ) and another dedicated to the v dd supply. this provides good decoupling and a good shielding effect. for many applications, economical reasons prohibit the use of this type of boar d. in this case, the ma jor requirement is to ensure a good structure for ground and for the power supply. 6.2 component position a preliminary layout of the pcb must make separate circuits: ? high-current circuits ? low-voltage circuits ? digital component circuits ? circuits separated according to their emi contribution. th is will reduce cross-coupling on the pcb that introduces noise. 6.3 ground and power supply (v ss , v dd , v ssa , v dda ) every block (noisy, low-level sensitive, digital, etc.) should be grounded individually, and all ground returns should be to a single point. loops must be avoided or have a minimum area. in order to improve analog performance, you must use separate supply sources for v dd and v dda , and place the decoupling capacitors as close as possible to the device. the power supplies should be implemented close to the ground line to minimize the area of the supplies loop. this is due to the fact that the s upply loop acts as an antenna, and acts as the main transmitter and receiver of emi. all component-free pcb areas must be filled with additional grounding to create a kind of shield ing (especially when us ing single-layer pcbs). 6.4 decoupling all power supply and ground pins must be prop erly connected to the power supplies. these connections, including pads, tracks and vias sh ould have as low an impedance as possible. this is typically achieved with thick track widt hs and, preferably, the use of dedicated power supply planes in multilayer pcbs. in addition, each power supply pair should be decoupled with filteri ng ceramic capacitors c (100 nf) and a tantalum or ceramic capacitor c of about 10 f connected in parallel on the stm32l1xxx device. these capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the pcb. typical values are 10 nf to 100 nf, but exact values depend on the application needs. figure 15 shows the typical layout of such a v dd /v ss pair.
recommendations AN3216 26/33 docid17496 rev 7 figure 15. typical layout for v dd /v ss pair 6.5 other signals when designing an application, the emc perf ormance can be improved by closely studying the following: ? signals for which a temporary disturbance affects the running process permanently (which is the case for interrupts and handsha king strobe signals but, not the case for led commands). for these signals, a surrounding ground trac e, shorter lengths, and the absence of noisy and sensitive traces nearby (cro sstalk effect) improve emc performance. for digital signals, the best possible electr ical margin must be reached for the two logical states and slow schmitt triggers are recommended to eliminate parasitic states. ? noisy signals (example, clock) ? sensitive signals (example, high impedance) 6.6 unused i/os and features all microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the mcu resources. to increase emc performance and avoid extra power consumption, unused clocks, counters or i/os, should not be left free. i/os should be connected to a fixed logic level of 0 or 1 by an external or internal pull-up or pull- down on the unused i/o pin. the other option is to configure gpio as output mode using softwa re. unused features should be frozen or disabled, which is their default value. vi a to v ss vi a to v dd c a p. v dd v ss s tm 3 2l1xxx
docid17496 rev 7 27/33 AN3216 reference design 32 7 reference design 7.1 description the reference design shown in figure 16 , is based on the stm32l152vb(t6) . this reference design can be tailored to any stm32l1xxx de vice with a different package, using the pin correspondence given in table 7: reference connection for all packages . 7.1.1 clock two clock sources are used for the microcontroller: ? lse: x1? 32.768 khz crystal for the embedded rtc ? hse: x2? 8 mhz crystal for the stm32l1xxx microcontroller refer to section 3: clocks on page 16 . 7.1.2 reset the reset signal in figure 16 is active low. the reset sources include: ? reset button (b1) ? debugging tools via the connector cn1 refer to section 2.3: reset and power supply supervisor on page 11 . 7.1.3 boot mode the boot option is configured by setting swit ches sw2 (boot 0) and sw1 (boot 1). refer to section 4: boot configuration on page 20 . note: when waking up from standby mode, the boot pins are sampled. in this situation, you need to pay attention to their values. 7.1.4 swj interface the reference design shows the connection between the stm32l1xxx and a standard jtag connector. refer to section 5: debug management on page 22 . note: it is recommended to connect the reset pins so as to be able to re set the application from the tools. 7.1.5 power supply refer to section 2: power supplies on page 7 .
reference design AN3216 28/33 docid17496 rev 7 7.2 component references table 5. mandatory components reference components name value quantity comments u1a microcontroller stm32l152vb(t6) 1 100-pin package c5, c10, c11, c12, c13, c14 capacitor 100 nf 3 ... 6 ceramic capacitors (decoupling capacitors) c9 capacitor 10 f 1 ceramic capacitor (decoupling capacitor) c4, c6 capacitor 1 f 2 ceramic capacitor (lcd booster or decoupling capacitor) table 6. optional components reference components name value quantity comments r2, r4, r5, r7, r8 resistor 10 k 9 pull-up and pull-down for jtag and boot mode. r6 resistor 390 1 used for hse: the value depends on the crystal characteristics. r1 resistor x 1 used for lse: the value depends on the crystal characteristics. this resistor value depends on the chosen crystal (refer to application note an2867). r3 resistor 0 1 for low pass filter c3, c15 capacitor 100 nf 2 ceramic capacitors (decoupling capacitors) c1, c2 capacitor 6.8 pf 2 used for lse: the value depends on the crystal characteristi cs. fits for mc-306 32.768k-e3, which has a load capacitance of 6 pf. c7, c8 capacitor 20 pf 2 used for hse: the value depends on the crystal characteristics. x2 quartz 8 mhz 1 used for hse x1 quartz 32 khz 1 used for lse cn1 jtag connector he10 1 sw1, sw2 switch 2 used to select the right boot mode b1 push-button 1 l1 ferrite bead 1 for emc reduction on v dda supply
docid17496 rev 7 29/33 AN3216 reference design 32 figure 16. stm32l152vb(t6) microcontroller reference schematic pe2 1 pe3 2 pe4 3 pe5 4 pe6 5 pc13-anti_tamp 7 pc14-osc32_in 8 pc15-osc32_out 9 ph0-osc_in 12 ph1-osc_out 13 nrst 14 pc0 15 pc1 16 pc2 17 pc3 18 pa 0-wkup 23 pa 1 24 pa 2 25 pa 3 26 pa 4 29 pa 5 30 pa 6 31 pa 7 32 pc4 33 pc5 34 pb0 35 pb1 36 pb2- boot1 37 pe7 38 pe8 39 pe9 40 pe10 41 pe11 42 pe12 43 pe13 44 pe14 45 pe15 46 pb10 47 pb11 48 pb12 51 pb13 52 pb14 53 pb15 54 pd8 55 pd9 56 pd10 57 pd11 58 pd12 59 pd13 60 pd14 61 pd15 62 pc6 63 pc7 64 pc8 65 pc9 66 pa 8 67 pa 9 68 pa 10 69 pa 11 70 pa 12 71 pa 13 72 pf2 73 pa 14 76 pa 15 77 pc10 78 pc11 79 pc12 80 pd0 81 pd1 82 pd2 83 pd3 84 pd4 85 pd5 86 pd6 87 pd7 88 pb3 89 pb4 90 pb5 91 pb6 92 pb7 93 boot0 94 pb8 95 pb9 96 pe0 97 pe1 98 u1a stm32l152vbt6 1 4 3 2 b1 reset c15 100nf c8 20pf c7 20pf x2 8mhz r6 390 r7 10k vdd 2 3 1 sw1 4 1 3 2 x1 32.768 khz c1 6.8pf c2 6.8pf r1 0 vlcd 6 vss_5 10 vdd_5 11 vssa 19 vref- 20 vref+ 21 vdda 22 vss_4 27 vdd_4 28 vss_1 49 vdd_1 50 vss_2 74 vdd_2 75 vss_3 99 vdd_3 100 u1b stm32l152vbt6 l1 bead c5 100nf r3 0 vdda vdd_mcu vref+ vref- c3 100nf vdd_mcu c10 100nf c11 100nf c12 100nf c13 100nf c14 100nf vdd_mcu c6 1uf vlcd tms/swdio tck/swclk tdi tdo/swo trst reset# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 cn1 jtag vdd r4 10k r5 10k r2 10k hse jtag connector reset boot mode decoupling capacitor mcu supply lse mcu vdd 2 3 1 sw2 r8 10k c4 1uf c9 10uf ai17479b
reference design AN3216 30/33 docid17496 rev 7 table 7. reference connection for all packages pin name pin numbers for lqfp packages pin numbers for bga packages pin numbers for ufqfpn package 144 pins 100 pins 64 pins 48 pi ns 132 pins 100 pins 64 pins 48 pins ph0-osc_in 23 12 5 5 f1 f1 c1 5 ph1-osc_out 24 13 6 6 g1 g1 d1 6 pc15- osc32_out 9 9 4 4 e1 e1 b1 4 pc14- osc32_in 8833d1d1a1 3 boot0 138 94 60 44 a4 a4 b4 44 pb2-boot1 48 37 28 20 l6 l6 g6 20 nrst 25 14 7 7 h2 h2 e1 7 pa13 105 72 46 34 a11 a11 a8 34 pa14 109 76 49 37 a10 a10 a7 37 pa15 110 77 50 38 a9 a9 a6 38 pb4 134905640a7a7a4 40 pb3 133895539a8a8a5 39 v ss_1 71 49 31 23 f12 f12 d6 23 v ss_2 107 74 47 35 f11 f11 d5 35 v ss_3 143996347d3d3d4 47 v ss_4 38 27 18 - - e3 c2 ? v ss_5 16 10 - - f2 f2 - ? v ss_6 51 - - - e3 - - ? v ss_7 61 - - - - - - ? v ss_8 83 - - - - - - ? v ss_9 94 - - - f6 - - ? v ss_10 120 - - - f7 - - ? v ss_11 130 - - - - - - ? v dd_1 72 50 32 24 g12 g12 e6 24 v dd_2 108 75 48 36 g11 g11 e5 36 v dd_3 144 100 64 48 c4 c4 e4 48 v dd_4 39 28 19 - - h3 d2 ? v dd_5 17 11 - - g2 g2 - ? v dd_6 52 - - - h3 - - ? v dd_7 62 - - - - - - ? v dd_8 84 - - - - - - ?
docid17496 rev 7 31/33 AN3216 reference design 32 v dd_9 95 -- - - g6 - - ? v dd_10 121 -- - - g7 - - ? v dd_11 131 - - - - - - ? v ref+ 32 21 - - l1 l1 g1 ? v ref- 31 20 - - - k1 - ? v ssa 30 19 12 8 j1 j1 f1 8 v dda 33 22 13 9 m1 m1 h1 9 v lcd 6 6 1 1 e2 e2 b2 1 table 7. reference connection for all packages (continued) pin name pin numbers for lqfp packages pin numbers for bga packages pin numbers for ufqfpn package 144 pins 100 pins 64 pins 48 pi ns 132 pins 100 pins 64 pins 48 pins
revision history AN3216 32/33 docid17496 rev 7 8 revision history table 8. document revision history date revision changes 28-jun-2010 1 initial release 29-jul-2010 2 updated the following sections: section 2.1: introduction , section 2.1.1: independent a/d converter supply and reference voltage , section 2.1.2: independent lcd supply , section 2.3.1: power-on reset (por)/power-down reset (pdr), brownout reset (bor) , and section 2.3.4: system reset . added section 2.3.3: brownout reset (bor) . replaced figure 4 , figure 5 , figure 6 , and figure 7 . in section 3.3.2 , replaced rcc_icr register by rcc_cir register. replaced pf0_osc_in and pf1_osc_out by ph0_osc_in and ph1_osc_out in figure 16 and ta ble 7 . updated value of c4 and c9 decoupling capacitors in figure 16 . 01-oct-2010 3 modified section 2.3.4: system reset on page 15 updated capacitors in table 5 and table 5 07-apr-2011 4 changed title of document from ?stm32l1xxx hardware development: getting started? to ?getting started with stm32l1xxx hardware development?. modified section 3.1: msi clock , section 2.2: power supply schemes , and figure 2 . 29-jun-2011 5 updated section 2.1.1: independent a/d converter supply and reference voltage and section 2.2: power supply schemes . 30-may-2012 6 updated to adapt to stm32l1xxx high density devices 20-jun-2013 7 document reformatted. replaced ?stm32l15xxx? by ?stm32l1xxx? in the entire document. updated: ? section 2.1: introduction , section 2.1.2: i ndependent lcd supply , section 6.2: component position , section 6.3: ground and power supply (v ss , v dd , v ssa , v dda ) , section 6.4: decoupling and section 7.1.3: boot mode ? figure 1: power supply overview , figure 2: power supply scheme , figure 7: reset circuit and figure 16: stm32l152vb(t6) microcontroller re ference schematic ? table 5: mandatory components and table 6: optional components added: ? table 1: applicable products ? section 1: glossary ? figure 3: optional lcd power supply scheme
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