View ST8034HCQR_8346833.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. october 2013 docid024511 rev 2 1/31 1 st8034hn, st8034hc 24-pin smartcard interfaces datasheet - production data features ? complete smartcard interface ? iso 7816, nds and emv 4.3 payment systems compatible ? three protected half-duplex bidirectional buffered i/o lines to the smartcard ? 5 v, 3 v or 1.8 v supply voltage for the smartcard (v cc ), pin-select able. ensures controlled v cc rise and fall times and provides smart overload detection with glitch immunity. ? very low power consumpt ion in deep shutdown mode ? chip select function allows the device interface to be isolated from the microcontroller signals - allows parallel combin ation of the card interface devices (st8034hc) ? card clock generation by integrated crystal oscillator or from external clock source ? card clock frequency up to 20 mhz, programmable by clkdiv1 and clkdiv2 pins (st8034hn) or by clkdiv pin (st8034hc), with synchronous frequency changes ? automatic activation and deactivation sequences initiated by the microcontroller ? emergency deactivation sequences initiated by a card supply short-circuit, card take-off, falling v dd , v ddp , or v dd(intf) or by the interface device overheating ? voltage supply supervisors ? with a fixed threshold (v dd , v ddp ) ? with an external resistor divider to set the v dd(intf) threshold (poradj pin) ? multipurpose card status signal off ? non-inverted card reset pin rst driven by the rstin input ? thermal and short-circuit protection of all card contacts ? card presence detection contacts debounced ? enhanced card side esd protection of 8 kv ? space saving qfn24 4 x 4 x 0.8 mm package ? temperature range -25 to +85 c applications smartcard readers for ? set-top boxes ? pay-tv ? identification ? banking ? tachographs qfn24 4 x 4 x 0.8 mm www.st.com
contents st8034hn, st8034hc 2/31 docid024511 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 electrical characteristics over recommended operating conditions . . . . . . . . . . . 11 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 clock circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 input and output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 deep shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.8 deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.9 v cc generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.10 fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.11 vcc_sel pin-programmed card supply voltage (v cc ) . . . . . . . . . . . . . . 27 6.12 chip select (st8034hc only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
docid024511 rev 2 3/31 st8034hn, st8034hc list of tables list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. pin description st8034hn and st8034hc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. clock frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. v cc selection by vcc_sel1, vcc_sel2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. qfn24 4 x 4 x 0.8 mm, 0.5 mm pitch package mech anical data, . . . . . . . . . . . . . . . . . . . 29 table 15. tape and reel specification for qf n24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of figures st8034hn, st8034hc 4/31 docid024511 rev 2 list of figures figure 1. block diagram st8034hn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. block diagram st8034hc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. pin connections st8034hn (top-through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. pin connections st8034hc (top-through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. definition of duty cycle and input and output rise /fall times . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. voltage supervisor, configured with adjustable v dd(intf) threshold. . . . . . . . . . . . . . . . . . 19 figure 7. voltage supervisor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. external clock usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. shutdown and deep shutdown mode activation and deactivation . . . . . . . . . . . . . . . . . . . 23 figure 10. activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. deactivation sequence after card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13. debounce at off , cmdvcc , pres and v cc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. qfn24 4 x 4 x 0.8 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. qfn24 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16. carrier tape for qfn24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
docid024511 rev 2 5/31 st8034hn, st8034hc description 1 description the st8034hn and st8034hc devices are complete low-cost analog interfaces for asynchronous and synchronous smartcards operating at a supply voltage of 5 v, 3 v or 1.8 v. the st8034hn and st8034hc devices can be placed between the card and the microcontroller to provide all supply, protecti on, detection and control functions, with just a few external components. table 1. device summary order code poradj v cc selection pins chip select clkdiv inputs nds compliant package shipment package topmark st8034hnqr ?? 2 ? qfn24 4 x 4 x 0.85 mm, 0.5 mm pitch tape and reel 8034hn ST8034HCQR ??? 1 ? qfn24 4 x 4 x 0.85 mm, 0.5 mm pitch tape and reel 8034hc
block diagrams st8034hn, st8034hc 6/31 docid024511 rev 2 2 block diagrams figure 1. block diagram st8034hn 1. optional external resist or divider. if not used, c onnect the poradj pin to v dd(intf) for a direct v dd(intf) voltage monitoring. $09 9 '',17) 5 5 325$'- 35(6 567,1 &0'9&& 2)) &/.',9 9&&b6(/ 9&&b6(/ ,28& $8;8& $8;8& &/.',9 q) 9 '',17) /(9(/ 6+,)7(5 ;7$/ ;7$/ q) 9 '' *1' 6833/< ,17(51$/ 5()(5(1&( 92/7$*( 6(16( $/$50 ,17(51$/ 26&,//$725 &/2&. &,5&8,7 &5<67$/ 26&,//$725 7+(50$/ 3527(&7,21 &/. 6(48(1&(5 &/.83 (1 (1 (1 39 && 9 && /'2 5(6(7 *(1(5$725 &/2&. *(1(5$725 (1 9 && 567 &/. ,2 $8; $8; q) q) &$5' &211(&725 & & & & & & & & ,2 75$16&(,9(5 ,2 75$16&(,9(5 ,2 75$16&(,9(5 67+1 9 ''3 q)
docid024511 rev 2 7/31 st8034hn, st8034hc block diagrams figure 2. block diagram st8034hc 1. optional external resist or divider. if not used, c onnect the poradj pin to v dd(intf) for a direct v dd(intf) voltage monitoring. $09 9 '',17) 5 5 325$'- 35(6 567,1 &0'9&& 2)) &/.',9 9&&b6(/ 9&&b6(/ ,28& $8;8& $8;8& q) 9 '',17) /(9(/ 6+,)7(5 ;7$/ ;7$/ q) 9 '' *1' 6833/< ,17(51$/ 5()(5(1&( 92/7$*( 6(16( $/$50 ,17(51$/ 26&,//$725 &/2&. &,5&8,7 &5<67$/ 26&,//$725 7+(50$/ 3527(&7,21 &/. 6(48(1&(5 &/.83 (1 (1 (1 39 && 9 && /'2 5(6(7 *(1(5$725 &/2&. *(1(5$725 (1 9 && 567 &/. ,2 $8; $8; q) q) &$5' &211(&725 & & & & & & & & ,2 75$16&(,9(5 ,2 75$16&(,9(5 ,2 75$16&(,9(5 67+& 9 ''3 q) &+,3 6(/(&7 &6
pin description st8034hn, st8034hc 8/31 docid024511 rev 2 3 pin description figure 3. pin connections st 8034hn (top-through view) figure 4. pin connections st 8034hc (top-through view) $09 67+1 4)1[[ppppslwfk7khupdosdgqrwfrqqhfwh g 9 '',17) 9&&b6(/ 567,1 9&&b6(/ &0'9&& &/.',9 325$'- 9 '' 9 ''3 9 && 567 &/. ;7$/ ;7$/ 2)) ,28& $8;8& $8;8& &/.',9 35(6 ,2 $8; *1' $8; $09 67+& 4)1[[ppppslwfk7khupdosdgqrwfrqqhfwh g 9 '',17) 9&&b6(/ 567,1 9&&b6(/ &0'9&& &6 325$'- 9 '' 9 ''3 9 && 567 &/. ;7$/ ;7$/ 2)) ,28& $8;8& $8;8& &/.',9 35(6 ,2 $8; *1' $8;
docid024511 rev 2 9/31 st8034hn, st8034hc pin description table 2. pin description st8034hn and st8034hc pin number symbol ref. supply function 1v dd(intf) v dd(intf) microcontroller interface supply voltage 2 vcc_sel2 v dd(intf) v cc selection control signal 5 v or 3 v (see table 13 on page 27 ) 3rstinv dd(intf) card reset input from mi crocontroller; active high 4 vcc_sel1 v dd(intf) v cc selection control signal 1.8 v, overrides vcc_sel2 (see table 13 on page 27 ) 5cmdvcc v dd(intf) activation sequence start, input (from microcontroller, active low) 6 clkdiv1 v dd(intf) clk frequency division control in put (together with clkdiv2), see ta ble 12 on page 21 (st8034hn) cs v dd(intf) chip select input. high = device active, low = all microcontroller interface pins in high impedance (st8034hc) 7 clkdiv2 v dd(intf) clk frequency division control (together with clkdiv1), see table 12 on page 21 (st8034hn) clkdiv v dd(intf) clk frequency division control, see table 12 on page 21 (st8034hc) 8pres v dd(intf) card presence input (active low: pres low = card is present). debounced. 9i/o v cc card input/output data line (c7); internal 9 k ? pull-up resistor to v cc 10 aux1 v cc auxiliary card input/output data line (c4); internal 9 k ? pull-up resistor to v cc 11 aux2 v cc auxiliary card input/output data line (c8); internal 9 k ? pull-up resistor to v cc 12 gnd ground 13 clk v cc clock to card (c3) 14 rst v cc card reset, output (c2) 15 v cc supply voltage for the card, output (c1) 16 v ddp ldo supply voltage input (for v cc generation) 17 v dd control logic supply voltage input 18 poradj v dd(intf) power-on reset threshold adjustment input (with an optional external resistor divider) 19 off v dd(intf) interrupt to microcontroller (active low output); internal 20 k ? pull-up resistor to v dd(intf) 20 i/ouc v dd(intf) microcontroller data i/o line (with internal 10 k ? pull-up resistor connected to v dd(intf) ) 21 auxuc1 v dd(intf) auxiliary microcontroller input/ output data line; internal 10 k ? pull-up resistor to v dd(intf) 22 auxuc2 v dd(intf) auxiliary microcontroller input/ output data line; internal 10 k ? pull-up resistor to v dd(intf) 23 xtal1 v dd crystal or external clock input 24 xtal2 v dd crystal connection (leave this pin open if external clock is used)
maximum ratings st8034hn, st8034hc 10/31 docid024511 rev 2 4 maximum ratings table 3. absolute maximum ratings (1) , (2) 1. absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condi tions is not implied. 2. all card contacts are protected against short-circuit to any other card contact. symbol parameter min. max. unit v dd supply voltage, logic -0.3 6 v v ddp supply voltage, power -0.3 6 v v dd(intf) supply voltage, interface -0.3 6 v v in input voltage on xtal1, xt al2, rstin, i/ouc, aux1uc, aux2uc, clkdiv1, clkdiv2, cs, vcc_sel1, vcc_sel2, poradj, cmdvcc , off , pres , i/o, aux1, and aux2 pins -0.3 6 v v esd (hbm) human body model (hbm) on card lines - i/o, rst, v cc , clk, and pres pins -8 8 kv human body model (hbm), all other pins -2 2 kv v esd (mm) machine model (mm), all pins -200 200 v v esd (fcdm) field charged device model (fcdm), all pins -500 500 v p tot total power dissipation (t a = -25 to +85 c) 0.25 w t j(max) maximum operating junction temperature 125 c t stg storage temperature range -55 150 c table 4. thermal data symbol parameter test conditions typ. unit r thja thermal resistance junction-ambient temperature (multilayer test board - jedec standard) qfn24 47 c/w table 5. recommended operating conditions symbol parameter test conditions min. max. unit t a ambient temperature range -25 85 c
docid024511 rev 2 11/31 st8034hn, st8034hc electrical characteristics 5 electrical characteristics electrical characteristics over recommended operating conditions table 6. supply voltages symbol parameter test conditions (1) min. typ. max. unit device supply voltages v dd supply voltage, logic 2.7 3.3 3.6 (2) v v ddp supply voltage, power v cc = 5 v 4.85 5 5.5 v v cc = 3 v or 1.8 v 3 3.3 5.5 v dd(intf) supply voltage, microcontroller interface 1.6 3.3 v dd +0.3 (3) v i dd supply current, logic shutdown mode 35 ? a deep shutdown mode 12 active mode 2 ma i ddp supply current, power shutdown mode, f xtal stopped 5 ? a active mode, f clk = f xtal /2, no i cc load 1.5 ma active mode, f clk = f xtal /2, i cc = 65 ma 70 i dd(intf) supply current, interface shutdown mode 6 ? a active mode 2 ma card supply voltage v cc card supply voltage (output) (4) active mode, v cc = 5 v, i cc < 65 ma 4.75 5.0 5.25 v with current pulses of 40 nas at i cc < 200 ma, t < 400 ns (5) 4.65 5.0 5.25 active mode, v cc = 3 v, i cc < 65 ma 2.85 3.05 3.15 with current pulses of 40 nas at i cc < 200 ma, t < 400 ns (5) 2.76 3.20 active mode, v cc = 1.8 v, i cc < 65 ma 1.71 1.83 1.89 with current pulses of 15 nas at i cc < 200 ma, t < 400 ns (5) 1.66 1.94 i cc card supply current (refer also to table 10: protection characteristics on page 17 ) v cc = 5 v, 3 v or 1.8 v 65 ma v cc shorted to gnd 90 120 150 c vcc v cc decoupling capacitor (4) v cc to gnd 160 320 530 nf sr v cc slew rate (rising or falling) (4) v cc = 5 v 0.055 0.180 0.300 v/ ? s v cc = 3 v 0.040 0.180 0.300 v cc = 1.8 v 0.025 0.180 0.300
electrical characteristics st8034hn, st8034hc 12/31 docid024511 rev 2 v cc(shdn) v cc output voltage in shutdown mode no load -0.1 0.1 v i cc = 1 ma -0.1 0.3 i cc(shdn) v cc output current in shutdown mode v cc connected to gnd -1 ma device supply voltages monitoring v th falling supply voltage threshold v dd pin 2.3 2.4 2.5 v v ddp pin (v cc = 5 v) 3.0 4.1 4.4 v ddp pin (v cc = 3 v or 1.8 v) 2.3 2.4 2.5 poradj pin 1.20 1.24 1.29 v hys hysteresis on supply voltage threshold v dd pin 50 100 150 mv v ddp pin (v cc = 5 v) 100 200 350 v ddp pin (v cc = 3 v or 1.8 v) 50 100 150 poradj pin 10 20 30 i i(poradj) input current, poradj pin -1 1 ? a t w power-on or undervoltage reset pulse width (minimum) 5.1 8 10.2 ms 1. t a = 25 c, v dd = 3.3 v, v ddp = 5 v, v dd(intf) = 3.3 v, f xtal = 10 mhz, unless otherwise noted. 2. the device can operate at v dd supply voltage up to 5.5 v, however the spec ified parameters (mainly related to current consumption) are guaranteed in the basic v dd range 2.7 to 3.6 v. 3. the device can operate at v dd(intf) supply voltage up to 5.5 v, however the specif ied parameters (mainly related to current consumption and input currents) are guaranteed in the basic v dd(intf) range 1.6 to 3.6 v. 4. two low esr (< 350 m ? ) ceramic capacitors for v cc decoupling recommended: 100 nf 20% (up to 330 nf 20%) close to the st8034 and 100 nf 20% (up to 330 nf 20%) close to the card. 5. these current pulses are filtered by the decoupling capacitors on the v cc pin, therefore for the ldo just the mean value matters. table 6. supply voltages (continued) symbol parameter test conditions (1) min. typ. max. unit
docid024511 rev 2 13/31 st8034hn, st8034hc electrical characteristics table 7. card interface symbol parameter test conditions (1) min. typ. max. unit data lines to the card (i/o, aux1, aux2 pins) (2) t d delay time falling edge on pin i/o to falling edge on i/ouc or vice versa 200 ns t w(pu) pull-up pulse width 100 400 ns f io input/output frequency 1 mhz c i input capacitance 10 pf v o output voltage in shutdown mode no load 0 0.1 v i o = 1 ma 0 0.3 v i o output current in shutdown mode i/o connected to gnd -1 ma v ol output voltage low i ol = 1 ma 0 0.3 v i ol ? 15 ma (current limit) v cc - 0.4 v cc v oh output voltage high no load 0.9 v cc v cc + 0.1 v i oh < -40 ? a, 5 v or 3 v 0.75 v cc v cc + 0.1 i oh < -20 ? a, 1.8 v 0.75 v cc v cc + 0.1 i oh ? -15 ma (current limit) 0 0.4 v il input voltage low -0.3 0.8 v v ih input voltage high v cc = 5 v 0.6 v cc v cc + 0.3 v v cc = 3 v or 1.8 v 0.7 v cc v cc + 0.3 v hys hysteresis i/o pin 50 mv i il input current low i/o pin, v il = 0 v 750 ? a i ih input current high i/o pin, v ih = v cc 10 ? a t r(i) input rise time v il max. to v ih min. 0.15 ? s t r(o) output rise time c l ? 80 pf, 10% to 90%, 0 v to v cc 0.1 ? s t f(i) input fall time v il max. to v ih min. 0.15 ? s t f(o) output fall time c l ? 80 pf, 10% to 90%, 0 v to v cc 0.1 ? s r pu pull-up resistance to v cc 7911k ? i pu pull-up current (one-shot circuit active) v oh = 0.9 v cc -8 -6 -4 ma reset output to the card (rst pin) v o output voltage in shutdown mode no load 0 0.1 v i o = 1 ma 0 0.3 i o output current in shutdown mode rst connected to gnd -1 ma t d delay time between rstin and rst; rst enabled 2 ? s
electrical characteristics st8034hn, st8034hc 14/31 docid024511 rev 2 v ol output voltage low i ol = 200 ? a, v cc = 5 v 0 0.3 v i ol = 200 ? a, v cc = 3 v or 1.8 v 0 0.2 i ol = 20 ma (current limit) v cc - 0.4 v cc v oh output voltage high i oh = -200 ? a0.9 v cc v cc v i oh = -20 ma (current limit) 0 0.4 t r rise time c l = 100 pf 0.1 ? s t f fall time c l = 100 pf 0.1 clock output to the card (clk pin) v o output voltage in shutdown mode no load 0 0.1 v i o = 1 ma 0 0.3 i o output current in shutdown mode clk connected to gnd -1 ma v ol output voltage low i ol = 200 ? a00.3 v i ol = 70 ma (current limit) v cc - 0.4 v cc v oh output voltage high i oh = -200 ? a0.9 v cc v cc v i oh = -70 ma (current limit) 0 0.4 t r rise time (3) c l = 30 pf 16 ns t f fall time (3) c l = 30 pf 16 ns f clk frequency on pin clk operational 0 20 mhz dc duty cycle (3) c l = 30 pf 45 55 % sr slew rate (rise and fall, c l = 30 pf) v cc = 5 v 0.2 v/ns v cc = 3 v or 1.8 v 0.12 card detection input (pres pin) (4) v il input voltage low -0.3 0.3 v dd(intf) v v ih input voltage high 0.7 v dd(intf) v dd(intf) + 0.3 v v hys hysteresis 0.14 v dd(intf) v i il input current low 0 < v il < v dd(intf) 5 ? a i ih input current high 0 < v ih < v dd(intf) 5 ? a 1. t a = 25 c, v dd = 3.3 v, v ddp = 5 v, v dd(intf) = 3.3 v, f xtal = 10 mhz, unless otherwise noted. 2. with an internal 9 k ? pull-up resistor to v cc . 3. for rise and fall times and duty cycle definitions, see figure 5 on page 18 . 4. pres is active low, with an internal current source of 1.25 ? a (pull-up) to v dd(intf) . table 7. card interface (continued) symbol parameter test conditions (1) min. typ. max. unit
docid024511 rev 2 15/31 st8034hn, st8034hc electrical characteristics table 8. microcontroller interface symbol parameter test conditions (1) min. typ. max. unit data lines to the microcontrol ler (i/ouc, aux1uc, aux2uc pins) (2) t d delay time falling edge on pin i/o to falling edge on i/ouc or vice versa 200 ns t w(pu) pull-up pulse width 100 400 ns f io input/output frequency 1 mhz c i input capacitance 10 pf v ol output voltage low i ol = 1 ma 0 0.3 v v oh output voltage high no load 0.9 v dd(intf) v dd(intf) + 0.1 v i oh ? -40 ? a; v dd(intf) > 2 v 0.75 v dd(intf) v dd(intf) + 0.1 i oh ? -20 ? a; v dd(intf) < 2 v 0.75 v dd(intf) v dd(intf) + 0.1 v il input voltage low -0.3 0.3 v dd(intf) v v ih input voltage high 0.7 v dd(intf) v dd(intf) + 0.3 v v hys hysteresis i/ouc pin 0.14 v dd(intf) v i il input current low v il = 0 v 500 ? a i ih input current high v ih = v dd(intf) 10 ? a r pu pull-up resistance to v dd(intf) 81012k ? i pu pull-up current (one-shot circuit active) v oh = 0.9 v dd(intf) -1 ma t r(i) input rise time v il max. to v ih min. 0.15 ? s t r(o) output rise time c l ? 30 pf, 10% to 90%, 0 v to v dd(intf) 0.1 ? s t f(i) input fall time v il max. to v ih min. 0.15 ? s t f(o) output fall time c l ? 30 pf, 10% to 90%, 0 v to v dd(intf) 0.1 ? s device control inputs (cl kdiv1, clkdiv2, rstin, vcc_sel1, vcc_sel2, cs pins) (3) v il input voltage low -0.3 0.3 v dd(intf) v v ih input voltage high v dd(intf) v dd(intf) + 0.3 v v hys hysteresis 0.14 v dd(intf) v
electrical characteristics st8034hn, st8034hc 16/31 docid024511 rev 2 i il input current low 1 ? a i ih input current high 1 ? a control input cmdvcc (4) v il input voltage low -0.3 0.3 v dd(intf) v v ih input voltage high 0.7 v dd(intf) v dd(intf) + 0.3 v v hys hysteresis 0.14 v dd(intf) v i il input current low v il = 0 v 1 ? a i ih input current high v ih = v dd(intf) 1 ? a f cmdvcc frequency at cmdvcc pin 100 hz off output (5) v ol output voltage low i ol = 2 ma 0 0.3 v v oh output voltage high i oh = -15 ? a 0.75 v dd(intf) v r pu pull-up resistance to v dd(intf) 16 20 24 k ? 1. t a = 25 c, v dd = 3.3 v, v ddp = 5 v, v dd(intf) = 3.3 v, f xtal = 10 mhz, unless otherwise noted. 2. with an internal 10 k ? pull-up resistor to v dd(intf) . 3. for clock frequency division control (clkdiv), see table 12 on page 21 . 4. cmdvcc is active low. 5. off is an nmos open drain, with an internal 20 k ? pull-up resistor to v dd(intf) . the pull-up is connected only when used (i.e. when off = high), otherwise disconnected. table 8. microcontroller interface (continued) symbol parameter test conditions (1) min. typ. max. unit
docid024511 rev 2 17/31 st8034hn, st8034hc electrical characteristics table 9. clock circuits symbol parameter test conditions (1) min. typ. max. unit internal oscillator f osc(int)low internal oscillator frequency shutdown mode 100 150 200 khz f osc(int) active state 2 2.7 3.2 mhz crystal oscillator (xtal1 and xtal2 pins) c ext external capacitances xtal1 and xtal2 to gnd (according to the crystal or resonator specification) 15 pf f xtal external crystal frequency card clock reference, crystal oscillator 226mhz f ext external clock frequency external clock on xtal1 0.032 26 mhz t r(fext) external clock frequen cy rise time external clock on xtal1 10 ns t f(fext) external clock frequency fall time external clock on xtal1 10 ns v il input voltage low crystal oscillator -0.3 0.3 v dd v external clock on xtal1 -0.3 0.3 v dd(intf) v ih input voltage high crystal oscillator 0.7 v dd v dd + 0.3 v external clock on xtal1 0.7 v dd(intf) v dd(intf) + 0.3 1. t a = 25 c, v dd = 3.3 v, v ddp = 5 v, v dd(intf) = 3.3 v, f xtal = 10 mhz, unless otherwise noted. table 10. protection characteristics symbol parameter test conditions (1) min. typ. max. unit i olim output current limit (2) i/o pin -15 15 ma clk pin -70 70 rst pin -20 20 i sd(vcc) limit and shutdown card supply current v cc pin 90 120 150 ma t sd shutdown junction temperature 150 c 1. t a = 25 c, v dd = 3.3 v, v ddp = 5 v, v dd(intf) = 3.3 v, f xtal = 10 mhz, unless otherwise noted. 2. all card contacts are protected against short-circuit to any other card contact.
electrical characteristics st8034hn, st8034hc 18/31 docid024511 rev 2 figure 5. definition of duty cycle and input and output rise/fall times duty cycle (dc) = t 1 / (t 1 + t 2 ). table 11. timing characteristics symbol parameter test conditions (1) min. typ. max. unit t act activation time see figure 10 on page 24 2090 4160 s t deact deactivation time see figure 11 on page 25 35 90 250 s t d(start) , t d(end) delay time, clk sent to card using an external clock t d(start) = t 3 , see figure 10 on page 24 2090 4112 s t d(end) = t 5 , see figure 10 on page 24 2120 4160 t deb debounce time pres pin 3.2 4.5 6.4 ms 1. t a = 25 c, v dd = 3.3 v, v ddp = 5 v, v dd(intf) = 3.3 v, f xtal = 10 mhz, unless otherwise noted. $0 w 5 w ) w w 9 2+ 9 2+ 9 2/ 9 2/
docid024511 rev 2 19/31 st8034hn, st8034hc functional description 6 functional description throughout this doc ument it is assumed that the reader is familiar with iso7816 terminology. 6.1 power supplies all interface signals to the host microcontroller are referenced to v dd(intf) . all card contacts remain inactive during power-up or power-down. after powering up the device, off output remains low until cmdvcc input is set high and pres input is low. during power-down, off output goes low when v ddp falls below the v ddp falling threshold voltage. the internal oscillator clock frequency f osc(int) is used only during the activation sequence. when the card is not activated (cmdvcc input is high), the internal oscillator is in low frequency mode to reduce power consumption. power-on sequence: supply voltages may be applied to the st8034 in any sequence. 6.2 voltage supervisor figure 6. voltage supervisor, configured with adjustable v dd(intf) threshold $0 9 '',17) 325$'- 9 '' 9 ''3 9&&b6(/ 5 5 9 '',17) 9 '' 5()(5(1&( 92/7$*(
functional description st8034hn, st8034hc 20/31 docid024511 rev 2 the voltage supervisor monitors the v ddp , v dd , and v dd(intf) voltages and provides both power-on reset (por) and supply dropout detecti on during a card session. the supervisor threshold voltages for v ddp and v dd are set internally, and v dd(intf) is set externally by an external resistor divider on the poradj pin, which provides additional voltage monitoring flexibility (this pin can be used for monitori ng any external voltage, with adjustable threshold): undervoltage (uvlo) threshold adjustment on the poradj input with the resistor divider: v dd(intf) uvlo threshold (fallin g) = (r1+r2)/r2 x v th(poradj) v dd(intf) uvlo threshold (rising) = (r1+r2)/r2 x (v th(poradj) + v hyst(poradj) ) if the external resistor divider is no t used, connect the poradj pin to v dd(intf) , then v dd(intf) uvlo threshold = v th(poradj) . as long as v ddp , v dd or v dd(intf) is less than the corresponding v th + v hys , the device remains inactive irrespective of the command line levels. after v ddp , v dd , and v dd(intf) has reached a level higher than the corresponding v th + v hys , the device still remains inactive for the duration of t w , a defined reset pulse of approximately 8 ms (t w = 1024 x 1/f osc(int)low ) when the output of the supervisor keeps the control logic in reset state. this is used to maintain the device in shutdown mode during the supply voltage power-on, see figure 7 . a deactivation sequence is performed when either v dd , v ddp or v dd(intf) falls below the corresponding v th . figure 7. voltage supervisor waveforms 6.3 clock circuits the clock signal for the card (c lk output) is either provided by an external clock signal connected to the xtal1 pin or generated by a crystal connected between the xtal1 and xtal2 pins. the st8034 automatically detects if an external clock is connected to xtal1, which eliminates the need for a separate clock source selection pin. automatic clock source detection is performed on each acti vation command (falling edge of cmdvcc ). the presence of an external clock on the xtal1 pin is checked during a time window defined by the internal oscillator. if the ex ternal clock is detected, the cr ystal oscillator is stopped. if the clock is not detected, the crystal oscillator is started. when the external clock is used, the clock signal must be present on the xtal1 pin before the cmdvcc falling edge. if the external clock is used, connect it to xtal1 input and leave the xtal2 pin floating. the xtal1 pin can not be left floating, either a crystal or an external clock source needs to be connected, or the xtal1 pin needs to be grounded. $0 9 7+ 9 +<6 9 7+ 9 '' 9 ''3 9 '',17) 9 325$'- $/$50 lqwhuqdovljqdo srzhurq srzhurii vxsso\gursrxw w : w :
docid024511 rev 2 21/31 st8034hn, st8034hc functional description figure 8. external clock usage the clock frequency is selected by t he clkdiv1 and clkdiv2 pins and is f xtal , f xtal /2, f xtal /4 or f xtal /8 in the case of the st8034hn or either f xtal or f xtal /2 in the case of the st8034hc, selected by the clkdiv pin, see table 12 . the frequency change is synchronous, meaning that after transition on the clkdiv input, the present clock period is completed and after that the new whole clock period starts, therefore no clock period is shortened during the frequency switchover. if an external crystal is used , the duty cycle on the clk pin should be between 45% and 55%. if an external clock is connected to the xtal1 pin, its duty cycle must be between 48% and 52% so that the clk output duty cycle is between 45% and 55%. 6.4 input and output circuits when the i/o and i/ouc pins are pulled high by a 9 k ? resistor between i/o and v cc and/or 10 k ? resistor between i/ouc and v dd(intf) , both lines enter the idle state. the i/o pin is referenced to v cc and the i/ouc pin to v dd(intf) , which allows operation at v cc level different from v dd(intf) level. table 12. clock frequency selection st8034hn clkdiv1 pin level clkdiv2 pin level clk frequency low low f xtal /8 low high f xtal /4 high high f xtal /2 high low f xtal st8034hc clkdiv pin level clk frequency high f xtal /2 low f xtal $09 /2*,& 08/7,3/(;(5 &5<67$/ ;7$/ ;7$/ (1&/.,1 &/.;7$/
functional description st8034hn, st8034hc 22/31 docid024511 rev 2 the first side on which a falling edge occurs becomes the master. an anti-latch circuit disables falling edge detection on the other side , making it the slave. after a time delay t d , the logic 0 present on the master side is sent to the slave side. when the master side returns logic 1, the slave side sends logic 1 during time delay (t w(pu) ). after this sequence, both master and slave sides return to their idle states. the active pull-up feature (one-shot circuit) ensures fast low to high transitions, making the st8034 outputs capable of delivering more th an 1 ma, up to an output voltage of 0.9 v cc , at a load of 80 pf. at the end of the active pull-up pulse, the output voltage is dependent on the internal pull-up resistor value and load current. the current sent to and received from the card's i/o lines is limited to 15 ma at a maximum frequency of 1 mhz. 6.5 shutdown mode after a power-on reset, if cmdvcc is high, the st8034 enters shutdown mode, ensuring only the minimum number of circuits are active while the st8034 waits for the microcontroller to start a session. ? all card contacts are inactive. the impe dance between the contacts and gnd is approximately 200 ? ? i/ouc, aux1uc, aux2uc pins are in high impedance with the 10 k ? pull-up resistor connected to v dd(intf) ? the voltage generators are stopped ? the voltage supervisor is active ? the internal oscillator runs at its lowest frequency (f osc(int)low ).
docid024511 rev 2 23/31 st8034hn, st8034hc functional description 6.6 deep shutdown mode when the smartcard reader is inactive, the st8034hn and st8034hc enter a deep shutdown mode if the cmdvcc pin is forced high and the vcc_sel1 and vcc_sel2 pins are low. in deep shutdown mode, all circuits are disabled and the off pin follows the status of the pres pin. changing the status of either cmdvcc , vcc_sel1 or vcc_sel2 exits the deep shutdown mode, see figure 9 . figure 9. shutdown and deep shutdown mode activation and deactivation 6.7 activation sequence the following device activation sequence is applie d when using an external clock, also see figure 10 : 1. cmdvcc is pulled low (t 0 ). 2. the internal osc illator is triggered (t 0 ). 3. the internal o scillator changes to high frequency (t 1 ). 4. v cc rises from 0 v to 1.8 v or to 3 v or to 5 v on a controlled slope (t 2 ). 5. i/o, aux1, aux2 are driven high (t 3 ). 6. the clock on the clk output is applied to the c3 contact (t 4 ). 7. rst is enabled (t 5 ). $09 'hdfwlydlrq vhtxhqfh 'herxqfh &0'9&& 9&&b6(/ 9&&b6(/ 0rgh 2)) 35(6 9 && 'hhsvkxwgrzq 6kxwgrzq $fwlyh $fwlyh
functional description st8034hn, st8034hc 24/31 docid024511 rev 2 time delays ? t 1 = t 0 + 384 1/f osc(int)low ? t 2 = t 1 ? t 3 (t d(start) ) = t 1 + 17t/2 ? t 4 = driven by host microcontroller; > t 3 and < t 5 ? t 5 (t d(end) ) = t 1 + 23t/2. t = 64 x 1/f osc(int) . figure 10. activation sequence 6.8 deactivati on sequence when a session ends, the microcontroller sets cmdvcc high. the st8034 device then executes an automatic deactivation sequence by counting the sequencer back to the inactive state (see figure 11 ): 1. rst goes low (t 11 ). 2. the clock is stopped, clk is low (t 12 ). 3. i/o, aux1, aux2 are pulled low (t 13 ). 4. v cc falls to 0 v (t 14 ). the deactivation sequence is completed when v cc reaches its inactive state. 5. v cc < 0.4 v (t deact ). 6. all card contacts become low imped ance to gnd. the i/ou c, aux1uc and aux2uc pins remain pulled up to v dd(intf) by the internal 10 k ? pull-up resistor. 7. the internal osc illator returns to its low frequency mode. $0 $75 &0'9&& ;7$/ 9 && ,2 &/. 567,1 567 ,28& ,17(51$/ !qv w w w w w w '(1' w $&7 w w '67$57 orziuhtxhqf\ kljkiuhtxhqf\ 26&,//$725
docid024511 rev 2 25/31 st8034hn, st8034hc functional description time delays ? t 11 = t 10 + 3t / 64 ? t 12 = t 11 + t / 2 ? t 13 = t 11 + t ? t 14 = t 11 + 3t / 2 ? t deact = t 11 + 3t / 2 + v cc fall time. t = 64 x 1/f osc(int) . figure 11. deactivation sequence 6.9 v cc generator the ldo on the v cc output is capable of supplying up to 65 ma continuously at any selected v cc value (5 v, 3 v or 1.8 v). this output is overcurrent protected by the current limiter with a limit threshold value of 120 ma ty p., with a glitch immuni ty allowing overcurrent pulses up to 200 ma with duration up to several microseconds not causing a deactivation (the average current value must stay below the specified current limit, see table 6 on page 11 and table 10 on page 17 ). a 100 nf capacitor (min.) with esr < 350 m ? should be tied to gnd near the v cc pin and another low esr 100 nf capacitor (min.) should be tied to gnd also on the card side, near the card reader contact c1. $0 &0'9&& 567 &/. ,2 9 && ;7$/ ,17(51$/ 26&,//$725 orziuhtxhqf\ w w w w w w '($&7 kljkiuhtxhqf\
functional description st8034hn, st8034hc 26/31 docid024511 rev 2 6.10 fault detection the fault conditions monitored by the device are: ? short-circuit or overcurrent on the v cc pin ? card removal during transaction ? v dd falling ? v ddp falling ? v dd(intf) falling ? overheating. there are two different fault detection situations: ? outside card session (cmdvcc pin is high): the off pin is low if the card is not in the reader and high if the card is in the reader. any voltage drop on v dd , v ddp or v dd(intf) is detected by the voltage supervisor. this generates an internal power-on reset pulse but does not act upon the off pin signal. the card is not powered-up and short-circuits or overheating are not detected. ? in card session (cmdvcc pin is low): when the off pin goes low, the fault detection circuit triggers the automatic emergency deactivation sequence (see figure 12 ). on card insertion or removal, bouncing can o ccur on the card presence switch (i.e. on the pres signal). therefore a debouncing feature is integrated into the st8034 (4.5 ms typically, t deb = 640 1/f osc(int)low ). see figure 13 . on card insertion, the off pin goes high after the debounce time has elapsed. when the card is extracted, the automatic card deactivation sequence is performed on the first high to low transition on the pres pin. after this, the off pin goes low. figure 12. deactivation sequence after card removal $0 2)) 35(6 567 &/. ,2 9 && ;7$/ ,17(51$/ 26&,//$725 w w w w w '($&7 orziuhtxhqf\ kljkiuhtxhqf\
docid024511 rev 2 27/31 st8034hn, st8034hc functional description figure 13. debounce at off , cmdvcc , pres and v cc pins 1. deactivation caused by card withdrawal. 2. deactivation caused by sh ort-circuit on card side. 6.11 vcc_sel pin-programmed card supply voltage (v cc ) the card supply voltage (v cc ) is selected by the vcc_sel1 and vcc_sel2 inputs, see table 13 . 6.12 chip select (st8034hc only) the chip select (cs) input pin of the st8034 hc replaces the clkdiv1 pin and is active high, meaning normal operation of the device when cs is in logic high state. when the cs pin goes low, the status of the st8034hc device is frozen (i.e. status of control inputs rstin, cmdvcc , clkdiv, vcc_sel1 and vcc_sel2 is latched) and the i/ouc, aux1uc, and aux2uc pins on the microcontro ller interface go into high impedance mode (with pull-up resistors to v dd(intf) ), not transferring any data to or from the card. the off output pin also goes into high impedance mode. this allows the microcontroller to share interface pins among multiple smartcard interfac es connected in parallel. status and all the st8034hc device functions (including the card ) are maintained for immediate use when the cs goes high again. for this reason clock input is not affected by the chip select, the clock is provided to the st8034hc device and to the card even when the cs is low. $0 35(6 2)) &0'9&& 9 && w '(% w '(% table 13. v cc selection by vcc_sel1, vcc_sel2 pins vcc_sel1 pin level vc c_sel2 pin level v cc low x (1) 1. x = ?don't care?. however keep in mind that combination vcc_sel1 = vcc_sel2 = gnd and cmdvcc = high initiates deep shutdown mode. 1.8 v high high 5 v high low 3 v
package information st8034hn, st8034hc 28/31 docid024511 rev 2 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 14. qfn24 4 x 4 x 0.8 mm, 0.5 mm pitch package outline & 4)1 ( ' % $ ,qgh[duhd '[( & ddd [ & ddd [ 7239,(: 3,1,' 5 / ' h e [ ( eee 0 0 ggg &$% & [ . [ %277209,(: fff & $ & hhh [ 6,'(9,(: 6($7,1* 3/$1( $
docid024511 rev 2 29/31 st8034hn, st8034hc package information figure 15. qfn24 recommended footprint table 14. qfn24 4 x 4 x 0.8 mm, 0.5 mm pitch package mechanical data (1) , (2) 1. dimensioning and tolerancing conform to asme y14.5-2009. 2. the location of the terminal #1 identifier is within the hatched area. symbol dimensions (mm) note min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 (3) 3. dimension b applies to metallized terminal. if the te rminal has a radius on its end, dimension b should not be measured in that radius area. d 3.90 4.00 4.10 e 3.90 4.00 4.10 e 0.5 ref. d2 1.95 2.10 2.20 e2 1.95 2.10 2.20 k0.20- - l 0.30 0.40 0.50 aaa 0.05 0.05 bbb 0.10 0.10 ccc 0.10 0.10 ddd 0.05 0.05 eee 0.08 0.08
tape and reel information st8034hn, st8034hc 30/31 docid024511 rev 2 8 tape and reel information figure 16. carrier tape for qfn24 1. 10 sprocket hole pitch cumulative tolerance ? 0.2. 2. camber in compliance with eia 481. 3. pocket position relative to sprocket hole m easured as true position of pocket, not pocket hole. 9 revision history ? 5pd[ 6hfwlrq$$ .r ? 5 $r %r ? plq $ ? ? $ $r %r .r table 15. tape and reel specification for qfn24 quantity per reel carrier tape cover tape lockreel 7 / 13" part no. (vendor) description part no. (vendor) description part no. (vendor) description 3000 434146 (cpak) carrier tape 12 mm width, 8 mm pitch 437150 (cpak) cover tape 9.2 mm width 434543 (peak) 13" lockreel table 16. document revision history date revision changes 22-apr-2013 1 initial release. 22-oct-2013 2 updated title on page 1 (removed st8034hn and st8034hc). updated table 1 on page 5 (removed note 1). minor modifications throughout document.
docid024511 rev 2 31/31 st8034hn, st8034hc please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of ST8034HCQR

	To Download ST8034HCQR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .