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| 1 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 data sheet: ACD82124 24 ports 10/100 fast ethernet switch controller rev.1.1.1.f last update: november 5, 1998 subject to change acd confidential material for acd authorized customer use only. no reproduction or redistribution without acds prior permission. please check acds website for update information before starting a design web site: http://www.acdcorp.com or contact acd at: email: support@acdcorp.com tel: 408-433-9898x115 fax: 408-545-0930 advanced communication devices
2 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 table of contents page 1 general description 3 2 main features 3 3 system block diagram 3 4system description 4 5 functional description 4 6 interface description 10 7 register description 16 8 pin description 27 9 timing description 32 10 electrical specifications 38 11 packaging 39 appendix a1 address resolution logic 40 (the built-in arl) section 3 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 buffer queue manager lookup engine (2k mac addr.) led controller bist handler arl acd80800 (11k mac addr.) (optional) mib acd80900 (optional) arl interface sram mac-0 mac-1 mac-22 mac-23 sram interface mib interface pmd/ phy-0 pmd/ phy-1 pmd/ phy-22 pmd/ phy-23 mx dmx buffer buffer buffer buffer buffer buffer buffer fifo fifo fifo fifo fifo fifo fifo fifo ACD82124 3. system block diagram 1. general description the ACD82124 is a single chip implementation of a 24 port 10/100 ethernet switch system intended for ieee 802.3 and 802.3u compatible networks. the device includes 24 independent 10/100 macs. each mac interfaces with an external pmd/phy device through a standard mii interface. speed can be automatically configured through the mdio port. each port can op- erate at either 10mbps or 100mbps. the core logic of the ACD82124, implemented with patent pending basiq (bandwidth assured switching with intelligent queuing) technology, can simultaneously process 24 asynchronous 10/100mbps port traffic. the queue manager inside the ACD82124 provides the capability of routing traffic with the same order of sequence, without any packet loss. a complete 24 port 10/100 switch can be built with the use of the ACD82124, 10/100 phy and asram. the mac addresses can be expanded from the built-in 2k to 11k by the use of acds external arl chip (acd80800 address resolution logic). advanced net- work management features can be supported with the use of acds mib (acd80900 management informa- tion base) chip. 2. features 24 ports 10/100 auto-sensing with mii interface half-duplex operation, with optional full-duplex con- figuration by combining 2 adjacent ports 2.4 gbps aggregated throughput true non-blocking switch architecture flexible port configuration (up to 12 full duplex 10/ 100 ports, up to 24 half duplex 10/100 ports) built-in storage of 2,000 mac address automatic source address learning zero-packet loss back-pressure flow control store-and-forward switch mode port based v-lan support uart type cpu management interface supports up to 11k mac addresses with the acd80800 rmon and snmp support with acd80900 status leds: link, speed, full duplex, transmit, receive, collision and frame error reversible mii option for cpu and expansion port interface wire speed forwarding rate 576 pin bga package 3.3v power supply, 3.3v i/o with 5v tolerance 4 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 4. system description the ACD82124 is a single chip implementation of a 24-port fast ethernet switch. together with external asram and transceiver devices, it can be used to build a complete desktop class fast ethernet switch. each individual port can be either auto-sensed or manu- ally selected to run at 10 mbps or 100 mbps speed rate, under half duplex mode. the ACD82124 ethernet switch contains three major functional blocks: the media access controller (mac), the queue manager, and the lookup engine. there are 24 independent macs within the ACD82124. the mac controls the receiving, transmitting, and de- ferring process of each individual port, in accordance to ieee 802.3 and 802.3u standard. the mac logic also provides framing, fcs checking, error handling, status indication and back-pressure flow control func- tions. each mac interfaces with an external transceiver through standard mii interface. the device utilizes acds proprietary basiq (band- width assured switching with intelligent queuing) tech- nology. it is a technology to enforce the first-in-first- out rule of ethernet bridge-type devices in a very effi- cient way. the technology enables a true non-block- ing frame switching operation at wire speed for a high throughput and high port density ethernet switch. the on-chip 2,000 mac addresses lookup engine maps each destination address into a destination port. each ports mac address is automatically learned by the lookup engine when it receives a frame with no error. therefore, the ACD82124 alone can be used to build a desktop class fast ethernet switch without any additional switching devices. the mac address space can be expanded from 2,000 to 8,000 per system by using the acd80800. the ACD82124 has a proprietary arl interface that allows direct connection with acd80800. system designers can also use this arl interface to implement a ven- dor-specific address resolution algorithm. the ACD82124 provides management support through its mib (management information base) interface. the mib interface can be used to monitor all traffic activi- ties of the switch system. acds supporting chip (the acd80900) provides a full set of statistical counters to support both snmp and rmon network management. the mib interface can also be used by system de- signers to implement vendor-specific network manage- ment functionality. among the 24 mii interfaces, 10 of them can be con- figured as reversed mii, to connect directly with stand- alone mac controller devices. a mac in the ACD82124 can be viewed logically as a phy device if it is config- ured as a reversed mii interface. the reversed mii is intended for a cpu network interface, or expansion port interface. a system cpu can access various registers inside the ACD82124 through a serial cpu management interface. the cpu can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers. the cpu can also access the registers of external transceiver (phy) devices through the cpu management interface. 5 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 5. functional description the mac controller performs transmit, receive, and defer functions, in accordance to ieee 802.3 and 802.3u standard specification. the mac logic also handles frame detection, frame generation, error de- tection, error handling, status indication and flow con- trol functions. frame format the ACD82124 assumes that the received data packet will have the following format: where, preamble is a repetitive pattern of 1010. of any length with nibble alignment. sfd (start frame delimiter) is defined as an oc- tet pattern of 10101011. da (destination address) is a 48-bit field that speci- fies the mac address of the destined dte. if the first bit of da is 1, the ACD82124 will treat the frame as a broadcast/multicast frame and will for- ward the frame to all ports within the source ports vlan except the source port itself or bpdu ad- dress. sa (source address) is a 48-bit field that con- tains the mac address of the source dte that is transmitting the frame to the ACD82124. after a frame is received with no error, the sa is learned as the ports mac address. type/len field is a 2-byte field that specifies the type (dix ethernet frame) or length (ieee 802.3 frame) of the frame. the ACD82124 does not pro- cess this information. data is the encapsulated information within the ethernet packet. the ACD82124 does not pro- cess any of the data information in this field. fcs (frame check sequence) is a 32-bit field of a crc (cyclic redundancy check) value based on the destination address, the source address, the type/length and the data field. the ACD82124 will verify the fcs field for each frame. the pro- cedure of computing fcs is described in section of fcs calculation. start of frame detection when a ports mac is idle, assertion of the rxdv in the mii interface will cause the port to go into the re- ceive state. the mii presents the received data in 4-bit nibbles that are synchronous to the receive clock (25mhz or 2.5mhz). the ACD82124 will convert this data into a serial bit stream, and attempt to detect the occurrence of the sfd (10101011) pattern. all data prior to the detection of sfd are discarded. once sfd is detected, the following frame data are forwarded and stored in the buffer of the switch. frame reception under normal operating conditions, the ACD82124 expects a received frame to have a minimum inter frame gap (ifg). the minimum ifg required by the device is 80 bt (bit time). in the event the ACD82124 receives a packet with ifg less than 80bt, the ACD82124 does not guarantee to be able to receive the frame. the packet will be dropped if the ACD82124 cannot receive the frame. the device will check all received frames for errors such as symbol error, fcs error, short event, runt, long event, jabber etc. frames with any kind of error will not be forwarded to any port. preamble bit processing the preamble bit in the header of each frame will be used to synchronize the mac logic with the incoming bit stream. the minimum length of the preamble is 0 bits and there is no limitation on the maximum length of preamble. after the receive data valid signal rxdv is asserted by the external phy device, the port will wait for the occurrence of the sfd pattern (10101011) and then start a frame receiving process. source address and destination address after a frame is received by the ACD82124, the em- bedded destination address and source address are retrieved. the destination address is passed to the lookup table to find the destination port. the source address is automatically stored into the address lookup table. for applications that use an external arl, the ACD82124 will disable the internal lookup table and pass the da and sa to the external arl for address lookup and learning. preamble sfd da sa type/len data fcs 6 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 a ports mac address register is cleared on power- up, hardware reset, or when the port enters into link fail state. if the sa aging option is enabled (register- 16 bit 4) , the learned sa will be cleared if it does not reappear within five minutes. during the receive process, the lookup engine will attempt to match the destination address with the ad- dresses stored in the address table. if a match is found, a link between the source port and the destination port is established. if an external arl is used, the ACD82124 indicates the presence of a 48-bit da through the sta- tus line of the arl interface. the external arl will use the value of da for address comparison and return a result of the lookup to the ACD82124. frame data frame data are transparent to the ACD82124. the ACD82124 will forward the data to the destination port(s) without interpreting the content of the frame data field. fcs calculation each port of the ACD82124 has crc checking logic to verify if the received frame has a correct fcs value. a wrong fcs value is an indication of a fragmented frame or a frame with frame bit error. the method of calculating the crc value is using the following poly- nomial, g(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 as a divider to divide the bit sequence of the incoming frame, beginning with the first bit of the destination address field, to the end of the data field. the result of the calculation, which is the residue after the polyno- mial division, is the value of the frame check sequence. this value should be equal to the fcs field appended at the end of the frame. if the value does not match the fcs field of the frame, the frame bit error led of the port will be turned on once and the packet will be dropped. frame length during the receiving process, the mac will monitor the length of the received frame. legal ethernet frames should have a length of not less than 64 bytes and no more than 1518 bytes. if the carrier sense signal of a frame is asserted for less than 76 bt, the frame is flagged with short event error. if the length of a frame is less then 64 bytes, the frame is flagged with runt error. in order to support an application where extra byte length is required, an extra-long-frame option is pro- vided. when the extra long frame option is enabled (table 12: cfg7) , only frames longer than 1530 bytes are marked with a long event error. frame length is measured from the first byte of da to the last byte of fcs. frame filtering frames with any kind of error will be filtered. types of error include code error (indicated by assertion of rxer signal), fcs error, alignment error, short event, runt, and long event. any frame heading to its own source port will be fil- tered. if external arl is used, the ACD82124 will filter the frame as directed by the external arl. if the spanning tree support option is enabled, frames containing da equal to any reserved bridge manage- ment group address specified in table 3.5 of ieee 802.1d will not be forwarded to any ports, except the port-23, which may receive bpdu frames . if span- ning tree support is not enabled, frames with da equal to the reserved group address for pbdu will be broad- casted to all ports in the same vlan of the source port. jabber lockup protection if a receiving port is active continuously for more than 50,000 bt, the port is considered to be jabbering. a jabbering port will automatically be partitioned from the switch system in order to prevent it from impairing the performance of the network. the partitioned port will be re-activated as soon as the offending signal dis- continues. excessive collision in the event that there are more than 16 consecutive collision, the ACD82124 will reset the counter to zero and retransmit the packet. this implementation insures there is no packet loss even under channel capture situation. however, ACD82124 has an option to drop the packet on excessive collision. when this option is enabled (table 12: cg11) , the frame will be dropped after 16 consecutive collisions. 7 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 false carrier events if the rxer signal in the mii interface is asserted when the receive data valid (rxdv) signal is not asserted, the port is considered to have a false carrier event. if a port has more than two consecutive false carrier events, the port will automatically be partitioned from the switch system. the partitioned port will be re-acti- vated if it has been idling for 33,000 bt or it has re- ceived a valid frame. frame forwarding if the first bit of the destination address is 0, the frame is handled as a unicast frame. the destination ad- dress is passed to the address resolution logic, which returns a destination port number to identify which port the frame should be forwarded to. if address resolu- tion logic cannot find any match for the destination address, the frame will be treated as a frame with un- known da. the frame will be processed in one of two ways. if the option flood-to-all-port is enabled, the switch will forward the frame to all ports within the same vlan of the source port, except the source port itself. if the option is not enabled, the frame will be forwarded to the dumping port of the source port vlan only. the dumping port is determined by the vlan id of the source port. if the source port belongs to multiple vlans, a frame with unknown da will then be for- warded to multiple dumping ports of the vlans. if the first bit of the destination address is a 1, the frame is handled as a multicast or broadcast frame. the ACD82124 does not differentiate a multicast packet from a broadcast packet except the reserved bridge management group address, as specified in table 3.5 of the ieee 802.1d standard. the destination ports of the broadcast frame is all ports within the same vlan except the source port itself. the order of all broadcast frames with respect to the unicast frames is strictly enforced by the ACD82124. frame t ransmission the ACD82124 transmits all frames in accordance to ieee 802.3 standard. the ACD82124 will send the frames with a guaranteed minimum interframe gap of 96 bt, even if the received frames have an ifg less than the minimum requirement. before the transmit process is started, the mac logic will check if the chan- nel has been silent for more than 64 bt. within the 64 bt silent window, the transmission process will defer on any receiving process. if the channel has been silent for more than 64 bt, the mac will wait an addi- tional 32 bt before starting the transmit process. in the event that the carrier sense signal is asserted by the mii during the wait period, the mac logic will gen- erate a jam signal to cause a forced collision. the mac logic will abort the transmit process if a colli- sion is detected through the assertion of the col signal of the mii. re-transmission of the frame is scheduled in accordance to ieee 802.3s truncated binary expo- nential backoff algorithm. if the transmit process has encountered 16 consecutive collisions, an excessive collision error is reported, and the ACD82124 will try to re-transmit the frame, unless the drop-on-exces- sive-collision option of the port is enabled. it will first reset the number of collisions to zero and then start the transmission after 96 bt of interframe gap. if drop- on-excessive-collision is enabled, the ACD82124 will not try to re-transmit the frame after 16 consecutive collisions. if a collision is detected after 512 bt of the transmission, a late collision error will be reported, but the frame will still be retransmitted after proper backoff time. frame generation during a transmit process, frame data is read out from the memory buffer and is forwarded to the destination ports phy device in nibbles. 7 bytes of preamble sig- nal (10101010) will be generated first followed by the sfd (10101011), and then the frame data and 4 bytes of fcs are sent out last. frame buffer all ports of the ACD82124 work in store-and-forward mode so that all ports can support both 10mbps and 100mbps data speed. the ACD82124 utilizes a global memory buffer pool, which is shared by all ports. the device has a unique architecture that inherits the ad- vantage of both output buffer-based and input buffer- based switches. an output buffer-based switch stores the received data only once into the memory, and hence has a short latency. whereas an input buffer-based switch typically has more efficient flow control. flow control under half duplex mode of operation, when the switch cannot handle the receiving of an incoming frame, a collision is generated by sending a jam pattern to the sending party to force it to back off and re-transmit the frame later. back pressure flow control is applied to a port when its reserved-buffer is full and no more shared buffer is available, or when starvation control is active. 8 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 this process is used to ensure that there are no dropped frames. backpressure flow control can be disabled by setting the corresponding bit of the regis- ter-21. vlan support (register 23 & 24) the ACD82124 can support up to 4 port-based secu- rity vlans. each port of the ACD82124 can be as- signed up to four vlan. on power up, every port is assigned to vlan-0 as default vlan. frames from the source port will only be forwarded to destination ports within the same vlan domain. a broadcast/ multicast frame will be forwarded to all ports within the vlan(s) of the source port. a unicast frame will be forwarded to the destination port only if the destination port is in the same vlan as the source port. other- wise, the frame will be treated as a frame with un- known da. each vlan can be assigned with a dedi- cated dumping port. multiple vlans can also share a dumping port. unicast frames with unknown destina- tion addresses will be forwarded to the dumping port of the source port vlan. security vlan can be disabled by setting the corre- sponding bit in the system configuration register (bit 8 of register 16 ). when security vlan is disabled, each vlan becomes a leaky vlan and is equivalent to a broadcast domain. four dumping ports of four differ- ent virtual vlan can be grouped together to form a fat pipe uplink (for example, if port 0&1, port 2&3, port 3&4, port 5&6 are combined to form 4 full duplex ports with 200mbps per port throughput, these 4 full duplex ports can be grouped to form an 800 mbps uplink port). when multiple dumping ports are grouped as a single pipe, each port has to be assigned to one and only one vlan. a unicast frame with a matched da will be forwarded to any destination, even if the vlan id is different. all unmatched da packets will be forwarded to the designated dumping port of the source port vlan. the broadcast and multicast packets will only be forwarded to the ports in the same vlan of the source port. therefore, a 200 to 800 mbps pipe can be established by carefully grouping the dumping ports, and connects directly with the segmentation switches. dumping port each vlan can be assigned with a dedicated dump- ing port. multiple vlans can share a dumping port. each dumping port can be used for up-link connec- tion or for dte connection. that is, the dumping port can be used to connect the switch with a computer repeater hub, a workgroup switch, a router, or any type of interconnecting device compliant with the ieee 802.3 standard. the ACD82124 will direct the follow- ing frames to the dumping port: frame with unicast destination address that does not match with any ports source address within the vlan of the source port frame with broadcast/multicast destination address* * see spanning tree support if the device is configured to work under flood-to-all- port mode (register 25, bit 8) , frames listed above will be forwarded to all the ports in the vlan(s) of the source port except the source port itself. mode of operation by default, all ports of the ACD82124 work in half du- plex mode. a full-duplex port can be configured by combining two half-duplex ports. in this case, the op- eration mode of the port is determined by the ports phy device through auto-negotiation. the mode of a port can also be assigned by the duplex mode indica- tion/assignment register (register 27) . spanning t ree support the ACD82124 supports spanning tree protocol. when spanning tree support is enabled (register 16 bit 1) , frames from the cpu port (port 23) having a da equal to the reserved bridge management group ad- dress for bpdu will be forwarded to the port specified by the cpu. frames from all other ports with a da equal to the reserved group address for bpdu will be forwarded to the cpu port if the port is in the same vlan of the cpu port. port 23 is designed as the default cpu port. when spanning tree support is dis- abled, all reserved group addresses for bridge man- agement is treated as broadcast address. every port of the ACD82124 can be set to block-and- listen mode through the cpu interface. in this mode, incoming frames with da equal to the reserved group address for bpdu will be forwarded to the cpu port. incoming frames with all other da value will be dropped. outgoing frames with da value equal to the group ad- dress for bpdu will be forwarded to the attached phy device; all other outgoing frames will be filtered. queue management each port of the ACD82124 has its own individual transmission queue. all frames coming into the ACD82124 are stored into the shared memory buffer, 9 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 and are lined up in the transmission queues of the corresponding destination port. the order of all frames, unicast or broadcast, is strictly enforced by the ACD82124. the ACD82124 is designed with a non- blocking switching architecture. it is capable of achiev- ing wire-speed frame forwarding rate and handling maximum traffic load. mii interface the mac of each port of the ACD82124 interfaces with the ports phy device through the standard mii interface. for reception, the received data (rxd) can be sampled by the rising edge (default) or the falling edge of the receive clock (rxclk). assertion of the receive data valid (rxdv) signal will cause the mac to look for start of frame delimiter (sfd). for transmis- sion, the transmit data enable (txen) signal is as- serted when the first preamble nibble is sent on the transmit data (txd) lines. the transmit data are clocked out by the falling edge of the transmit clock (txclk). the ACD82124 supports phy device management through the serial mdio and mdc signal lines. the ACD82124 can continuously poll the status of the phy devices through the serial management interface, with- out cpu intervention. the ACD82124 will also config- ures the phy capability field to ensure proper opera- tion of the link. the ACD82124 also enables the cpu to access any registers in the phy devices through the cpu interface. reversed mii interface ten ports of the ACD82124 can be configured as re- versed mii interface. reversed mii behaves as a phy mii, that the txclk, col, rxd<3:0>, rxclk, rxdv, crs signals (names specified by ieee 802.3u) be- come output signals of the ACD82124, and the txer, txd<3:0>, txen, rxer, signals (names specified by ieee 802.3u) become input signals of the ACD82124. reversed mii interface enables an external mac de- vice to be connected directly with the ACD82124. asram interface the ACD82124 requires the use of asynchronous sram as a memory buffer. each read or write cycle takes up to 20 ns. an asram chip with access speed at 12 ns or faster should be used. the asram inter- face contains a 52-bit data bus, a 17-bit address bus and 4 chip-select signals. cpu interface the ACD82124 does not require a microprocessor for operation. initialization and most configurations can be done with the use of external hardware pins. how- ever, the ACD82124 provides a cpu interface for a microprocessor to access some of its control regis- ters and status registers. the microprocessor can send a read command to retrieve the status of the switch, or send a write command to configure the switch through a serial interface. this interface is a commonly used uart type interface. the cpu interface can also be used to access the registers inside each phy device connected with the ACD82124. arl interface the ACD82124 has a built-in arl that can store up to 2,000 mac addresses. it is actually a subset of the full acd80800 arl ic. for detailed description, please refer to the acd80800 data sheet. the uartid for this built-in arl is shared with the ACD82124 (cfg16 & 17). the ACD82124 also provides an arl interface (table 12: cfg9) for supporting additional mac addresses. through the arl interface, the external arl (acd80800) device can tap the value of da out from the data bus in the asram interface, and execute a lookup process to map the value of da into a port number. the external arl device also learns the sa values embedded in the received frames via the arl interface. the value of sa is used to build up the ad- dress lookup table. mib interface traffic activities on all ports of the ACD82124 can be monitored through the mib interface. through the mib interface, a mib device can view what the source port is receiving, or what the destination port is transmit- ting. therefore, the mib device can maintain a record of traffic statistics for each port to support network management. since all received data are stored into the memory buffer, and all transmitted data are re- trieved from the memory buffer, the data of the activi- ties can also be captured from the data bus of asram interface. the status of each data transaction between the ACD82124 and the asram is displayed by some dedicated status signal pins of the ACD82124. 10 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 led interface the ACD82124 provides a wide variety of led indica- tors for simple system management. the update of the led is completely autonomous and merely requires low speed ttl or cmos devices as led drivers. the status display is designed to be flexible to allow the system designer to choose those indicators appropri- ate for the specification of the equipment. there are two led control signals, ledvld0 and ledvld1, used to indicate the start and end of the led data signal. ledclk signal is a 2.5mhz clock signal. the rising edge of ledclk should be used to latch the led data signal into the led driver circuitry. the led data signals contain lnk, xmt, rcv, col, err, adr, fdx and spd, which represent link status, trans- mit status, receive status, collision indication, frame error indication, port address learning status, full du- plex operation and operational speed status respec- tively. these status signals are sent out sequentially from port 23 to port 0, once every 50ms. for details about the timing diagrams of the led signals, refer to the chapter of timing description life pulse the ACD82124 continuously sends out life pulses to the wchdog pin when it is operating properly. in a catastrophic event, the ACD82124 will not send the life pulse to cause the external watchdog circuitry to time-up and reset the switch system. 11 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 6. interface description mii interface (mii) the ACD82124 communicates with the external 10/ 100 ethernet transceivers through standard mii inter- face. the signals of mii interface are described in table-6.1 : for mii interface, signal pxrxdv, pxrxer and pxrxd0 through pxrxd3 are sampled by the rising edge of pxrxclk. signal pxtxen, and pxtxd0 through pxtxd3 are clocked out by the falling edge of pxtxclk. the detailed timing requirement is described in the chapter of timing description ports 0,1, 2, 3, 4, 5, 6, 7, 22 and 23 can be config- ured as reversed mii ports ( register 28 , the reversed mii enable register). these ports, when configured as normal mii, have the same characteristics as all other mii ports. however, when configured as reversed mii interface, they will behave logically like a phy device, and can interface directly with a mac device. the signal of reversed mii interface are described by table- 6.2 : note: * collision indication for half-duplex mode. not-ready (output) for full duplex mode. for reversed mii interface, signal pxrxdvr, and pxrxd0r through pxrxd3r are clocked out by the falling edge of pxrxclkr. signal pxtxenr, and pxtxd0r through pxtxd3r can be sampled by the falling edge or rising edge of pxtxclkr, depends on the setting of bit 9 of register 16 . the timing behavior is described in the chapter of timing description. phy management interface all control and status registers of the phy devices are accessible through the phy management interface. the interface consists of two signals: mdc and mdio, which are described in table-6.3 . frames transmitted on mdio has the following format ( table-6.4 ): table-6.1: mii interface signals name type description pxcrs i carrier sense pxrxdv i receive data valid pxrxclk i receive clock (25/2.5 mhz) pxrxerr i receive error pxrxd0 i receive data bit 0 pxrxd1 i receive data bit 1 pxrxd2 i receive data bit 2 pxrxd3 i receive data bit 3 pxcol i collision indication pxtxen o transmit data valid pxtxclk i transmit clock (25/2.5 mhz) pxtxd0 o transmit data bit 0 pxtxd1 o transmit data bit 1 pxtxd2 o transmit data bit 2 pxtxd3 o transmit data bit 3 table-6.2: reversed mii interface signals name type description pxcrsr o carrier sense pxrxdvr i transmit data valid pxrxclkr o transmit clock (25/2.5 mhz) pxrxerr i not-ready (input) pxrxd0r i transmit data bit 0 pxrxd1r i transmit data bit 1 pxrxd2r i transmit data bit 2 pxrxd3r i transmit data bit 3 pxcolr o collision indication/ not-ready (output) pxtxenr o receive data valid pxtxclkr o receive clock (25/2.5 mhz) pxtxd0r o receive data bit 0 pxtxd1r o receive data bit 1 pxtxd2r o receive data bit 2 pxtxd3r o receive data bit 3 table-6.3: phy management interface signals name type description mdc o phy management clock (1.25mhz) mdio i/o phy management data table-6.4: mdio format operation pre st op phy-id reg-ad ta data idle write 11 01 01 aaaaa rrrrr 10 dd z read 11 01 10 aaaaa rrrrr z0 dd z 12 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 prior to any transaction, the ACD82124 will output thirty-two bits of 1 as a preamble signal. after the preamble, a 01 signal is used to indicate the start of the frame. for a write operation, the device will send a 01 to signal a write operation. following the 01 write signal will be the 5 bit id address of the phy device and the 5 bit register address. a 10 turn around signal is then followed. after the turn around, the 16 bit of data will be written into the register. after the completion of the write transaction, the line will be left in a high imped- ance state. for a read operation, the ACD82124 will output a 10 to indicate read operation after the start of frame indi- cator. following the 10 read signal will be the 5-bit id address of the phy device and the 5-bit register ad- dress. then, the ACD82124 will cease driving the mdio line, and wait for one bt. during this time, the mdio should be in a high impedance state. the ACD82124 will then synchronize with the next bit of 0 driven by the phy device, and continue on to read 16 bits of data from the phy device. the system designer should set the id of the phy devices as 1 for port-0, 2 for port-1, and 24 for port-23. the detail timing requirement on phy man- agement signals are described in the chapter of tim- ing description. cpu interface the ACD82124 includes a cpu interface to enable an external cpu to access the internal registers of the ACD82124. the protocol used in the cpu is the asyn- chronous serial signal (uart). the baud rate can be from 1200 bps to 76800 bps. the ACD82124 auto- matically detects the baud rate for each command, and returns the result at the same baud rate. the sig- nals in cpu interface are described in table-6.5 . a command sent by cpu comes through the cpudi line. the command consists of 9 octets. command frames transmitted on cpudi have the following for- mat ( table-6.6 ): the byte order of data in all fields follows the big-endian convention, i.e. most significant octet first. the bit or- der is least significant order first. the command octet specifies the type of the operation. bit 2 and bit 3 of the command octet is used to specify the device id of the chip. they are set by bit 16 and bit 17 of the reg- ister 25 at power on strobing. the address octet speci- fies the type of the register. the index octet specifies the id of the register in a register array. for write operation, the data field is a 4-octet value to specify what to write into the register. for read operation, the data field is a 4-octet 0 as padded data. the checksum value is an 8-bit value of exclusive-or of all octets in the frame, starting from the command octet. the ACD82124 will respond to each valid command received by sending a response frame through the cpudo line. the response frames have the following format ( table-6.7 ): the command octet specifies the type of the response. the result octet specifies the result of the execution. the result field in a response frame is defined as: 00 for no error 01 for checksum 10 for address incorrect 11 for mdio waiting time-out for response to a read operation, the data field is a 3- octet value to indicate the content of the register. for response to a write operation, the data field is 24 bits of 0. the checksum value is an 8-bit value of exclu- sive-or of all octets in the response frame, starting from the command octet. table-6.5: cpu interface signals name type description cpudi i cpu data input cpudo o cpu data output cpuirq o cpu interrupt request table-6.7: response format response command result data che cksum write 00100011 8-bit 24-bit 8-bit read 00100001 8-bit 24-bit 8-bit table-6.6: cpu command format operation command register index data che cksum write 0010xx11 8-bit 8-bit 24-bit 8-bit read 0010xx01 8-bit 8-bit 24-bit 8-bit 13 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 cpuirq is used to inform the cpu of some special status has been encountered by the ACD82124, like port partition, fatal system error, etc. by clearing the appropriate bit in the interrupt mask register, one can stop the specific source from generating an interrupt request. reading the interrupt source register retrieves the source of the interrupt and clears the interrupt source register. asram interface all received frames are stored into the shared memory buffer through the asram interface. when the desti- nation port is ready to transmit the frame, data is read from the shared memory buffer through the asram interface. the signals in asram interface are de- scribed in table-6.8 . data is written into the asram or read from the asram in 52-bit wide words. the data is a 48-bit wide value and the control is a 4 bit-wide value. addr specifies the address of the word, and data contains the con- tent of the word. bit 0 ~ 47 of data bus are used to pass 48-bit frame data. bit 48 are used to indicate the start and end of a frame. bit 49 ~ 51 are used to indicate the length of actual data presented on data0 ~ data47. noe and nwe are used to control the timing of read or write operation respectively. ncsx selects the asram chip corresponding to the word address. the timing requirement on asram access is described in the chapter-9 timing description. arl interface arl interface provides a communication path between the ACD82124 and an arl device, which can provide up to 8k of additional address lookup function. as the ACD82124 receives a frame, the destination address and source address of the frame are displayed on the arldo data lines for the external arl device. after the external arl finds the corresponding destination port, it returns the result through the arldix lines to the ACD82124. the timing requirement on arl sig- nals is described in chapter-9 timing description. table-6.9 shows the associated signals in arl inter- face. the data signal is tapped from the data bus of asram interface. since all data of the received frames will be written into the shared memory through the data bus, the bus can be used to monitor occurrences of da and sa values, indicated by the status signal of arlstat. therefore, arld0 through arld51 are the same signals of data0 through data47. arldir1 and arldir0 are used to indicate the di- rection of data on the arldo bus: 00: idle 01: for receiving data 10: for transmitting data 11: header arlsync is used to indicate port 0 is driving the data bus. since the bus is pre-allocated in time division multiplexing manner, the arl device can determine which port is driving the data bus. arlstat are used to indicate the status of the data shown on the first 48 bits of data bus. the 4-bit status is defined as: 0000 - idle 0001 - first word (da) 0010 - second word (sa) 0011 - third through last word 0100 - filter event 0101 - drop event 0110 - jabber 0111 - false carrier/deferred transmission* 1000 - alignment error/single collision* table-6.8: asram interface name type description data0-data51 i/o memory data bus addr0-addr16 o memory address bus noe o output enable, low active nwe o write enable, low active ncs0 - ncs3 o chip select signals, low active. table-6.9: arl interface signals name type description arldo0-rldo51 o arl data output, shared with data 0 - data 51 arldir1-arldir0 o arl data direction indicator 00 for idle 01 for receive 10 for transmit 11 for control arlsync o arl port synchronization arlstat0- arlstat3 o arl data state indicator arlclk o arl clock arldi0 - arldi3 i arl data input arldiv i arl input data valid 14 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 1001 - flow control/multiple collision* 1010 - short event/excessive collision * 1011 - runt/late collision * 1100 - symbol error 1101 - fcs error 1110 - long event 1111 - reserved * note: error type depends on whether the port is re- ceiving or transmitting. arldix is used to receive the lookup result from the external arl. result is returned by external arl de- vice through the arldix lines. returned data is sampled by the rising edge of arlclk. the arl result has the following format: where sid is a 5-bit id of the source port (0 - 23) rslt is a 2-bit result, defined as: 00 - reserved 01 - matched 10 - not matched 11 - forced discard did is a 5-bit id of the destination port (0 - 23) the start of each arl result is indicated by assertion of arldiv signal. led interface the signals in the led interface is described in table- 6.10 : the status of each port is displayed on the led inter- face for every 50ms. ledvld0 and ledvld1 are used to indicate the start and end of the led data. led data is clocked out by the falling edge of ledclk, and should be sampled by the rising edge of ledclk. led data of port 23 are clocked out first, followed by port 22 down to port 0. all led signals are low active. sid rslt did table-11: led interface signals name type description signal group 1 signal group 2 ledvld0 o led signal valid #0 1 0 ledvld1 o led signal valid #1 0 1 nledclk o 2.5 mhz led clock - - nled0 o dual purpose indicator address learning status frame error indicator nled1 o dual purpose indicator full duplex indication collision indication nled2 o dual purpose indicator port speed (1=10mbps,0=100mbps) receiving activity nled3 o dual purpose indicator link status transmit activity 15 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 table-6.11: configuration interface pin name register # bit # setting p7txd0 0 p7txd1 1 p7txd2 2 p7txd3 3 p6txd0 4 p6txd1 5 p6txd2 6 p6txd3 7 ledclk 8 ledvld0 9 ledvld1 10 nled3 11 nled2 12 nled1 13 nled0 14 p5txd0 15 p5txd1 16 p5txd2 17 p5txd3 18 p2txd0 0 p2txd1 1 p2txd2 2 p2txd3 3 p3txd0 4 p3txd1 5 p3txd2 6 p3txd3 7 p4txd0 8 p4txd1 9 p4txd2 10 p4txd3 11 p0txd0 0 p0txd1 1 p0txd2 2 p0txd3 3 p1txd0 4 p1txd1 5 p1txd2 6 p1txd3 7 p23txd0r 0 p23txd1r 1 p23txd2r 2 p23txd3r 3 20, inside the internal arl 0 see appendix- a1 25 26 30 see table- 7.25 see table- 7.30 see table- 7.26 configuration interface there are 20 pins whose pull-up or pull-down state will be used as power-on-strobing configuration data (reg- ister 25, & cfg0 - cfg19) to specify various working modes of the ACD82124. the cfg pins are shared with other functional pins of the ACD82124. the pull- high or pull-low status of the cfg pins are used to indicate specific configuration settings, described in table-6.11 . the register description section will pro- vide more details about the pos configuration regis- ter . other interface ( table-6.12 ) clk50 should come from a clock oscillator, with 0.01% (100 ppm) accuracy. assertion of the nreset pin will cause the ACD82124 to go through the power-up initialization process. all registers are set to their default value after reset. when the ACD82124 is working properly, it will gener- ate pulses from the wchdog pin continuously. it is used as a safeguard, so that in case something unex- pected happens, the external watchdog circuit will re- set the switch system. vdd is 3.3v power supply. vss is power ground. table-6.12: other interface name type description clk50 i 50 mhz clock input nreset i hardware reset wchdog o watch dog life pulse signal vdd - 3.3 v power vss - ground 16 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 7. register description registers in the ACD82124 are used to define the op- eration mode of various function modules of the switch controller and the peripheral devices. default values at power-on are defined by the factory. the manage- ment cpu (optional) can read the content of all regis- ters and modify some of the registers to change the operation mode. table-7.0 lists all the registers inside the switch controller. intsrc register (register 1) the intsrc register indicates the source of the inter- rupt request. before the cpu starts to respond to an interrupt request, it should read this register to find out the interrupt source. this register is automatically cleared after each read. table-7.1 lists all the bits of this register. syserr register (register 2) the syserr register indicates the presence of sys- tem errors. it is automatically cleared after each read. table-7.2 lists all kind of system error. table-7.1: intsrc register bit description default 0 system initialization completed 0 1 system error occurred 0 2 port partition occurred 0 3 arl interrupt 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0 table-7.2: syserr register bit description default 0 bist failure indication 0 1 reserved 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0 8 reserved 0 table-7.0: register list address name type size depth description 0 1 intsrc r 8 bit 1 interrupt source 2 syserr r 24 bit 1 system error 3 par r 24 bit 1 port partition indication 4 pmerr r 24 bit 1 phy management error 5 act r 24 bit 1 port avtivity 6-15 16 syscfg r/w 16 bit 1 system configuration 17 intmsk r/w 8 bit 1 interrupt mask 18 speed r/w 24 bit 1 port speed 19 link r/w 24 bit 1 port link 20 nfwd r/w 24 bit 1 port forward disable 21 nbp r/w 24 bit 1 port back pressure disable 22 nport r/w 24 bit 1 port disable 23 pvid r/w 4 bit 24 port vlan id 24 vpid r/w 5 bit 4 vlan dumping port 25 poscfg r/w 19 bit 1 power-on-strobe configuration 26 npause r/w 24 bit 1 port pause frame disable 27 dplx r/w 24 bit 1 port duplex mode 28 rvsmii r/w 5 bit 1 reversed mii selection 29 npm r/w 24 bit 1 port phy management disable 30 errmsk r/w 8 bit 1 error mask 31 clkadj r/w 4 bit 1 arl clock delay adjustment 32-63 phyreg r/w 16 bit 24 registers in phy device, (reg# - 32) reserved reserved 17 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 p ar register (register 3) the par register indicates the presence of the parti- tioned ports and the port id. a port can be automati- cally partitioned if there is a consecutive false carrier event, an excessive collision or a jabber. this register is automatically cleared after each read. table-7.3 lists all the bits of this register. pmerr register (register 4) the pmerr register indicates the presence of phys that have failed to respond to the phy management command issued through the mdio line. this register is automatically cleared after each read. table-7.4 describes all the bit of this register. table-7.3: par register bit default 0 - port 0 not partitioned. 1 - port 0 partitioned. 0 - port 1 not partitioned. 1 - port 1 partitioned. 0 - port 2 not partitioned. 1 - port 2 partitioned. 0 - port 3 not partitioned. 1 - port 3 partitioned. 0 - port 4 not partitioned. 1 - port 4 partitioned. 0 - port 5 not partitioned. 1 - port 5 partitioned. 0 - port 6 not partitioned. 1 - port 6 partitioned. 0 - port 7 not partitioned. 1 - port 7 partitioned. 0 - port 8 not partitioned. 1 - port 8 partitioned. 0 - port 9 not partitioned. 1 - port 9 partitioned. 0 - port 10 not partitioned. 1 - port 10 partitioned. 0 - port 11 not partitioned. 1 - port 11 partitioned. 0 - port 12 not partitioned. 1 - port 12 partitioned. 0 - port 13 not partitioned. 1 - port 13 partitioned. 0 - port 14 not partitioned. 1 - port 14 partitioned. 0 - port 15 not partitioned. 1 - port 15 partitioned. 0 - port 16 not partitioned. 1 - port 16 partitioned. 0 - port 17 not partitioned. 1 - port 17 partitioned. 0 - port 18 not partitioned. 1 - port 18 partitioned. 0 - port 19 not partitioned. 1 - port 19 partitioned. 0 - port 20 not partitioned. 1 - port 20 partitioned. 0 - port 21 not partitioned. 1 - port 21 partitioned. 0 - port 22 not partitioned. 1 - port 22 partitioned. 0 - port 23 not partitioned. 1 - port 23 partitioned. 0 23 19 20 21 22 15 16 17 18 11 12 13 14 7 8 9 10 3 4 5 6 description 0 1 2 table-7.4: pmerr register bit default 0 - port 0 phy responded 1 - port 0 phy failed to respond 0 - port 1 phy responded 1 - port 1 phy failed to respond 0 - port 2 phy responded 1 - port 2 phy failed to respond 0 - port 3 phy responded 1 - port 3 phy failed to respond 0 - port 4 phy responded 1 - port 4 phy failed to respond 0 - port 5 phy responded 1 - port 5 phy failed to respond 0 - port 6 phy responded 1 - port 6 phy failed to respond 0 - port 7 phy responded 1 - port 7 phy failed to respond 0 - port 8 phy responded 1 - port 8 phy failed to respond 0 - port 9 phy responded 1 - port 9 phy failed to respond 0 - port 10 phy responded 1 - port 10 phy failed to respond 0 - port 11 phy responded 1 - port 11 phy failed to respond 0 - port 12 phy responded 1 - port 12 phy failed to respond 0 - port 13 phy responded 1 - port 13 phy failed to respond 0 - port 14 phy responded 1 - port 14 phy failed to respond 0 - port 15 phy responded 1 - port 15 phy failed to respond 0 - port 16 phy responded 1 - port 16 phy failed to respond 0 - port 17 phy responded 1 - port 17 phy failed to respond 0 - port 18 phy responded 1 - port 18 phy failed to respond 0 - port 19 phy responded 1 - port 19 phy failed to respond 0 - port 20 phy responded 1 - port 20 phy failed to respond 0 - port 21 phy responded 1 - port 21 phy failed to respond 0 - port 22 phy responded 1 - port 22 phy failed to respond 0 - port 23 phy responded 1 - port 23 phy failed to respond 0 1 2 description 3 4 5 6 7 8 9 10 11 12 13 14 0 23 19 20 21 22 15 16 17 18 18 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 act register (register 5) the act register indicates the presence of transmit or receive activities of each port since the register was last read. this register is automatically cleared after each read. table-7.5 describes all the bits of this reg- ister. syscfg register (register 16) the syscfg register specifies certain system con- figurations. the system options are described in the chapter of function description. table-7.16 describes all the bit of this register. table-7.5: act register bit default 0 - port 0 no activity 1 - port 0 has activity 0 - port 1 no activity 1 - port 1 has activity 0 - port 2 no activity 1 - port 2 has activity 0 - port 3 no activity 1 - port 3 has activity 0 - port 4 no activity 1 - port 4 has activity 0 - port 5 no activity 1 - port 5 has activity 0 - port 6 no activity 1 - port 6 has activity 0 - port 7 no activity 1 - port 7 has activity 0 - port 8 no activity 1 - port 8 has activity 0 - port 9 no activity 1 - port 9 has activity 0 - port 10 no activity 1 - port 10 has activity 0 - port 11 no activity 1 - port 11 has activity 0 - port 12 no activity 1 - port 12 has activity 0 - port 13 no activity 1 - port 13 has activity 0 - port 14 no activity 1 - port 14 has activity 0 - port 15 no activity 1 - port 15 has activity 0 - port 16 no activity 1 - port 16 has activity 0 - port 17 no activity 1 - port 17 has activity 0 - port 18 no activity 1 - port 18 has activity 0 - port 19 no activity 1 - port 19 has activity 0 - port 20 no activity 1 - port 20 has activity 0 - port 21 no activity 1 - port 21 has activity 0 - port 22 no activity 1 - port 22 has activity 0 - port 23 no activity 1 - port 23 has activity 0 23 19 20 21 22 15 16 17 18 11 12 13 14 7 8 9 10 3 4 5 6 0 1 2 description table-7.16: syscfg register bit description default 0 0 - bist enabled; 0 1 - bist disabled. 1 0 - spanning tree support disabled; 0 1 - spanning tree support enabled 2 reserved. 0 3 reserved. 0 4 reserved. 0 5 0 - wait for cpu. 0 1 - system ready to start *this bit is used by the cpu when bit-15 of register-25 is set as "0" (for system with control cpu). the system will wait for cpu to set this bit. 6 0 - phy management not completed 0 1 - phy management completed. *this bit is used by the cpu when bit-15 of register-25 is set as "0" (for system with a control cpu). the mac will not start until this bit is set sy the cpu. 7 0 - watchdog function enabled. 0 1 - watchdog function disabled. 8 0 - secure vlan checking rule enforced. 0 1 - leaky vlan checking rule enforced. 9 0 - rising edge of rxclk to latch data. 0 1 - falling edge of rxclk to latch data. *for reversed mii port only. 10 0 - late back-pressure scheme disabled 0 1 - late back-pressure scheme enabled *when enabled, the mac will generate back- pressure only after reading the first bit of da 11 0 - special handling of broadcast frames disabled 0 1 - special handling of broadcast frames enabled *when enabled, all broadcast frames from non-cpu port are forwarded to the cpu port only, and all broadcast frames from the cpu port are forwarded to all other ports. 12 software reset: "1" to start a system reset to innitialize all state machines. 0 13 hardware reset: "1" to stop the life pulse on the watchdog pin, which in turn will trigger the external watchdog circuitry to reset the whole system. 14 reserved 0 15 reserved 0 19 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 intmsk register (register 17) the intmsk register defines the valid interrupt sources allowed to assert interrupt request pin. table-7.17 lists all the bits of this register. speed register (register 18) the speed register specifies or indicates the speed rate of each port. it is read-only, unless the bit-12 of register-25 is set (through pos to disable automatic phy management). at read-only mode, it indicates the speed achieved through phy management. at the write-able mode, the control cpu will be able to assign speed rate for each port. table-7.18 describes all the bit of this register. link register (register 19) the link register specifies or indicates the link status of each port. it is read-only, unless bit-12 of register- 25 is set (through pos, to disable automatic phy man- agement). at read-only mode, it indicates the result achieved by phy management. at write-able mode, table-7.17: intmsk register bit description default 0 enable "system initialization completion" to interrupt 1 1 enable "internal system error" to interrupt 1 2 enable "port partition event" to interrupt 1 3 reserved 1 4 reserved 1 5 reserved 1 6 reserved 1 7 reserved 1 table-7.18: speed register bit default 0 - port 0 at 10 mbps 1 - port 0 at 100 mbps 0 - port 1 at 10 mbps 1 - port 1 at 100 mbps 0 - port 2 at 10 mbps 1 - port 2 at 100 mbps 0 - port 3 at 10 mbps 1 - port 3 at 100 mbps 0 - port 4 at 10 mbps 1 - port 4 at 100 mbps 0 - port 5 at 10 mbps 1 - port 5 at 100 mbps 0 - port 6 at 10 mbps 1 - port 6 at 100 mbps 0 - port 7 at 10 mbps 1 - port 7 at 100 mbps 0 - port 8 at 10 mbps 1 - port 8 at 100 mbps 0 - port 9 at 10 mbps 1 - port 9 at 100 mbps 0 - port 10 at 10 mbps 1 - port 10 at 100 mbps 0 - port 11 at 10 mbps 1 - port 11 at 100 mbps 0 - port 12 at 10 mbps 1 - port 12 at 100 mbps 0 - port 13 at 10 mbps 1 - port 13 at 100 mbps 0 - port 14 at 10 mbps 1 - port 14 at 100 mbps 0 - port 15 at 10 mbps 1 - port 15 at 100 mbps 0 - port 16 at 10 mbps 1 - port 16 at 100 mbps 0 - port 17 at 10 mbps 1 - port 17 at 100 mbps 0 - port 18 at 10 mbps 1 - port 18 at 100 mbps 0 - port 19 at 10 mbps 1 - port 19 at 100 mbps 0 - port 20 at 10 mbps 1 - port 20 at 100 mbps 0 - port 21 at 10 mbps 1 - port 21 at 100 mbps 0 - port 22 at 10 mbps 1 - port 22 at 100 mbps 0 - port 23 at 10 mbps 1 - port 23 at 100 mbps 0 1 2 description 3 4 5 6 7 8 9 10 11 12 13 14 0 23 19 20 21 22 15 16 17 18 20 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 the control cpu can assign link status for each port. table-7.19 describes all the bit of this register. nfwd register (register 20) the nfwd register defines the forwarding mode of each port. under forwarding mode, a port can forward all frames. under block-and-listen mode, a port will not forward regular frames, except bpdu frames. if the spanning tree algorithm discovers redundant links, the control cpu will allow only one link remaining in forwarding mode and force all other links into block- and-listen mode. setting the associated bit in this reg- ister will put the port into block-and-listen mode. table- 7.20 describes all the bit of this register. table-7.20: nfwd register bit default 0 - port 0 in forwarding state 1 - port 0 in block-and-listen state 0 - port 1 in forwarding state 1 - port 1 in block-and-listen state 0 - port 2 in forwarding state 1 - port 2 in block-and-listen state 0 - port 3 in forwarding state 1 - port 3 in block-and-listen state 0 - port 4 in forwarding state 1 - port 4 in block-and-listen state 0 - port 5 in forwarding state 1 - port 5 in block-and-listen state 0 - port 6 in forwarding state 1 - port 6 in block-and-listen state 0 - port 7 in forwarding state 1 - port 7 in block-and-listen state 0 - port 8 in forwarding state 1 - port 8 in block-and-listen state 0 - port 9 in forwarding state 1 - port 9 in block-and-listen state 0 - port 10 in forwarding state 1 - port 10 in block-and-listen state 0 - port 11 in forwarding state 1 - port 11 in block-and-listen state 0 - port 12 in forwarding state 1 - port 12 in block-and-listen state 0 - port 13 in forwarding state 1 - port 13 in block-and-listen state 0 - port 14 in forwarding state 1 - port 14 in block-and-listen state 0 - port 15 in forwarding state 1 - port 15 in block-and-listen state 0 - port 16 in forwarding state 1 - port 16 in block-and-listen state 0 - port 17 in forwarding state 1 - port 17 in block-and-listen state 0 - port 18 in forwarding state 1 - port 18 in block-and-listen state 0 - port 19 in forwarding state 1 - port 19 in block-and-listen state 0 - port 20 in forwarding state 1 - port 20 in block-and-listen state 0 - port 21 in forwarding state 1 - port 21 in block-and-listen state 0 - port 22 in forwarding state 1 - port 22 in block-and-listen state 0 - port 23 in forwarding state 1 - port 23 in block-and-listen state 0 23 19 20 21 22 15 16 17 18 11 12 13 14 7 8 9 10 3 4 5 6 0 1 2 description table-7.19: link register bit default 0 - port 0 link not established 1 - port 0 link established 0 - port 1 link not established 1 - port 1 link established 0 - port 2 link not established 1 - port 2 link established 0 - port 3 link not established 1 - port 3 link established 0 - port 4 link not established 1 - port 4 link established 0 - port 5 link not established 1 - port 5 link established 0 - port 6 link not established 1 - port 6 link established 0 - port 7 link not established 1 - port 7 link established 0 - port 8 link not established 1 - port 8 link established 0 - port 9 link not established 1 - port 9 link established 0 - port 10 link not established 1 - port 10 link established 0 - port 11 link not established 1 - port 11 link established 0 - port 12 link not established 1 - port 12 link established 0 - port 13 link not established 1 - port 13 link established 0 - port 14 link not established 1 - port 14 link established 0 - port 15 link not established 1 - port 15 link established 0 - port 16 link not established 1 - port 16 link established 0 - port 17 link not established 1 - port 17 link established 0 - port 18 link not established 1 - port 18 link established 0 - port 19 link not established 1 - port 19 link established 0 - port 20 link not established 1 - port 20 link established 0 - port 21 link not established 1 - port 21 link established 0 - port 22 link not established 1 - port 22 link established 0 - port 23 link not established 1 - port 23 link established 0 23 19 20 21 22 15 16 17 18 11 12 13 14 7 8 9 10 3 4 5 6 0 1 2 description 21 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 nbp register (register 21) the nbp register defines back-pressure flow control capability for each port. table-7.21 describes all the bit of this register. nport register (register 22) the nport register is used to isolate ports from the network. setting the associated bit in this register will stop a port from receiving or transmitting any frame. table-7.22 describes all the bits of this register. table-7.21: nbp register bit default 0 - port 0 back-pressure scheme enabled 1 - port 0 back-pressure scheme disabled 0 - port 1 back-pressure scheme enabled 1 - port 1 back-pressure scheme disabled 0 - port 2 back-pressure scheme enabled 1 - port 2 back-pressure scheme disabled 0 - port 3 back-pressure scheme enabled 1 - port 3 back-pressure scheme disabled 0 - port 4 back-pressure scheme enabled 1 - port 4 back-pressure scheme disabled 0 - port 5 back-pressure scheme enabled 1 - port 5 back-pressure scheme disabled 0 - port 6 back-pressure scheme enabled 1 - port 6 back-pressure scheme disabled 0 - port 7 back-pressure scheme enabled 1 - port 7 back-pressure scheme disabled 0 - port 8 back-pressure scheme enabled 1 - port 8 back-pressure scheme disabled 0 - port 9 back-pressure scheme enabled 1 - port 9 back-pressure scheme disabled 0 - port 10 back-pressure scheme enabled 1 - port 10 back-pressure scheme disabled 0 - port 11 back-pressure scheme enabled 1 - port 11 back-pressure scheme disabled 0 - port 12 back-pressure scheme enabled 1 - port 12 back-pressure scheme disabled 0 - port 13 back-pressure scheme enabled 1 - port 13 back-pressure scheme disabled 0 - port 14 back-pressure scheme enabled 1 - port 14 back-pressure scheme disabled 0 - port 15 back-pressure scheme enabled 1 - port 15 back-pressure scheme disabled 0 - port 16 back-pressure scheme enabled 1 - port 16 back-pressure scheme disabled 0 - port 17 back-pressure scheme enabled 1 - port 17 back-pressure scheme disabled 0 - port 18 back-pressure scheme enabled 1 - port 18 back-pressure scheme disabled 0 - port 19 back-pressure scheme enabled 1 - port 19 back-pressure scheme disabled 0 - port 20 back-pressure scheme enabled 1 - port 20 back-pressure scheme disabled 0 - port 21 back-pressure scheme enabled 1 - port 21 back-pressure scheme disabled 0 - port 22 back-pressure scheme enabled 1 - port 22 back-pressure scheme disabled 0 - port 23 back-pressure scheme enabled 1 - port 23 back-pressure scheme disabled 0 1 2 description 3 4 5 6 7 8 9 10 11 12 13 14 0 23 19 20 21 22 15 16 17 18 table-7.22: nport register bit default 0 - port 0 enabled 1 - port 0 disabled 0 - port 1 enabled 1 - port 1 disabled 0 - port 2 enabled 1 - port 2 disabled 0 - port 3 enabled 1 - port 3 disabled 0 - port 4 enabled 1 - port 4 disabled 0 - port 5 enabled 1 - port 5 disabled 0 - port 6 enabled 1 - port 6 disabled 0 - port 7 enabled 1 - port 7 disabled 0 - port 8 enabled 1 - port 8 disabled 0 - port 9 enabled 1 - port 9 disabled 0 - port 10 enabled 1 - port 10 disabled 0 - port 11 enabled 1 - port 11 disabled 0 - port 12 enabled 1 - port 12 disabled 0 - port 13 enabled 1 - port 13 disabled 0 - port 14 enabled 1 - port 14 disabled 0 - port 15 enabled 1 - port 15 disabled 0 - port 16 enabled 1 - port 16 disabled 0 - port 17 enabled 1 - port 17 disabled 0 - port 18 enabled 1 - port 18 disabled 0 - port 19 enabled 1 - port 19 disabled 0 - port 20 enabled 1 - port 20 disabled 0 - port 21 enabled 1 - port 21 disabled 0 - port 22 enabled 1 - port 22 disabled 0 - port 23 enabled 1 - port 23 disabled 0 23 19 20 21 22 15 16 17 18 11 12 13 14 7 8 9 10 3 4 5 6 0 1 2 description 22 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 pvid registers (register 23) the pvid registers assign vlan ids for each port. there are 24 pvid registers, one for each port. a pvid consists of 4 bits, each corresponding to one of the 4 vlans. a port can belong to more than one vlan at the same time. table-7.23 describes the bits of one of the registers. vpid registers (register 24) the vpid registers specify the dumping port for each vlan. there are 4 vpid 5-bit registers, one for each vlan. a valid vpid are 0 through 23 (other values are reserved and should not used). table-7.24 de- scribes the bits one of the registers. table-7.23: pvid re g isters (24 registers) bit description default 0 0 - port not in vlan-i. 1 1 - port in vlan-i. 1 0 - port not in vlan-ii. 0 1 - port in vlan-ii. 2 0 - port not in vlan-iii. 0 1 - port in vlan-iii. 3 0 - port not in vlan-iv. 0 1 - port in vlan-iv. table-7.24: vpid re g isters (4 registers) bit description default 4:0 dumping port id for vlan-1 "00000" 4:0 dumping port id for vlan-2 "11111" 4:0 dumping port id for vlan-3 dumping port 4:0 dumping port id for vlan-4 not defined 23 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 table-7.25: poscfg register bit description default 3:0 8 timing adjustment levels for sram read data latching: 0000 0000 - no delay 0001 - level 1 delay 0011 - level 2 delay 0101 - level 3 delay 0111 - level 4 delay 1001 - level 5 delay 1011 - level 6 delay 1101 - level 7 delay 1111 - level 8 delay 4 0 - absolute address mode: 1 row of 512k words, ncs2=a ddr17, ncs3=addr18 0 1 - chip-select address mode: 4 rows of 128k words, ncs[3:0] to select 4 rows of memory 6:5 sram size selection: 000 00 - 64k words 01 - 128k words 10 - 256k words 11 - 512k words 7 0 - long event defined as frame longer than 1518 byte. 0 1 - long event defined as frame longer than 1530 byte. 8 0 - frames with unknown da forwarded to the dumping port. 0 1 - frames with unknown da forwarded to all ports. 9 0 - internal arl selected (2k mac address entry). 0 1 - external arl selected (11k mac address entry). 10 0 - phy ids start from 1, range from 1 to 24. 0 1 - phy ids start from 4, range from 4 to 27. 11 0 - re-transmit after excessive collision. 0 1 - drop after excessive collision. 12 0 - automatic phy management enabled 0 1 - automatic phy management disabled: the control cpu need to update the speed, link, dplx and npause registers 13 0 - rising edge of rxclk triggering for regular mii ports 0 0 - falling edge of rxclk triggering for regular mii ports 14 0 - sysem errors will trigger software reset 0 1 - sysem errors will trigger hardware reset 15 0 - system start itself without a control cpu 0 1 - system start after system-ready bit in register-16 is set by the control cpu 17:16 2-bit device id for uart communication. the device responses only to uart commands with matching id 00 18 0 - rising edge of arlclk to latch arldi. 0 1 - falling edge of arlclk to latch arldi. poscfg register (register 25) the poscfg register specifies a certain configura- tion setting for the switch system. the default values of this register can be changed through pull-up/pull-down of specific pins, as described in the configuration interface section of the interface description chap- ter. table-7.25 describes all the bit of this register. fden register ( register 26 ) fden register is used to specify if an even numbered port has been connected as a full duplex port. the default value of fdcfg is determined by pull-high or pull-low status of the hardware pins shown in table- 26 . dplx register (register 27) the dplx register specifies or indicates the half/full- duplex mode of each of the 12 even-numbered ports ( port 0, 2, 4, .. 20 and 22 ). it is read-only, unless bit- 12 of register-25 is set (through pos, to disable auto- matic phy management). at read-only mode, it indi- cates the result achieved by the phy management. at write-able mode, the control cpu can assign a half- duplex or full-duplex mode for each of the 12 even- 24 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 table-7.26: fden register bit default 0 - port 0 & 1 each in half-duplex mode 1 - port 0 & 1 paired into one full-duplex-capable port 0 - port 2 & 3 each in half-duplex mode 1 - port 2 & 3 paired into one full-duplex-capable port 0 - port 4 & 5 each in half-duplex mode 1 - port 4 & 5 paired into one full-duplex-capable port 0 - port 6 & 7 each in half-duplex mode 1 - port 6 & 7 paired into one full-duplex-capable port 0 - port 8 & 9 each in half-duplex mode 1 - port 8 & 9 paired into one full-duplex-capable port 0 - port 10 & 11 each in half-duplex mode 1 - port 10 & 11 paired into one full-duplex-capable port 0 - port 12 & 13 each in half-duplex mode 1 - port 12 & 13 paired into one full-duplex-capable port 0 - port 14 & 15 each in half-duplex mode 1 - port 14 & 15 paired into one full-duplex-capable port 0 - port 16 & 17 each in half-duplex mode 1 - port 16 & 17 paired into one full-duplex-capable port 0 - port 18 & 19 each in half-duplex mode 1 - port 18 & 19 paired into one full-duplex-capable port 0 - port 20 & 21 each in half-duplex mode 1 - port 20 & 21 paired into one full-duplex-capable port 0 - port 22 & 23 each in half-duplex mode 1 - port 22 & 23 paired into one full-duplex-capable port 8 9 10 11 0 description 0 1 2 3 4 5 6 7 table-7.27: dplx register bit default 0 - port 0 & 1 run as two independant half-duplex ports 1 - port 0 & 1 pair run as one full-duplex port 0 - port 2 & 3 run as two independant half-duplex ports 1 - port 2 & 3 pair run as one full-duplex port 0 - port 4 & 5 run as two independant half-duplex ports 1 - port 4 & 5 pair run as one full-duplex port 0 - port 6 & 7 run as two independant half-duplex ports 1 - port 6 & 7 pair run as one full-duplex port 0 - port 8 & 9 run as two independant half-duplex ports 1 - port 8 & 9 pair run as one full-duplex port 0 - port 10 & 11 run as two independant half-duplex ports 1 - port 10 & 11 pair run as one full-duplex port 0 - port 12 & 13 run as two independant half-duplex ports 1 - port 12 & 13 pair run as one full-duplex port 0 - port 14 & 15 run as two independant half-duplex ports 1 - port 14 & 15 pair run as one full-duplex port 0 - port 16 & 17 run as two independant half-duplex ports 1 - port 16 & 17 pair run as one full-duplex port 0 - port 18 & 19 run as two independant half-duplex ports 1 - port 18 & 19 pair run as one full-duplex port 0 - port 20 & 21 run as two independant half-duplex ports 1 - port 20 & 21 pair run as one full-duplex port 0 - port 22 & 23 run as two independant half-duplex ports 1 - port 22 & 23 pair run as one full-duplex port 8 9 10 11 0 description 0 1 2 3 4 5 6 7 25 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 number ports. table-7.27 describes all the bits of this register. rvsmii register (register 28) the rvsmii register defines the reversed mii mode for each port. table-7.28 describes all the bits of this register. npm register (register 29) the npm register indicates the automatic phy man- agement capability of each port. if a bit is set in this register, the corresponding speed, link, dplx, and npause status registers of a port will remain un- changed. table-7.29 describes all the bits of this reg- ister. table-7.28: rvsmii register bit description default 0 0 - port 0 under normal mii mode 0 1 - port 0 under reversed mii mode 1 0 - port 1under normal mii mode 0 1 - port 1 under reversed mii mode 2 0 - port 2 under normal mii mode 0 1 - port 2under reversed mii mode 3 0 - port 3 under normal mii mode 0 1 - port 3 under reversed mii mode 4 0 - port 4 under normal mii mode 0 1 - port 4 under reversed mii mode 5 1 - port 5 under normal mii mode 0 2 - port 5 under reversed mii mode 6 1 - port 6 under normal mii mode 0 2 - port 6 under reversed mii mode 7 1 - port 7 under normal mii mode 0 2 - port 7 under reversed mii mode 8 1 - port 22 under normal mii mode 0 2 - port 22 under reversed mii mode 9 1 - port 23 under normal mii mode 0 2 - port 23 under reversed mii mode table-7.29: npm register bit default 0 - port 0 status update enabled 1 - port 0 status update disabled 0 - port 1 status update enabled 1 - port 1 status update disabled 0 - port 2 status update enabled 1 - port 2 status update disabled 0 - port 3 status update enabled 1 - port 3 status update disabled 0 - port 4 status update enabled 1 - port 4 status update disabled 0 - port 5 status update enabled 1 - port 5 status update disabled 0 - port 6 status update enabled 1 - port 6 status update disabled 0 - port 7 status update enabled 1 - port 7 status update disabled 0 - port 8 status update enabled 1 - port 8 status update disabled 0 - port 9 status update enabled 1 - port 9 status update disabled 0 - port 10 status update enabled 1 - port 10 status update disabled 0 - port 11 status update enabled 1 - port 11 status update disabled 0 - port 12 status update enabled 1 - port 12 status update disabled 0 - port 13 status update enabled 1 - port 13 status update disabled 0 - port 14 status update enabled 1 - port 14 status update disabled 0 - port 15 status update enabled 1 - port 15 status update disabled 0 - port 16 status update enabled 1 - port 16 status update disabled 0 - port 17 status update enabled 1 - port 17 status update disabled 0 - port 18 status update enabled 1 - port 18 status update disabled 0 - port 19 status update enabled 1 - port 19 status update disabled 0 - port 20 status update enabled 1 - port 20 status update disabled 0 - port 21 status update enabled 1 - port 21 status update disabled 0 - port 22 status update enabled 1 - port 22 status update disabled 0 - port 23 status update enabled 1 - port 23 status update disabled 0 1 2 description 3 4 5 6 7 8 9 10 11 12 13 14 0 23 19 20 21 22 15 16 17 18 26 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 table-7.31: clkadj register bit description default 0 0 - arlclk not inverted 0 1 - arlclk inverted 3:1 arlclk delay levels: 000 000 - level 0 delay 001 - level 1 delay 010 - level 2 delay 011 - level 3 delay 100 - level 4 delay 101 - level 5 delay 110 - level 6 delay 111 - level 7 delay table-7.30: errmsk register bit description setting 0 reserved 1 reserved 2 reserved 3 reserved 4 reserved 5 reserved 6 reserved 7 reserved 0 all "1", unless otherwise advised, to ensure proper operation. errmsk register (register 30) the errmsk register defines certain errors as sys- tem errors . it is reserved for factory use only. table- 7.30 lists all the error masks specified by this register. clkadj register (register 31) the clkadj register defines the delay time of the arlclk relative to the transition edge of the data sig- nals. the arlclk provides reference timing for sup- porting chips, such as the acd80800 and the acd80900, which need to snoop the data bus for cer- tain activities. table-7.31 describes all the bits of this register. phyreg registers (register 32-63) the phyreg refers to the registers residing on the phy devices. there are 24 sets of these registers. each port has its own corresponding set of register 32-63. the ACD82124 merely provides an access path for the control cpu to access the registers on the phys. for detailed information about these registers, please refer to the phy data sheet. since the native registers id 0 through 31 on the phys have been used by the internal registers of the ACD82124, they need to be re-mapped into 32 through 63 by adding 32 to each original register id. an index is used by the ACD82124 to specify the phy id. for example, register-32 with index-4 would refer to the control register (register-0) in the phy-4. 27 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 8. pin descriptions a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pin diagram bottom view 28 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 pin list by location: part 1 pin signal name i/o type pin signal name i/o type pin signal name i/o type pin signal name i/o type a01 p 23r x d0r i c13 p 20r x cl k i e 25 p 16t x d1 o k 01 dat a40 i/ o a02 vdd c14 p 20t x d0 o e 26 vdd k 02 dat a39 i/ o a03 p 23t x d2r o c15 p 19r x d3 i e 27 p 15r x cl k i k 03 addr 2 o a04 p 22r x d3r i c16 p 19r x cl k i e 28 p 15t x d3 o k 04 ncs 3 o a05 p 22r x e r r i c17 p 19t x d0 o e 29 p 14r x d0 i k 05 vdd a06 p 22t x d1r o c18 p 19col i e 30 p 14t x e n o k 06 vs s a07 p 22t x d3r o c19 p 18r x d1 i f 01 dat a48 i/ ok25 vss a08 p 21r x d0 i c20 p 18r x e r i f 02 dat a47 i/ ok26 vdd a09 p 21t x cl k i c21 p 18t x d1 o f 03 ar l di3 i k 27 p 13r x d0 i a10 p 21t x d0 o c22 p 17r x d2 i f 04 ar l cl k o k 28 p 13t x cl k i a11 p 20r x d3 i c23 p 17r x cl k i f 05 ar l s y nc o k 29 p 13t x d1 o a12 p 20r x d0 i c24 p 17t x d2 o f 06 vs s k 30 p 13t x d2 o a13 p 20t x cl k i c25 p 17cr s i f 07 p 23r x e r r i l 01 dat a38 i/ o a14 p 20t x d2 o c26 p 16r x d0 i f 08 vs s l 02 dat a37 i/ o a15 p 19r x d1 i c27 p 16t x d3 o f 09 p 22r x d1r i l 03 addr 3 o a16 p 19r x d0 i c28 p 15r x d2 i f 10 vs s l 04 ncs 2 o a17 p 19t x cl k i c29 p 15t x d0 o f 11 p 22cr s r i/ ol05 vdd a18 p 19t x d2 o c30 p 15col i f 12 vs s l 06 vs s a19 vs s d01 s t at 3 o f 13 p 21col i l 25 p 13r x d2 i a20 p 18r x dv i d02 dat a51 i/ o f 14 vs s l 26 p 13r x d1 i a21 p 18t x e n o d03 ar l di0 i f 15 p 20t x d3 o l 27 p 13t x e n o a22 p 18cr s i d04 p 23r x d3r i f 16 vs s l 28 p 13t x d3 o a23 p 17r x d1 i d05 p 23r x cl k r i/ o f 17 vs s l 29 p 13col i a24 p 17r x e r i d06 p 23t x d0r o f 18 p 18r x d2 i l 30 p 12r x d1 i a25 p 17t x d3 o d07 p 23col r i/ o f 19 vs s m01 dat a36 i/ o a26 p 16r x d2 i d08 p 22r x dvr i f 20 p 18t x d3 o m02 dat a35 i/ o a27 p 16r x e r i d09 p 22t x d0r o f 21 vs s m03 ncs 0 o a28 p 16t x d0 o d10 p 21r x d2 i f 22 p 17t x d0 o m04 addr 16 o a29 p 16cr s i d11 p 21r x e r i f 23 vs s m05 vdd a30 p 15r x d0 i d12 p 21t x d3 o f 24 p 16t x cl k i m06 vs s b 01 s t at 0 o d13 p 20r x dv i f 25 vs s m25 vs s b 02 p 23r x d1r i d14 p 20t x e n o f 26 p 15r x dv i m26 vdd b 03 p 23t x cl k r i/ o d15 p 20cr s i f 27 p 15t x d2 o m27 p 13cr s i b 04 p 23t x d3r o d16 p 19r x dv i f 28 p 14r x d2 i m28 p 12r x d0 i b 05 p 22r x d2r i d17 p 19t x d1 o f 29 p 14t x d0 o m29 p 12r x dv i b 06 p 22t x cl k r i/ o d18 p 19cr s i f 30 p 14t x d3 o m30 p 12r x cl k i b 07 p 22t x d2r o d19 p 18r x d0 i g01 dat a46 i/ o n01 dat a34 i/ o b 08 p 21r x d1 i d20 p 18t x cl k i g02 dat a45 i/ o n02 dat a33 i/ o b 09 p 21r x dv i d21 p 18col i g03 ar l dir 0 o n03 vdd b 10 p 21t x e n o d22 p 17r x d0 i g04 ar l dir 1 o n04 addr 15 o b 11 p 21t x d2 o d23 p 17t x d1 o g05 vdd n05 vdd b 12 p 20r x d1 i d24 p 16r x d3 i g06 vs s n06 vs s b 13 p 20r x e r i d25 p 16r x cl k i g25 p 15r x e r i n25 p 12r x d3 i b 14 p 20t x d1 o d26 p 16t x d2 o g26 p 15t x d1 o n26 p 12r x d2 i b 15 p 19r x d2 i d27 p 15r x d3 i g27 p 14r x d3 i n27 p 12r x e r i b 16 p 19r x e r i d28 p 15t x cl k i g28 p 14t x cl k i n28 p 12t x cl k i b 17 p 19t x e n o d29 p 15cr s i g29 p 14col i n29 p 12t x e n o b 18 p 19t x d3 o d30 p 14r x d1 i g30 p 14cr s i n30 p 12t x d0 o b 19 vdd e 01 dat a50 i/ o h01 dat a44 i/ o p 01 dat a32 i/ o b 20 p 18r x cl k i e 02 dat a49 i/ o h02 dat a43 i/ o p 02 dat a31 i/ o b 21 p 18t x d0 o e 03 ar l di 2 i h03 addr 0 o p 03 nw e o b22 p17rxd3 i e04 arldi1 i h04 arldiv i p04 vs s b 23 p 17r x dv i e 05 vdd h05 vdd p 05 vdd b 24 p 17t x cl k i e 06 p 23r x dvr i h06 vs s p 06 vs s b 25 p 17col i e 07 p 23t x e nr o h25 vs s p 25 vs s b 26 p 16r x d1 i e 08 vdd h26 vdd p 26 vdd b 27 p 16t x e n o e 09 p 22r x d0r i h27 p 14r x e r i p 27 p 12t x d1 o b 28 p 16col i e 10 vdd h28 p 14t x d1 o p 28 p 12t x d2 o b 29 p 15r x d1 i e 11 p 21r x d3 i h29 p 13r x dv i p 29 p 12t x d3 o b 30 p 15t x e n o e 12 vdd h30 p 13r x cl k i p 30 p 12col i c01 s t at 1 o e 13 p 21cr s i j01 dat a42 i/ o r 01 dat a30 i/ o c02 stat2 o e14 vdd j02 data41 i/ o r 02 dat a29 i/ o c03 p 23r x d2r i e 15 p 20col i j03 addr 1 o r 03 addr 4 o c04 v s s e 16 v dd j 04 n cs 1 o r 04 n oe i / o c05 p 23t x d1r o e 17 vdd j05 vdd r 05 vdd c06 p 23cr s r i/ o e 18 p 18r x d3 i j06 vs s r 06 vs s c07 p 22r x cl k r i/ o e 19 vdd j25 p 14r x dv i r 25 p 12cr s i c08 p 22t x e nr o e 20 p 18t x d2 o j26 p 14r x cl k i r 26 p 11r x d3 i c09 p 22col r i/ o e 21 vdd j27 p 14t x d2 o r 27 p 11r x d2 i c10 p 21r x cl k i e 22 p 17t x e n o j28 p 13r x d3 i r 28 p 11r x d1 i c11 p 21t x d1 o e 23 vdd j29 p 13r x e r i r 29 p 11r x d0 i c12 p 20r x d2 i e 24 p 16r x dv i j30 p 13t x d0 o r 30 p 11r x dv i 29 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 pin list by location: part 2 pin signal name i/o type pin signal name i/o type pin signal name i/o type pin signal name i/o type t 01 dat a28 i/ o ab 01 dat a16 i/ o af 07 p 0t x e nr o ah19 p 4r x d0r i t 02 dat a27 i/ o ab 02 dat a15 i/ o af 08 vdd ah20 p 5t x d3r i / o t 03 addr 5 o ab 03 vdd af 09 p 1t x d3r i/ oah21 p5txclkr i/ o t04addr14oab04led3i/ o af 10 vdd ah22 p 5r x d3r i t 05 vdd ab 05 vdd af 11 p 1r x d3r i ah23 p 6t x d1r i/ o t 06 vs s ab 06 vs s af 12 vdd ah24 p 6t x cl k r i/ o t 25 vs s ab 25 vs s af 13 p 2r x d1r i ah25 p 6r x d2r i t 26 vdd ab 26 vdd af 14 vdd ah26 p 7t x d3r i/ o t 27 p 11r x e r i ab 27 p 9t x cl k i af 15 vdd ah27 vdd t 28 p 11t x cl k i ab 28 p 9r x cl k i af 16 p 3r x d3r i ah28 p 7r x d0r i t 29 p 11t x e n o ab 29 p 9r x dv i af 17 vdd ah29 p 7r x d3r i t 30 p 11r x cl k i ab 30 p 9r x d0 i af 18 p 4r x d2r i ah30 p 8t x d2 o u01 dat a26 i/ o ac01 dat a14 i/ o af 19 vdd aj01 dat a2 i/ o u02 dat a25 i/ o ac02 dat a13 i/ o af 20 p 5r x d1r i aj02 dat a1 i/ o u03 addr 6 o ac03 l e d2 i / oaf21 vdd aj03 vss u04addr13oac04led0i/ oaf22p6rxclkri/ o aj04 p 0t x d3r i/ o u05 vdd ac05 vdd af 23 vdd aj05 p 0r x e r r i u06 vs s ac06 vs s af 24 p 7t x d1r i/ o aj06 p 0r x d1r i u25 vs s ac25 vs s af 25 p 7r x e r r i aj07 p 1t x d2r i/ o u26 vdd ac26 vdd af 26 vdd aj08 p 1t x e nr o u27 p 11t x d3 o ac27 p 9t x d3 o af 27 p 8col i aj09 p 1r x dvr i u28 p 11t x d2 o ac28 p 9t x d0 o af 28 p 8r x cl k i aj10 p 2col r i/ o u29 p 11t x d1 o ac29 p 9t x e n o af 29 p 8r x dv i aj11 p 2t x d0r i/ o u30 p 11t x d0 o ac30 p 9r x e r i af 30 p 8r x d0 i aj12 p 2r x cl k r i/ o v01 dat a24 i/ o ad01 dat a12 i/ o ag01 dat a6 i/ oaj13 p3crsr i/ o v02 dat a23 i/ o ad02 dat a11 i/ o ag02 dat a5 i/ o aj14 p 3t x d1r i/ o v03 addr 7 o ad03 l e d1 i / o ag03 cpuirq o aj15 p3t xenr o v04 addr 12 o ad04 l e dvl d0 i / o ag04 mdc o aj16 p 3r x d0r i v05 vdd ad05 vdd ag05 nre s e t i aj17 p 4t xd3r i/ o v06 vs s ad06 vs s ag06 p 0t x d0r i/ oaj18 p4txenr o v25 p 10r x d0 i ad25 p 8t x d0 o ag07 p 0r x dvr i aj19 p 4r x dvr i v26 p 10r x d1 i ad26 p 8r x e r i ag08 p 1cr s r i/ oaj20 p5colr i/ o v27 p 10r x d2 i ad27 p 8r x d1 i ag09 p 1t x cl k r i/ o aj21 p 5t x d1r i/ o v28 p 10r x d3 i ad28 p 9col i ag10 p 1r x d1r i aj22 p 5r x e r r i v29 p 11cr s i ad29 p 9t x d2 o ag11 p 2t x d2r i/ oaj23 p5rxdvr i v30 p 11col i ad30 p 9t x d1 o ag12 p 2t x cl k r i/ oaj24 p6colr i/ o w 01 dat a22 i/ o ae 01 dat a10 i/ o ag13 p 2r x d2r i aj25 p 6t x d0r i/ o w 02 dat a21 i/ o ae 02 dat a9 i/ o ag14 p 3t x d3r i/ o aj26 p 6r x d0r i w 03 addr 8 o ae 03 l e dvl d1 i / o ag15 p 3r x e r r i aj27 p 7cr s r i/ o w04 addr11 o ae04 ledclk i/ o ag16 p 3r x d2r i aj28 p 7t x d0r i/ o w 05 vdd ae 05 vs s i ag17 p 4t x d1r i/ oaj29 p7rxdvr i w06 vs s ae 06 vs s ag18 p 4r x e r r i aj30 p 7r x d2r i w25 vs s ae07 p0t xd2r i/ oag19 p5crsr i/ o ak 01 dat a0 i/ o w26 vdd ae 08 vs s ag20 p 5t x e nr o ak 02 cl k 50 i w27 p 10t x cl k i ae 09 p 1col r i/ o ag21 p 5r x d0r i ak 03 p 0col r i/ o w28 p 10r x e r i ae 10 vs s ag22 p 6t x d2r i/ o ak 04 p 0t x d1r i/ o w29 p 10r x cl k i ae 11 p 1r x d2r i ag23 p 6r x e r r i ak 05 p 0r x cl k r i/ o w30 p 10r x dv i ae 12 vs s ag24 p 6r x d3r i ak 06 p 0r x d2r i y 01 dat a20 i/ o ae 13 p 2r x d0r i ag25 p 7t x d2r i/ o ak 07 p 1t x d1r i/ o y 02 dat a19 i/ oae14 vss ag26p7txclkri/ oak08 p1rxerr i y 03 addr 9 o ae 15 vs s ag27 p 7r x d1r i ak 09 p 1r x d0r i y 04 addr 10 o ae 16 p 4cr s r i/ o ag28 p 8cr s i ak 10 p 2t x d3r i/ o y 05 vdd ae 17 vs s ag29 p 8t x d1 o ak 11 p 2t x e nr o y06 vss ae18 p4rxd3r i ag30 p8t xen o ak12 p2rxdvr i y 25 p 9r x d2 i ae 19 vs s ah01 dat a4 i/ oak13 p3colr i/ o y 26 p 9r x d3 i ae 20 p 5r x d2r i ah02 dat a3 i/ o ak 14 p 3t x d0r i/ o y 27 p 10t x d2 o ae 21 vs s ah03 mdio i/ oak15 p3rxclkr i/ o y 28 p 10t x d1 o ae 22 p 6r x dvr i ah04 wchdog o ak 16 p 3r x dvr i y 29 p 10t x d0 o ae 23 vs s ah05 p 0t x cl k r i/ oak17 p4colr i/ o y 30 p 10t x e n o ae 24 vs s ah06 p 0r x d0r i ak 18 p 4t x d0r i/ o aa01 dat a18 i/ o ae 25 vs s ah07 p 0r x d3r i ak 19 p 4r x cl k r i/ o aa02 dat a17 i/ o ae 26 p 8t x d3 o ah08 p 1t x d0r i/ o ak 20 p 4r x d1r i aa03 vdd ae 27 p 8t x cl k i ah09 p 1r x cl k r i/ o ak 21 p 5t x d2r i/ o aa04 vs s ae 28 p 8r x d2 i ah10 p 2cr s r i/ o ak 22 p 5t x d0r i/ o aa05 vdd ae 29 p 8r x d3 i ah11 p 2t x d1r i/ oak23 p5rxclkr i/ o aa06 vs s ae 30 p 9cr s i ah12 p 2r x e r r i ak 24 p 6cr s r i/ o aa25 vs s af 01 dat a8 i/ o ah13 p 2r x d3r i ak 25 p 6t x d3r i/ o aa26 vdd af 02 dat a7 i/ o ah14 p 3t x d2r i/ oak26 p6txenr o aa27 p 9r x d1 i af 03 cp udi i ah15 p 3t x cl k r i/ o ak 27 p 6r x d1r i aa28 p 10cr s i af 04 cp udo i/ o ah16 p 3r x d1r i ak 28 p 7col r i/ o aa29 p 10col i af 05 vdd ah17 p 4t x d2r i/ oak29 p7txenr o aa30 p 10t x d3 o af 06 p 0cr s r i/ oah18p4txclkri/ oak30 p7rxclkr i/ o 30 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 pin list by name (with voltage rating): part 1 signal name pin i/o type signal name pin i/o type signal name pin i/o type signal name pin i/o type addr 0 h03 3.3v o dat a41 j02 3.3v i/ o p 03cr s r aj13 3.3v i/ o p 07t x d3r ah26 3.3v i/ o addr 01 j03 3.3v o dat a43 h02 3.3v i / o p 03r x d0r aj16 3.3v i p 08col af 27 3.3v i addr 02 k 03 3.3v o dat a44 h01 3.3v i / o p 03r x d1r ah16 3.3v i p 08cr s ag28 3.3v i addr 03 l 03 3.3v o dat a45 g02 3.3v i / o p 03r x d2r ag16 3.3v i p 08r x cl k af 28 3.3v i addr 04 r 03 3.3v o dat a46 g01 3.3v i / o p 03r x d3r af 16 3.3v i p 08r x d0 af 30 3.3v i addr 05 t 03 3.3v o dat a47 f 02 3.3v i / o p 03r x dvr ak 16 3.3v i p 08r x d1 ad27 3.3v i addr 06 u03 3.3v o dat a48 f 01 3.3v i / o p 03r x e r r ag15 3.3v i p 08r x d2 ae 28 3.3v i addr 07 v03 3.3v o dat a49 e 02 3.3v i / op03txclkrah153.3vi/ o p 08r x d3 ae 29 3.3v i addr 08 w 03 3.3v o dat a50 e 01 3.3v i / o p 03t x d0r ak 14 3.3v i/ o p 08r x dv af 29 3.3v i addr 09 y 03 3.3v o dat a51 d02 3.3v i / o p 03t x d1r aj14 3.3v i/ o p 08r x e r ad26 3.3v i addr 10 y 04 3.3v o l e d0 ac04 3.3v i/ o p 03t x d2r ah14 3.3v i/ o p 08t x cl k ae 27 3.3v i addr 11 w04 3.3v o l e d1 ad03 3.3v i/ o p 03t x d3r ag14 3.3v i/ o p 08t x d0 ad25 3.3v o addr 12 v04 3.3v o l e d2 ac03 3.3v i/ o p 03t x e nr aj15 3.3v o p 08t x d1 ag29 3.3v o addr 13 u04 3.3v o l e d3 ab 04 3.3v i/ o p 04col r ak 17 3.3v i/ o p 08t x d2 ah30 3.3v o addr 14 t 04 3.3v o l e dcl k ae 04 3.3v i/ o p 04cr s r ae 16 3.3v i/ o p 08t x d3 ae 26 3.3v o addr 15 n04 3.3v o l e dvl d0 ad04 3.3v i / op04rxclkrak193.3vi/ o p 08t x e n ag30 3.3v o addr 16 m04 3.3v o l e dvl d1 ae 03 3.3v i / o p 04r x d0r ah19 3.3v i p 09col ad28 3.3v i ar l cl k f 04 3.3v o mdc ag04 3.3v o p 04r x d1r ak 20 3.3v i p 09cr s ae 30 3.3v i ar l di0 d03 3.3v i mdio ah03 3.3v i/ o p 04r x d2r af 18 3.3v i p 09r x cl k ab 28 3.3v i ar l di1 e 04 3.3v i ncs 0 m03 3.3v o p 04r x d3r ae 18 3.3v i p 09r x d0 ab 30 3.3v i ar l di2 e 03 3.3v i ncs 1 j04 3.3v o p 04r x dvr aj19 3.3v i p 09r x d1 aa27 3.3v i ar l di3 f 03 3.3v i ncs 2 l 04 3.3v o p 04r x e r r ag18 3.3v i p 09r x d2 y 25 3.3v i ar l dir 0 g03 3.3v o ncs 3 k 04 3.3v o p 04t x cl k r ah18 3.3v i/ o p 09r x d3 y 26 3.3v i ar l dir 1 g04 3.3v o noe r 04 3.3v i/ o p 04t x d0r ak 18 3.3v i/ o p 09r x dv ab 29 3.3v i ar l div h04 3.3v i nr e s e t ag05 3.3v i p 04t x d1r ag17 3.3v i/ o p 09r x e r ac30 3.3v i ar l s y nc f 05 3.3v o nwe p 03 3.3v o p 04t x d2r ah17 3.3v i/ o p 09t x cl k ab 27 3.3v i clk50 ak02 3.3v i p00colr ak03 3.3v i/ o p 04t x d3r aj17 3.3v i/ o p 09t x d0 ac28 3.3v o cpudi af03 3.3v i p00crsr af06 3.3v i/ o p 04t x e nr aj18 3.3v o p 09t x d1 ad30 3.3v o cp u do af 04 3. 3v i / op00rxclkrak053.3vi/ o p 05col r aj20 3.3v i/ o p 09t x d2 ad29 3.3v o cp uir q ag03 3.3v o p 00r x d0r ah06 3.3v i p 05cr s r ag19 3.3v i/ o p 09t x d3 ac27 3.3v o dat a0 ak 01 3.3v i/ o p 00r x d1r aj06 3.3v i p 05r x cl k r ak 23 3.3v i/ o p 09t x e n ac29 3.3v o dat a01 aj02 3.3v i/ o p 00r x d2r ak 06 3.3v i p 05r x d0r ag21 3.3v i p 10col aa29 3.3v i dat a02 aj01 3.3v i/ o p 00r x d3r ah07 3.3v i p 05r x d1r af 20 3.3v i p 10cr s aa28 3.3v i dat a03 ah02 3.3v i/ o p 00r x dvr ag07 3.3v i p 05r x d2r ae 20 3.3v i p 10r x cl k w29 3.3v i dat a04 ah01 3.3v i/ o p 00r x e r r aj05 3.3v i p 05r x d3r ah22 3.3v i p 10r x d0 v25 3.3v i dat a05 ag02 3.3v i/ op00txclkrah053.3vi/ o p 05r x dvr aj23 3.3v i p 10r x d1 v26 3.3v i dat a06 ag01 3.3v i/ o p 00t x d0r ag06 3.3v i/ o p 05r x e r r aj22 3.3v i p 10r x d2 v27 3.3v i dat a07 af 02 3.3v i/ o p 00t x d1r ak 04 3.3v i/ op05txclkrah213.3vi/ o p 10r x d3 v28 3.3v i dat a08 af 01 3.3v i/ o p 00t x d2r ae 07 3.3v i/ o p 05t x d0r ak 22 3.3v i/ o p 10r x dv w30 3.3v i dat a09 ae 02 3.3v i/ o p 00t x d3r aj04 3.3v i/ o p 05t x d1r aj21 3.3v i/ o p 10r x e r w28 3.3v i dat a10 ae 01 3.3v i/ o p 00t x e nr af 07 3.3v o p 05t x d2r ak 21 3.3v i/ o p 10t x cl k w27 3.3v i dat a11 ad02 3.3v i/ o p 01cr s r ag08 3.3v i/ o p 05t x d3r ah20 3.3v i/ o p 10t x d0 y 29 3.3v o dat a12 ad01 3.3v i/ op01rxclkrah093.3vi/ o p 05t x e nr ag20 3.3v o p 10t x d1 y 28 3.3v o dat a13 ac02 3.3v i/ o p 01r x d0r ak 09 3.3v i p 06col r aj24 3.3v i/ o p 10t x d2 y 27 3.3v o dat a14 ac01 3.3v i/ o p 01r x d1r ag10 3.3v i p 06cr s r ak 24 3.3v i/ o p 10t x d3 aa30 3.3v o dat a15 ab 02 3.3v i/ o p 01r x d2r ae 11 3.3v i p 06r x cl k r af 22 3.3v i/ o p 10t x e n y 30 3.3v o dat a16 ab 01 3.3v i/ o p 01r x d3r af 11 3.3v i p 06r x d0r aj26 3.3v i p 11col v30 3.3v i dat a17 aa02 3.3v i/ o p 01r x dvr aj09 3.3v i p 06r x d1r ak 27 3.3v i p 11cr s v29 3.3v i dat a18 aa01 3.3v i/ o p 01r x e r r ak 08 3.3v i p 06r x d2r ah25 3.3v i p 11r x cl k t 30 3.3v i dat a19 y 02 3.3v i/ op01txclkrag093.3vi/ o p 06r x d3r ag24 3.3v i p 11r x d0 r 29 3.3v i dat a20 y 01 3.3v i/ o p 01t x d0r ah08 3.3v i/ o p 06r x dvr ae 22 3.3v i p 11r x d1 r 28 3.3v i dat a21 w 02 3.3v i/ o p 01t x d1r ak 07 3.3v i/ o p 06r x e r r ag23 3.3v i p 11r x d2 r 27 3.3v i dat a22 w 01 3.3v i/ o p 01t x d2r aj07 3.3v i/ op06txclkrah243.3vi/ o p 11r x d3 r 26 3.3v i dat a23 v02 3.3v i/ o p 01t x d3r af 09 3.3v i/ o p 06t x d0r aj25 3.3v i/ o p 11r x dv r 30 3.3v i dat a24 v01 3.3v i/ o p 01t x e nr aj08 3.3v o p 06t x d1r ah23 3.3v i/ o p 11r x e r t 27 3.3v i dat a25 u02 3.3v i/ o p 02col r aj10 3.3v i/ o p 06t x d2r ag22 3.3v i/ o p 11t x cl k t 28 3.3v i dat a26 u01 3.3v i/ o p 02cr s r ah10 3.3v i/ o p 06t x d3r ak 25 3.3v i/ o p 11t x d0 u30 3.3v o data27 t02 3.3v i/ op02rxclkraj123.3vi/ o p 06t x e nr ak 26 3.3v o p 11t x d1 u29 3.3v o data28 t01 3.3v i/ o p 02r x d0r ae 13 3.3v i p 07col r ak 28 3.3v i/ o p 11t x d2 u28 3.3v o dat a29 r 02 3.3v i/ o p 02r x d1r af 13 3.3v i p 07cr s r aj27 3.3v i/ o p 11t x d3 u27 3.3v o dat a30 r 01 3.3v i/ o p 02r x d2r ag13 3.3v i p 07r x cl k r ak 30 3.3v i/ o p 11t x e n t 29 3.3v o dat a31 p 02 3.3v i/ o p 02r x d3r ah13 3.3v i p 07r x d0r ah28 3.3v i p 12col p 30 3.3v i dat a32 p 01 3.3v i/ o p 02r x dvr ak 12 3.3v i p 07r x d1r ag27 3.3v i p 12cr s r 25 3.3v i dat a33 n02 3.3v i/ o p 02r x e r r ah12 3.3v i p 07r x d2r aj30 3.3v i p 12r x cl k m30 3.3v i dat a34 n01 3.3v i/ op02txclkrag123.3vi/ o p 07r x d3r ah29 3.3v i p 12r x d0 m28 3.3v i dat a35 m02 3.3v i/ o p 02t x d0r aj11 3.3v i/ o p 07r x dvr aj29 3.3v i p 12r x d1 l 30 3.3v i dat a36 m01 3.3v i/ o p 02t x d1r ah11 3.3v i/ o p 07r x e r r af 25 3.3v i p 12r x d2 n26 3.3v i dat a37 l 02 3.3v i/ o p 02t x d2r ag11 3.3v i/ op07txclkrag263.3vi/ o p 12r x d3 n25 3.3v i dat a38 l 01 3.3v i/ o p 02t x d3r ak 10 3.3v i/ o p 07t x d0r aj28 3.3v i/ o p 12r x dv m29 3.3v i dat a39 k 02 3.3v i/ o p 02t x e nr ak 11 3.3v o p 07t x d1r af 24 3.3v i/ o p 12r x e r n27 3.3v i dat a40 k 01 3.3v i/ o p 03col r ak 13 3.3v i/ o p 07t x d2r ag25 3.3v i/ o p 12t x cl k n28 3.3v i dat a42 j01 3.3v i/ op03rxclkrak153.3vi/ o p 07t x e nr ak 29 3.3v o p 12t x d0 n30 3.3v o 31 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 pin list by name (with voltage rating): part 2 signal name pin i/o type signal name pin i/o type signal name pin i/o type signal name pin i/o type p 12t x d1 p 27 3.3v o p 17r x e r a24 3.3v i p 22r x d1r f 09 3.3v i vdd y 05 3.3v p ower p 12t x d2 p 28 3.3v o p 17t x cl k b 24 3.3v i p 22r x d2r b 05 3.3v i vdd ab 26 3.3v p ower p 12t x d3 p 29 3.3v o p 17t x d0 f 22 3.3v o p 22r x d3r a04 3.3v i vdd af 05 3.3v p ower p 12t x e n n29 3.3v o p 17t x d1 d23 3.3v o p 22r x dvr d08 3.3v i vdd af 12 3.3v p ower p 13col l 29 3.3v i p 17t x d2 c24 3.3v o p 22r x e r r a05 3.3v i vdd af 19 3.3v p ower p 13cr s m27 3.3v i p 17t x d3 a25 3.3v o p 22t x cl k r b 06 3.3v i/ o vdd af 26 3.3v p ower p 13r x cl k h30 3.3v i p 17t x e n e 22 3.3v o p 22t x d0r d09 3.3v o vdd e 05 3.3v p ower p 13r x d0 k 27 3.3v i p 18col d21 3.3v i p 22t x d1r a06 3.3v o vdd e 12 3.3v p ower p 13r x d1 l 26 3.3v i p 18cr s a22 3.3v i p 22t x d2r b 07 3.3v o vdd e 19 3.3v p ower p 13r x d2 l 25 3.3v i p 18r x cl k b 20 3.3v i p 22t x d3r a07 3.3v o vdd e 26 3.3v p ower p 13r x d3 j28 3.3v i p 18r x d0 d19 3.3v i p 22t x e nr c08 3.3v o vdd m05 3.3v p ower p 13r x dv h29 3.3v i p 18r x d1 c19 3.3v i p 23col r d07 3.3v i/ ovddm263.3vpower p 13r x e r j29 3.3v i p 18r x d2 f 18 3.3v i p 23cr s r c06 3.3v i/ ovddw053.3vpower p 13t x cl k k 28 3.3v i p 18r x d3 e 18 3.3v i p 23r x cl k r d05 3.3v i/ ovddw263.3vpower p 13t x d0 j30 3.3v o p 18r x dv a20 3.3v i p 23r x d0r a01 3.3v i vs s a19 ground p 13t x d1 k 29 3.3v o p 18r x e r c20 3.3v i p 23r x d1r b 02 3.3v i vs s aa04 ground p 13t x d2 k 30 3.3v o p 18t x cl k d20 3.3v i p 23r x d2r c03 3.3v i vs s aa06 ground p 13t x d3 l 28 3.3v o p 18t x d0 b 21 3.3v o p 23r x d3r d04 3.3v i vs s aa25 ground p 13t x e n l 27 3.3v o p 18t x d1 c21 3.3v o p 23r x dvr e 06 3.3v i vs s ab 06 ground p 14col g29 3.3v i p 18t x d2 e 20 3.3v o p 23r x e r r f 07 3.3v i vs s ab 25 ground p 14cr s g30 3.3v i p 18t x d3 f 20 3.3v o p 23t x cl k r b 03 3.3v i/ ovssac06 ground p 14r x cl k j26 3.3v i p 18t x e n a21 3.3v o p 23t x d0r d06 3.3v o vs s ac25 ground p 14r x d0 e 29 3.3v i p 19col c18 3.3v i p 23t x d1r c05 3.3v o vs s ad06 ground p 14r x d1 d30 3.3v i p 19cr s d18 3.3v i p 23t x d2r a03 3.3v o vs s ae 05 ground p 14r x d2 f 28 3.3v i p 19r x cl k c16 3.3v i p 23t x d3r b 04 3.3v o vs s ae 06 ground p 14r x d3 g27 3.3v i p 19r x d0 a16 3.3v i p 23t x e nr e 07 3.3v o vs s ae 08 ground p 14r x dv j25 3.3v i p 19r x d1 a15 3.3v i s t at 0 b 01 3.3v o vs s ae 10 ground p 14r x e r h27 3.3v i p 19r x d2 b 15 3.3v i s t at 1 c01 3.3v o vs s ae 12 ground p 14t x cl k g28 3.3v i p 19r x d3 c15 3.3v i s t at 2 c02 3.3v o vs s ae 14 ground p 14t x d0 f 29 3.3v o p 19r x dv d16 3.3v i s t at 3 d01 3.3v o vs s ae 15 ground p 14t x d1 h28 3.3v o p 19r x e r b 16 3.3v i vdd a02 3.3v p ower vs s ae 17 ground p 14t x d2 j27 3.3v o p 19t x cl k a17 3.3v i vdd aa03 3.3v p ower vs s ae 19 ground p 14t x d3 f 30 3.3v o p 19t x d0 c17 3.3v o vdd aa05 3.3v p ower vs s ae 21 ground p 14t x e n e 30 3.3v o p 19t x d1 d17 3.3v o vdd aa26 3.3v p ower vs s ae 23 ground p 15col c30 3.3v i p 19t x d2 a18 3.3v o vdd ab 03 3.3v p ower vs s ae 24 ground p 15cr s d29 3.3v i p 19t x d3 b 18 3.3v o vdd ab 05 3.3v p ower vs s ae 25 ground p 15r x cl k e 27 3.3v i p 19t x e n b 17 3.3v o vdd ac05 3.3v p ower vs s aj03 ground p 15r x d0 a30 3.3v i p 1col r ae 09 3.3v i/ o vdd ac26 3.3v p ower vs s c04 ground p 15r x d1 b 29 3.3v i p 20col e 15 3.3v i vdd ad05 3.3v p ower vs s f 06 ground p 15r x d2 c28 3.3v i p 20cr s d15 3.3v i vdd af 08 3.3v p ower vs s f 08 ground p 15r x d3 d27 3.3v i p 20r x cl k c13 3.3v i vdd af 10 3.3v p ower vs s f 10 ground p 15r x dv f 26 3.3v i p 20r x d0 a12 3.3v i vdd af 14 3.3v p ower vs s f 12 ground p 15r x e r g25 3.3v i p 20r x d1 b 12 3.3v i vdd af 15 3.3v p ower vs s f 14 ground p 15t x cl k d28 3.3v i p 20r x d2 c12 3.3v i vdd af 17 3.3v p ower vs s f 16 ground p 15t x d0 c29 3.3v o p 20r x d3 a11 3.3v i vdd af 21 3.3v p ower vs s f 17 ground p 15t x d1 g26 3.3v o p 20r x dv d13 3.3v i vdd af 23 3.3v p ower vs s f 19 ground p 15t x d2 f 27 3.3v o p 20r x e r b 13 3.3v i vdd ah27 3.3v p ower vs s f 21 ground p 15t x d3 e 28 3.3v o p 20t x cl k a13 3.3v i vdd b 19 3.3v p ower vs s f 23 ground p 15t x e n b 30 3.3v o p 20t x d0 c14 3.3v o vdd e 08 3.3v p ower vs s f 25 ground p 16col b 28 3.3v i p 20t x d1 b 14 3.3v o vdd e 10 3.3v p ower vs s g06 ground p 16cr s a29 3.3v i p 20t x d2 a14 3.3v o vdd e 14 3.3v p ower vs s h06 ground p 16r x cl k d25 3.3v i p 20t x d3 f 15 3.3v o vdd e 16 3.3v p ower vs s h25 ground p 16r x d0 c26 3.3v i p 20t x e n d14 3.3v o vdd e 17 3.3v p ower vs s j06 ground p 16r x d1 b 26 3.3v i p 21col f 13 3.3v i vdd e 21 3.3v p ower vs s k 06 ground p 16r x d2 a26 3.3v i p 21cr s e 13 3.3v i vdd e 23 3.3v p ower vs s k 25 ground p 16r x d3 d24 3.3v i p 21r x cl k c10 3.3v i vdd g05 3.3v p ower vs s l 06 ground p 16r x dv e 24 3.3v i p 21r x d0 a08 3.3v i vdd h05 3.3v p ower vs s m06 ground p 16r x e r a27 3.3v i p 21r x d1 b 08 3.3v i vdd h26 3.3v p ower vs s m25 ground p 16t x cl k f 24 3.3v i p 21r x d2 d10 3.3v i vdd j05 3.3v p ower vs s n06 ground p 16t x d0 a28 3.3v o p 21r x d3 e 11 3.3v i vdd k 05 3.3v p ower vs s p 04 ground p 16t x d1 e 25 3.3v o p 21r x dv b 09 3.3v i vdd k 26 3.3v p ower vs s p 06 ground p 16t x d2 d26 3.3v o p 21r x e r d11 3.3v i vdd l 05 3.3v p ower vs s p 25 ground p 16t x d3 c27 3.3v o p 21t x cl k a09 3.3v i vdd n03 3.3v p ower vs s r 06 ground p 16t x e n b 27 3.3v o p 21t x d0 a10 3.3v o vdd n05 3.3v p ower vs s t 06 ground p 17col b 25 3.3v i p 21t x d1 c11 3.3v o vdd p 05 3.3v p ower vs s t 25 ground p 17cr s c25 3.3v i p 21t x d2 b 11 3.3v o vdd p 26 3.3v p ower vs s u06 ground p 17r x cl k c23 3.3v i p 21t x d3 d12 3.3v o vdd r 05 3.3v p ower vs s u25 ground p 17r x d0 d22 3.3v i p 21t x e n b 10 3.3v o vdd t 05 3.3v p ower vs s v06 ground p 17r x d1 a23 3.3v i p 22col r c09 3.3v i/ o v dd t 26 3. 3v p ower v s s w 06 gr ou n d p 17r x d2 c22 3.3v i p 22cr s r f 11 3.3v i/ o v dd u 05 3. 3v p ower v s s w 25 gr ou n d p 17r x d3 b 22 3.3v i p 22r x cl k r c07 3.3v i/ o v dd u 26 3. 3v p ower v s s y 06 gr ou n d p 17r x dv b 23 3.3v i p 22r x d0r e 09 3.3v i vdd v05 3.3v p ower wchdog ah04 o 32 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 t1 t2 rxclk rxdv rxd[3:0] rxer t# description: min typ max unit t1 rx_dv, rxd, rx_er setup time 5 - - ns t2 rx_dv, rxd, rx_er hold time 5 - - ns mii receive timing 9. timing description txclk txen txd[3:0] t2 t1 t# desciption min typ max unit t1 txen, txd setup time 10 - - ns t2 txen, txd hold time 10 - - ns mii transmit timing 33 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 rxclk rxdv rxd[3:0] t1 t2 t# description: min typ max unit t1 rxdv, rxd setup time 10 - ns t2 rxdv, rxd hold time 10 ns reversed mii receive timing t1 t2 txclk txen txd[3:0] t# description: min typ max unit t1 rxdv, rxd setup time 5 - ns t2 rxdv, rxd hold time 5 ns reversed mii transmit timing 34 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 rxclk rxd[3:0] rxdv t1 t# desciption min typ max unit t1 rxd to rxdv 0 - - ns reversed mii packet timing (start of packet) rxclk rxd[3:0] rxdv t1 t# desciption min typ max unit t1 pxd to rxdv delay time 0 - - ns reversed mii packet timing (end of packet) 35 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 t1 mdc mdio phy management read timing t2 t# description min typ max unit t1 mdio setup time 0 - 300 ns t2 mdc cycle - 800 - ns t1 t2 mdc mdio t3 t4 t5 t# description min typ max unit t1 mdc high time - 400 - ns t2 mdc low time - 400 - ns t3 mdc period - 800 - ns t4 mdio set up time 10 - - ns t5 mdio hold time 10 - - ns phy management write timing 36 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 t1 address data __ oe __ ce t2 t3 valid data t4 t5 t7 t6 t9 t8 high-z high-z t# description min typ max unit t1 read cycle time - 20 - ns t2 address access time - - 12 ns t3 output hold time 0 - - ns t4 oe access time - - 12 ns t5 ce access time - - 12 ns t6 o e to low-z output 0 - - ns t7 ce to low-z output 0 - - ns t8 oe to high-z output - - 6 ns t9 ce to high-z output - - 6 ns sram read timing asram read timing t1 address data __ ce t2 t3 valid data t6 t4 t8 t7 ___ we t5 t# description min typ max unit t1 w rite cycle time - 20 - ns t2 address setup to w rite end time 12 - - ns t3 address hold for w rite end time 0 - - ns t4 ce to w rite end time 12 - - ns t5 address setup time 4 - - ns t6 w e pulse width 8 - - ns t7 data setup to w rite end 8 - - ns t8 data hold for w rite end 0 - - ns asram w rite timing 37 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 t2 cpudi idle state start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit t1 cpudo stop bit start bit stop bit t3 bit 7 bit 6 bit0 cpu command timing t4 t# description min typ max unit t1 cp u idle time 0 - - us t2 cp u command bit time 1 0 - - us t3 response time 0 - 20 ms t4 command time - - 2 0 ms t2 t3 da1 result1 da2 arlclk arldo arldi t1 result2 arl result timing t# description min typ max unit t1 time between das 0 - - ns t2 time for ar l res ult 0 - 200 ns t3 time between res ults 0 - - ns 38 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 nled0 nled1 nled3 nled2 ledclk p23 p22 p21 p2 p1 p0 p23 p22 p21 p2 p1 p0 led signal timing ledvld0 ledvld1 fdx spd lnk fdx spd lnk fdx spd lnk fdx spd lnk fdx spd lnk fdx spd lnk err col rcv xmt err col rcv xmt err col rcv xmt err col rcv xmt err col rcv xmt err col rcv xmt 10. electrical specification absolute maximum ratings operation at absolute maximum ratings is not implied. exposure to stresses outside those listed could cause permanent damage to the device. recommended operation conditions supply voltage: vdd 3.3v, +/-0.3v operating temperature: ta 0 o c -70 o c maximum power consumption 3.5w dc supply voltage : vdd -0.3v ~ +5.0v dc input current: iin +/-10 ma dc input voltage: vin -0.3 ~ vdd + 0.3v dc output voltage: vout -0.3 ~ vdd + 0.3v storage temperature: tstg -40 to +125 o c 39 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 11. packaging bottom view a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36.83 1.27 0.75+/-0.15 34.50 40.00+/-0.20 top view 0.60+/-0.05 2.33+/-0.13 side view o.56 advanced comm. devices flllllsmayyww ACD82124 pin - a1 pin - a1 40 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 address resolution logic (the built-in arl with 2048 mac addresses) appendix-a1 41 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 1. summary the internal address resolution logic (arl) of acds switch controllers automatically builds up an address table and maps up to 2,048 mac addresses into their associated port. it can work by itself without any cpu intervention in an un-managed system. for a managed system, the management cpu can configure the operation mode of the arl, learn all the address in the address table, add new address into the table, control security or filtering feature of each address entry etc. the arl is designed with such a high performance that it will never slow down the frame switching opera- tion. it helps the switch controllers to reach wire speed forwarding rate under any type of traffic load. the address space can be expanded to 11k entries by using the external arl, the acd80800. 2. features supports up to 2,048 mac address lookup provides uart type of interface for the manage- ment cpu wire speed address lookup time. wire speed address learning time. address can be automatically learned from switch without the cpu intervention address can be manually added by the cpu through the cpu interface each mac address can be secured by the cpu from being changed or aged out each mac address can be marked by the cpu from receiving any frame each newly learned mac address is notified to the cpu each aged out mac address is notified to the cpu automatic address aging control, with configurable aging period cpu interface address registers data registers command registers control registers switch interface address learning engine cpu interface engine address table (2048 entries) figure-1. arl block diagram address aging engine address lookup engine 42 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 3. functional description the arl provides address resolution service for acds switch controllers. figure 2 is a block diagram of the arl. t raf fic snooping all ethernet frames received by acds switch control- ler have to be stored into memory buffer. as the frame data are written into memory, the status of the data shown on the data bus are displayed by acds switch controller through a state bus. the arls switch con- troller interface contains the signals of the data bus and the state bus. by snooping the data bus and the state bus of acds switch controller, the arl can de- tect the occurrence of any destination mac address and source mac address embedded inside each frame. address learning each source address caught from the data bus, to- gether with the id of the ingress port, is passed to the address learning engine of the arl. the address learning engine will first determine whether the frame is a valid frame. for a valid frame, it will first try to find the source address from the current address table. if that address doesnt exist, or if it does exist but the port id associated with the mac address is not the ingress port, the address will be learned into the ad- dress table. after an address is learned by the ad- dress learning engine, the cpu will be notified to read this newly learned address so that it can add it into the cpus address table. address aging after each source address is learned into the address table, it has to be refreshed at least once within each address aging period. refresh means it is caught again from the switch interface. if it has not occurred for a pre-set aging period, the address aging engine will remove the address from the address table. after an address is removed by the address aging engine, the cpu will be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the cpus address table. address lookup each destination address is passed to the address lookup engine of the arl. the address lookup en- gine checks if the destination address matches with any existing address in the address table. if it does, the arl returns the associated port id to acds switch controller through the output data bus. otherwise, a no match result is passed to acds switch controller through the output data bus. cpu interface the cpu can access the registers of the arl by send- ing commands to the uart data input line. each com- mand is consisted by action (read or write), register type, register index, and data. each result of com- mand execution is returned to the cpu through the uart data output line. cpu interface registers the arl provides a bunch of registers for the control cpu. through the registers, the cpu can read all ad- dress entries of the address table, delete particular addresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algorithm etc. through a proper interrupt request sig- nal, the cpu can be notified whenever it needs to retrieve data for a newly-learned address or an aged- out address so that the cpu can build an exact same address table learned by the arl. cpu interface engine the command sent by the control cpu is executed by the cpu interface engine. for example, the cpu may send a command to learn the first newly-learned ad- dress. the cpu interface engine is responsible to find the newly-learned address from the address table, and passes it to cpu. the cpu may request to learn next newly-learned address. then, it is again the re- sponsibility of the cpu interface engine to search for next newly-learned address from the address table. address t able the address table can hold up to 2,048 mac ad- dresses, together with the associated port id, security flag, filtering flag, new flag, aging information etc. the address table resides in the embedded sram inside the arl. 43 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 header address data checksum header address data checksum 4. interface description cpu interface the cpu can communicate with the arl through the uart interface of the switch ic. the management cpu can send command to the arl by writing into associ- ated registers, and retrieve result from arl by read- ing corresponding registers. the registers are de- scribed in the section of register description. the cpu interface signals are described by table-1 : uartdi is used by the control cpu to send command into the arl. the baud rate will be automatically de- tected by the arl. the result will be returned through the uartdo line with the detected baud rate. the for- mat of the command packet is shown as follows: where: header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7, same as the host switch con- troller) b7:b5 - device type, 010 for arl address - 8-bit value used to select the register to access data - 32-bit value, only the lsb is used for write operation, all 0 for read opera- tion checksum - 8-bit value of xor of all bytes uartdo is used to return the result of command ex- ecution to the cpu. the format of the result packet is shown as follows: where: header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7) b7:b5 - device type, 010 for arl address - 8-bit value for address of the selected register data - 32-bit value, only the lsb is used for read operation, all 0 for write opera- tion checksum - 8-bit value of xor of all bytes the arl will always check the cmd header to see if both the device type and the device number matches with its setting. if not, it ignores the command and will not generate any response to this command. table-1: cpu interface name i/o description uartdi i uart input data line. uartdo o uart output data line. 44 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 table-3: command list command description 0x09 add the specified mac address into the address table 0x0a set a lock for the specified mac address 0x0b set a filtering flag for the specified mac address 0x0c delete the specified mac address from the address table 0x0d assign a port id to the specified mac address 0x10 read the first entry of the address table 0x11 read next entry of address book 0x20 read first valid entry 0x21 read next valid entry 0x30 read first new page 0x31 read next new page 0x40 read first aged page 0x41 read next aged page 0x50 read first locked page 0x51 read next locked page 0x60 read first filtered page 0x61 read next filtered page 0x80 read first page with specified pid 0x81 read next page with specified pid 0xff s y stem reset 5. register description acd80800 provides a bunch of registers for the cpu to access the address table inside it. command is sent to acd80800 by writing into the associated registers. before the cpu can pass a command to acd80800, it must check the result register (register 11) to see if the command has been done. when the result regis- ter indicates the command has been done, the cpu may need to retrieve the result of previous command first. after that, the cpu has to write the associated parameter of the command into the data registers. then, the cpu can write the command type into the command register. when a new command is written into the command register, acd80800 will change the status of the result register to 0. the result register will indicate the completion of the command at the end of the execution. before the completion of the execu- tion, any command written into the command register is ignored by acd80800. the registers accessible to the cpu are described by table-2 : the dataregx are registers used to pass the param- eter of the command to the acd80800, and the result of the command to the cpu. the addrregx are registers used to specify the ad- dress associated with the command. the cmdreg is used to pass the type of command to the acd80800. the command types are listed in table- 3 . the details of each command is described in the chapter of command description. the rstreg is used to indicate the status of command execution. the result code is listed as follows: 01 - command is being executed and is not done yet 10 - command is done with no error 1x - command is done, with error indi- cated by x, where x is a 4-bit error code: 0001 for cannot find the entry as speci- fied table-2: register description reg. name description 0 datareg0 byte 0 of data 1 datareg1 byte 1 of data 2 datareg2 byte 2 of data 3 datareg3 byte 3 of data 4 datareg4 byte 4 of data 5 datareg5 byte 5 of data 6 datareg6 byte 6 of data 7 datareg7 byte 7 of data 8 addrreg0 lsb of address value 9 addrreg1 msb of address value 10 cmdreg command register 11 rsltreg result register 12 cfgreg configuration register 13 intsrcreg interrupt source register 14 intmskreg interrupt mask register 15 nlearnreg0 address learning disable register for port 0 - 7 16 nlearnreg1 address learning disable register for port 8 - 15 17 nlearnreg2 address learning disable register for port 16 - 23 18 agetimereg0 lsb of aging period register 19 agetimereg1 msb of aging period register 20 poscfg power on strobe configuration register 0 45 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 the cfgreg is used to configure the way the acd80800 works. the bit definition of cfgreg is described as: bit 0 - disable address aging bit 1 - disable address lookup bit 2 - disable da cache bit 3 - disable sa cache bit 7:4 - hashing algorithm selection, de- fault is 0000 the intsrcreg is used to indicate what can cause in- terrupt request to cpu. the source of interrupt is listed as: bit 0 - aged address exists bit 1 - new address exists bit 2 - reserved bit 3 - reserved bit 4 - bucket overflowed bit 5 - command is done bit 6 - system initialization is completed bit 7 - self test failure the intmskreg is used to enable an interrupt source to generate an interrupt request. the bit definition is the same as intsrcreg. a 1 in a bit enables the corre- sponding interrupt source to generate an interrupt re- quest once it is set. the nlearnreg[2:0] are used to disable address learn- ing activity from a particular port. if the bit correspond- ing to a port is set, acd80800 will not try to learn new addresses from that port. the agetimereg[1:0] are used to specify the period of address aging control. the aging period can be from 0 to 65535 units, with each unit counted as 2.684 second. the poscfgreg is a configuration register whose de- fault value is determined by the pull-up or pull-down status of the associated hardware pin. the bits of poscfgreg0 is listed as follows: bit 3 C bisten: 0 = self test disabled, 1 = self test enabled; bit 2 - testen, 0 = normal operation, 1 = production test enabled; bit 1* - nocpu * , 0 = presence of con- trol cpu, 1 = no control cpu; bit 0 - cpugo, 0 = wait for system start command from cpu before start- ing self initialization, 1 = cpu ready. only effective when bit-1 (nocpu) is set to 0; note: when nocpu is set as 0, acd80800 will not start the initialization process until a system start com- mand is sent to the command register. 46 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 b7 b6 b5 b4 b3 b2 b1 b0 rsvd rsvd filter lock new old age valid 6. command description command 09h description: add the specified mac address into the address table. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the associated port number into datareg6. result: the mac address will be stored into the ad- dress table if there is space available. the result is indicated by the result register. command 0ah description: set the lock bit for the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the state machine will seek for an entry with matched mac address, and set the lock bit of the entry. the result is indicated by the result register. command 0bh description: set the filter flag for the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the state machine will seek for an entry with matched mac address, and set the filter bit of the entry. the result is indicated by the result register. command 0ch description: delete the specified mac address from the address table. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the mac address will be removed from the address table. the result is indicated by the result register. command 0dh description: assign the associated port number to the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the port number into datareg6. result: the port id field of the entry containing the specified mac address will be changed accordingly. the result is indicated by the result register. command 10h description: read the first entry of the address table. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the first entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag * bits are stored in datareg7.the read pointer will be set to point to second entry of the address book. note - the flag bits are defined as: where: filter - 1 indicates the frame heading to this address should be dropped. lock - 1 indicates the entry should never be changed or aged out. new - 1 indicates the entry is a newly learned address. old - 1 indicates the address has been aged out. age - 1 indicates the address has not been visited for current age cycle. valid - 1 indicates the entry is a valid one. rsvd - reserved bits. 47 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 command 1 1h description: read next entry of address book. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the address book entry pointed by read pointer will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer will be increased by one. command 20h description: read first valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first valid entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 21h description: read next valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next valid entry from the read pointer of the ad- dress book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this en- try. command 30h description: read first new page. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first new entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 31h description: read next new entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next new entry from the read pointer of the ad- dress book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this en- try. command 40h description: read first aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first aged entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 41h description: read next aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next aged entry from the read pointer of the ad- dress book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this en- try. 48 acd confidential. do not reproduce. use under non-disclosure agreement only. introductory data sheet: ACD82124 command 50h description: read first locked entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first locked entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 51h description: read next locked entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next locked entry from the read pointer of the ad- dress book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this en- try. command 60h description: read first filtered page. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first filtered entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 61h description: read next valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next filtered entry from the read pointer of the ad- dress book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this en- try. command 80h description: read first entry with specified port num- ber. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of first entry of the address book with the said port number will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 81h description: read next valid entry. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of next entry from the read pointer of the address book with the said port number will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command ffh description: system reset. parameter: none result: this command will reset the arl system. all entries of the address book will be cleared. |
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