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march 2014 docid025682 rev 1 1/11 AN4421 application note migrating from m24lr to m24sr series introduction both m24lrxx and m24srxx dynamic tags can be accessed through the i2c-bus. this application note aims at helping to design an application able to interface through the i2c- bus either the m24lrxx (a) or the m24srxx (b) . some references are also made when accessing the standard m24xxx (eeprom accessed through the i2c-bus). a. also accessible through rf (iso15693 standard) b. also accessible through rf (iso14443 standard) www.st.com
contents AN4421 2/11 docid025682 rev 1 contents 1 hardware and ac/dc considerati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 hardware considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 ac/dc differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 pull resistor on sda line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 software considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 i2c-bus and standard eeprom memories (m24x xx) . . . . . . . . . . . . . . . . 7 2.2 differences when accessing a standard eeprom (m24xxx) or an m24lrxx dynamic tag (iso15693) through the i2c-bus . . . . . . . . . . . . 7 2.3 differences when accessing an iso15693 dynamic tag (m24lrxx) or an iso/iec 1443 dynamic tag (m24srxx) through the i2c-bus . . . . . . . . . 9 3 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
docid025682 rev 1 3/11 AN4421 list of tables 3 list of tables table 1. pinout differences between m24lrxx and m24srxx devices . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. ac/dc differences between m24lrxx and m24srxx de vices . . . . . . . . . . . . . . . . . . . . . . 5 table 3. device select byte (fir st byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. standard eeprom devi ce select byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. m24lrxx device select byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
list of figures AN4421 4/11 docid025682 rev 1 list of figures figure 1. maximum rbus value versus bus parasitic capacitance (cbus) for an i2c bus at maximum frequency fc = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. maximum rbus value versus bus parasitic capacitance (cbus) for an i2c bus at maximum frequency fc = 1 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. access to a standard eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. command+response sequence between the i2c-bus master and the m24srxx. . . . . . . . . 9
docid025682 rev 1 5/11 AN4421 hardware and ac/dc considerations 10 1 hardware and ac/dc considerations 1.1 hardware considerations both m24lrxx and m24srxx devices are offered in an 8-pin package. the hardware differences between the two devices are detailed in table 1 . although pin1 and pin7 differ between the m 24srxx and the m24lrxx, the i2c specific (and rf specific) inputs are identical for th e m24srxx and m24lrxx. both m24lrxx and m24srxx can therefore be accessed through the i2c-bus, on the same pins, sda and scl (pin5 and pin6). the only pin to connect differ ently is pin7 (input for the m24lrxx and output for the m24srxx). 1.2 ac/dc characteristics 1.2.1 ac/dc differences table 2 summarizes the ac/dc differences to consider when designing an application moving from m24lrxx to m2 4srxx (or reverse move). table 1. pinout differences between m24lrxx and m24srxx devices m24lrxx m24srxx comments pin1 e0 rf disable e0 input functionality is different from the rf disable input functionality pin2 ac0 ac0 antenna coil pin3 ac1 ac1 antenna coil pin4 vss vss ground pin5 sda sda serial data pin6 scl scl serial clock pin7 e1 gpo e1 input functionality is different from the general purpose output functionality. pin8 vcc vcc supply voltage table 2. ac/dc differences betw een m24lrxx and m24srxx devices m24lrxx m24srxx comments vcc supply voltage 1.8 v / 5.5 v 2.7 v / 5.5 v operating temperatur e range -40c / 85c maximum clock frequency 400 khz 1 mhz see section 1.2.2 supply current during a write 700 a 550 a worst case value, at max. scl frequency, no rf signal on ac0/ac1, vcc = 5.5 v supply current during a read 500 a write cycle (byte or page) 5 ms
hardware and ac/dc considerations AN4421 6/11 docid025682 rev 1 1.2.2 pull resistor on sda line the i2c-bus specification defines the sda output as an open drain so that, if two devices are in conflict while outputting a "1" and a "0" at the same time, this conflict cannot induce critical current peaks. the "0" level is driven by the open drain output, while the "1" level is sourced with an external pull up resistor r bus . this r bus resistor value has to be: ? high enough so that the current flowing through r bus and sda remains lower than the specified i ol value (a few ma) ? reasonably low so that the cut-off frequency (a) defined with the sda line parasitic capacitor c bus is higher than the maximum scl clock frequency. depending on the application parasitic capacitor value r bus , c bus can be defined as explained in figure 1 curves. figure 1. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 2. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz a. the time constant = r bus * c bus defines the cut-off frequency: f cut-off = ? * pi * r bus * c bus aib "uslinecapacitorp& "uslinepull upresistor k )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! 2 bus # bus ns (ere2 bus # bus ns k ? p& 4he2x#timeconstant mustbebelowthens timeconstantlinerepresented ontheleft bus bus "uslinecapacitorp& "uslinepull upresistork -36 )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! (ere 2 bus # bus ns 2 bu s # bu s ns 4he2 bus # bus timeconstant mustbebelowthens timeconstantlinerepresented ontheleft
docid025682 rev 1 7/11 AN4421 software considerations 10 2 software considerations 2.1 i2c-bus and standard eeprom memories (m24xxx) the i2c-bus specification defines a data transfer as a string of bytes inside which the first byte handles one rw bit defining the transfer direction: from master to slave or from slave to master. m24xxx is always a slave device. to start a communication between the bus master and the slave device, the bus master must first initiate a start condition. following this, the bus master sends the device select byte. the device select byte consists of a 4-bit device type identifier and up to 3 chip enable address bits. a device type identifier handling any value other than 1010b (to select the memory) is not acknowledged by the memory device. when the device select code is received, th e memory device only responds if the chip enable address is the same as the value decoded on the ei inputs. the 8th bit is the read/write bit (rw ). this bit is set to 1 for read (from slave) and 0 for write (to slave) operations. 2.2 differences when accessing a standard eeprom (m24xxx) or an m24lrxx dynamic tag (i so15693) through the i2c-bus the standard eeproms are accessed, after a start condition, with a sequence composed of the device select byte (where the rw bit defines the data transfer direction) followed by two address bytes and the data bytes. this sequence is ended by the bus master sending a stop condition, as in the write sequence example shown in figure 3 . table 3. device select byte (first byte) device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address rw b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 e2 e1 e0 rw
software considerations AN4421 8/11 docid025682 rev 1 figure 3. access to a standard eeprom the m24lrxx dynamic tags are accessed with the same read and write sequences as the sequences used for the standa rd eeprom m24xxx, that is a sequence initiated with a start condition and composed of the device select byte followed by the address bytes and the data bytes. this sequence is ended by the bus master sending a stop condition, as shown in figure 3 . the difference between a st andard eeprom m24xxx and the m24lrxx comes from the device select byte content: ? the standard eeprom device se lect byte is defined in table 4 . ? the m24lrxx device select byte is defined in table 5 . table 4. standard eeprom device select byte device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0 bit and e1 bit are compared against the respective values read from external pins e0, e1 of the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 e2 e1 e0 rw table 5. m24lrxx device select byte device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0 bit and e1 bit are compared against the respective values read from external pins e0, e1 of the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 1 010e2 (3) 3. e2 is not connected to any exte rnal pin, see m24lrxx for details. e1 e0 rw 3top 3tart "yte7rite $evselect "yteaddress "yteaddress $atain 3tart 0age7rite $evselect "yteaddress "yteaddress $atain $atain !) 0age7rite contgd 3top $atain. !#+ !#+ !#+ ./!#+ 27 !#+ !#+ !#+ ./!#+ 27 ./!#+ ./!#+
docid025682 rev 1 9/11 AN4421 software considerations 10 the reader can see that bit e2 makes the diff erence between the two products; this has to be taken into account when developing the software routine accessing either a standard eeprom or an m24lrxx dynamic tag. 2.3 differences when accessing an iso15693 dynamic tag (m24lrxx) or an iso/iec 1443 dynamic tag (m24srxx) through the i2c-bus the m24srxx dynamic tags are accessed through the i2c-bus protocol where each byte is acknowledged by the device receiving the transmitted byte, but the sequence content is different from the m24lrxx sequence. for the m24srxx, the i2c communication is built on a system of command and reply exchange: 1. the i2c-bus master starts the communication by sending a request, that is a device select byte with the r w bit set to 0 followed by the command field. 2. once a valid request is received by the m24srxx, it prepares its answer. 3. then the i2c-bus master sends a response r equest, that is a device select byte with the r w bit set to 1, followed by the data received from the m24srxx. figure 4 shows a simplified overview of the (c ommand+response) sequence between the i2c-bus master and the m24srxx. figure 4. command+response sequence between the i2c-bus master and the m24srxx 1. s is the i2c start condition. 2. rw is the 8th bit of device select. 3. p is the i2c stop condition. note: the m24srxx command response details are offered in the an4433 (storing data into the ndef memory of m24sr). d^???s d??? ] ^o? z??}v? d?e^z?? zt a w ] ^o? zt a ^ }uuv w ^ w
revision history AN4421 10/11 docid025682 rev 1 3 revision history table 6. document revision history date revision changes 17-mar-2014 1 initial release.
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