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revision 2.2, 2014-09-19
edition 2014-09-19 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
PX3519 datasheet 3 revision 2.2, 2014-09-19 revision history page or item subjects (major changes since previous revision) revision 2.0 2013-07-17 first issue revision 2.1 2014-08-21 changes: table 5 page 8: phase voltage, pulsed minimum to -12v revision 2.2 2014-09-19 changes: r phase added in the simplified block diagram soa diagram for r phase introduced trademarks of infineon technologies ag aurix ? , bluemoon ? , comneon ? , c166 ? , crossave ? , canpak ? , cipos ? , coolmos ? , coolset ? , corecontrol ? , dave ? , easypim ? , econobridge ? , econodual ? , econopack ? , econopim ? , eicedriver ? , eupec ? , fcos ? , hitfet ? , hybridpack ? , isoface ? , i2rf ? , isopack ? , mipaq ? , modstack ? , my-d ? , novalithic ? , omnitune ? , optimos ? , origa ? , profet ? , pro-sil ? , primarion ? , primepack ? , rasic ? , reversave ? , satric ? , sieget ? , sindrion ? , smarti ? , smartlewis ? , tempfet ? , thinq! ? , tricore ? , trenchstop ? , x-gold ? , xmm ? , x-pmu ? , xposys ? . other trademarks advance design system ? (ads) of agilent technologies, amba ? , arm ? , multi-ice ? , primecell ? , realview ? , thumb ? of arm limited, uk. autosar ? is licensed by autosar development partnership. bluetooth ? of bluetooth sig inc. cat-iq ? of dect forum. colossus ? , firstgps ? of trimble navigation ltd. emv ? of emvco, llc (visa holdings inc.). epcos ? of epcos ag. flexgo ? of microsoft corporation. flexray ? is licensed by flexray consortium. hyperterminal ? of hilgraeve incorporated. iec ? of commission electrotechnique internationale. irda ? of infrared data association corporation. iso ? of international organization for standardization. matlab ? of mathworks, inc. maxim ? of maxim integrated products, inc. microtec ? , nucleus ? of mentor graphics corporation. mifare ? of nxp. mipi ? of mipi alliance, inc. mips ? of mips technologies, inc., usa. murata ? of murata manufacturing co., microwave office ? (mwo) of applied wave research inc., omnivision ? of omnivision technologies, inc. openwave ? openwave systems inc. red hat ? red hat, inc. rfmd ? rf micro devices, inc. sirius ? of sirius sattelite radio inc. solaris ? of sun microsystems, inc. spansion ? of spansion llc ltd. symbian ? of symbian software limited. taiyo yuden ? of taiyo yuden co. teaklite ? of ceva, inc. tektronix ? of tektronix inc. toko ? of toko kabushiki kaisha ta. unix ? of x/open company limited. verilog ? , palladium ? of cadence design systems, inc. vlynq ? of texas instruments incorporated. vxworks ? , wind river ? of wind river systems, inc. zetex ? of diodes zetex limited. last trademarks update 2010-06-09
PX3519 applications datasheet 4 revision 2.2, 2014-09-19 1 applications ? desktop and server vr12.x vcore and non-vcore buck-converters ? network and telecom processor vr ? single phase and multiphase pol ? cpu/gpu regulation in notebook, graphics cards and gaming ? voltage modules requiring high power density ? memory (ddr2/3) 2 features ? high frequency operation: up to 1.2mhz ? capability to drive mosfet for 50a per phase ? wide vcc input voltage range: 4.5v to 9v ? wide input voltage range: up to 13.2v ? low power dissipation ? includes bootstrap diode ? gate disable pin for fast low side switch off ? adaptive shoot through protection ? compatible to standard +3.3v controller. ? tri-state pwm input functionality ? small package: 3mmx3mm vdson-8 ? rohs compliant table 1 product identification part number temp range package marking px351 9 -25 to 125 ? c 3x3 8-leads vdson-8 3519 figure 1 picture of the product
PX3519 description datasheet 5 revision 2.2, 2014-09-19 3 description 3.1 pinout figure 2 pinout, numbering and name of pins (transparent top view) table 2 i/o signals pin no. name pin type buffer type function 1 boot o analog floating bootstrap supply pin for the upper gate drive . connect the bootstrap capacitor 1) between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. see the internal bootstrap device section herein for guidance in choosing the capacitance value. 2 pwm i logic pwm drive logic input connect this pin to the pwm output from the controller. 3 en i logic enable signal used to activate the device. when connected to high level the status of the driver outputs (ugate, lgate), is determined by the pwm. when connected to low level the driver outputs are disabled regardless of signal levels on pwm input. en input must be driven high or low and must not be left floating. 5 lgate o analog low side gate signal connect to the gate of the low-side power n-channel mosfet 7 phase i analog return path for the upper gate driver. connect this pin to the source of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate drive. 8 ugate o analog upper gate drive output. connect to the gate of high-side power n-channel mosfet 1) see section 5.2 for guidance in choosing capaciatance value
PX3519 description datasheet 6 revision 2.2, 2014-09-19 table 3 power supply pin no. name pin type buffer type function 4 vcc power - supply for housekeeping/logic and driver sections power to the ic. connect to +4.5v ? 8v. place a high quality low esr ceramic capacitor from this pin to gnd. table 4 ground pins pin no. name pin type buffer type function 6 gnd gnd - gnd connection. can be left open since main gnd connection to circuit board is via die pad. must not be used as single ground connection. - die pad gnd - bias and reference ground. all signals are referenced to this node. it is also the power ground return of the driver. it is mandatory to connect the die paddle electrically and thermally to the circuit board. 3.2 general description the PX3519 is a dual high speed driver designed to drive a wide range of high-side and low-side power n- channel mosfets in synchronous rectified buck converters. when combined with the infineon px38xx/px88xx family of digital multi-phase controllers or px75xx digital point of load (dipol ? ) controllers and n-channel mosfets, the PX3519 forms a complete core-voltage regulator solution for advanced micro and graphics processors as well as point-of-load applications. the PX3519 provides the capability of driving the high-side gate and low-side gate with a variable gate driving voltage, ranging from 4.5v up to 8v, to tailor the efficiency of the system based on the customer conditions and needs.the input voltage for the power stage can range from 5v up to 13.2v. adaptive shoot-through protection is integrated into the ic which prevents both upper and lower mosfets from conducting simultaneously while minimizing dead time. an enable pin is provided to switch off the outputs of the driving stage.
PX3519 description datasheet 7 revision 2.2, 2014-09-19 figure 3 simplified block diagram shoot through protection unit hs logic ls logic - ls driver hs driver uvlo input logic 3 state phase
datasheet 4 4.1 stresses above those listed in device. these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended device. table 5 parameter vcc supply voltage (dc) boot voltage boot boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc v en junction temperature storage temperature 2) figure 4 datasheet 4 4.1 stresses above those listed in device. these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended device. table 5 parameter vcc supply voltage (dc) boot voltage boot boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc v pwm en junction temperature storage temperature 2) the pulse duration is 2ns for the minimum and 10ns for the maximum. figure 4 datasheet 4.1 stresses above those listed in device. these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended device. table 5 parameter vcc supply voltage (dc) boot voltage boot boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc pwm junction temperature storage temperature the pulse duration is 2ns for the minimum and 10ns for the maximum. figure 4 datasheet stresses above those listed in device. thes these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended device. table 5 parameter vcc supply voltage (dc) boot voltage voltage, pulsed boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc junction temperature storage temperature the pulse duration is 2ns for the minimum and 10ns for the maximum. figure 4 datasheet stresses above those listed in thes these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended parameter vcc supply voltage (dc) boot voltage voltage, pulsed boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc junction temperature storage temperature the pulse duration is 2ns for the minimum and 10ns for the maximum. electrical specification absolute maximum ratings stresses above those listed in thes e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings vcc supply voltage (dc) boot voltage , dc voltage, pulsed boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc junction temperature storage temperature the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r electrical specification absolute maximum ratings stresses above those listed in e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings vcc supply voltage (dc) , dc voltage, pulsed boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc junction temperature storage temperature the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r electrical specification absolute maximum ratings stresses above those listed in e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings vcc supply voltage (dc) voltage, pulsed boot to phase voltage phase voltage, dc phase voltage, pulsed lgate voltage, dc hgate voltage to phase, dc junction temperature storage temperature the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r electrical specification absolute maximum ratings stresses above those listed in e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings vcc supply voltage (dc) voltage, pulsed boot to phase voltage phase voltage, pulsed hgate voltage to phase, dc the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r typical server vcore application electrical specification absolute maximum ratings stresses above those listed in e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings vcc supply voltage (dc) boot to phase voltage hgate voltage to phase, dc the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r typical server vcore application electrical specification absolute maximum ratings stresses above those listed in e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings hgate voltage to phase, dc the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r typical server vcore application electrical specification absolute maximum ratings stresses above those listed in table 5 e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings hgate voltage to phase, dc the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r typical server vcore application conditions electrical specification absolute maximum ratings table 5 e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings symbol v vcc v boot v boot v boot v phase v phase l gate h gate v t t t t the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r typical server vcore conditions electrical specification absolute maximum ratings table 5 e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings symbol vcc boot boot boot phase phase gate gate v en t ttb jmax t ttb stg the pulse duration is 2ns for the minimum and 10ns for the maximum. safe operating area of r phase typical server vcore conditions electrical specification absolute maximum ratings table 5 ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings symbol boot boot boot - v phase phase gate gate - v jmax tb stg tb the pulse duration is 2ns for the minimum and 10ns for the maximum. phase typical server vcore conditions electrical specification absolute maximum ratings ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended absolute maximum ratings (tambient =25c) symbol v phase v phase the pulse duration is 2ns for the minimum and 10ns for the maximum. phase typical server vcore conditions electrical specification absolute maximum ratings ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s to the absolute maximum ratings for extended periods may adversely affect the operation and reliability of the (tambient =25c) phase phase the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the (tambient =25c) the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the (tambient =25c) min. - 0.3 - 0.3 - 0.3 - 0.3 - 1 - 12 - 0.3 - 0.3 - 40 - 55 the pulse duration is 2ns for the minimum and 10ns for the maximum. 8 ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the (tambient =25c) min. 0.3 0.3 0.3 0.3 1 12 0.3 0.3 40 55 the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the (tambient =25c) min. typ. ? ? the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the (tambient =25c) typ. ? ? the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the values typ. the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the values max. 9 25 30 9 16 2 9.3 9.3 3.6 3.6 150 150 the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s periods may adversely affect the operation and reliability of the values max. 9 25 30 9 16 2 5 9.3 9.3 3.6 3.6 150 150 the pulse duration is 2ns for the minimum and 10ns for the maximum. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s ections of this specification. periods may adversely affect the operation and reliability of the max. ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the ?absolute maximum ratings? may cause p e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the unit v v v v v v v v v v ? c ? c electr revision 2.2 ?absolute maximum ratings? may cause p ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the unit c c electr revision 2.2 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the note / test condition 2) ? ? electr ical specification revision 2.2 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the note / test condition 2) ? ? ical specification revision 2.2 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the note / test condition ical specification revision 2.2 , 2014 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. periods may adversely affect the operation and reliability of the note / test condition PX3519 ical specification 2014 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at ections of this specification. exposure periods may adversely affect the operation and reliability of the note / test condition s PX3519 ical specification 2014 - 09 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at exposure periods may adversely affect the operation and reliability of the PX3519 ical specification 09 - 19 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at exposure periods may adversely affect the operation and reliability of the PX3519 ical specification 19 ermanent damage to the e are absolute stress ratings only and operation of the device is not implied or recommended at exposure periods may adversely affect the operation and reliability of the
PX3519 electrical specification datasheet 9 revision 2.2, 2014-09-19 note: t on refers to the on-time of the hs-mosfet. for input voltages below 12 v no limits on the duration of t on need to be applied.the relative position of a typical server vcore application conditions v in =12v v out =1.8v f sw =450khz is represented as reference.this safe operating area is verified by design, not 100% tested in production. note: all rated voltages are relative to voltages on the gnd pins unless otherwise specified.
PX3519 electrical specification datasheet 10 revision 2.2, 2014-09-19 4.2 thermal characteristics table 6 thermal characteristics parameter symbol values unit note / test condition min. typ. max. thermal resistance, junction -soldering point 3 js - 7 - k/w - thermal resistance, junction -top of package jtop - 20 - - 4.3 recommended operating conditions and electrical characteristics note: vcc = 5v, tambient = 25c table 7 recommended operating conditions parameter symbol values unit test conditions min. typ. max. supply voltage rising edge between 3.1v and 4.5v : dv cc /dt>5v/100ms t v ttb vcc tb 4.5 - 8 v ? frequency of the pwm f sw - - 1.2 mhz note 4 enable pin voltage t v ttb en b 0 - 3.3 v junction temperature t t ttb jop tb -25 - +125 c ? minimum on time 20 ns note 4 minimum off time 30 ns note 4 table 8 voltage supply and biasing current parameter symbol values unit test conditions min. typ. max. uvlo rising rising edge between 3.1v and 4.5v : dv cc /dt>5v/100ms v uvlo_r - 3.6 4.3 v vcc rising uvl o falling v uvlo_f - 3.2 - vcc falling ic current i vcc_300khz - 2 - ma f sw = 300khz i vcc_pwml - 1.67 - pwm = 0v i vcc_enl_pwml - 1 1 0 0 - a en = 0v pwm=0v i vcc_o - 780 - pwm = open 3 the junction-soldering point is referred to the gnd bottom exposed pad.
PX3519 electrical specification datasheet 11 revision 2.2, 2014-09-19 table 9 logic inputs and threshold parameter symbol values unit test conditions min. typ. max. en input low t v ttb en_l tb 0.8 v input high t v ttb en_h tb 2.0 pwm input low t v ttb pwm_l tb ? ? 0.8 v t v ttb pwm tb falling input high t v ttb pwm_h tb 2.5 ? ? t v ttb pwm tb rising input resistance t r ttb in-pwm tb - 2 . 0 6 - k t v ttb pwm tb = 1 v open voltage t v ttb pwm_o tb ? 1.6 ? v t v ttb pwm_o tb tristate shutdown window tpfpt t v ttb pwm_s tb 1.2 ? 2.0 ? table 10 timing characteristics parameter symbol values unit test conditions min. typ. max. upper gate (ugate) output shutdown hold off time t sshd_u 50 ns note, no load ugate rise time t r_u 10 note 4 , 3nf load ugate fall time t f_u 10 note 4 , 3nf load tri-state to high propagation delay t pdts_u 15 note, no load ugate turn-on propagation delay t pdh_u 15 note, no load ugate turn-off propagation delay t pdl_u 20 note, no load lower gate (lgate) output shutdown hold-off time t sshd_l 50 ns note, no load lgate rise time t r_l 10 note 4 , 3nf load lgate fall time t f_l 5 note 4 , 3nf load tri-state to low propagation delay time t pdts_l 15 note, no load lgate turn-on propagation delay time t pdh_l 15 note, no load lgate turn-off propagation delay time t pdl_l 7 note, no load enable (en) propagation delay time rising falling t pden 15 ns 4) parameter verified by design, not 100% tested in production
PX3519 electrical specification datasheet 12 revision 2.2, 2014-09-19 table 11 output characteristics parameter symbol values unit test conditions min. typ. max. output characteristics upper drive source current i src_ug 2 a note 2 current pulse < 20ns upper drive source impedance r src_ug 0.8 i src_ug = 200ma upper drive sink current i snk_ug 2 a note 2 , current pulse < 20ns upper drive sink impedance r snk_ug 0.6 i sink_ug = 200ma lower drive source current i src_lg 2 a note 2 , current pulse < 40ns lower drive source impedance r src_lg 0.8 i src_ug = 200ma lower drive sink current i snk_lg 4 a note 2 , current pulse < 40ns lower drive sink impedance r snk_lg 0.35 i sink_ug = 200ma
PX3519 theory of operation datasheet 13 revision 2.2, 2014-09-19 5 theory of operation the PX3519 functionality is enabled by the en pin. when the en pin voltage overcomes the rising voltage threshold of the uvlo the driver begins to operate depending on the pwm status and the vcc pin status (vcc has to be higher then the rising threshold voltage). for vcc is recommended to have a slope for the rising edge higher than 5v/100ms around the rising uvlo threshold. the vcc can range between 4.5v and 8v and it is the supply pin for both driver and logic sections. the PX3519 functionality is driven by the pwm signal transitions. when the pwm signal performs a transition between low state to high state (pwm voltage higher than 2.5v) the low side mosfet is turned off, after the turn off delay propagation time. then the high side mosfet is turned on, after the turn on propagation delay time. once the on time is expired the pwm signal provides a transition between the high state to the low state (pwm voltage lower than 0.8v). this will drive the high side mosfet from the on state to the off state, after the turn off propagation delay time. the PX3519 is also capable to drive the two external mosfets both in off state. when the pwm signal enters in the shut down window or tri-state (typically between 1.2v and 2.0v) after the shut down hold off time both mosfets are switched off. this feature is useful when the ic controller wants to reduce the number of active phases in order to reduce the power consumption. in principle the tri-state status can be used also to improve the transition between high loads to low load. the PX3519 implements an embedded resistor network, which forces the pwm pin of the device in the middle of the shut down window if the pwm input from the controller is floating. in order to avoid cross conduction between the high side mosfet and the low side mosfet an anti-shoot- through control is implemented with the adaptive scheme. the adaptive scheme is implemented in order to use a variety of different power mosfets for different kind of conversion. nevertheless the dead time is kept as short as possible in order to increase the efficiency of the overall solution. the driver includes gate drive functionality to protect against shoot through. in order to protect the power stage from overlap, both high side and low side mosfets being on at the same time, the adaptive control circuitry monitors the voltage at the ?phase? pin. when the pwm signal goes low, the high side mosfet will begin to turn off. once the ?phase? pin falls below 1v, the low side mosfet is gated on. additionally, the gate to source voltage of the high side mosfet is also monitored. when vgs (high side) is discharged below 1v, a threshold known to turn the high side mosfet off, a secondary delay is initiated, which results in the low side being gated ?on? regardless of the state of the ?phase? pin. this way it will be ensured that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. during the start up depending on several factors it can be that the power input for the conversion (input rail) rises before the vcc input. in this case it could happen that the high side has an induced turn on. in order to avoid this undesirable effect the PX3519 embeds a resistance of 10 kohm between ugate pin and phase pin. in order to reduce the sensitivity to issues generated during the power on sequence (like the induced turn on of the high side mosfet) and to reduce further the power consumption an en pin is implemented; in this case the designer has the possibility to create a short delay time between the vcc and the en pin voltage to ensure the proper functionality. moreover the en pin can be used to disable the driver stage in case a very low consumption is required. 5.1 driver characteristics the gate driver of the PX3519 has one supply voltage to simplify the layout of the system.the vcc pin is used to power the section related to the logic for detecting the status of pwm pin and en pin. this pin is used also to supply the power section related to the driver of the power mosfet. the mosfets selected for this application are optimized for 5v gate drive, thus giving the end user optimized high load as well as light load efficiency. nevertheless the driving voltage can be increased up to 8v in order to have a customized efficiency curve depending on the application conditions. the reference for the power circuitry including the driver output stage and the reference for the gate driver control circuit is gnd.
PX3519 theory of operation datasheet 14 revision 2.2, 2014-09-19 5.2 current capability and internal bootstrap the PX3519 implements high current capability and low ohmic pull down resistances for the driving stages. the high current capability ensures fast switching transition for the mosfets in order to reduce the switching losses (2a of driving source/sink current for the upper mosfet) even with high gate charge high side. the low ohmic pull down resistance (low driver sink impedance 0.35 ohm) is mainly important to avoid the induced turn on phenomenon on the low side during the fast turn on of the high side mosfet. the high side is powered through the bootstrap circuitry. the PX3519 provides an embedded bootstrap diode. to complete the power network only a capacitance between phase and boot is needed. in many cases the PX3519 is optimized for the best switching behavior. an external resistance is not needed. the bootstrap capacitance is chosen depending on the high side gate charge. the following formula is giving a good estimation of the voltage drop across the bootstrap capacitance due to the charging of the high side: where the ? vboot is the desired variation of the bootstrap voltage. the low side driver is powered through the vcc pin. the same considerations and formula done for the bootstrap capacitance can be done for the capacitance used to filter the vcc pin. the flexibility to adjust the driving voltage from 4.5v to 8v gives designers the possibility to shape the efficiency curve in anyway that is desired. 5.3 power dissipation the power dissipation of the driver is given by the gate charge of the external power mosfets. the following formulas held: where fsw is the switching frequency and qghs and qgls are respectively the gate charge of the high side and the gate charge of the low side at the vcc driving voltage. the very low thermal resistance package used for the PX3519 allows the device to avoid any usage of external resistances to decrease the power dissipation inside the driver even with high driving voltage. since the thermal resistance is strongly influenced by the numbers of layers used in the board, it is recommended to check roughly the expected junction temperature via the power calculation. 5.4 inputs to the internal control circuits the pwm is the control input to the ic from an external pwm controller and is compatible with 3.3v. the pwm input has tri-state functionality. when the voltage remains in the specified pwm-shutdown-window for at least the pwm-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both mosfet gate outputs low. once left open, the pin is internally fixed to v pwm_o = 1.6 v level. table 12 pwm pin functionality pwm logic level driver output low lgate= high, ugate = low high lgate = low, ugate = high open (left floating, or high impedance) lgate = low, ugate = low during power-up sequence, the initial state of the pwm signal is ignored, until the first rising edge. since all the thresholds are derived from an internal linear regulator they will not depend on the vcc input.
PX3519 theory of operation datasheet 15 revision 2.2, 2014-09-19 5.5 enable pin the en pin has the main function to control the driver stage itself and enables operation. once the voltage across the en pin is higher than the rising edge threshold of the en pin and the voltage across the vcc pin is above the rising edge threshold of the uvlo, the driver stage turns on and off the mosfet based on the pwm status. the en pin can not be left floating. the enable can be used for three different purposes: 1. power sequence: it can be delayed in order to turn on the power stage once vcc is at the expected level. this will reduce the probability of improper turn on sequences or oscillation created by unstable conditions. 2. power saving: there are two ways of disabling the driver stage: the first one is through the pwm signal; once the pwm signal is in the tri-state window the gate activity is stopped. the second one is the en pin; once the enable pin is pulled below the falling edge threshold the driver stage is completely switched off. the difference between the two methods is basically that the pwm still leaves alive all the comparators and the auxiliary voltages, so that the consumption of the power stage is not at the minimum level. 3. zero cross: if the controller is capable to detect the crossing of the inductor current, the en pin could be used to switch off the low side mosfet faster than the pwm (due to the hold off time)in order to avoid the current reverse. figure 5 enable pin 5.6 layout consideration the PX3519 has a good protection system against unwanted overshoot and undershoot; the phase pin can range between dynamically -12v to 25v. the parasitic inductances of the pcb and of the power devices? packaging (both upper and lower mosfets) can cause serious ringing, exceeding absolute maximum rating of the devices. careful layout can help minimize such unwanted stress. the following advice is meant to lead to an optimized layout: keep decoupling loops (vcc-gnd and boot-phase) as short as possible and use high quality ceramic capacitance with low esr (10mohm) and low esl (lower than 1nh). minimize trace inductance, especially on low-impedance lines. all power traces (ugate, phase, lgate, gnd, vcc) should be short and wide, as much as possible. minimize the area of the phase node. ideally, the source of the upper and the drain of the lower mosfet should be as close as close as possible.minimize the current loop of the output and input power trains. short the source connection of the lower mosfet to ground as close to the transistor pin as feasible. input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower mosfets as possible. to optimize heat spreading, copper should be placed directly underneath the ic whether it has an exposed pad or not. the copper area can be extended beyond the bottom area of the ic and/or connected to buried copper plane(s) with thermal vias. this combination of vias for vertical heat escape, extended copper plane, and buried planes for heat spreading allows the ic to achieve its full thermal potential. vcc ?h? ?l? v en_ f v en_r en logic level shutdown enable
PX3519 application datasheet 16 revision 2.2, 2014-09-19 6 application figure 6 pin interconnection outline (transparent top view)
PX3519 gate driver timing diagram datasheet 17 revision 2.2, 2014-09-19 7 gate driver timing diagram figure 7 adaptive gate driver timing diagram pwm gl gh vswh 1 v 1 v v pwm_l t _ pdhl t_tsshd t _ pdll t _ pdhu t _ pdlu v pwm_h v pwm_h v pwm_l t_tsshd t_pts t_pts pwm gl gh vswh 1 v 1 v three-state v pwm_l t _ pdhl t_tsshd t _ pdll t _ pdhu t _ pdlu v pwm_h v pwm_h v pwm_l t_tsshd t_pts t_pts
PX3519 enable timing diagram datasheet 18 revision 2.2, 2014-09-19 8 enable timing diagram figure 8 enable vs pwm timing diagram pwm gh pwm gh t pden en gl t pden v pwm_h v v pwm_l v v en_h v v en_l v
PX3519 mechanical drawing datasheet 19 revision 2.2, 2014-09-19 9 mechanical drawing figure 9 mechanical dimensions
PX3519 mechanical drawing datasheet 20 revision 2.2, 2014-09-19 figure 10 footprint and solder stencil recommendations
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