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this is information on a product in full production. november 2014 docid16891 rev 30 1/45 m24c64-w m24c64-r m24c64-f m24c64-df 64-kbit serial i2c bus eeprom datasheet - production data features ? compatible with all i 2 c bus modes: ?1 mhz ? 400 khz ? 100 khz ? memory array: ? 64 kbit (8 kbytes) of eeprom ? page size: 32 bytes ? additional write lockable page (m24c64-d order codes) ? single supply voltage: ? 1.7 v to 5.5 v over ?40 c / +85 c ? 1.6 v to 5.5 v over 0 c / +85 c ? write: ? byte write within 5 ms ? page write within 5 ms ? random and sequential read modes ? write protect of the whole memory array ? enhanced esd/latch-up protection ? more than 4 million write cycles ? more than 200-year data retention packages ? pdip8 ecopack1 ? ? so8 ecopack2 ? ? tssop8 ecopack2 ? ? ufdfpn8 ecopack2 ? ? wlcsp ecopack2 ? ? ufdfpn5 ecopack2 ? pdip8 (bn) so8 (mn) 150 mil width tssop8 (dw) 169 mil width ufdfpn8 (mc) wlcsp (cs) thin wlcsp (ct) ufdfpn5 (mh) www.st.com
contents m24c64-w m24c64-r m24c64-f 2/45 docid16891 rev 30 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e2, e1, e0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 write identification page (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 lock identification page (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . 17 5.1.6 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 18 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid16891 rev 30 3/45 m24c64-w m24c64-r m24c64-f 3 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 read identification page (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 read the lock status (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of tables m24c64-w m24c64-r m24c64-f 4/45 docid16891 rev 30 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. operating conditions (voltage range w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. operating conditions (voltage range r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. operating conditions (voltage range f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. dc characteristics (m24c64-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. dc characteristics (m24c64-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. dc characteristics (m24c64-f, m24c64-df, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 28 table 16. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. ufdfpn5 (mlp5) ? package dime nsions (ufdfpn: ult ra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 19. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 34 table 20. so8n ? 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 35 table 21. pdip8 ? 8-pin plastic dip, 0.25 mm lead fram e, package mechanical data. . . . . . . . . . . . 36 table 22. ufdfpn8 (mlp8) ? package dime nsions (ufdfpn: ult ra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 23. wlcsp 5-bump wafer-length chip-scale package mechanical data (m24c64-fcs6tp/k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 24. thin wlcsp 8-bump wafer-length chip-scale package mechanical data (m24c64-dfct6tp/k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 25. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 26. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
docid16891 rev 30 5/45 m24c64-w m24c64-r m24c64-f 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. ufdfpn5 package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. 5-bump wlcsp connections (m24c64-fcs6tp/k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. 8-bump thin wlcsp connections (m24c64-dfct6tp/k ) . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. maximum rbus value versus bus pa rasitic capacitance (cbus) for an i2c bus at maximum frequency fc = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. ufdfpn5 (mlp5) ? package outline (ufdfpn: ultra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 35 figure 20. pdip8 ? 8-pin plastic dip, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 36 figure 21. ufdfpn8 (mlp8) ? package outline (ufdfpn: ultra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 22. wlcsp 5-bump wafer-length chip-scale package outline (m24c64-fcs6tp/k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 23. thin wlcsp 8-bump wafer-length chip-scale package outline (m24c64-dfct6tp/k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
description m24c64-w m24c64-r m24c64-f 6/45 docid16891 rev 30 1 description the m24c64 is a 64-kbit i 2 c-compatible eeprom (electri cally erasable programmable memory) organized as 8 k 8 bits. over an ambient temperature range of -40 c / +85 c, the m24c64-w can operate with a supply voltage from 2.5 v to 5.5 v, the m24c64-r can operate with a supply voltage from 1.8 v to 5.5 v, and the m24c64-f and m24c64 -df can operate with a supply voltage from 1.7 v to 5.5 v ( the m24c64-f can also operate down to 1.6 v, under some restricting conditions). the m24c64-d offers an additional page, named the identification page (32 bytes). the identification page can be used to store se nsitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram table 1. signal names signal name function direction e2, e1, e0 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage - v ss ground - $,i (( 6'$ 9&& 0[[[ :& 6&/ 966
docid16891 rev 30 7/45 m24c64-w m24c64-r m24c64-f 44 figure 2. 8-pin package connections, top view 1. see section 9: package mechanical data for package dimensions, and how to identify pin 1 figure 3. ufdfpn5 package connections note: inputs e2, e1, e0 are not connected, therefore read as (000). please refer to section 2.3 for further explanations. figure 4. 5-bump wlcsp connections (m24c64-fcs6tp/k) note: inputs e2, e1, e0 are internally connected to (001). please refer to section 2.3 for further explanations. figure 5. 8-bump thin wlcsp connections (m24c64-dfct6tp/k) $,i 6'$ 966 6&/ :& ( ( 9&& ( -36 3$! 3#, 7# 6 ## 6 33 6 33 4opview markingside "ottomview padsside !"#$ 89:7 069 ^ ^> s s ^^ t %xpsvlgh erwwrpylhz s s ^^ ^ t ^> 0dunlqjvlgh wrsylhz 069 t 9&& ^ ^> s^^ ? t s ^ ^> s^^ ? %xpsvlgh erwwrpylhz 0dunlqjvlgh wrsylhz
signal description m24c64-w m24c64-r m24c64-f 8/45 docid16891 rev 30 2 signal description 2.1 serial clock (scl) the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be co nnected from serial data (sda) to v cc ( figure 14 indicates how to calculate the value of the pull-up resistor). 2.3 chip enable (e2, e1, e0) (e2,e1,e0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see table 2 ). these inputs must be tied to v cc or v ss , as shown in figure 6 . when not connected (left floating), these inputs are read as low (0). for the 5-balls wlcsp package (see figure 3 ), the (e2,e1,e0) inputs are internally connected to (0,0,1). figure 6. chip enab le inputs connection 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disa bled to the entire memory array when write control ( wc ) is driven high. write operations are enabled when write control ( wc ) is either driven low or left floating. when write control ( wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. $l 9&& 0[[[ 966 (l 9&& 0[[[ 966 (l
docid16891 rev 30 9/45 m24c64-w m24c64-r m24c64-f 44 2.5 v ss (ground) v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 8: dc and ac parameters ) . in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ) and the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 8: dc and ac parameters ). in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the power-on-reset threshold voltage, the device stops resp onding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
memory organization m24c64-w m24c64-r m24c64-f 10/45 docid16891 rev 30 3 memory organization the memory is organized as shown below. figure 7. block diagram -36 7# #ontrollogic (ighvoltage generator )/shiftregister !ddressregister andcounter $ata register page 8decoder 9decoder )dentificationpage % % 3#, 3$! %
docid16891 rev 30 11/45 m24c64-w m24c64-r m24c64-f 44 4 device operation the device supports the i 2 c protocol. this is summarized in figure 8 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a dat a transfer can only be initia ted by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 8. i 2 c bus protocol 3#, 3$! 3#, 3$! 3$! 34!24 #ondition 3$! )nput 3$! #hange !)" 34/0 #ondition -3" !#+ 34!24 #ondition 3#, -3" !#+ 34/0 #ondition
device operation m24c64-w m24c64-r m24c64-f 12/45 docid16891 rev 30 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is followed by noack can be fo llowed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
docid16891 rev 30 13/45 m24c64-w m24c64-r m24c64-f 44 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start conditio n. following this, the bus master s ends the device select code, shown in table 2 (on serial data (sda), most significant bit first). when the device select code is received, the device only responds if the chip enable address is the same as the value on its chip enable e2,e1,e0 inputs. the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, the device deselects itself from the bus, and goes into standby mode. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0, e1 and e2 are compared with the value read on input pins e0, e1,and e2. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code when addressing the memory array 1010e2e1e0rw device select code when accessing the identification page 1011e2e1e0rw
instructions m24c64-w m24c64-r m24c64-f 14/45 docid16891 rev 30 5 instructions 5.1 write operations following a start condition the bus master sends a device select code with the r/ w bit (r w ) reset to 0. the device acknowledges this, as shown in figure 9 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is triggered. a stop condition at any othe r time slot does not trigger the internal write cycle. after the stop condition and the successful completion of an internal write cycle (t w ), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 10 . table 3. most significant address byte a15 a14 a13 a12 a11 a10 a9 a8 table 4. least significant address byte a7 a6 a5 a4 a3 a2 a1 a0
docid16891 rev 30 15/45 m24c64-w m24c64-r m24c64-f 44 5.1.1 byte write after the device select code and the address byte s, the bus master send s one data byte. if the addressed location is write-protected, by write control ( wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 9 . figure 9. write mode sequences with wc = 0 (data write enabled) 3top 3tart "yte7rite $evsel "yteaddr "yteaddr $atain 7# 3tart 0age7rite $evsel "yteaddr "yteaddr $atain 7# $atain !)d 0age7ritecontgd 7#contgd 3top $atain. !#+ 27 !#+ !#+ !#+ !#+ !#+ !#+ !#+ 27 !#+ !#+
instructions m24c64-w m24c64-r m24c64-f 16/45 docid16891 rev 30 5.1.2 page write the page write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a15/a5, are the same. if more bytes are se nt than will fit up to the end of the page, a ?roll-over? occurs, i.e. the by tes exceeding the page end are written on the same page, from location 0. the bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the device if write control ( wc ) is low. if write control ( wc ) is high, the contents of the addressed memory location are not modified, an d each data byte is followed by a noack, as shown in figure 10 . after each transferred byte, the internal page address counter is incremented. the transfer is terminated by the bu s master generating a stop condition. figure 10. write mode sequences with wc = 1 (data write inhibited) 3top 3tart "yte7rite $evsel "yteaddr "yteaddr $atain 7# 3tart 0age7rite $evsel "yteaddr "yteaddr $atain 7# $atain !)d 0age7ritecontgd 7#contgd 3top $atain. !#+ !#+ !#+ ./!#+ 27 !#+ !#+ !#+ ./!#+ 27 ./!#+ ./!#+
docid16891 rev 30 17/45 m24c64-w m24c64-r m24c64-f 44 5.1.3 write identificati on page (m24c64-d only) the identification page (32 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. it is writ ten by issuing the write identification page instruction. this instruction us es the same protocol and format as page write (into memory array), except for the following differences: ? device type identifier = 1011b ? msb address bits a15/a5 are don't care except for address bit a10 which must be ?0?. lsb address bits a4/a0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). 5.1.4 lock identificati on page (m24c64-d only) the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is si milar to byte write (into memory array) with the following specific conditions: ? device type identifier = 1011b ? address bit a10 must be ?1?; all other address bits are don't care ? the data byte must be equal to the binary value xxxx xx1x, where x is don't care 5.1.5 ecc (error correction code) and write cycling the ecc is offered only in devices identified with process letter k, all other devices (identified with a different process letter) do not embed the ecc logic. the error correction code (ecc) is an internal logic function which is transparent for the i 2 c communication protocol. the ecc logic is implemented on each group of four eeprom bytes (1) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on group s of four bytes, a single byte can be written/cycled independently. in this case, th e ecc function also writes/cycles the three other bytes located in the same group (1) . as a consequence, the maximum cycling budget is defined at group level and the cycling can be di stributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined table 11: cycling performance . 1. a group of four bytes is located at addresses [4 *n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
instructions m24c64-w m24c64-r m24c64-f 18/45 docid16891 rev 30 5.1.6 minimizing write delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its intern al latches to the memory ce lls. the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to make use of this, a pollin g sequence can be used by the bus master. the sequence, as shown in figure 11 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 11. write cycle polling flowchart using ack 1. the seven most significant bits of the device se lect code of a random read (bottom right box in the figure) must be identical to the seven most significant bi ts of the device select code of the write (polling instruction in the figure). t?]??o ]v??}p??? $,h e?? k???]}v]? ???]vp?z uu}?? ^???}v]?]}v ]?o? ]?zzta < ???v z^ ek z^ ek z^??? ^?}? ?(}??z t?]????]}v 'hylfhvhohfw zlwk5: ^v??? vz]< z^ ek 6wduw&rqglwlrq }v?]v?z t?]?}???]}v }v?]v?z zv}uz}???]}v )luvwe\whrilqvwuxfwlrq zlwk5: douhdg\ ghfrghge\wkhghylfh
docid16891 rev 30 19/45 m24c64-w m24c64-r m24c64-f 44 5.2 read operations read operations are performed independently of the state of the write control ( wc ) signal. after the successful completion of a read oper ation, the device internal address counter is incremented by one, to point to the next byte address. for the read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. if the bus master does not acknowledge during this 9th time, the device terminates t he data transfer and switches to its standby mode. figure 12. read mode sequences start dev sel * byte addr byte addr start dev sel data out 1 ai01105d data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequention random read start dev sel * data out1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
instructions m24c64-w m24c64-r m24c64-f 20/45 docid16891 rev 30 5.2.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 12 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the r w bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/ w bit set to 1. the device acknowledges this, and outputs the byte addressed by the inter nal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition , as shown in figure 12 , without acknowledging the byte. note that the address counter value is defined by instructions accessing either the memory or the identification page. when accessing the identification page, the address counter value is loaded with the byte location in the identification page, therefore the next current address read in the memory uses this new address counter value. when accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory, see section 5.2.1 ) instead of the current address read instruction. 5.2.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next by te in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 12 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.3 read identification page (m24c64-d only) the identification page (32 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. the identification page can be re ad by issuing an read identifica tion page instruction. this instruction uses the same protocol and form at as the random address read (from memory array) with device type identifier defined as 1011b. the msb address bits a15/a5 are don't care, the lsb address bits a4/a0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g.: when reading the identification page from location 10 d, the number of bytes should be less than or equal to 22, as the id page boundary is 32 bytes).
docid16891 rev 30 21/45 m24c64-w m24c64-r m24c64-f 44 5.4 read the lock status ( m24c64-d only) the locked/unlocked status of the identifica tion page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. the device returns an acknowledge bit if the identification page is unlocked, otherwise a noack bit if the identification page is locked. right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: ? start: the truncated command is not execut ed because the start condition resets the device internal logic, ? stop: the device is then set back into standby mode by the stop condition. 6 initial delivery state the device is delivered with all the memory array bits and identification page bits set to 1 (each byte contains ffh).
maximum rating m24c64-w m24c64-r m24c64-f 22/45 docid16891 rev 30 7 maximum rating stressing the device outside the ratings listed in table 5 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for small b ody, sn-pb or pb-free assembly), the st ecopack? 7191395 specification, and the european directive on re strictions of hazardous substances (rohs directive 2011/65/eu of july 2011). c pdip-specific lead temperature during soldering - 260 (2) 2. t lead max must not be applied for more than 10 s. c i ol dc output current (sda = 0) - 5 ma v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (3) 3. positive and negative pulses applied on different co mbinations of pin connections, according to aec- q100-002 (compliant with ansi/esda/jede c js-001-2012 standard, c1=100 pf, r1=1500 ). - 3000 (4) 4. 4000 v for devices identified with process letter k and p. v
docid16891 rev 30 23/45 m24c64-w m24c64-r m24c64-f 44 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. table 6. operating conditions (voltage range w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 1 (1) 1. f cmax is 400 khz devices identified by process letter p. mhz table 7. operating conditions (voltage range r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 1 (1) 1. f cmax is 400 khz devices identified by process letter p. mhz table 8. operating conditions (voltage range f) symbol parameter min. max. unit v cc supply voltage 1.6 (1) 1. only for devices identified with process letter t 1.7 5.5 v t a ambient operating temperature:read -40 -40 85 c ambient operating temperature: write 0 -40 85 f c operating clock frequency @1.6 v (1) -400 khz operating clock frequency @1.7 v - 1000
dc and ac parameters m24c64-w m24c64-r m24c64-f 24/45 docid16891 rev 30 figure 13. ac measurement i/o waveform table 9. ac measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf - scl input rise/fall time, sda input fall time - 50 ns - input levels 0.2 v cc to 0.8 v cc v - input and output timing reference levels 0.3 v cc to 0.7 v cc v table 10. input parameters symbol parameter (1) 1. characterized only, not tested in production. test condition min. max. unit c in input capacitance (sda) - - 8 pf c in input capacitance (other pins) - - 6 pf z l input impedance (e2, e1, e0, wc ) (2) 2. e2, e1, e0 input impedance when the memory is selected (after a start condition). v in < 0.3 v cc 30 - k z h v in > 0.7 v cc 500 - k -36 6 ## 6 ## 6 ## 6 ## )nputandoutput 4imingreferencelevels )nputvoltagelevels
docid16891 rev 30 25/45 m24c64-w m24c64-r m24c64-f 44 table 11. cycling performance symbol parameter test condition max. (1) 1. cycling performance for products ident ified by process letter k or t (pre vious products were specified with 1 million cycles at 25 c) unit ncycle write cycle endurance (2) 2. the write cycle endurance is defined by characterization and qualificat ion. for devices embedding the ecc functionality (see chapter 5.1.5 ), the write cycle endurance is defined for group of four bytes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer. t a 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycle (3) 3. a write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page instruction is decoded. when usi ng the byte write, the page write or the write identification page, refer also to section 5.1.5: ecc (error corr ection code) and write cycling t a = 85 c, v cc (min) < v cc < v cc (max) 1,200,000 table 12. memory ce ll data retention parameter test condition min. unit data retention (1) 1. the data retention behavior is checked in production, while the data retent ion limit defined in this table is extracted from characteriza tion and qualification results. t a = 55 c 200 (2) 2. for products identified by process letter k or t (previ ous products were specified with a data retention of 40 years at 55c). year
dc and ac parameters m24c64-w m24c64-r m24c64-f 26/45 docid16891 rev 30 table 13. dc characteristics (m24c64-w, device grade 6) symbol parameter test conditions (in addition to those in table 6 ) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc , device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) 2.5 v < v cc < 5.5 v, f c = 400 khz (rise/fall time < 50 ns) -2ma 2.5 v < v cc < 5.5 v, f c = 1 mhz (1) (rise/fall time < 50 ns) 1. for devices identified with process letter k or t. -2.5ma i cc0 supply current (write) (2) 2. for devices identified with process letter k or t during t w , 2.5 v v cc 5.5 v -2.5 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 2.5 v 4. the device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -2a device not selected (4) , v in = v ss or v cc , v cc = 5.5 v -3 (5) 5. previous products (identified with pr ocess letter p) offer icc1(max) = 5 a a v il input low voltage (scl, sda, wc , e2, e1, e0) (6) 6. e i inputs should be tied to v ss (see section 2.3 ). - ?0.45 0.3 v cc v v ih input high voltage (scl, sda) -0.7 v cc 6.5 v input high voltage (wc , e2, e1, e0) (7) 7. e i inputs should be tied to v cc (see section 2.3 ). -0.7 v cc v cc +0.6 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v or i ol = 3 ma, v cc = 5.5 v -0.4v
docid16891 rev 30 27/45 m24c64-w m24c64-r m24c64-f 44 table 14. dc characteristics (m24c64-r, device grade 6) symbol parameter test conditions (1) (in addition to those in table 7 ) 1. if the application uses the voltage range r device with 2.5 v < v cc < 5.5 v and -40 c < t a < +85 c, please refer to table 13 instead of this table. min. max. unit i li input leakage current (e0, e1, e2, scl, sda) v in = v ss or v cc , device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) v cc = 1.8 v, f c = 400 khz - 0.8 ma f c = 1 mhz (2) 2. only for devices operating at f c max = 1 mhz (see note (1) in table 17 ). -2.5ma i cc0 supply current (write) (3) 3. for devices identified with process letter k or t during t w , 1.8 v v cc 2.5 v -1.5 (4) 4. characterized value, not tested in production. ma i cc1 standby supply current device not selected (5) , v in = v ss or v cc , v cc = 1.8 v 5. the device is not selected after power-up, after a re ad instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -1a v il input low voltage (scl, sda, wc , e2, e1, e0) (6) 6. e i inputs should be tied to v ss (see section 2.3 ). 1.8 v v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) 1.8 v v cc < 2.5 v 0.75 v cc 6.5 v input high voltage (wc ) (7) 7. e i inputs should be tied to v cc (see section 2.3 ). 1.8 v v cc < 2.5 v 0.75 v cc v cc + 0.6 v v ol output low voltage i ol = 1 ma (8) , v cc = 1.8 v 8. i ol = 0.7 ma for previous devices (identified by process letter p). -0.2v
dc and ac parameters m24c64-w m24c64-r m24c64-f 28/45 docid16891 rev 30 table 15. dc characteristics (m24c64-f, m24c64-df, device grade 6) symbol parameter test conditions (1) (in addition to those in table 8 ) 1. if the application uses the voltage range f device with 2.5 v < v cc < 5.5 v and -40 c < t a < +85 c, please refer to table 13 instead of this table. min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) v cc = 1.6 v or 1.7 v, f c = 400 khz - 0.8 ma f c = 1 mhz (2) 2. only for devices identified by process letter k or t (see table 17 ). -2.5ma i cc0 supply current (write) during t w vcc < 2.5 v - 1.5 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 1.6 v or 1.7 v 4. the device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -1a v il input low voltage (scl, sda, wc, e i ) (5) 5. e i inputs should be tied to v ss (see section 2.3 ). v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) v cc < 2.5 v 0.75 v cc 6.5 v input high voltage (wc, e2, e1, e0) (6) 6. e i inputs should be tied to v cc (see section 2.3 ). v cc < 2.5 v 0.75 v cc v cc +v v ol output low voltage i ol = 1 ma, v cc = 1.6 v or 1.7 v - 0.2 v
docid16891 rev 30 29/45 m24c64-w m24c64-r m24c64-f 44 table 16. 400 khz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (1) 1. characterized only, not tested in production. t f sda (out) fall time 20 (2) 2. with c l = 10 pf. 300 ns t xh1xh2 t r input signal rise time (3) 3. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz. (3) ns t xl1xl2 t f input signal fall time (3) (3) ns t dxch t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. to avoid spurious start and stop conditions, a mini mum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 50 (5) 5. the previous products were specified with t clqx longer than 50 ns. it should be noted that any t clqx value longer than 50ns offers a safe margin when comp ared to the i2c-bus specification recommendations. -ns t clqv (6) 6. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3v cc or 0.7v cc , assuming that r bus c bus time constant is within the values specified in figure 14. t aa clock low to next data valid (access time) - 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t wldl (7)(1) 7. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (8)(1) 8. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr internal write cycle duration - 5 ms t ns (1) pulse width ignored (input filter on scl and sda) - single glitch -50 (9) 9. the previous products were specified with tns longer than 50 ns. it should be noted that the i2c-bus specification recommends a t ns value longer than 50ns. ns
dc and ac parameters m24c64-w m24c64-r m24c64-f 30/45 docid16891 rev 30 table 17. 1 mhz ac characteristics symbol alt. parameter (1) 1. only for devices identified by the process letter k or t (devices qualified at 1 mhz). min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 260 - ns t clch t low clock pulse width low 500 - ns t xh1xh2 t r input signal rise time (2) 2. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fall times be less than 120 ns when f c < 1 mhz. (2) ns t xl1xl2 t f input signal fall time (2) (2) ns t ql1ql2 (3) 3. characterized only, not tested in production. t f sda (out) fall time 20 (4) 4. with c l = 10 pf. 120 ns t dxch t su:dat data in setup time 50 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (5) 5. to avoid spurious start and stop conditions, a mini mum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 50 (6) 6. the previous products were specified with t clqx longer than 50 ns. it should be noted that any t clqx value longer than 50ns offers a safe margin when comp ared to the i2c-bus specification recommendations. -ns t clqv (7) 7. t clqv is the time (from the falling edge of scl) requi red by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time cons tant is within the values specified in figure 15 . t aa clock low to next data valid (access time) - 450 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t wldl (8)(3) 8. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (9)(3) 9. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr write time - 5 ms t ns (3) pulse width ignored (input filter on scl and sda) -50 (10) 10. the previous products were specified with tns longer than 50 ns. it should be noted that the i2c-bus specification recommends a tns value longer than 50ns. ns
docid16891 rev 30 31/45 m24c64-w m24c64-r m24c64-f 44 figure 14. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 15. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz aib "uslinecapacitorp& "uslinepull upresistor k )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! 2 bus # bus ns (ere2 bus # bus ns k ? p& 4he2x#timeconstant mustbebelowthens timeconstantlinerepresented ontheleft bus bus "uslinecapacitorp& "uslinepull upresistork -36 )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! (ere 2 bus # bus ns 2 bu s # bu s ns 4he2 bus # bus timeconstant mustbebelowthens timeconstantlinerepresented ontheleft
dc and ac parameters m24c64-w m24c64-r m24c64-f 32/45 docid16891 rev 30 figure 16. ac waveforms ^> ^k? ^> ^/v ?o] ?>ys ?>yy ?,, ^?}? }v]?]}v ?,> ^??? }v]?]}v t?]??o ?t /??] ?o] ?y>y>? ^/v ?,> ^??? }v]?]}v ?y, ?>y ^ /v?? ^ zvp ?,, ?,> ^?}? }v]?]}v ^??? }v]?]}v ?y,y,? ^> ?,> ?>> ?>, ?y,y,? ?y>y>? ?y>y>? t ?t>> ?,t, ?,>
docid16891 rev 30 33/45 m24c64-w m24c64-r m24c64-f 44 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 17. ufdfpn5 (mlp5) ? package outline (ufdfpn: ultra thin fine pitch dual flat package, no lead) 1. on the bottom side, pin 1 is identified by the specif ic pad shape and, on the top side, pin 1 is defined from the orientation of the marking: when reading the ma rking, pin 1 is below the upper left package corner. table 18. ufdfpn5 (mlp5) ? package dimensions (ufdfpn: ultra thin fine pitch dual flat package, no lead) symbol millimeters inches (1) 1. typ min max typ min max a 0.550 0.500 0.600 0.0217 0.0197 0.0236 a1 ? 0 0.050 ? 0 0.0020 b 0.220 0.180 0.260 0.0087 0.0071 0.0102 d 1.700 1.600 1.800 0.0669 0.0630 0.0709 d1 1.500 1.400 1.600 0.0591 0.0551 0.0630 e 1.400 1.300 1.500 0.0551 0.0512 0.0591 e1 0.220 0.180 0.260 0.0087 0.0071 0.0102 e 0.400 ? ? 0.0157 ? ? l 0.550 0.500 0.600 0.0217 0.0197 0.0236 k 0.400 ? ? 0.0157 ? ? 7rsylhz pdunlqjvlgh ' ( 6lghylhz $ $ $8.b0(b9 %rwwrpylhz sdgvvlgh ' ( e n / h 3lq 3lq
package mechanical data m24c64-w m24c64-r m24c64-f 34/45 docid16891 rev 30 figure 18. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 19. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ. min. max. typ. min. max. a ? ? 1.200 ? ? 0.0472 a1 ? 0.050 0.150 ? 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b ? 0.190 0.300 ? 0.0075 0.0118 c ? 0.090 0.200 ? 0.0035 0.0079 cp ? ? 0.100 ? ? 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 ? ? 0.0394 ? ? ? 0 8 ? 0 8 #0 c , % % $ ! ! a e b ! , 433/0"-
docid16891 rev 30 35/45 m24c64-w m24c64-r m24c64-f 44 figure 19. so8n ? 8-lead plas tic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 20. so8n ? 8-lead pl astic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a ? ? 1.750 ? ? 0.0689 a1 ? 0.100 0.250 ? 0.0039 0.0098 a2 ? 1.250 ? ? 0.0492 ? b ? 0.280 0.480 ? 0.0110 0.0189 c ? 0.170 0.230 ? 0.0067 0.0091 ccc ? ? 0.100 ? ? 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 ? ? 0.0500 ? ? h ? 0.250 0.500 ? 0.0098 0.0197 k ? 0 8 ? 0 8 l ? 0.400 1.270 ? 0.0157 0.0500 l1 1.040 ? ? 0.0409 ? ? 62$b9 ( fff e ' f ( k[? $ n pp / $ *$8*(3/$1( h $ /
package mechanical data m24c64-w m24c64-r m24c64-f 36/45 docid16891 rev 30 figure 20. pdip8 ? 8-pin plastic dip, 0.25 mm lead frame, package outline 1. drawing is not to scale. 2. not recommended for new designs. table 21. pdip8 ? 8-pin plastic dip, 0.25 mm lead frame, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ. min. max. typ. min. max. a ? ? 5.33 ? ? 0.2098 a1 ? 0.38 ? ? 0.0150 ? a2 3.30 2.92 4.95 0.1299 0.1150 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.0220 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.20 0.36 0.0098 0.0079 0.0142 d 9.27 9.02 10.16 0.3650 0.3551 0.4000 e 7.87 7.62 8.26 0.3098 0.3000 0.3252 e1 6.35 6.10 7.11 0.2500 0.2402 0.2799 e 2.54 ? ? 0.1000 ? ? ea 7.62 ? ? 0.3000 ? ? eb ? ? 10.92 ? ? 0.4299 l 3.30 2.92 3.81 0.1299 0.1150 0.1500 3',3%b9 ? ? ? >
docid16891 rev 30 37/45 m24c64-w m24c64-r m24c64-f 44 figure 21. ufdfpn8 (mlp8) ? package outline (ufdfpn: ultra thin fine pitch dual flat package, no lead) 1. drawing is not to scale. 2. the central pad (area e2 by d2 in the above illustration) is internally pulled to v ss . it must not be connected to any other voltage or signal line on the pcb, for example during the soldering process. table 22. ufdfpn8 (mlp8) ? package dimensions (ufdfpn: ultra thin fine pitch dual flat package, no lead) symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 (rev mc) ? 1.200 1.600 ? 0.0472 0.0630 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 (rev mc) ? 1.200 1.600 ? 0.0472 0.0630 e 0.500 ? ? 0.0197 ? ? k (rev mc) ? 0.300 ? ? 0.0118 ? l ? 0.300 0.500 ? 0.0118 0.0197 l1 ? ? 0.150 ? ? 0.0059 l3 ? 0.300 ? ? 0.0118 ? eee (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. ? 0.080 ? ? 0.0031 ? $ % :7?-%e6 ! ! eee , e b $ , % , 0in +
package mechanical data m24c64-w m24c64-r m24c64-f 38/45 docid16891 rev 30 figure 22. wlcsp 5-bump wafer- length chip-scale package outline (m24c64-fcs6tp/k) 1. drawing is not to scale. 2. the index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). table 23. wlcsp 5-bump wafer-length chip-scale package mechanical data (m24c64-fcs6tp/k) symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.545 0.490 0.600 0.0215 0.0193 0.0236 a1 0.190 0.0075 a2 0.355 0.0140 b (2) 2. dimension measured at the maximum bump diameter parallel to primary datum z. 0.270 0.0106 d 0.959 1.074 0.0378 0.0423 e 1.073 1.168 0.0422 0.0460 e 0.693 0.0273 e1 0.400 0.0157 e2 0.3465 0.0136 f 0.280 0.0110 g 0.190 0.0075 aaa 0.110 0.0043 eee 0.060 0.0024 "ump $etail! rotatedby? 7aferbackside 3ideview $etail! "umpside ! ! e e e # " ! ' & ! $ % b #d?-% )ndex )ndex
docid16891 rev 30 39/45 m24c64-w m24c64-r m24c64-f 44 figure 23. thin wlcsp 8-bump wafer-length chip-scale package outline (m24c64-dfct6tp/k) 1. drawing is not to scale. 2. the index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). table 24. thin wlcsp 8-bump wafer-length chip-scale package mechanical data (m24c64-dfct6tp/k) symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.315 0.300 0.330 0.0124 0.0118 0.0130 a1 0.115 0.0045 a2 0.200 0.0079 b (2) 2. dimension measured at the maximum bump di ameter parallel to primary datum z. 0.160 0.0063 d 1.073 1.093 0.0422 0.0430 e 0.959 0.979 0.0378 0.0385 e 0.693 0.0273 e1 0.800 0.0315 e2 0.400 0.0157 f 0.133 0.0052 g 0.137 0.00524 aaa 0.110 0.0043 eee 0.060 0.0043 8 aaa 7aferbackside $ % 3ideview $etail! ! ! e e e ' & "umpsside & $etail! 2otated? "ump eee 3eatingplane #i?-%?6 e b 8 9 : : 2eference /rientation reference ( !
part numbering m24c64-w m24c64-r m24c64-f 40/45 docid16891 rev 30 10 part numbering table 25. ordering information scheme example: m24c64 -d w mc 6 t p /p device type m24 = i 2 c serial access eeprom device function c64 = 64 kbit (8192 x 8 bit) device family blank = without identification page d = with identification page operating voltage w = v cc = 2.5 v to 5.5 v r = v cc = 1.8 v to 5.5 v f = v cc = 1.7 v to 5.5 v package bn = pdip8 (1) 1. rohs-compliant (ecopack1 ? ) mn = so8 (150 mil width) (2) 2. ecopack2 ? ((rohs compliant and free of brominat ed, chlorinated and antimony oxide flame retardants)) dw = tssop8 (169 mil width) (2) mc = ufdfpn8 (mlp8) (2) mh = ufdfpn5 (mlp5) (2) cs = 5-bump wlcsp (2) ct = 8-bump wlcsp (2) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option t = tape and reel packing blank = tube packing plating technology p or g = ecopack2 ? process (3) 3. the process letter is used only when ordering wlcsp packages, the process letter is not specified when ordering any other package. these process letters appear on the device package (marking) and on the shipment box. please contact your nearest st sales office for further information. /p or /k or /t = manufacturing technology code
docid16891 rev 30 41/45 m24c64-w m24c64-r m24c64-f 44 engineering samples parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity.
revision history m24c64-w m24c64-r m24c64-f 42/45 docid16891 rev 30 11 revision history table 26. document revision history date revision changes 14-mar-2011 22 updated information concerning e2, e1, e0 for the wlcsp package: ? note under figure 3: ufdfpn5 package connections ? comment under figure 6: chip enable inputs connection ? note 3 under table 2: device select code 07-apr-2011 23 updated mlp8 package data and section 10: part numbering added footnote (a) in section 4.5: memory addressing . 18-may-2011 24 updated: ? figure 3: ufdfpn5 package connections ? table 5: absolute maximum ratings ? small text changes added: ? figure 12: memory cell characteristics 08-sep-2011 25 updated: ? table 22: ufdfpn8 (mlp8) ? package dimensions (ufdfpn: ultra thin fine pitch dual flat package, no lead) ? figure 15: maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz ? figure 6: i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus ) . added t wldl and t dhwh in: ? table 16: 400 khz ac characteristics ? table 17: 1 mhz ac characteristics ? figure : minor text changes. 16-dec-2011 26 updated a dimension in table 23: wlcsp 5-bump wafer-length chip- scale package mechanical data (m24c64-fcs6tp/k) .
docid16891 rev 30 43/45 m24c64-w m24c64-r m24c64-f 44 28-aug-2012 27 datasheet split into: ? m24c64-df, m24c64-w, m24c64-r, m24c64-f (this datasheet) for standard products (range 6), ? m24c64-125 datasheet for automotive products (range 3). added 8-bump thin wlcsp. updated single supply voltage and nu mber of write cycles on cover page. updated section 2.1: serial clock (scl) and section 2.2: serial data (sda) . updated figure 7: block diagram . added section 4.5: device addressing . section 5.1: write operations move to section 5: instructions and updated. moved figure 9: write mode sequences with wc = 0 (data write enabled) to section 5.1.1: byte write . section 5.1.2: page write : changed address bits to a15/a5 and updated figure 10 . case of locked write identification page removed from section 5.1.4: lock identification page (m24c64-d only) . updated section 5.1.5: ecc (error corre ction code) and write cycling and move figure 11: write cycle polling flowchart using ack to section 5.1.6: minimizing write delays by polling on ack . added note 1 in table 6: operating conditions (voltage range w) and table 7: operating conditions (voltage range r) . added ta b l e 1 1 and updated table 12: memory cell data retention . removed note 2 in table 16: 400 khz ac characteristics for t ql1ql2, t wldl, t dhwh, and t ns. table 25: ordering information scheme : removed ambient operating temperature for device grade 5 and added note 3. to mlp8 and wlcsp packages. 18-nov-2013 28 added text in chapter 5.2.2: current address read updated note (1) under table 5: absolute maximum ratings . removed note (3) in table 2: device select code . updated notes below table 13: dc characteristics (m24c64-w, device grade 6) and table 14: dc characteristics (m24c64-r, device grade 6) renamed figure 21 and table 23 . updated captions above figure 22 and figure 23 . table 26. document revi sion history (continued) date revision changes
revision history m24c64-w m24c64-r m24c64-f 44/45 docid16891 rev 30 21-jul-2014 29 updated figure 3 , figure 5 , table 14 , table 8 , table 16 , table 17 and table 25 . updated ecopack info on front page. updated notes: ?(1) on ta ble 6 , table 7 , table 13 , table 17 ? (2) merged with (3) on table 14 ?(8) on table 14 ?(2) on table 15 ?(3) on table 25 added: ? note (1) on table 8 added: ? supply voltage level specification on cover page. ? package ufdfpn5 on cover page ? table 18 and figure 17 related to ufdfpn5 package. ? note (1) on section 5.1.5 12-nov-2014 30 added: ? note 2 on table 13 ? note 2 on dw, mc and cs package on table 25 ? note 1on bn package on table 25 ? figure 3 updated: ? section 1: description ? chapter 5.1.5 ? note 3 on table 5 ? note 1 on table 8 ? note 1 on table 11 ? note 1 on table 12 ?i cc0 max value and note 5 on table 13 ?i cc0 max value on table 14 ?i cc0 max value on table 15 ? note 2 on table 25 table 26. document revi sion history (continued) date revision changes
docid16891 rev 30 45/45 m24c64-w m24c64-r m24c64-f 45 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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