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shanghai belling corp., ltd bl24c 512 g 1 ? features ? two - wire serial interface, i 2 c tm compatible C bi - directional data transfer protocol ? wide - voltage operation C v cc = 1. 7 v to 5.5v ? speed: 400 khz (1. 7 v) and 1 mhz (2.5v~5.5v) ? standby current (max.) : 1 ? a , 1. 7 v ? operating current (max.) : 2 ma , 1. 7 v ? hardw are data protection C write protect pin ? sequential & random read features ? memory organization: 65 , 536 x 8 bits ? page size: 128 bytes ? page write mode C up to 128 bytes per page write ? self timed write cycle with auto clear: 5ms (max.) ? filtered inputs for noise su ppression ? high - reliability C endurance: 1 million cycles C data retention: 100 years ? industrial temperature grades ? packages: soic/sop, tssop , dfn and csp ? lead - free, rohs, halogen free, green ? description the bl 24c512 g are eeprom devices that use the industri al standard 2 - wire interface for communications. the bl 24c512 g contains a memory array of 512 k - bits ( 65 , 536 x8), which is organized in 128 - byte per page. the eeprom can operate in a wide voltage range from 1. 7 v to 5.5v which fits most application. this prod uct can provide a low - power 2 - wire eeprom solution. the device is offered in lead - free, rohs, halogen free or green. the available package types are 8 - pin soic/sop, tssop , dfn and csp. the bl24c512 g is compatible with the industrial standard 2 - wire bus prot ocol. if in case the bus is not responded, a new sent op - code command will reset the bus and the device will respond correctly. the simple bus consists of the serial clock wire (scl) and the serial data wire (sda). utilizing such bus protocol, a master dev ice, such as a microcontroller, can usually control one or more slave devices, alike this bl 24c512 g . the bit stream over the sda line includes a series of bytes, which identifies a particular slave device, an instruction, an address within that slave device , and a series of data, if appropriate. the bl24c512 g also has a write protect pin (wp) to allow blocking any write operations over specified memory area. under no circumstance, the device will be hung up. in order to refrain the state machine entering into a wrong state during power - up sequence or a power toggle off - on condition, a power on reset circuit is embedded. during power - up, the device does not respond to any instructio ns until the supply voltage ( v cc ) has reached an acceptable stable level above t he r eset threshold voltage. once v cc passes the power on reset threshold, the device is reset and enters into the standby mode. this would also avoid any inadvertent write operations during power - up stage. during power - down process, the device will e nter i nto standby mode, once v cc drops below the power on reset threshold voltage. in addition, the device will be in standby mode after receiving the stop command, provided that no internal write operation is in progress. nevertheless, it is illegal to send a c ommand unless the v cc is within its operating level.
shanghai belling corp., ltd bl24c 512 g 2 ? functional block diagram h i g h v o l t a g e g e n e r a t o r t i m i n g & c o n t r o l e e p r o m a r r a y y d e c o d e r x d e c o d e r d a t a r e g i s t e r c o n t r o l l o g i c w o r d a d d r e s s c o u n t e r s l a v e a d d r e s s r e g i s t e r & c o m p a r a t o r 5 6 7 1 2 3 4 8 g n d a 2 a 1 a 0 w p s c l s d a v c c a c k n m o s d i / o c l o c k
shanghai belling corp., ltd bl24c 512 g 3 ? pin configuration 8 - pin soic/sop and tssop top view 8 - lead dfn top view pin de finition pin no. pin name i/o definition 1 a0 i device address input 2 a1 i device address input 3 a2 i device address input 4 gnd - ground 5 sda i/o serial address and data input and data out put 6 scl i serial clock input 7 wp i write protect inpu t 8 v cc - power supply p in descriptions scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi - directional pin used to transfer addresses and data into and out of the device. the sda pin is an ope n drain output and can be wired with other open drain or open collector outputs. however, the sda pin requires a pull - up resistor connected to the power supply. a0, a1, a2 the a0, a1 and a2 are the device address inputs. typically, the a0, a1, and a2 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. when a0, a1, and a2 are left floating, the inputs are defaulted to zero. wp wp is the write protect pin. while the wp pin is connected to the power supply of bl 24c512 g , the entire array becomes write protected (i.e. the device becomes read only). when wp is tied to ground or left floating, the normal write operations are allowed. v cc supply voltage gnd ground of supply voltage a 0 a 1 v c c s c l s d a g n d a 2 w p 1 2 3 4 8 7 6 5 a 0 a 1 v c c s c l s d a g n d a 2 w p 1 2 3 4 8 7 6 5
shanghai belling corp., ltd bl24c 512 g 4 ? d evice o peration the bl24c512 g se rial interface supports communications using industrial standard 2 - wire bus protocol, such as i 2 c. 2 - wire b us the two - wire bus is defined as serial data (sda), and serial clock (scl). the protocol defines any device that sends data onto the sda bus as a tr ansmitter, and the receiving devices as receivers. the bus is controlled by master device that generates the scl, controls the bus access, and generates the start and stop conditions. the bl24c512 g is the slave device. the bus protocol data transfer may be initiated only when the bus is not busy. during a data transfer, the sda line must remain stable whenever the scl line is high. any changes in the sda line while the scl line is high will be interpreted as a start or stop condition. the state of the sda l ine represents valid data after a start condition. the sda line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed during the low period of the clock signal. there is one clock pulse per bit of d ata. each data transfer is initiated with a start condition and terminated by a stop condition. start condition the start condition precedes all commands to the device and is defined as a high to low transition of sda when scl is high. the eeprom monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defined as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge after a successful dat a transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the bl24c512 g contains a reset function in case the 2 - wire bus transmission on is accidentally interrupted (e.g. a power loss), or need s to be terminated mid - stream. the reset is initiated when the master device creates a start condition. to do this, it may be necessary for the master device to monitor the sda line while cycling the scl up to nine times. (for each clock signal transition to high, the master checks for a high level on sda.) standby mode while in standby mode, the power consu mption is minimal. the bl24c512 g enters into standby mode during one of the following conditions: a) after power - up, while no op - code is sent; b) after t he completion of an operation and followed by the stop signal, provided that the previous operation is not write related; or c) after the completion of any internal write operations. d evice a ddressing the master begins a transmission on by sending a start condition, then sends the address of the particular slave devices to be communicated. the slave device address is 8 bits format as shown in fig ure . 1 - 5 . the four most significant bits of the slave addres s are fixed (1010) for bl24c512 g . the next three bits , a0, a1 and a2, of the slave address are specifically related to eeprom. up to eight bl24c512 g units can be connected to the 2 - wire bus. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, read operation is selected. while it is set to 0, write operation is selected. after the master transmits the start condition and slave address byte appropriately, the associate d 2 - wire slave device, bl24c512 g , will respond with ack on the sda line. then bl24c512 g will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the bl24c512 g then prepares for a read or write operation by monitoring the bus. w rite o peration byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/w set to zero) to the slave device. after the slave generates an ack, the master sends the byte address that is to be written into the address pointer of the bl24c512 g . after rec eiving another ack from the slave, the master device transmits the data byte to be written into the address
shanghai belling corp., ltd bl24c 512 g 5 memory location. the bl24c512 g acknowledges once more and the master generates the stop condition, at which time the device begins its internal progr amming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the bl24c512 g is capable of 128 - byte page - write operation. a page - write is initiated in the same manner as a byte write, bu t instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to 127 more bytes. after the receipt of each data word, the eeprom responds immediately with an ack on sda line, and the seven low er order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. if a byte address is incremented from the last byte of a page, it returns to the first byte of that page. if the master device should transmit more than 128 bytes prior to issuing the stop condition, the address counter will roll over, and the previously written data will be overwritten. once all 128 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the bl24c512 g in a single write cycle. all inputs are disabled until completion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be u sed to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the bl24c512 g initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the eeprom is still busy with the write operation, no ack will be returned. if the bl24c512 g has completed the write operation, an ack will be returned and the host can then proceed wi th the next read or write operation. r ead o peration read operations are initiated in the same manner as write operations, except that the (r/w) bit of the slave address is set to 1. there are three read operation options: current address read, random add ress read and sequential read. current address read the bl24c512 g contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addr essed to the address location n, the internal address counter would increment to address location n+1. when the eeprom receives the slave addressing byte with a read operation (r/w bit set to 1), it will respond an ack and transmit the 8 - bit data byte st ored at address location n+1. the master should not acknowledge the transfer but should generate a stop condition so the bl24c512 g discontinues transmission. if 'n' is the last byte of the memory, the data from location '0' will be transmitted. (refer to fi gure 1 - 8 . current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a 'dummy' write operation by sending the start con dition, slave address and byte address of the location it wishes to read. after the bl24c512 g acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/w bit set to one. the eeprom then responds with its ack and sends the data requested. the master device does not send an ack but will generate a stop condition. (refer to figure 1 - 9 . random address read diagram.) sequential read sequential reads can be initiated as either a current address read or random address read. after the bl24c512 g sends the initial byte sequence, the master device now responds with an ack indicating it requires additional data from the bl24c512 g . the eeprom continues to output data for each ack received. the master device term inates the sequential read operation by pulling sda high (no ack) indicating the last data word to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. the add ress counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operation. when the memory address boundary of the array is reached, the
shanghai belling corp., ltd bl24c 512 g 6 address counter rolls over to address 0, and the device continues to output data. (refer to figure 1 - 1 0 . sequential read diagram). d iagrams figure 1 - 1 . typical system bus configuration figure 1 - 2 . output acknowledge figure 1 - 3 . start and stop conditions bl24cxxx x m a s t e r t r a n s m i t t e r / r e c e i v e r g t 2 4 c x x s c l s d a v c c 1 8 9 s c l f r o m m a s t e r d a t a o u t p u t f r o m t r a n s m i t t e r d a t a o u t p u t f r o m r e c e i v e r a c k t a a t a a s t o p c o n d i t i o n s t a r t c o n d i t i o n s c l s d a
shanghai belling corp., ltd bl24c 512 g 7 figure 1 - 4 . data validity protocol figure 1 - 5 . slave address figure 1 - 6 . byte write figure 1 - 7 . page write s c l s d a d a t a s t a b l e d a t a s t a b l e d a t a c h a n g e 1 0 1 0 a 2 a 1 a 0 r / w 7 b i t 6 5 4 3 2 1 0 a c k a c k a c k a c k s d a b u s a c t i v i t y s t a r t m s b l s b w r i t e r / w d e v i c e a d d r e s s w o r d a d d r e s s w o r d a d d r e s s d a t a m s b s t o p a c k a c k a c k a c k a c k s d a b u s a c t i v i t y s t a r t m s b l s b w r i t e r / w d e v i c e a d d r e s s w o r d a d d r e s s ( n ) w o r d a d d r e s s ( n ) d a t a ( n ) m s b s t o p a c k d a t a ( n + 1 ) d a t a ( n + 1 2 7 )
shanghai belling corp., ltd bl24c 512 g 8 figure 1 - 8 . current address read figure 1 - 9 . random address read figure 1 - 10 . sequential read a c k s d a b u s a c t i v i t y s t a r t d e v i c e a d d r e s s m s b l s b r e a d d a t a s t o p n o a c k r / w a c k a c k a c k a c k s d a b u s a c t i v i t y s t a r t d e v i c e a d d r e s s w r i t e w o r d a d d r e s s ( n ) d a t a n r / w m s b l s b w o r d a d d r e s s ( n ) d e v i c e a d d r e s s s t a r t r e a d s t o p d u m m y w r i t e n o a c k a c k n o a c k a c k a c k d e v i c e a d d r e s s r e a d d a t a b y t e n a c k d a t a b y t e n + 1 d a t a b y t e n + 2 d a t a b y t e n + x s t o p s d a b u s a c t i v i t y r / w
shanghai belling corp., ltd bl24c 512 g 9 timing diagrams figure 1 - 11 . bus timing figure 1 - 12 . write cycle timing s c l s d a i n s d a o u t w p t s u : w p t h d : w p t b u f t s u : d a t t d h t a a t h d : d a t t h d : s t a t s u : s t a t s u : s t o t l o w t h i g h t f t r s d a w o r d n a c k s t o p c o n d i t i o n s t a r t c o n d i t i o n t w r s c l
shanghai belling corp., ltd bl24c 512 g 10 ? electrical characteristics absolute maximum ratings symbol parameter value unit v s supply voltage - 0.5 to + 6.5 v v p voltage on any pin C 0.5 t o v cc + 0.5 v t bias temperature under bias C 55 to +125 c t stg storage temperature C 65 to +150 c i out output current 5 ma note: stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli ability. o perating r ange range ambient temperature (t a ) v cc industrial C 40c to +85c 1. 7 v to 5.5v note: industrial grade for commercial applications (0 ? c to +70 ? c). c apacitance symbol parameter [ 1, 2 ] conditions max. unit c in input capacitance v i n = 0v 6 pf c i/o input / output capacitance v i/o = 0v 8 pf note s : [ 1 ] tested initially and after any design or process changes that may affect these parameters and not 100% tested. [ 2 ] test conditions: t a = 25c, f = 1 mhz, v cc = 5.0v.
shanghai belling corp., ltd bl24c 512 g 11 dc e lectrical c haracteristic industrial : t a = C 40c to +85c, v cc = 1. 7 v ~ 5.5v symbol parameter [1] v cc test conditions min. max. unit v cc supply voltage 1. 7 5.5 v v ih input high voltage 0.7* v cc v cc + 1 v v il input low voltage - 1 0.3* v cc v i li input leakage cu rrent 5 v v in = v cc max -- 2 a i lo output leakage current 5v -- 2 a v ol1 output low voltage 1. 7 v i ol = 0.15 ma 0.2 v v ol2 output low voltage 3 v i ol = 2.1 ma 0.4 v i sb1 standby current 1. 7 v v in = v cc or gnd 1 a i sb 2 standby current 2.5 v v in = v cc or gnd 2 a i sb 3 stan dby current 5 v v in = v cc or gnd 3 a i cc1 read current 1. 7 v read at 400 khz 0. 5 ma 2.5 v read at 1 m hz 1 ma 5.5 v read at 1 m hz 1 ma i cc2 write current 1. 7 v write at 400 khz 2 ma 2.5 v write at 1 m hz 3 ma 5.5 v write at 1 m hz 3 ma note : the parameters are characterized but not 100% tested.
shanghai belling corp., ltd bl24c 512 g 12 ac e lectrical c haracteristic industrial : t a = C 40c to +85c, supply voltage = 1. 7 v to 5.5v symbol parameter [1] [2] 1. 7 v ? v cc < 2.5v 2.5v ? v cc < 4.5v 4.5v ? v cc ? 5.5v unit min. max. min. max. min. max. f scl sck clock frequency 400 1000 1000 khz t low clock low period 1200 4 00 4 00 ns t high clock high period 600 400 400 ns t r rise time (scl and sda) 300 300 300 ns t f fall time (scl and sda) 300 100 100 ns t su:sta start cond ition setup time 600 2 0 0 2 0 0 ns t su:sto stop condition setup time 600 2 0 0 2 0 0 ns t hd:sta start condition hold time 600 2 0 0 2 0 0 ns t su:dat data in setup time 100 4 0 4 0 ns t hd:dat data in hold time 0 0 0 ns t aa clock to out put access time (scl low to sda data out valid) 100 900 50 400 50 400 ns t dh data out hold time (scl low to sda data out change) 100 50 50 ns t wr write cycle time 5 5 5 ms t buf bus free time before new transmission 1000 400 400 ns t su :wp wp pin setup time 600 4 00 4 00 ns t hd:wp wp pin hold time 1200 1200 1200 ns t noise suppression time 100 50 50 ns notes: [1] the parameters are characterized but not 100% tested. [2] ac measurement conditions: r l (connects to v cc ) : 1.3 k (2.5v, 5.0v), 10 k (1. 7 v) c l = 100 pf input pulse voltages: 0.3*v cc to 0.7*v cc input rise and fall times: 50 ns timing reference voltages: half v cc level
shanghai belling corp., ltd bl24c 512 g 13 ? p ackage i nformation soic/sop 8l 150mil sop package outline l 1 d e 1 e a a 1 e z d d e t a i l a l d e t a i l a g a u g e p l a n e s e a t i n g p l a n e n o t e : 1 . c o n t r o l l i n g d i m e n s i o n : m m 2 . d i m e n s i o n d a n d e 1 d o n o t i n c l u d e 3 . d i m e n s i o n b d o e s n o t i n c l u d e 4 . r e f e r t o j e d e c s t a n d a r d m s - 0 1 2 5 . d r a w i n g i s n o t t o s c a l e m o l d p r o t r u s i o n d a m b a r p r o t r u s i o n / i n t r u s i o n . b min nom max min nom max a 1.35 -- 1.75 0.053 -- 0.069 a1 0.10 -- 0.25 0.004 -- 0.010 b 0.33 -- 0.51 0.013 -- 0.020 d 4.80 -- 5.00 0.189 -- 0.197 e 5.80 -- 6.20 0.228 -- 0.244 e1 3.80 -- 4.00 0.150 -- 0.157 e l 0.38 -- 1.27 0.015 0.050 l1 zd 0 -- 8 0 -- 8 0.545 ref. 0.050 bsc. 0.010 bsc. 0.021 ref. symbols dimensions in millimeters dimensions in inches 1.27 bsc. 0.25 bsc.
shanghai belling corp., ltd bl24c 512 g 14 tssop 8l 3x4.4mm tssop package outline a 2 a 1 b a 1 2 ( 4 x ) 0 . 1 0 m m l c e e 1 e d n o t e : 1 . c o n t r o l l i n g d i m e n s i o n : m m 2 . d i m e n s i o n d a n d e 1 d o n o t i n c l u d e m o l d p r o t r u s i o n 3 . d i m e n s i o n b d o e s n o t i n c l u d e d a m b a r p r o t r u s i o n / i n t r u s i o n . 4 . r e f e r t o j e d e c s t a n d a r d m o - 1 5 3 a a 5 . d r a w i n g i s n o t t o s c a l e 6 . p a c k a g e m a y h a v e e x p o s e d t i e b a r . 1 8 min nom max min nom max a -- -- 1.20 -- -- 0.047 a1 0.05 -- 0.15 0.002 -- 0.006 a2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 -- 0.30 0.007 -- 0.012 c 0.09 -- 0.20 0.004 -- 0.008 d 2.90 3.00 3.10 0.114 0.118 0.122 e 4.30 4.40 4.50 0.169 0.173 0.177 e1 e l 0.45 0.60 0.75 0.018 0.024 0.030 0 -- 8 0 -- 8 0.252 bsc 0.026 bsc symbols dimensions in millimeters dimensions in inches 0.65 bsc 6.4 bsc
shanghai belling corp., ltd bl24c 512 g 15 dfn 8l 3x 3 mm dfn package outline n o t e : 1 . c o n t r o l l i n g d i m e n s i o n : m m 2 . d r a w i n g i s n o t t o s c a l e t o p v i e w b o t t o m v i e w s i d e v i e w d e p i n # 1 d o t b y m a r k i n g d 2 e e 2 k l b a a 1 p i n # 1 i d e n t i f i c a t i o n c h a m f e r min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 -- 0.05 0.000 -- 0.002 b 0.17 0.22 0.27 0.007 0.009 0.011 d d2 2.375 2.385 2.395 0.094 0.094 0.094 e e2 1.635 1.645 1.655 0.064 0.065 0.065 e k 0.23 0.28 0.33 0.009 0.011 0.013 l 0.35 0.40 0.45 0.014 0.016 0.018 symbols dimensions in millimeters dimensions in inches 0.50bsc. 3.00 bsc 0.118 bsc 3.00 bsc 0.118 bsc 0.020bsc

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