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this is information on a product in full production. february 2014 docid023810 rev 2 1/14 STL40N75LF3 n-channel 75 v, 16 m typ., 10 a stripfet? iii power mosfet in a powerflat? 5x6 package datasheet - production data figure 1. internal schematic diagram features ? n-channel enhancement mode ? low gate charge ? low threshold voltage device applications ? switching applications description this device is an n-channel enhancement mode power mosfet produced using stmicroelectronics? stripfet? iii technology, which is specifically designed to minimize on- resistance and gate charge to provide superior switching performance. am15540v2 5 6 7 8 12 34 top view d(5, 6, 7, 8) g(4) s(1, 2, 3) 1 2 3 4 powerflat? 5x6 order code v dss r ds(on) max. i d STL40N75LF3 75 v 19 m 10 a table 1. device summary order code marking package packaging STL40N75LF3 40n75lf3 powerflat? 5x6 tape and reel www.st.com
contents STL40N75LF3 2/14 docid023810 rev 2 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
docid023810 rev 2 3/14 STL40N75LF3 electrical ratings 14 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 75 v v gs gate-source voltage +20\-16 v i d (1) 1. the value is rated according to r thj-case drain current (continuous) at t c = 25 c 40 a i d (1) drain current (continuous) at t c = 100 c 26 a i dm (1)(2) 2. pulse width limited by safe operating area drain current (pulsed) 160 a i d (3) 3. the value is rated according to r thj-pcb drain current (continuous) at t pcb = 25 c 10 a i d (3) drain current (continuous) at t pcb =100 c 6 a p tot (1) total dissipation at t c = 25 c 75 w p tot (3) total dissipation at t pcb = 25 c 4.8 w t j t stg operating junction temperature storage temperature -55 to 175 c table 3. thermal resistance symbol parameter value unit r thj-case thermal resistance junction-case 2 c/w r thj-pcb (1) 1. when mounted on fr-4 board of 1 inch2, 2oz cu., t < 10 sec. thermal resistance junction-ambient 31.3 c/w
electrical characteristics STL40N75LF3 4/14 docid023810 rev 2 2 electrical characteristics (t case = 25 c unless otherwise specified). table 4. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 250 a 75 v i dss zero gate voltage drain current (v gs = 0) v ds = 75 v, v ds = 75 v, t c = 125 c 1 10 a a i gss gate body leakage current (v ds = 0) v gs = +20 / -16 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 v r ds(on) static drain-source on resistance v gs = 10 v, i d = 20 a v gs = 5 v, i d = 20 a 16 18.7 19 22 m m table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25 v, f = 1 mhz, v gs = 0 - 1300 228 15 - pf pf pf q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 37.5 v, i d = 40 a v gs = 5 v (see figure 14 ) - 12 5 5.3 - nc nc nc r g gate input resistance f=1 mhz gate dc bias=0 test signal level = 20 mv open drain -3.5 - table 6. switching times symbol parameter test conditions min. typ. max. unit t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 37.5 v, i d = 20 a, r g = 4.7 , v gs =10 v (see figure 13 ) - 12 25 25 3 - ns ns ns ns
docid023810 rev 2 5/14 STL40N75LF3 electrical characteristics 14 table 7. source-drain diode symbol parameter test conditions min typ. max unit i sd source-drain current - 40 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) 160 a v sd (2) 2. pulsed: pulse duration=300s, duty cycle 1.5% forward on voltage i sd = 40 a, v gs =0 - 1.1 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 40 a, di/dt = 100 a/s, v dd =60 v - 35 44 27 ns nc a
electrical characteristics STL40N75LF3 6/14 docid023810 rev 2 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance i d 0.1 0.01 0.1 1 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 10ms 1s 100ms tj= 175c tc=25c single pulse 1 10 100 am15409v1 k t p (s) single pulse 10 -2 = 0.5 0.2 0.1 0.05 0.02 0.01 10 -3 10 -4 10 -5 10 0 10 -2 10 -1 10 -3 10 -4 10 -5 10 -6 gipd130920131022fsr figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on-resistance i d 60 40 20 0 0 2 v ds (v) (a) 1 80 v gs = 3 v v gs = 4 v v gs = 10 v 100 v gs = 5 v 3 am15410v1 i d 60 40 20 0 0 2 v gs (v) 4 (a) 1 3 5 80 6 7 8 100 v ds = 4 v am15411v1 v gs 6 4 2 0 0 5 q g (nc) (v) 8 10 15 10 v dd =37.5 v i d =40a 20 25 am15412v1 r ds(on) 10 5 0 0 30 i d (a) (m ) 10 15 20 20 40 v gs =10v 25 30 am15413v1
docid023810 rev 2 7/14 STL40N75LF3 electrical characteristics 14 figure 8. capacitance variations figure 9. normalized v(br) dss vs temperature figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on-resistance vs temperature figure 12. source-drain diode forward characteristics c 1500 1000 500 0 0 20 v ds (v) (pf) 10 30 ciss coss crss 40 2000 2500 3000 3500 am15414v1 v(br) dss -55 -5 t j (c) (norm) -30 70 20 45 95 0.8 0.85 0.9 0.95 1 1.05 i d = 1ma 120 1.1 1.15 am15415v1 v gs(th) 0.8 0.6 0.4 0.2 -55 -5 t j (c) (norm) -30 1 70 20 45 95 120 1.2 i d =250 a am15344v1 r ds(on) 1.5 1 0.5 0 -55 -5 i d (a) -30 20 2 v gs =5 v i d= 20 a 45 70 95 120 (norm) am15417v1 v sd 0 20 i sd (a) (v) 10 30 0.4 0.5 0.6 0.7 0.8 0.9 t j =-50c t j =175c t j =25c 40 1 am15418v1
test circuits STL40N75LF3 8/14 docid023810 rev 2 3 test circuits figure 13. switching times test circuit for resistive load figure 14. gate charge test circuit figure 15. test circuit for inductive load switching and diode recovery times figure 16. unclamped inductive load test circuit figure 17. unclamped inductive waveform figure 18. switching time waveform am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd am01472v1 v (br)dss v dd v dd v d i dm i d am01473v1 v ds t on td on td off t off t f t r 90% 10% 10% 0 0 90% 90% 10% v gs
docid023810 rev 2 9/14 STL40N75LF3 package mechanical data 14 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 19. powerflat? 5x6 type s-c drawings 8231817_h_c
package mechanical data STL40N75LF3 10/14 docid023810 rev 2 figure 20. powerflat? 5x6 type s-c recommended footprint (dimensions in mm) table 8. powerflat? 5x6 type s-c mechanical data dim. mm min. typ. max. a0.80 1.00 a1 0.02 0.05 a2 0.25 b0.30 0.50 d5.20 e6.15 d2 4.11 4.31 e2 3.50 3.70 e1.27 e1 0.65 l 0.715 1.015 k1.05 1.35 footprint
docid023810 rev 2 11/14 STL40N75LF3 packaging information 14 5 packaging information figure 21. powerflat? 5x6 type s-c tape figure 22. powerflat? 5x6 type s-c package orientation in carrier tape measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . (i) (ii) (iii) measured from centerline of sprocket hole to centerline of pocket. 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p 4.00.1 (ii) ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 p 0 y y section y-y c l p1(8.000.1) do d1 e 1 (0.30 t ref.r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_tape_rev_c pin 1 identification
packaging information STL40N75LF3 12/14 docid023810 rev 2 figure 23. powerflat? 5x6 type s-c reel 2.20 ?21.2 13.00 core detail 2.50 1.90 r0.60 77 ?a 12 8 r1.10 2.50 4.00 r25.00 w1 w2 pa rt n o. 18.4 (max) w3 06 p s esd logo attention observe precautions for handling electros tatic 11.9/15.4 12.4 (+2/-0) sensitive device s a 330 (+0/-4.0) ?n 178(2.0) all dimensions are in millimeters 8234350_reel_rev_c
docid023810 rev 2 13/14 STL40N75LF3 revision history 14 6 revision history table 9. document revision history date revision changes 19-oct-2012 1 first release. 24-feb-2014 2 deleted note in the table of features . updated figure 1 . updated values of p tot , t j and t stg in table 2 . updated notes in table 2 . updated v gs test condition in table 5 . updated v dd test condition in table 6 . removed t j test condition from table 7 . updated figure 2 , figure 4 , figure 6 , figure 9 and figure 11 . updated mechanical data.
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