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enpirion ? power datasheet en5367qi 6a powersoc highly integrated synchronous buck with integrated inductor description the en5367 qi is a power system on a chip (powersoc) dc to dc converter with an integrated inductor, pwm controller, mosfets and compensation to provide the smallest solution size in a 5.5 x1 0 x3mm 54- pin qfn module. it offers high efficien cy , e xcellent line and load regulation over temperature and up to the full 6 a load range . the en5367 qi is specifically designed to meet the precise voltage and fast transient requirements of high - performance, low - power processor, dsp, fpga, memory boards and sy stem level applications in distributed power architecture. the en5367 qi also features switching frequency synchronization with an external clock , programmable soft -start as well as thermal shutdown, over - current and short circuit protection. the device?s advanced circuit techniques, ultra high switching frequency, and proprietary integrated inductor technology deliver high - quality, ultra compact, non - isolated dc - dc conversion. the altera enpirion integrated inductor solution significantly helps to reduce noise. the complete power converter solution enhances productivity by offering greatly simplified board design, layout and manufacturing requirements. all altera enpirion products are rohs compliant and lead - free manufacturing environment compatible. features ? high efficiency (up to 9 3%) ? excellent ripple and emi performance ? up to 6 a continuous operating current ? input voltage range (2.5v to 5.5 v) ? frequency synchronization ( external clock) ? 3 % v out accuracy (over line/load/temp erature ) ? optimized total solution size ( 16 0mm 2 ) ? programmable soft - start ? output enable pin and power ok ? thermal shutdown, over - current, short circuit, and under - voltage lockout protection ( uvlo) ? r ohs compliant, msl l evel 3, 260 c r eflow applications ? point of l oad r egulation for l ow -p ower , a sics m ulti -c ore and c ommunication processors, dsps, fpgas and distributed power architectures ? blade s ervers, raid s torage and lan/san adapter c ards, w ireless b ase s tations, i ndustrial a utomation, t est and m easurement, e mbedded c omputing , and p rinters ? beat f requency/ noise sensitive applications v out v in 47f 1206 vout enable vddb ss pvin avin pgnd pgnd en5367qi vfb r a r b r ca c a bgnd 47f 1206 agnd btmp pg sync 0.1f 0.1f 47nf 0805 0.1f 47nf 10 figure 1 . simplified applications circuit figure 2. highest efficiency in smallest solution size 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v vout = 1.2v conditions v in = 5.0v actual solution size 160mm 2 www. altera.com/enpirion 07013 october 11, 2013 rev d
e n5367qi ordering information part number package markings t emp rating (c) package description en5367 qi en5367 qi - 40 to +85 54 - pin ( 5.5 mm x 10 mm x 3mm) qfn t&r EVB-EN5367QI en5367 qi qfn evaluation board packing and marking information : www.altera.com/support/reliability/packing/rel - packing - and- marking.html pin assignments (top view) nc 1 nc nc nc nc nc nc nc nc 2 3 4 5 6 7 8 9 vout vout vout vout vout vout nc vout nc(sw) nc(sw) pgnd pgnd pgnd pgnd pgnd pvin pvin pvin pvin vddb btmp bgnd pg sync nc nc nc nc(sw) agnd avin nc vfb ss nc eaout nc pok enable nc 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 36 35 34 33 32 31 30 29 28 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 55 pgnd keep out keep out keep out vout pgnd pgnd nc(sw) nc(sw) nc(sw) figure 3: pin out diagram (top view) note a : nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or da mage. note b : shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the pcb. refer to figure 9 for details. note c : white ?dot? on top left is pin 1 indicator on top of the device package . pin description pin nam e function 1 - 9, 18, 37, 40, 42, 45, 48, 53 - 54 nc no connect ? these pins may be internally connected. do not connect them to each other or to any other electrical signal. failure to follow this guideline may result in device damage. 10- 17 vout regulated converter output. connect these pins to the load and place output capacitor between these pins and pgnd pins 21 - 24 . 19- 20, 49- 52 nc(sw) no connect ? these pins are internally connected to the common switching node of the internal mosfets. they are not to be electrically connected to any external signal, ground, or voltage. failure to follow this guideline may result in damage to the device. 21- 27 pgnd input/output power ground. connect these pins to the ground electrode of the i nput an d output filter capacitors. see vout and pvin pin descriptions for more details. 28- 31 pvin input power supply. connect to input power supply. decouple with input capacitor to pgnd pins 25 - 27 . 32 pg high - side fet gate. this pin needs to be connected to b tmp using a 0.1f capacitor. 2 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi pin nam e function 33 btmp low side of the flying capacitor that drives the high - side fet gate. connect to pg using a 0.1f capacitor. 34 vddb regulated voltage used for internal control circuitry. decouple with a 0.1f capacitor to bgnd. 35 b gnd internal gnd for vddb. connect to vddb using a 0.1f capacitor. do not tie to any grounds on the pcb. 36 sync a clocked input to this pin will synchronize the internal switching frequency to the external signal. if the sync function is not to be used, this pin has to be grounded. do not float this pin or tie it to a static high voltage. 38 enable input enable. applying a logic high enables the output and initiates a soft - start. applying a logic low disables the output. 39 pok power ok is an open drai n transistor used for power sy stem state indication. pok is logic high when vout is with in - 10% of vout nominal. 41 eaout optional error amplifier output. allows for customization of the control loop. 43 ss soft - start node. the soft - start capacitor is co nnected between this pin and agnd. the value of this capacitor determines the startup time. 44 vfb external feedback input. the feedback loop is closed through this pin. a voltage divider at vout is used to set the output voltage. the midpoint of the divider is connected to vfb. a phase lead capacitor from this pin to vout is also required to stabilize the loop. 46 agnd analog ground. this is the ground return for the controller. needs to be connected to the gnd plane using a via right next to the pin. 47 avin input power supply for the controller. needs to be decoupled to agnd with a 0.1f capacitor and connected to the input voltage at a quiet point through a 10 ? 3 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi absolute maximum ratings caution : absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute maximum ratings may impair device life. exposure to absolute maximum rated conditions for extended periods may affect device reliability. param eter sym bol min m ax units voltages on : pvin, avin, vout - 0.3 6.5 v voltages on: en able , pok, sync - 0.3 v in +0. 3 v voltages on: vfb , ss - 0.3 2. 7 5 v storage temperature range t stg - 65 150 c maximum operating junction temperature t j- abs max 150 c reflow temp, 10 sec, msl3 jedec j - std - 020a 260 c esd rating (based on h uman b ody m odel ) 2000 v esd rating (based on cdm) 500 v recommended operating conditions param eter sym bol min m ax units input voltage range v in 2.5 5 . 5 v out put voltage range ( note 1 ) v out 0.60 v in ? v do v out put current i out 6 a operating ambient temperature t a - 40 +8 5 c operatin g junction temperature t j - 40 +125 c thermal characteristics param eter sym bol typ units thermal resistance: junction to ambient (0 lfm) ( note 2 ) ja 22 c/w thermal resistance: junction to case (0 lfm) jc 2 c/w thermal shutdown t sd 150 c thermal s hutdown hysteresis t sdh 20 c note 1 : v do (d ropout v oltage) is defined as (i load x dropout resistance). please refer to electrical charac t eristics table. note 2 : based on 2oz. external copper layers and proper thermal design in line with eij/jedec jesd51 -7 standard for h igh thermal conductivity boards. 4 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi electrical characteristics note: v in =5.5v , minimum and m aximum values are over operating ambient temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ m ax units operating input voltage v in 2.5 5.5 v under voltage lock - out ? v in rising v uvlor voltage above which uvlo is not asserted 2.2 5 v under voltage lock - out ? v in falling v uvlof voltage below which uvlo is asserted 2.05 v shut - down supply current i s enable=0v 100 a feedback pin voltage v fb feedback node voltage at: v in = 5v, iload = 0, t a = 25c 0.735 0.75 0.765 v feedback pin voltage v fb feedback node voltage at: 2.5v v in 5.5 v 0a iload 6a 0.7275 0.75 0.7725 v feedback p in input leakage current (note 3 ) i fb vfb pin input leakage current -5 5 na v out rise time (note 3) t rise measured from when v in > v uvlor & enable pin voltage crosses its logic high threshold to when v out reaches its final value . c ss = 47 nf 2.82 3.76 4 .70 ms soft start capacitor range c ss_range 10 68 nf output drop out voltage r esistance (note 3) v do r do v inmin - v out at full load input to output resistance 300 50 600 100 mv m ? continuous output current i out_max_cont 0 6 a over current trip level i ocp v in = 5v, v out = 1.2v 9 a disable threshold v disable enable pin logic low. 0.0 0.6 v enable threshold v enable enable pin logic high 2.5 v v in 5.5 v 1.8 v in v enable lockout t ime t enlockout 2.4 ms enable pin input current i enable enabl e pin has ~ 1 80k ? pull down 30 a switching frequency (free running) f sw free running frequency of oscillator 4 mhz external sync clock frequency lock range f pll_lock range of sync clock frequency 3.2 4. 2 mhz sync pin threshold ? lo v sync_lo sync clock logic level 0.8 v sync pin threshold ? hi v sync_hi sync clock logic level (note 4) 1.8 2.5 v 5 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi parameter symbol test conditions min typ m ax units pok threshold pok t output voltage as a fraction of expected output voltage 90 % pok output low voltage v pokl with 1 ma current sink into pok 0.4 v pok output hi voltage v pokh 2.5 v v in 5.5 v v in v pok pin v oh leakage current (note 3) i pok pok high 1 a sync pin current sync pin is <2.5v <100 na note 3 : parameter not production tested but is guaranteed by design. note 4 : for proper operation of the sync circuit, the high - level amplitude of the sync signal should not be above 2.5v . 6 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi typical performance curves 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 efficiency (%) output current (a) efficiency vs. output current vout = 2.5v vout = 1.8v vout = 1.2v vout = 1.0v odto v = .v 0 10 20 0 40 50 60 0 80 0 100 0 1 2 4 5 6 outut ut a efficiency vs. output current vout = 3.3v vout = 2.5v vout = 1.8v vout = 1.2v vout = 1.0v conditions v in = 5.0v 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 1.0v conditions v in = 3.3v 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 1.2v conditions v in = 3.3v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 1.8v conditions v in = 3.3v 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 2.5v conditions v in = 3.3v 7 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi typical performance c urves (continued) 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 1.0v conditions v in = 5.0v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 1.8v conditions v in = 5.0v 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 2.5v conditions v in = 5.0v 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 0 1 2 3 4 5 6 output voltage (v) output current (a) output voltage vs. output current vout = 3.3v conditions v in = 5.0v 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 2.5 3 3.5 4 4.5 5 5.5 output voltage (v) input voltage (v) output voltage vs. input voltage load = 0a load = 2a load = 4a load = 6a odto t a = 25 v outo = 1.0v 1.80 1.85 1.0 1.5 1.800 1.805 1.810 1.815 1.820 2.5 .5 4 4.5 5 5.5 outut volta v ut volta v output voltage vs. input voltage load = 0a load = 2a load = 4a load = 6a odto t a = 25 v outo = 1.8v 8 . . 07013 october 11, 2013 rev d
en5367qi typical performance curves (continued) 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 - 40 - 15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0.1a load = 2a load = 4a load = 6a load = 8a conditions v in = 3.3v v out_nom = 1.8v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 - 40 - 15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0.1a load = 2a load = 4a load = 6a load = 8a conditions v in = 4.3v v out_nom = 1.8v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 - 40 - 15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0.1a load = 2a load = 4a load = 6a load = 8a conditions v in = 5.0v v out_nom = 1.8v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 - 40 - 15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0.1a load = 2a load = 4a load = 6a load = 8a conditions v in = 5.5v v out_nom = 1.8v 2.000 2.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de - rating vout = 1.8v vout = 2.5v conditions v in = 3.3v t jmax = 125 c ja = 22 c/w 5.5x10x3mm qfn no air flow 2.000 2.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de - rating vout = 1.0v vout = 1.8v vout = 2.5v vout = 3.3v conditions v in = 5.0v t jmax = 125 c ja = 22 c/w 5.5x10x3mm qfn no air flow 9 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi typical performance characteristics vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 3.3v vout = 2.5v no load cin = 47f (1206) cout = 47f(1206) + 10f(0805) vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 3.3v vout = 2.5v load = 6a cin = 47f (1206) cout = 47f(1206) + 10f(0805) vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 5 v vout = 1v no load cin = 47f (1206) cout = 47f(1206) + 10f(0805) vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 5 v vout = 1v load = 6a cin = 47f (1206) cout = 47f(1206) + 10f(0805) enable enable power up/down conditions vin = 5.5v, vout = 3.3v cin = 47f(1206 ) + 47nf(0805) cout = 47f(1206 ), css = 47nf vout pok no load enable enable power up/down conditions vin = 5.5v, vout = 3.3v cin = 47f(1206 ) + 47nf(0805) cout = 47f(1206 ), css = 47nf vout pok load = 6a 10 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi typical performance characteristics (continued) vout (ac coupled) load transient from 0.01 to 6a conditions vin = 5.5v, vout = 1.0v cin = 47f(1206) + 47nf (0805) cout = 47f (1206 ) load vout (ac coupled) load transient from 0.01 to 6a conditions vin = 5.5v, vout = 3.3v cin = 47f(1206) + 47nf (0805) cout = 47f (1206 ) load 11 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi functional block diagram soft start power good logic regulated voltage voltage reference compensation network thermal limit uvlo current limit mode logic p-drive n-drive pll/sawtooth generator sync enable ss agnd pok avin vfb pgnd vout nc(sw) pvin error amp pwm comp (+) (-) (-) (+) eaout btmp pg regulated voltage bgnd vddb figure 4 : functional block diagram 12 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi functional description sy nchronous buck converter the en5367qi is a synchronous, programmable power supply with integrated power mosfet switches and integrated inductor. the nominal input voltage range is 2.5v to 5.5v. the output voltage is programmed using an external resistor di vider network. the control loop is voltage - mode with a type iii compensation network. much of the compensation circuitry is internal to the device. however, a phase lead capacitor is required along with the output voltage feedback resistor divider to compl ete the type iii compensation network. the device uses a low - noise pwm topology. up to 6a of continuous output current can be drawn from this converter. the 4 mhz switching frequency allows the use of small size input / output capacitors, and realizes a wide loop bandwidth within a small foot print. protection features: the power supply has the following protection features: ? over- current protection ? thermal s hutdown with hysteresis. ? under - voltage l ockout additional f eatures: ? frequency synchronization (extern al clock) ? programmable soft -start ? output enable and power ok power up - down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. tying all three pins together meets these requirements. enable ca n also be tied to avin and come up with it, while pvin can be safely ramped up and down . alternatively, pvin can be brought high after avin is asserted, and the device can be turned on and off by toggling the enable pin. enable operation the enable pin p rovides a means to enable normal operation or to shut down the device. a logic high will enable the converter into normal operation. when the enable pin is asserted (high) the device will undergo a normal soft start. a logic low will disable the converter. a logic low will power down the device in a controlled manner and the device is subsequently shut down. the enable signal has to be low for at least the enable lock - out time ( 2.4ms) in order for the device to respond to a falling edge on this pin. note th at the device should not be enabled into a pre - biased output. pre - bias operation the en 5367 qi is not designed to be turned on into a pre - biased output voltage. be sure the output capacitors are not charged or the output of the en 5367 qi is not pre - biased wh en the en 5367 qi is first enabled. frequency synchronization the switching frequency of the dc/dc converter can be phase - locked to an external clock source to move unwanted beat frequencies out of band. to avail this feature, the clock source should be connected to the sync pin. an activity detector recognizes the presence of an external clock signal and automatically phase - locks the internal oscillator to this external clock. pha se- lock will occur as long as the input clock frequency is in the lock range specified in the electrical characteristics table. if the sync function is not to be used, this pin has to be grounded. do not float this pin or tie it to a static high voltage. spread spectrum mode the external clock frequency may be swept within the sync frequency lock range at repetition rates of up to 10 khz in order to reduce emi frequency components. soft - start operation during soft - start, the output voltage is ramped up gra dually upon start - up. the output rise time is controlled by the choice of soft - start capacitor, which is placed between the ss pin (30) and the agnd pin (32). rise time [ms]: t r (c ss [nf]* 0.08) 25% where rise time is in ms, and c ss is in nf. duri ng start- up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10ua. typical soft - start rise time is ~3.75ms with a soft- start capacitor of 47nf. the rise t ime is measured from when v in > v uvlor and enable pin voltage crosses its logic high threshold, to when v out reaches its programmed value. 13 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi pok operation the pok signal is an open drain signal (requires a pull up resistor to v in or similar voltage) from th e converter indicating the output voltage is within the specified range. the pok signal will be logic high (v in ) when the output voltage is above 90% of programmed v out . if the output voltage goes below this threshold, the pok signal will be a logic low. o ver - current protection the current limit function is achieved by sensing the current flowing through the power pfet. when the sensed current exceeds the over current trip point, both power fets are turned off for the remainder of the switching cycle. if the over - current condition is removed, the over - current protection circuit will enable normal pwm operation. if the over - current condition persists, the soft start capacitor will gradually discharge causing the output voltage to fall. when the ocp fault is r emoved, the output voltage will ramp back up to the desired voltage. this circuit is designed to provide high noise immunity. thermal overload protection thermal shutdown circuit will disable device operation when the junction temperature exceeds approxima tely 150oc. after a thermal shutdown event, when the junction temperature drops by approx 20oc, the converter will re - start with a normal soft - start. input under -v oltage lock -o ut internal circuits ensure that the converter will not start switching until the input voltage is above the specified minimum voltage. hysteresis, input de - glitch and output leading edge blanking ensure high noise immunity and prevent false uvlo triggers. compensation the en5367qi uses a type 3 compensation network. as noted earlier, a piece of the compensation network is the phase lead capacitor ca in figure 1 . this network is optimized for use with about 50f of output capacitance and will provide wide loop bandwidth and excellent t ransient performance for most applications. voltage mode operation provides high noise immunity at light load. in some applications modifications to the compensation may be required. for more information, contact altera power a pplications support. 14 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi application information the en5367qi output voltage is programmed using a simple resistor divider network. figure 1 shows the resistor divider configuration. vout vfb r a c a r ca r b figure 1: v out resistor divider & compensation capacitor the feedback and compensation network values depend on the input voltage and output voltage. calculate the external feedback and compensation network values with the equations below. r a [k ] = 30 x v in [v] *round r a up to closest standard value c a [p f] = 2975 / r a [k ] *round c a down to closest standard value r b [k ] = (v fb x r a ) / (v out ? v fb ) [v] v fb = 0.75v nominal * use closest suitable value for r b [k] r ca = v in x (1 .95 ? 0.46 x v out ) k input capacitor selection the en5367qi requires a 47 f /1206 and a 47nf/0805 input capacitor . low - cost, low - esr ceramic capacitors should be used as input capacitors for this converter. the dielectric must be x5r or x7r rated. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. the first capacitor next to the pvin and pgnd pins must be a 47nf, 0805, x7r capacitor. behind this first capacitor there can be either a single 47 f capacitor or 2x22 f capacitors. refer to t able 1 for recommendations . recommended input capacitors description mfg p/n 47n f, 50v or 25v , 1 0% x7 r, 0805 (1 capacitor needed ri g ht next to device input pins ) murata grm21br71h473ka0 1l taiyo yuden tmk212b7473kd -t 47 f , 10v, 2 0% x5 r, 1206 (1 capacitor needed in parallel with 47nf above ) murata grm31cr61a476me15l taiyo yuden lmk316bj476ml -t 22 f , 10v, 20% x5r, 1206 (2 capacitor s needed in parallel with 47nf above ) murata grm31cr6 1 a2 2 6me19l taiyo yuden lmk316bj226ml -t table 1. recommended input capacitors output capacitor selection the en5367qi has been nominally optimized for use with a 47f/1206 output capacitor . for better output ripple performance, use an additional 10f/080 5 capacitor. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. refer to t able 2 for recommendations . output ripple voltage is determined by the aggregate output capacitor impedance. output impedance, denoted as z, is comprised of effective series resistance, esr, and effective series inductance, esl: z = esr + esl placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. n total zzzz 1 ... 111 21 +++= typical ripple voltages output capacitor configuration typical output ripple (mvp - p) (as measured on en 5367 qi evaluation board)* 1 x 47 f 17 47 f + 10 f 9 * note: 20 mhz bw limit 15 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi recommended output capacitors description mfg p/n 47 f , 6.3v, 20% x5r, 1206 (1 capacitor needed) murata grm31cr60j476me19l taiyo yuden jmk316bj476ml - t 10 f , 10 v, 10% x5r, 1206 (optional 1 capacitor in parallel with 47 f above) murata grm31cr71a106ka01l taiyo yuden lmk316bj226ml -t table 2 . recommended out put capacitors power - up sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. tying all three pins together meets these requirements. technical suport contact altera power applications support regarding the use of this product ( www.altera.com/mysupport ). 16 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi thermal considerations thermal considerations are important power supply design facts that cannot be avoided in the real world. whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted f or. the altera enpirion en5367 qi dc -d c converter is packaged in a 5.5 x10 x3mm 54- pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (pcb) to act as a heat sink. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c may reduce long - term reliability. the device has a thermal over load protec tion circuit designed to turn off the device at an approximate junction temperature value of 150c. the following example and ca lculations illustrate the thermal performance of the en5367 qi. example: v in = 5v v out = 3.3v i out = 6a first calcula te the output power. p ou t = 3.3v x 6 a = 19.8 w next, determine the input power based on the efficiency () shown in figure 6 . figure 6 : effi ciency vs. output current for v in = 5v, v out = 3.3v at 6a , 88 % = p out / p in = 88 % = 0. 88 p in = p out / p in 19.8 w / 0. 88 22.5 w the power dissipation (p d ) is the power loss in the system and can be calculated by subtracting the output power from the input power. p d = p in ? p out 22.5 w ? 19.8 w 2.7 w with the power dissipation known , the temperature ri se in the device may be estimated based on the t heta ja value ( ja ). the ja parameter estimates how much the temperature will rise in the device for every watt of power dissipation. the en5367 qi has a ja value of 22 oc/w without airflow. determine the ch ange in temperature (t) based on p d and ja . t = p d x ja t 2.7 w x 22 c/w = 59.4 c 60c the junction temperature (t j ) of the device is approximately the ambient temperature (t a ) plus the change in temperature. we assume the initial ambient temperature to be 25c. t j = t a + t t j 25c + 60 c 85 c the maximum operating junction temperature (t j max ) of the device is 125c, so the device can operate at a higher ambient temperature. the maximum ambient temperature (t amax ) allowed can be calculated. t amax = t j max ? p d x ja 125c ? 60 c 65 c the ma ximum ambient temperature the device can reach is 6 5 c given the input and output conditions . note that the efficiency will be slightly lower at higher temperature s and this calculation is an esti mat e. 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v conditions v in = 5.0v 88% 17 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi engineering schematic figure 7: engineering schematic with engineering notes 18 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi layout recommendation figure 8 : top layout with critical components only (top view) . see figure 7 for corresponding schematic. this layout only shows the criti cal components and top layer traces for minimum footprint in single - supply mode with enable tied to avin. alternate circuit configurations & other low - power pins need to be connected and routed according to customer application. please see the gerber files at www. altera.com/enpirion for details on all layers. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en5367 qi package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the en5367 qi should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: the pgnd connections for the input and output capacitors on layer 1 need to have a slit between them in order to provide some separa tion between input and output current loops. recommendation 3 : the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and the input/output capacit ors. re comme ndation 4 : the thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. the drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the insi de wall, making the finished hole size around 0.20 - 0.26mm. do not use thermal reliefs or spokes to connect the vias to the ground plane. this connection provides the path for heat dissipation from the converter. re comme ndation 5 : multiple small vias (the same size as the thermal vias discussed in recommendation 4 ) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias along the edge of the gnd copper closest to th e +v copper. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. recommendation 6 : avin is the power supply for the small - signal control circuits. it should b e connected to the input voltage at a quiet point. in figure 8 this connection is made at the input capacitor. recommendation 7 : the layer 1 metal under the device must not be more than shown in figure 8 . refer to the section regarding e xposed m etal on b ot tom of p ackage. as with any switch - mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. re comme ndation 8: the v out sense point should be just after the last output filter capacitor. keep the sense trace short in order to avoid noise coupling into the node. recommendation 9 : keep r a , c a , r b , and r ca close to the vfb pin (refer to figure 8 ). the vfb pin is a high - impedance, sensitive node. keep the trace to this pin as short as possible. whe never possible, connect r b directly to the agnd pin instead of going through the gnd plane. recommendation 10: follow all the layout recommendations as close as possible to optimize performance. altera enpirion provides schematic and layout reviews for all customer designs. please contact local s ales r epresentatives for references to altera power applications support . 19 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi design considerations for lead -frame based modules exposed metal on bottom of package lead- frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead - frame cantilevers be exposed at the point where wire - bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package, as shown in figure 9. only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the pc board. the pcb top layer under the en5367 qi should be clear of any metal (copper pours, traces, or vias) except for the thermal pad. the ? shaded - out? area in figure 9 represents the area that should be clear of any metal on the top layer of the pcb. any layer 1 metal under the shade d- out area runs the risk of undesirable shorted connections even if it is covered by soldermask. the s older s tencil a perture should be smaller than the pcb ground pad. this will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. please consult en5367 qi qfn package soldering guidelines for more details and recommendations. figure 9 : lead- frame exposed metal (bottom view) shaded area highlights exposed metal that is not to be mechanically or electrically connected to the pcb. 20 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi recommended pcb footprint figure 1 0 : en 5367 qi pcb footprin t ( top view) the solder stencil aperture for the thermal pad is shown in blue and is based on enpirion power product manufacturing specifications. 21 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi package and mechanical figure 1 1 : en5367 qi package dimensions (bottom view) packing and marking information : www.altera.com/support/reliability/packing/rel - packing - and- marking.html 22 www.alter a .com/enpirion 07013 october 11, 2013 rev d
en5367qi contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 4 08-544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quart us and st rat ix w ords and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 23 www.alter a .com/enpirion 07013 october 11, 2013 rev d

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