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| 25a highly integrated sup ir buck ? single - input voltage, synchronous buck regulator ir3447 1 www.irf.com ? 20 1 5 international rectifier submit datasheet feedback j une 18, 2015 features ? single 5v to 21v application ? wide input voltage range from 1.5v to 21v with external vcc ? output voltage range: 0.6v to 0. 8 6 *p vin ? 0.5% accurate reference voltage ? enhanced line/load regulation with feed - f orward ? programmable switching frequency up t o 1.5mhz ? internal digital soft - start ? enable input with voltage monitoring capability ? remote sense amplifier with true differential voltage sensing ? thermally compensated current limit and hiccup mode over current protection ? smart ldo to enhance efficiency ? external synchronization with smooth clocking ? dedicated output voltage sensing for power good indication and overvoltage protection which remains active even when enable is low. ? enhanced pre - bias start up ? body braking to improve transient ? integrated mosfe t drivers and bootstrap diode ? thermal shut down ? post package trimmed rising edge dead - time ? programmable power good output ? small size 5mm x 6mm pqfn ? operating junction t emp: - 40 o c ir3447 3 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 functional block dia gram comp cbyp fb smart ldo vin lgnd dcm vcc / ldo _ out uvcc enable uven control logic rt / sync pgd over current driver + body braking control hdin ldin hdrv ldrv digital soft start ssok uven vsns oc fault intl _ ss fault boot pvin sw pgnd ov thermal shutdown fault control tsd uvcc oc + + - e / a over voltage por por uvcc zero crossing comparator zc por uvcc vref pvin por ocset rso rs + rs - vcc - + 0 . 6 v por clk vref fb fb dcm vref figure 3 : ir34 47 simplified block diagram ir3447 4 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 pin descriptions pin # pin name pin description 1 pv in input voltage for po wer stage. bypass capacitors between pvin and pgnd should be connected very close to this pin and pgnd; also forms input to feedforward block 2 boot supply voltage for high side driver 3 enable enable pin to turn ing on and off the ic. 4 r t /sync use an e xternal resistor from this pin to lgnd to set the switching frequency, very close to the pin. this pin can also be used for external synchronization. 5 oc set current limit setpoint. this pin allows the trip point to be set to one of three possible setting s by either floating this pi n, tying it to vcc or tying it to pgnd. 6 vsns sense pin for ovp and pgood 7 fb inverting input to the error amplifier. this pin is connected directly to the output of the regulator or to the output of the remote sense amplifi er, via resistor divider to set the output voltage and provide feedback to the error amplifier. 8 comp output of error amplifier. an external resistor and capacitor network is typically connected from this pin to fb to provide loop compensation. 9 rso re mote sense amplifier output 10, 26, 27, 29 pgnd power ground. this pin should be connected to the system?s power ground plane. bypass capacitors between pvin and pgnd should be connected very close to pvin pin (pin 1) and this pin. 11 lgnd signal ground for internal reference and control circuitry. 12 rs - remote sense amplifier input. connect to ground at the load. 13 rs+ remote sense amplifier input. connect to output at the load. 14 cb yp bypassing capacitor for internal reference voltage. a capacitor between 1 00 p f and 1 8 0 p f should be connected between this pin and lgnd. 15 , 19, 28, 30, 31, 33 nc no connection. 16 pgd power good status pin. output is open drain. connect a pull up resistor from this pin to vcc. 17 vin input voltage for ldo. 18 vcc / ldo_out bias voltage for ic and driv er section, output of ldo. add a minimum of 4.7 uf bypass cap from this pin to pgnd. 20, 21, 22, 23, 24, 25, 32 sw switch node. this pin is connected to the output inductor. ir3447 5 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 absolute maximum rat ings stresses beyond t hose listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifica tions are not implied. pvin - 0.3v to 25v vin - 0.3v to 25v vcc - 0.3v to 8v (note 1) sw - 0.3v to 25v (dc), - 4v to 25v (ac, 100ns) boot - 0.3v to 33v boot to sw - 0.3v to vcc + 0.3v (note 2) input/output pins - 0.3v to 3.9v rs+, rs - , rso, pgd, enable, ocset - 0.3v to 8v (note 1) pgnd to lgnd, rs - to lgnd - 0.3v to + 0.3v junction temperature range - 40c to 150c storage temperature range - 55c to 150c esd machine model class a human body model class 1c charged device model class iii moisture s ensitivity level jedec level 3 @ 26 0c rohs compliant yes note : 1. vcc must not exceed 7.5v for junction temperature between - 10c and - 40c. 2. must not exceed 8v. thermal information thermal resistance, junction to case top ( jc_top ) 31.5 c/w thermal resistance, junction to pcb ( jb ) 2.41 c/w thermal resistance , junction to ambient ( ja ) (n ote 3) 14.7 c/w note: 3. thermal resistance ( ja ) is measured with components mounted on a high effective thermal conductivity test board. ir3447 6 www.irf.com ? 20 1 5 international rectifier submit datasheet feedback j une 18, 2015 electrical specifications recommended operatin g conditions symbol definition min max units pvin input bus voltage * 1.5 21 v vin supply voltage 5.0 21 vcc supply voltage ** 4.5 7.5 boot to sw supply voltage 4.5 7.5 v o output voltage 0 .6 0.8 6 * p vin i o output current 0 25 a fs switching frequency 30 0 1 5 0 0 khz t j junction temperature - 40 125 c * sw node must not exceed 25v ** when vcc is connected to an externally regulated supply, also connect vin. electrical character istics unless otherwise specified, these specification apply over, 1.5v < p vin < 21 v, 4.5v < vcc < 7.5v, 0 o c < t j < 125 o c. typical values are specified at t a = 25 o c. parameter symbol conditions min typ max unit power loss power loss p loss v in = p v in = 12v, v o = 1. 2 v, i o = 25a, fs = 600khz, l=0. 215 uh, t a = 25c , note 4 3.62 w mosfet r ds(on) top switch rds(on)_top v boot ? v sw = 6. 8 v, i d = 25a, tj = 25c 4 5.2 m? bottom switch rds(on)_bot vcc =6.8 v, i d = 25a, tj = 25c 1.8 2.3 reference voltage feedback voltage v fb 0.6 v accuracy vref=0.6v, 0c < tj < 105c - 0.5 +0.5 % vref=0.6v, - 40c < tj < 125c - 1.0 +1.0 supply current v in supply curre nt (standby) i in(standby) vin=21v, enable low, no switching 300 425 a v in supply current (dyn) i in(dyn) vin=21v, enable high, fs = 600khz 40 ma vcc supply current (standby) i cc(standby) enable low, vcc =7v, no switching 300 425 a ir3447 7 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 parameter symbol conditions min typ max unit vcc supply c urrent (dyn) i cc(dyn) enable high, vcc =7v, fs = 600khz 40 ma under voltage lockout vcc ? start ? threshold vcc_uvlo_start vcc rising trip level 4.0 4.2 4.4 v vcc ? stop ? threshold vcc_uvlo_stop vcc falling trip level 3. 8 3.9 4. 2 enable ? start ? threshold enable_uvlo_start supply ramping up 1.14 1.2 1.36 v enable ? stop ? threshold enable_uvlo_stop supply ramping down 0.9 1.0 1.06 enable leakage current ien enable=3.3v 1 a oscillator rt voltage 1 v frequency range f s rt=80.6k 270 300 330 khz rt=39.2k 540 600 660 rt=15k 1350 1500 1650 ramp amplitude vramp pvin=6.8v, pvin(max) slew rate=1v/us , note 4 1.02 vp - p pvin=12v, pvin(max) slew rate=1v/us , note 4 1.8 pvin=16v, pvin(max) slew rate=1v/us , note 4 2.4 ramp offset ram p (os) note 4 0.16 v min pulse width tmin (ctrl) note 4 50 ns fixed off time note 4 200 230 ns max duty cycle dmax fs=300khz, pvin=vin=12v 86 % sync frequency range note 4 270 1650 khz sync pulse duration 100 200 ns sync level threshold high 3 v low 0.6 error amplifier input offset voltage vos_ cb yp vfb ? vref , vref = 0.6v - 1.5 +1.5 % input bias current ifb(e/a) - 0.5 +0.5 a sink current isink(e/a) 0.4 0.85 1.2 ma source current isource(e/a) 4 5 11 ma slew rate s r note 4 7 12 20 v / s gain - bandwidth product gbwp note 4 20 30 40 mhz dc gain gain note 4 100 110 120 db ir3447 8 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 parameter symbol conditions min typ max unit maximum output voltage vmax(e/a) 1.7 2 2.3 v minimum output voltage vmin(e/a) 100 mv common mode voltage vcm_vp note 4 0 1.2 v remote sen se differential amplifier unity gain bandwidth bw_rs note 4 3 6.4 9 mhz dc gain gain_rs note 4 110 db offset voltage offset_rs vref=0.6v, 0c < tj < 85c - 1.5 0 1.5 mv vref=0.6v, - 40c < tj < 125c - 2 2 mv source current isource_rs 3 13 2 0 m a sink current isink_rs 0.4 1 2 ma slew rate slew_rs note 4 , cload = 100pf 2 4 8 v / s rs+ input impedance rin_rs+ 45 63 85 kohm rs - input impedance rin_rs - note 4 63 kohm maximum voltage vmax_rs v(vcc) ? v(rs o ) 0.5 1 1.5 v minimum voltage min _rs 50 mv internal digital soft start soft start clock clk_ss note 4 180 200 220 khz soft start ramp rate ramp(ss_start) note 4 0.3 0.4 0.5 mv / s bootstrap diode forward voltage i(boot) = 30ma 360 520 960 mv switch node sw leakage current lsw sw = 0v, enable = 0v 1 a internal regulator (vcc/ldo) output voltage vcc vin(min) = 7.2v, io=0 - 30ma, cload = 2.2uf, dcm=0 6.3 6.8 7.1 v vin(min) = 7.2v, io=0 - 30ma, cload = 2.2uf, dcm=1 4 4.4 4.8 vcc dropout vcc_drop vin = 7v, io=70 ma, cload = 2.2uf 0.7 v short circuit current ishort note 4 70 ma zero - crossing comparator delay tdly_zc 256 / fs s zero - crossing comparator offset vos_zc note 4 0 mv ir3447 9 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 parameter symbol conditions min typ max unit body braking bb threshold bb_threshold fb > vref, sw duty cycle, note 3 0 % faults power good power good low upper t hreshold vpg_low(upper) vsns rising 115 120 125 % vref power good l ow upper threshold falling delay vpg_low(upper)_dly vsns > vpg_low(upper) 1.5 2.5 3.5 s power good high lower t hreshold vpg_high(lower) vsns rising 95 % vref power good h igh lower threshold rising delay vpg_high(lower)_dly vsns rising 1.28 ms power good low lower t hreshold vpg_low(lower) vsns falling 90 % vref power good low lower threshold falling d elay vpg_low(lower)_dly vsns < vp g_low(lower) 101 150 199 s pgood voltage low pg (voltage) i pgood = - 5ma 0.5 v over voltage protection (ovp) ovp trip threshold ovp (trip) vsns rising 115 120 125 % vref ovp fault prop delay ovp (delay) vsns rising 1.5 2.5 3.5 s over - current pr otection oc trip current i trip ocset=vcc, vcc = 6.8v, tj = 25c 29.25 32.5 35.75 a ocset=floating, vcc = 6.8v, tj = 25c 23.4 26 28.6 a ocset=pgnd, vcc =6.8v, tj = 25c 17.55 19.5 21.8 5 a hiccup blanking time tblk_hiccup note 4 20.48 ms therma l shutdown thermal shutdown note 4 145 c hysteresis note 4 20 c notes : 4 . guaranteed by design but not tested in production. ir3447 10 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical efficiency a nd power loss curves pvin = vin = 12v, vcc = internal ldo, io=0 - 25a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the efficiency measuremen t. vout (v) lout (uh) p/n dcr (m) 1.0 0.215 pcdc1008 - r215emo (cyntec) 0.29 1.2 0.215 pcdc1008 - r215emo (cyntec) 0.29 1.8 0.311 fp1109 - r33 - r ( coiltronics ) 0.42 3.3 0.68 74433 2 0 068 (wurth elektronik) 0. 7 2 ir3447 11 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical efficiency a nd power loss cu rves pvin = 12v, vin = vcc = 5v, io=0 - 25a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the efficiency measurement. vout (v) lout (uh) p/n dcr (m) 1.0 0.215 pcdc1008 - r215emo (cyntec) 0.29 1.2 0.215 pcdc1008 - r215emo (cyntec) 0.29 1.8 0.311 fp1109 - r33 - r (coiltronics) 0.42 3.3 0.68 7443320068 (wurth elektronik) 0. 7 2 ir3447 12 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical efficiency a nd power loss curves pvin = vin = vcc = 5v, io=0 - 25a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages i n the efficiency measurement. vout (v) lout (uh) p/n dcr (m) 1.0 0.215 pcdc1008 - r215emo ( cyntec ) 0.29 1.2 0.215 pcdc1008 - r215emo (cyntec) 0.29 1.8 0.311 fp1109 - r33 - r (coiltronics) 0.42 ir3447 13 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 thermal derating cur ves measurements are done on ir3 4 47 evaluation board. pcb is a 6 layer board with 2 oz copper and fr4 material. vin=pvin=12v, vout =1.2v, vcc =internal ldo (6.8v), fs = 600khz vin=pvin=12v, vout = 5.0 v, vcc=internal ldo (6.8v), fs = 600khz note: international rectifier corporation specifies current rating of supirbuck devices conservative ly. the continuous current l oad capa bility might be higher than the rating of the device if input voltage is 12v typical and switching frequency is below 60 0khz. however, the maximum current is limited by the internal current limit and designers need to consider enough guard bands between load current and minimum current limit to guarantee that the device does not trip at steady state condition. ir3447 14 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 mosfet rdson variation over temperature ir3447 15 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating ch aracteristics ( - 40c to +125c) ir3447 16 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating characteristics ( - 40c to +125c) ir3447 17 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating characteristics ( - 40c to +125c) ocset=v c c ocset=float ocset=gnd ocset=v c c ocset=float ocset=gnd ocset=v c c ocset=float ocset=gnd ir3447 18 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 theory of operation description the ir34 47 uses a pwm voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. the switching frequency is programmable from 300khz to 1.5mhz and provides the capability of optimizing the design in terms of size and performance. ir34 47 provides precisely regulated output voltage programmed via two external resistors from 0. 6 v to 0.86* p vin. the ir34 47 operates with an internal bias supply (ldo) which is connected to the v cc pin. this allows operation with single supply. the bias voltage is variable according to load condition. if the output load current is less than half of the peak - to - peak inductor current, a lower bias voltage, 4.4v, is used as the internal gate drive voltage; otherwise, a higher voltage, 6. 8 v, is used. this feature helps the converter to reduce power losses. the device can also be operated with an external supply from 4.5 v to 7.5v, allowing an extended operating inp ut voltage (pvin) range from 1.5 v to 21v. for using the in ternal ldo supply, the vin pin should be connected to pvin pin. if an external supply is used, it should be connected to v cc pin and the vin pi n should be shorted to vcc pin. the device utilizes the on - resistance of the low side mosfet (synchronous mosfet) as current sense element. this method enhances the converter?s efficiency and reduces cost by eliminating the need for external current sense resistor. ir34 47 includes two low r ds(on) mosfets using ir?s hexfet technology. these are specifically designed f or high efficiency applications. under - voltage lockout and por the under - voltage lockout circuit monitors the voltage of v cc pin and the enable input. it assures that the mosfet driver outputs remain in the off state whenever either of these two signals drop s below the set thresholds. normal operation resumes once v cc and enable rise above their thresholds. the por (power on ready) signal is generated when all these signals reach the valid logic level (see system block diagram). when the por is asserted t he soft start sequence starts (see soft start section). enable the enable features another level of flexibility for start up. the enable has precise threshold which is internally monitored by under - voltage lockout (uvlo) circuit. therefore, the ir34 47 will turn on only when the voltage at the enable pin exceeds this threshold, typically, 1.2v. if the input to the enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the ir34 47 does not turn on until the bus voltage reaches the desired level figure 4 . only after the bus voltage reaches or exceeds this level and voltage at the enable pin exceeds its threshold, ir34 47 will be enabled. therefore, in addition to being a l ogic input pin to enable the ir34 47 , the enable feature, with its precise threshold, also allows the user to implement an under - voltage lockout for the bus voltage (pvin). it can help prevent the ir34 47 from regulating at low pvin voltages that can cause e xcessive input current. vcc pvin intl _ ss en > 1 . 2 v 1 . 2 v en _ uvlo _ start 10 . 2 v 12 v figure 4 : normal start up, device turns on when the bus voltage reaches 10.2v a resistor divider is used at en pin from pvin to turn on the device at 10.2v. ir3447 19 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 vcc pvin = vin intl _ ss en > 1.2v vo figure 5 : recommended startup for normal operation figure 5 shows the recommended startup sequence for the typical operation of ir3 4 47 with enable used as logic input. pre - bias st artup ir34 47 is able to start up into pre - charged output, which prevents oscillation and disturbances of the output voltage. the output starts in asynchronous fashion and keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (ctrl fet) is generated . figure 6 shows a typical pre - bias condition at start up. the sync fet always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. the number of these startup pulses for each step is 16 and it?s internally programmed. figure 7 shows the series of 16x8 startup pulses. vo [ v ] [ time ] pre - bias voltage figure 6 : pre - bias startup ... ... ... hdrv ... ... ... 16 end of pb ldrv 12 . 5 % 25 % 87 . 5 % 16 ... ... ... ... figure 7 : pre - bias startup pulses soft - start ir34 47 has an internal digital soft - start to control the output voltage rise and to limit the current surge at the start - up. to ensure correct start - up, the soft - start sequence initiates when the enable and v cc rise above their uvlo thresholds and generate the power on ready (por) signal. the internal soft - start (intl_ss) signal linearly rises with the rat e of 0. 4 mv/s from 0v to 1.5v. figure 8 shows the waveforms during soft start. the normal vout start up time is fixed, and is equal to: ( ) ms s mv v v tstart 5 . 1 / 4 . 0 15 . 0 75 . 0 = ? = ( 1 ) during the soft start th e over - current protection (ocp) and over - voltage protection (ovp) is enabled to protect the device for any short circuit or over voltage condition. por intl _ ss vout 0 . 15 v 0 . 75 v t 1 t 2 t 3 1 . 5 v 3 . 0 v figure 8 : theoretical operation waveforms during sof t - start operating frequency the switching frequency can be programmed between 300khz ? 1500khz by connecting an external resistor ir3447 20 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 from r t pin to lgnd . table 1 tabulates the oscillator frequency versus r t . table 1 : switching freque ncy(fs) vs. external resistor( rt ) rt (k?) freq (khz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 21 1100 19.1 1200 17.4 1300 16.2 1400 15 1500 shutdown ir34 47 can be shutdown by pulling the enable pin belo w its 1.0 v threshold. during shutdown t he hig h side and the low side drivers are turned off . over current protect ion the o ver c urrent (oc) protection is performed by sensing the inductor current through the r ds(on) of the synchronous m osfet . this method enhances the converter?s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. the over c urrent (oc) limit can be set to one of three possible s ettings by floating the ocset pin, by pulling up the ocset pin to v cc, o r pulling down the ocset pin to pgnd. the current limit scheme in the ir34 47 uses an internal temperature compensated current source to achieve an almost constant oc limit over temperature . over current protection circuit senses the inductor current flowi ng through the synchronous mosfet. to help minimize false tripping due to noise and transients, inductor current is sampled for about 30 ns on the d ownward inductor current slope approximately 12.5% of the switching period before the inductor current valle y. however, if the synchronous mosfet is on for less than 12.5% of the switching period, the current is sampled approximately 40ns after the start of the downward slope of the inductor current. when the sampled current is higher than the oc limit, an oc event is detected. when an over current event is detected, the converter enters hiccup mode. hiccup mode is performed by latching the oc signal and pulling the intl_ss signal to ground for 20.48 ms (typ.). oc signal clears after the completion of hiccup mode and the converter attempts to return to the nominal output voltage using a soft start sequence . the converter will repeat hiccup mode and attempt to recover until the overload or short circuit condition is removed. because the ir34 47 uses valley curr ent sensing, t he actual dc output current limit will be greater than oc limit . the dc output current is approximately half of peak to peak inductor ripple current above selected oc limit. oc limit, inductor value, input voltage , output voltage and switchi ng frequency are used to calculate the dc output current limit for the converter . equation (2) to determine the approximate dc output current limit. 2 i i i limit ocp ' ( 2 ) i ocp = dc current limit hiccup point i limit = current limit valley point ? l = inductor ripple current 0 0 current limit 0 ... ... 0 hiccup tblk_hiccup 20.48 ms* *typical filter delay pgd ldrv hdrv il figure 9 : timing diagram for current limit hiccup thermal shutdown temperature sensing is provided inside ir34 47 . the trip threshold is typically 145 o c. when trip threshol d is exceeded, thermal shutdown turns off both mosfets and resets the internal soft start. ir3447 21 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 automatic restart is initiated when the sensed temperature drops within the operating range. there is a 20 o c hysteresis in the thermal shutdown threshold. remote vol tage sensing true differential remote sensing in the feedback loop is critical to high current applications where the output voltage across the load may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. the rs+ and rs - pins of the ir34 47 form the inputs to a remote sense differential amplifier (rsa) with high speed, low input offset and low input bias current which ensure accurate voltage sensing and fast transient response in such applications. the input range for the differential amplifier is limited to 1.5v bel ow the vcc rail. note that ir34 47 incorporates a smart ldo which switches the vcc rail voltage depending on the loading. when determining the in put range assume the part is in light load and using the lower vcc rail voltage. there are two remote sense configurations that are usually implemented. figure 10 shows a general remote sense (rs ) configuration. t his configuration allows the rsa to monitor output voltages above vcc. a resistor divider is placed in between the output and the rsa to provide a lower input voltage to the rsa inputs. typically, the resistor div id er is calculated to provide vref (0.6v) across the rsa inputs which is then outputted to rso. the input impedance of the rsa is 63 kohms typically and should be accounted for when determining values for the resistor divider. to account for the input impedance, assume a 63 kohm resistor in paral lel to the lower resistor in the divider network. the compensation is then designed for 0.6v to match the rso value. low voltage applications can use the second remote sense configuration. when the output voltage range is within the rsa input specificati ons, no resistor divider is needed in between the converter output and rsa. the second configuration is shown in figure 11. the rsa is used as a unity gain buffer and compensation is determined normally. ( < vcc - 1 . 5 v ) rsa + - + - rs + rs - rso vout fb compensation resistor divider figure 10 : general remote sense configuration + - vout (< vcc-1.5v) vo rsa + - rs+ rs- rso fb compensation figure 11 : remote sense configuration for vout less than vcc - 1.5v external synchroniza tion ir34 47 incorpor ates an internal phase lock loop (pll) circuit which enables synchronization of the internal oscillator to an external clock. this function is important to avoid sub - harmonic oscillations due to beat frequency for embedded systems when multiple point - of - lo ad (pol) regulators are used. a multi - function pin, rt/sync, is used to connect the external clock. if the external clock is present before the converter turns on, rt/sync pin can be connected to the external clock signal solely and no other resistor is ne eded. if the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free - running frequency, an external resistor from rt/sync pin to lgnd is require d to set the free - running frequency. when an external clock is applied to rt/sync pin after the converter runs in steady state with its free - running frequency, a transition from the free - running frequency to the external clock frequency will happen. this transition is to gradually make the actual switching frequency equal to the external clock frequency, no matter which one is higher. w hen the external clock signal is removed from rt/sync pin, the switching frequency is also changed to free - running gradual ly. in order to minimize the impact from these ir3447 22 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 transitions to output voltage, a diode is recommended to add between the external clock and rt/sync pin. figure 12 shows the timing diagram of these transitions. an i nternal circuit is used to change the pwm ramp slope according to the clock frequency applied on rt/sync pin. even though the frequency of the external synchronization clock can vary in a wide range, the pll circuit keeps the ramp amplitude constant, requi ring no adjustment of the loop compensation. p vin variation also affects the ramp amplitude, which will be discussed separately in feed - forward section. sw sync ... ... gradually change fs 1 fs 2 fs 1 free running frequency synchronize to the external clock return to free - running freq gradually change figure 12 : timing diagram for synchronization to t he external clock (fs1>fs2 or fs1 ir3447 24 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 respectively. pgood signal is high whenever vsns voltage is within the pgood comparator window thresholds. hysteresis has been applied to the lower threshold, pgood signal goes low when vsns drops below vpg_low(lower) instead of v pg_high(lower) . the pgood pin is open drain and it needs to be externally pulled high. high state indicates that output is in regulation. figure 19 show the timing diagram of the pgood signal. vsns signal is also used by ovp comparator for detecting output over voltage condition. pgood signal is low when enable is low. 0 0 0 cbyp pgd vsns 0 . 6 v 1 . 2 * vref 1 . 28 ms ovp latch 0 . 95 * vref 150 us 0 . 9 * vref figure 19 : pgood timing diagram over - voltage protection ( ovp) over - voltage protection in ir34 47 is achieved by comparing sense pin voltage vsns to a pre - set threshold . when vsns exceeds the over voltage threshold, an over voltage trip signal asser ts after 2 .5 u s (typ.) delay. t he hig h side drive signal hdrv is latched off immediately and pgood flags are set low. the low side drive signal is kept on until the vsns voltage drops below the threshold. hdrv remains latched off until a reset is performed by cycling v cc . ovp is active when enable is high or low. vsns voltage is set by the voltage divider c onnected to the output and i t can be programmed externally. figure 20 shows the timing diagram for ovp. hdrv 0 0 0 ldrv vsns 1 . 2 * vref comp 0 0 pgd vref 2 . 5 us figure 20 : timing diagram for ovp in non- tracking mode body braking tm the body braking feature of the ir34 47 allows improved transient response for step - down load transients. a severe step - down load transient would cause an overshoot in the output voltage and drive the comp pin voltage down until control saturati on occurs demanding 0% duty cycle and the pwm input to the control fet driver is kept off. when the f irst such skipped pulse occurs, the ir3 4 47 enters body braking mode, wherein the sync fet also turned off. the inductor current then decays by freewheeli ng through the body diode of the sync fet. thus, with body braking, the forward voltage drop of the body diode provides and additional voltage to discharge the inductor current faster to the light load value as shown in equation ( 3 ) and equation ( 4 ) below: l v v dt di d o l + ? = , with body braking ( 3 ) l v dt di o l ? = , without body braking ( 4 ) i l = inductor current v d = forward voltage drop o f the body diode of the sync fet. v o = output voltage l = inductor value the body braking mechanism is kept off during pre - bias operation. also, in the event of an extremely severe load step - down transient causing ovp, the ir3447 25 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 body brake is overridden by the ovp latch, which turns on the sync fet. minimum on time cons iderations the minimum on time is the shortest amount of time for ctrl fet to be reliably turned on. this is very critical parameter for low duty cycle, high frequency applications. conventional approach limits the pulse width to prevent noise, jitter and pulse skipping. this results to lower closed loop bandwidth. ir has developed a proprietary scheme to improve and enhance minimum pulse width which utilizes the benefits of voltage mode control scheme with higher switching frequency, wider conversion ratio and higher closed loop bandwidth, the latter results in reduction of output capacitors. any design or application using ir34 47 must ensure operation with a pulse width that is h igher than the minimum on - time. this is necessary for the circuit to operate without jitter and pulse - skipping, which can cause high inductor current ripple and high output voltage ripple. s in out s on f pv v f d t = = ( 5 ) in any application that u ses ir34 47 , the following condition must be satisfied: on on t t (min) ( 6 ) s in out on f pv v t (min) ( 7 ) (min) on out s in t v f pv ( 8 ) the minimum output voltage is li mited by the reference voltage and hence v out(min) = 0. 6 v. therefore, for v out(min) = 0. 6 v, (min) on out s in t v f pv ( 9 ) s v ns v f pv s in / 12 50 6 . 0 = therefore, at the maximum recommended input voltage 21v and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 571 khz. c onversely, for operation at the maximum recom mended operating frequency (1.5 mhz) an d minimum output voltage (0.6 v). the input voltage (pvin) should not exceed 8 v , ot herwise pulse skipping may happen. maximum duty ratio a certain off - time is specified for ir34 47 . this provides an upper limit on the operating duty ratio at any given switching frequency. the off - time remains at a relatively fixed ratio to switching peri od in low and mid frequency range, while in high frequency range this ratio increases, thus the lower the maximum duty ratio at which ir34 47 can operate. figure 21 shows a plot of the maximum duty ratio vs. the sw itching frequency with built in input voltage feed forward mechanism. figure 21 : maximum duty cycle vs. switching frequency ir3447 26 www.irf.com ? 20 1 5 international rectifier submit datasheet feedback j une 18, 2015 typical operating waveform design example the following example is a typical application for ir34 47 . t he application circuit is shown in figure 28. v in = pv in = 12v f s = 600khz v o = 1.2v i o = 25a ripple voltage = 1% * v o v o = 4% * vo (for 3 0% load transient) enabling the ir34 47 as explained earlier, the precise threshold of the enable lends itself well to implementation of a uvlo for the bus voltage as shown in figure 22. r 1 r2 enable ir3447 pvin figure 22 : using enable pin for uvlo i mplementation for a typical enable threshold of v en = 1.2 v 2 . 1 2 1 2 (min) u en in v r r r pv ( 10) en in en v pv v r r (min) 1 2 ( 11 ) for p v in (min) =9.2v, r 1 =49.9k and r 2 =7.5k ohm is a good choice. programming the f requency for f s = 600 khz, select r t = 39.2 k , using table 1 . output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb pin is the inverting input of the error amplifier, which is internally referenced to vref. the divider ratio is set to equal vref at the fb pin when the output is at its desired value. when an external resistor divider is connected to the output as shown in figure 23 , the output voltage is defined by using the following equation: ? ? 1 ? u 6 5 1 r r v v ref o ( 12 ) ? ? 1 ? u ref o ref v v v r r 5 6 ( 13 ) for the calculated values of r5 and r6, see feedback compensatio n section. r5 r6 fb ir3447 vout figure 23 : typ ical application of the ir34 47 for programming the output voltage bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v gr eater than the voltage at the sw pin, which is connected to the source of the control fet. this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (c1). the operation of the cir cuit is as follows: when the sync fet is turned on, the capacitor node connected to sw is pulled down to ground. the capacitor charges towards v cc through the internal bootstrap diode ( figur e 24 ), which has a forwa rd voltage drop v d . the voltage v c across the bootstrap capacitor c1 is approximately given as: d cc c v v v # ( 14 ) ir3447 27 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 when the control fet turns on in the next cycle, the capacitor node connected to sw rises to the bus v oltage v in . however, if the value of c1 is appropriately chosen, the voltage v c across c1 remains approximately unchanged and the voltage at the boot pin becomes: d cc in boot v v v v ? + ? ( 15 ) l vc c 1 v cc sw + - boot pgnd + v d - ir3447 cvin pvin figur e 24 : bootstrap circuit to generate vc voltage a bootstrap capacitor of value 0.1uf is suitable for most applications. input capacitor selection the ripple currents generated during the on time of the control fets should be provid ed by the input capacitor. the rms value of this ripple for each channel is expressed by: ( ) d d i i o rms ? = ( 16 ) in o v v d = ( 17 ) where: d is the duty cycle i rms is the rms value of the input capacitor current. io is the output current. i o =25a and d = 0.1, the i rms = 7.5a. ceramic capacitors are recommended due to their peak current capabilities. they also feature low esr and esl at higher frequency which enables better efficienc y. for this application, it is advisable to have 7x22uf, 25v ceramic capacitors, grm31cr61e226ke15l from murata. in addition to these, although not mandatory, a 1x330uf, 25v smd capacitor eev - fk1e331p from panasonic may also be used as a bulk capacitor a nd is recommended if the input power supply is not located close to the converter. inductor selection inductors are selected based on output power, operating frequency and efficiency requirements. a low inductor value causes large ripple current, resul ting in the smaller size, faster response to a load transient but may also result in reduced ef ficiency and high output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( ?i ). the opt imum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: s o in f d t t i l v v 1 ; = ? ? ? = ? ( ) s in o o in f i v v v v l ? ? = ( 18 ) where: v in = maximum input voltage v 0 = output voltage ? l = inductor ripple current f s = switching frequency ? t = on time for control fet d = duty cycle if ?i i o , then the inductor is calculated to be 0.24 h. select l =0.215 h, pcdc1008 - r215emo, from cyntec which provides an inductor suitable for thi s application. ir3447 28 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 output capacitor selection the voltage ripple and transient requirements determine the output capacitors type and values. the criterion is normally based on the value of the effective series resistance (esr). however the actual capacitanc e value and the equivalent series inductance (esl) are other contributing components. these components can be described as: ( ) ( ) ) ( c o esl o esr o o v v v v ? + ? + ? = ? esr i v l esr ? = ? ) ( 0 esl l v v v o in esl ? ? ? ? ? ? ? = ? ) ( 0 s o l c f c i v ? = ? 8 ) ( 0 ( 19 ) whe re: ? 9 0 = output voltage ripple ? , l = inductor ripple current since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. the ir34 47 can p erform well with all types of capacitors. as a rule, the capacitor must have low enough esr to meet output ripple and load transient requirements. the goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. t herefore it is advisable to select ceramic capacitors due to their low esr and esl and small size. ten of tdk c2012x5r0j476m (47uf/0805/x5r/6.3v) capacitors is a good choice. it is also recommended to use a 0.1f ceramic capacitor at the output for high frequency filtering. feedback compensation the ir34 47 is a voltage mode controller. the control loop is a single voltage feedback path including error amplifier and error comparator. to a chieve fast transient response and accurate output regulation, a com pensation circuit is necessary. the goal of the compensation network is to provide a closed - loop transfer function with the highest 0 db crossing frequency and adequate phase margin (greater than 45 o ). the output lc filter introduces a double pole, - 40db/d ecade gain slope above its corner resonant frequency, and a total phase lag of 180 o . the resonant frequency of the lc filter is expressed as follows: o o lc c l f = 2 1 ( 20 ) figure 25 shows gain and phase of the lc filter. since we already have 180 o phase shift from the output filter alone, the system runs the risk of being unstable. phase 0 0 f lc 0 frequency f lc frequency 0 0 - 180 0 0 db - 40db / decade - 90 gain figure 25 : gain and phase of lc filter the ir3 4 47 uses a voltage - type error amplifier with high - gain and high - bandwidth . the output of the amplifier is available for dc gain control and ac phase compensation. the error amplifier can be compensated either in type ii or type iii compensation. local feed back with type ii compensation is shown in figure 26 . this method req uires that the output capacitor have enough esr to satisfy stability requirements. if the output capacitor?s esr generates a zero at 5khz to 50k hz, the zero generates acceptable phase margin and the type ii compensator can be used. the esr zero of the output capacitor is expressed as follows: o esr c esr f = 2 1 ( 21 ) ir3447 29 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 v out v ref r 6 r 5 c pole c 3 r 3 ve f z f pole e / a z f frequency gain ( db ) h ( s ) db fb comp z in figure 26 : type ii compensation network and its asymptotic gain plot the transfer function ( v e /v out ) is given by: 3 5 3 3 1 ) ( c sr c sr z z s h v v in f out e + ? = ? = = ( 22 ) the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: 5 3 ) ( r r s h = ( 23 ) 3 3 2 1 c r f z = ( 24 ) first select the desired zero - crossover frequency ( f o ): esr o f f > a nd s o f f ) 10 / 1 ~ 5 / 1 ( ( 25 ) use the following equation to calculate r3: 2 5 3 lc in esr o ramp f v r f f v r = ( 26 ) where: v in = maximum input voltage v ramp = amplitude of the oscillator ramp voltage f o = cross over frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter = (rs+ - rs - ) / vo r 5 = feedback resistor to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: lc z f f = % 75 o o z c l f = 2 1 75 . 0 ( 27 ) use equation (2 4), (25 ) and (2 6 ) to calculate c3. one more capacitor is sometimes added in parallel with c3 and r3. this introduces one more pole which is mainly used to suppr ess the switching noise. the additional pole is given by: pole pole p c c c c f + = 3 3 2 1 ( 28 ) the pole sets to one half of the switching frequency which results in the capacitor c pole : s s pole f r c f r c ? ? = 3 3 3 1 1 1 ( 29 ) for a general unconditional stable solution for any type of output capacitors with a wide range of esr values, we use a local feedback with a type iii compensation network. the typically used compensation network for voltage - mode controller is shown i n figure 27. ir3447 30 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 v out v ref r 6 r5 r 4 c 4 c2 c3 r 3 ve f z 1 f z 2 f p 2 f p 3 e / a z f z in frequency gain ( db ) | h(s) | db fb comp figure 27: type iii compensation network and its asymptotic gain plot again, the transfer function is given by: in f out e z z s h v v ? = = ) ( by repl acing z in and z f , according to figure 27 , the transfer function can be expressed as: ( ) ( ) [ ] ( ) ( ) 4 4 3 2 3 2 3 3 2 5 5 4 4 3 3 1 1 1 1 ) ( c sr c c c c sr c c sr r r sc c sr s h + ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + ? = ( 30 ) the compensation network has three poles and two zeros and they are expre ssed as follows: 0 1 = p f ( 31 ) 4 4 2 2 1 c r f p = ( 32 ) 2 3 3 2 3 2 3 3 2 1 2 1 c r c c c c r f p ? ? ? ? ? ? ? ? ? + = ( 33 ) 3 3 1 2 1 c r f z = ( 34 ) ( ) 5 4 5 4 4 2 2 1 2 1 r c r r c f z ? = ( 35 ) cross over frequency is expressed as: o o ramp in o c l v v c r f = 2 1 4 3 ( 36 ) based on the frequency of the zero generated by the output capacitor and its esr, relative to the crossover freque ncy, the compensation type can be different. table 2 shows the compensation types for relative locations of the crossover frequency. table 2 : different types of compensators compensator type f esr vs f o typical output capacitor type ii f lc < f esr < f o < f s /2 electrolytic type iii f lc < f o < f esr sp cap, ceramic the higher the crossover frequency is, the potentially faster the load transient response will be. however, the crossover frequency s hould be low enough to allow attenuation of switching noise. typically, the control loop bandwidth or crossover frequency ( f o ) is selected such that: ( ) s o f f * 1/10 ~ 1/5 the dc gain should be large enough to provide high dc - regulation accuracy. the phase margin should be greater than 45 o for overall stability. the specifications for designing channel 1: v in = 12v v o = 1.2v v ramp = 1.8v (this is a function of vin, pls. see feed - f orward section) v ref = 0.6v = (rs+ - rs - ) / vo (this assumes the resis tor divider placed between vout and the rsa scales down the output voltage to vref. if the rsa is not used or vout is connected directly ir3447 31 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 to the rsa, = 1. please refer to the remote sensing amplifier section) l o = 0.215 h c o = 10 x 47f, esr3m each it must be noted here that the value of the capacitance used in the compensator design must be the small signal value. for instance, the small signal capacitance of the 47f capacitor used in this design is 25.7f at 1.2 v dc bias and 600 khz frequency. it is this value that must be used for all computations related to the compensation. the small signal value may be obtained from the manufacturer?s datasheets, design tools or spice models. alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency f lc and using equation ( 20 ) to compute the small signal c o . these result to: f lc = 21.4 khz f esr = 2 .06 m hz f s /2 = 300 khz select crossover frequenc y f 0 =100 khz since f lc ir3447 33 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical application internally biased si ngle supply ir3447 boot sw fb vsns vcc pgood vin pgnd agnd cbyp rt/sync comp rs+ rs- rso cpvin2 cboot lo cout cbyp cvcc rpg rt cvin 39.2 k 10 k 10uf 100pf vin 0.1uf 10 x 47uf 0.215uh 7 x 22 uf cpvin3 0.1uf 1uf ren 1 7.5 k ren 2 49.9 k cc3 160pf cc2 8.2nf cc1 2200pf rbode 20 rfb2 4.22 k rfb1 4.22 k rsns2 4.22 k rsns1 4.22 k rc2 1.91 k rc1 127 vo pgood cpvin1 330uf pvin en ocselect co1 0.1 uf figure 28 : application circuit for a 12v to 1.2v, 25a point of load converter using the internal ldo suggested bill of material for application circuit 12v to 1.2v part reference qty value description manufacturer part number cpvin1 1 330uf smd, electrolytic, 25v, 20% panasonic eev - fk1e331p cpvin2 7 22uf 1206, 25v, x5r, 1 0% murata grm31cr61e226ke15l cref 1 100pf 0603, 50 v, c0g , 5 % murata grm1 88 5c1h101ja01d cvin 1 1.0uf 0603, 25v, x5r, 20% murata grm188r61e105ka12d cvcc 1 10uf 0603, 10v, x5r, 20% tdk c1608x5r1a106m cpvin3 cboot co1 3 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01d cc1 1 2200pf 0603, 50v, x7r, 10% murata grm188r71h222ka0 1d cc2 1 8.2nf 0603, 50v, x7r, 10% murata grm188r71h822ka01d cc3 1 160pf 0603, 50v, npo, 5% murata grm1885c1h161ja01d cout1 10 47uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j476m l0 1 0.215uh 10.1x7.8x7.3mm, dcr=0.29m cyntec pcdc1008 - r215emo rbd 1 20 thick film, 0603, 1/10w, 1% panasonic erj - 3ekf20r0v rc1 1 127 thick film, 0603, 1/10w, 1% panasonic erj - 3ekf1270v rc2 1 1.91k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf1911v ren1 1 7.5k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf7501v ren2 1 49.9k th ick film, 0603, 1/10w, 1% panasonic erj - 3ekf4992v rfb1 rfb2 rsns1rsns1 4 4.22k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf4221v rt 1 39.2k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf3922v rpg 1 10k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf100 2v u1 1 ir34 47 pqfn 5x6mm international rectifier ir34 47mpbf ir3447 34 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 externally biased du al supplies ir3447 boot sw fb vsns vcc pgood vin pgnd agnd cbyp rt/sync comp rs+ rs- rso cpvin2 cboot lo cbyp cvcc rpg rt cvin 39.2 k 10 k 10uf 100pf pvin 0.1uf 0.215uh 7 x 22uf cpvin3 0.1uf 1uf ren 1 7.5 k ren 2 49. 9 k cc3 160pf cc2 8.2nf cc1 2200pf rbode 20 rfb2 4.22 k rfb1 4.22 k rsns2 4.22 k rsns1 4.22 k rc2 1.91 k rc1 127 vo pgood cpvin1 330uf pvin en ocselect vin cout 10 x 47 uf co1 0.1 uf figure 29 : application circuit for a 12v to 1.2v, 2 1 a point of load converter using external 5v vcc su ggested bill of material for appl ication circuit 12v to 1.2v using external 5v vcc part reference qty value description manufacturer part number cpvin1 1 330uf smd, electrolytic, 25v, 20% panasonic eev - fk1e331p cpvin2 7 22uf 1206, 25v, x5r, 1 0% murata g rm31cr61e226ke15l cref 1 100pf 0603, 50v, c0g, 5% murata grm1885c1h101ja01d cvin 1 1.0uf 0603, 25v, x5r, 20% murata grm188r61e105ka12d cvcc 1 10uf 0603, 10v, x5r, 20% tdk c1608x5r1a106m cpvin3 cboot co1 3 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104k a01d cc1 1 2200pf 0603, 50v, x7r, 10% murata grm188r71h222ka01d cc2 1 8.2nf 0603, 50v, x7r, 10% murata grm188r71h822ka01d cc3 1 160pf 0603, 50v, npo, 5% murata grm1885c1h161ja01d cout1 10 47uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j476m l0 1 0.215uh 10.1x 7.8x7.3mm, dcr=0.29m cyntec pcdc1008 - r215emo rbd 1 20 thick film, 0603, 1/10w, 1% panasonic erj - 3ekf20r0v rc1 1 52.3 thick film, 0603, 1/10w, 1% panasonic erj - 3ekf52r3v rc2 1 1.91k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf1911v ren1 1 7.5k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf7501v ren2 1 49.9k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf4992v rfb1 rfb2 rsns1rsns1 4 4.22k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf4221v rt 1 39.2k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf392 2v rpg 1 10k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf1002v u1 1 ir34 47 pqfn 5x6mm international rectifier ir34 47mpbf ir3447 35 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 externally biased si ngle supply ir 3447 boot sw fb vsns vcc pgood vin pgnd agnd cbyp rt / sync comp rs + rs - rso cpvin 2 cboot lo cbyp cvcc rpg rt cvin 39 . 2 k 10 k 10 uf 100 pf vin 0 . 1 uf 0 . 215 uh 7 x 22 uf cpvin 3 0 . 1 uf 1 uf ren 1 21 k ren 2 41 . 2 k cc 3 120 pf cc 2 5 . 6 nf cc 1 2200 pf rbode 20 rfb 2 4 . 22 k rfb 1 4 . 22 k rsns 2 4 . 22 k rsns 1 4 . 22 k rc 2 2 . 8 k rc 1 127 vo pgood cpvin 1 330 uf pvin en ocselect cout 10 x 47 uf co 1 0 . 1 uf figure 30 : application circuit for a 5v to 1.2v, 2 1 a point of load converter suggested bill of material for application circuit 5v to 1.2v part reference qty value description manufacturer part number cpvin1 1 330uf smd, electrolytic, 25v, 20% panasonic eev - fk1e331p cpvin2 7 22uf 1206, 25v, x 5r, 1 0% murata grm31cr61e226ke15l cref 1 100pf 0603, 50v, c0g, 5% murata grm1885c1h101ja01d cvin 1 1.0uf 0603, 25v, x5r, 20% murata grm188r61e105ka12d cvcc 1 10uf 0603, 10v, x5r, 20% tdk c1608x5r1a106m cpvin3 cboot co1 3 0.1uf 0603, 25v, x7r, 10% murat a grm188r71e104ka01d cc1 1 2200pf 0603, 50v, x7r, 10% murata grm188r71h222ka01d cc2 1 5.6nf 0603, 50v, x7r, 10% murata grm188r71h562ka01d cc3 1 120pf 0603, 50v, npo, 5% murata grm1885c1h121ja01d cout1 10 47uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j476m l0 1 0.215uh 10.1x7.8x7.3mm, dcr=0.29 m cyntec pcdc10 08 - r215emo rbd 1 20 thick film, 0603, 1/10w, 1% panasonic erj - 3ekf20r0v rc1 1 127 thick film, 0603, 1/10w, 1% panasonic erj - 3ekf1270v rc2 1 2.8k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf2801v ren1 1 21k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf2102v ren2 1 41.2k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf4122v rfb1 rfb2 rsns1rsns1 4 4.22k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf4221v rt 1 39.2k thick film, 0603, 1/10w, 1% panasonic erj - 3ekf3922v rpg 1 10k thick fi lm, 0603, 1/10w, 1% panasonic erj - 3ekf1002v u1 1 ir34 47 pqfn 5x6mm international rectifier ir34 47mpbf ir3447 36 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating waveforms vin = pvin=12v, vout=1.2v, iout= 0 - 25a, fs=600khz, room temperature, no air flow figure 31 : startu p with full load , enable signal c h 1: vin, c h 2:vout , c h 3: pgood , c h 4: enable figure 32 : startup with full load , vcc signal c h 1:vin, c h 2:vout , c h 3:pgood, c h 4: vcc figure 33 : vout startup with pre - bias, 1. 0 8 v c h 1: enable, ch2 : vout , c h 3: pgood figure 34 : recovery from hiccup c h 2: vout , c h 3 : pgood , ch4:iout figure 35 : inductor switch node at full load c h 2:sw figure 36 : output volt age ripple at full load c h 1:vout ir3447 37 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating waveforms vin=pvin= 12v, vout = 1.2v, iout = 2.5a - 10 a, fs =600khz, room temperature, no a ir f low figure 37 : vout transient response, 2.5 a to 1 0.0 a step at 2.5a/usec ch2 :v out, ch4:iout (10a/v) ir3447 38 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating waveforms vin=pvin= 12v, vout = 1. 2v, iout= 17.5a - 25a, fs = 600khz, room temperature, no a ir f low figure 38 : vout transient response, 1 7. 5 a to 25 a step at 2.5a/usec ch2:vout, ch 4: iout (10a/v) ir3447 39 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating waveforms vin=pvin= 12v, vout = 1. 2v, iout= 25a, fs = 600khz, room temperature, no a ir f low figure 39 : bode plot with 25a load: fo=108 khz, phase margin= 50.2 degrees ir3447 40 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 typical operating waveforms vin= pvin=12v, vout=1.2v, iout= 0 - 25a, fs = 600khz, room temperature, no air f low figure 40 : efficiency versus load current figure 41 : power loss versus load current ir3447 41 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 layout recommendations the layout is ve ry important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. make the connections for the power components in the top layer with wide, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. the inductor, input capacitors, output capacitors and the ir34 47 should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capacitor directly at the pvin pin of ir34 47. the feedback part of the system should be kept away from the inductor and other noise sour ces. the critical bypass components such as capacitors for pvin, vin and vcc should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. in a multilayer pcb use at least one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more se nsitive analog control function. these two grounds must be connected together on the pc board layout at a single point. it is recommended to place all the compensation parts over the analog ground plane in top layer. the power qfn is a thermally enhanced p ackage. based on thermal performance it is recommended to use at least a 6 - layers pcb. to effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. figure 42a - f il lustrates the implementation of the layout guidelines outlined above, on t he ir dc 34 47 6 - layer demo board. - figure 42 a: ir dc 34 47 demo board layout considerations ? top layer - compensation parts should be placed as close as possible to the comp pins - sw node c opper is kept only at the top layer to minimize the switching noise - single point connection between agnd & pgnd, should be placed near the part and kept away from noise sources pgnd p vin vout agnd - ground path between vin - and vout - should be minimized with maximum copper - bypass c aps should be placed as close as possible to their connecting pins - filled vias placed under pgnd and pvin pads to help thermal performance. ir3447 42 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 figure 42 b: ir dc 34 47 demo board layout considerations ? bottom layer figure 42 c: ir dc 34 47 demo board layout considerations ? mid layer 1 figure 42 d: ir dc 34 47 demo board layout considerations ? mid layer 2 pgnd vout vout pgnd pgnd ir3447 43 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 figure 42e : ir dc 34 47 demo board layout considerations ? mid layer 3 figure 42f : ir dc 3447 demo board layout considerations ? mid layer 4 - feedback and vsns trace s ro uting should be kept away from noise sources pgnd vout pgnd remote sense traces - tap output where voltage value is critical . - avoid noisy areas and noise coupling. - rs+ and rs - lines near each other. - minimize trace resistance. ir3447 44 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 pcb metal and compon ent placement evaluations have shown that the best overall performance is achieved using the substrate/pcb layout as shown in following fi gures. pqfn devices should be placed to an accuracy of 0.050mm on both x and y axes. self - centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self - centering on specific processes. for furt her information, please refer to ?supirbuck? multi - chip module (mcm) power quad flat no - lead (pqfn) board mounting application note .? (an1132) pcb pad sizes (detail 1) pcb pad sizes (detail 2) ir3447 45 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 pcb pad spacing (detail 1) pcb pad spacing (detail 2) ir3447 46 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 solder resist ? ir recommends that the larger power or land area pads are solder mask defined (smd). this allows the underlying coppe r traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. ? when using smd pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the solder mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in x & y). ? however, for the smaller signal type leads around the edge of the device, ir recommends that these are non solder mask defined or copper defined. ? when using nsmd pads, the solder resist window should be larger than the copper pad by at least 0.025mm on each edge, (i.e. 0.05mm in x & y), in order to accommodate any layer to layer misalignment. ? ensure that the solder resist in - between the smaller signal lead areas are at least 0.15 mm wide, due to the high x/y aspect ratio of the solder mask strip. solder mask design pad sizes (detail 1) solder mask design pad sizes (detail 2) ir3447 47 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 solder mask design pad spacing (detail 1 ) solder mask design pad spacing (detail 2) ir3447 48 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 stencil design ? stencils for pqfn can be used with thicknesses of 0.100 - 0.250mm (0.004 - 0.010?). stencils thinner than 0.100mm are unsuitable becau se they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. stencils in the range of 0.125mm - 0.200mm (0.005 - 0.008?), with suitable reductions, give best results. ? evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. this design for a stencil thickness of 0.127mm (0.005?). the reduction should be adjusted for stencils of other thicknesses. solder paste ste ncil pad sizes (detail 1) solder paste stencil pad sizes (detail 2) ir3447 49 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 solder paste stencil pad spacing (detail 1) solder paste stencil pad spacing (detail 2) mark ing information figure 43 : marking information ir3447 50 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 packaging information ir3447 51 www.irf.com ? 20 14 international rectifier submit datasheet feedback j une 18, 2015 environmental qualif ications qualification level industrial moisture sensitivity level 5mm x 6mm pqfn msl2 esd machine model (jesd22 - a115a) class a <200v human body model (jesd22 - a114f) class 1c 1000v to <2000v charged device model (jesd22 - c101d) class iii rohs compliant yes data and specifications subject to change without notice. qualification standards can be found on ir?s web site. ir wo rld headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com |
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