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1. general description nxps asc8848/49/50/51 soc is a single chip platform that is designed for embedded multimedia communication, security and entertainment applications. powered by the most popular arm926ej processor and high performance nxp video hardware accelerators, asc8848/49/50/51 soc could provide upto 1080p @ 45fps mpeg-4 avc (h.264) and jpeg encoding simultaneously at 1080p @ 40 fps. with its built-in high performance image front-end processing engine, it can also provide better video quality than any smart sensor. due to its highly flexible architecture, multiple stream real time encoding with up to 8x d1 (704x480) resolution is also practicable. version 2.0 of asc8848/49/50/51 datasheet highlights the feature differences of asc8848/49/50 with respect to ASC8851. it also provides details on ASC8851 pinouts. asc8848; asc8849; asc8850; ASC8851 multimedia soc rev. 2.06 ? 24 september 2011 data sheet free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 2 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 2. features and benefits 2.1 high quality media nxps expertise on multimedia processing an d compression provides the state-of-the-art audio visual quality for entertainment and professional applications. the software based video encoding system guarant ees perfect synchronization between audio and video channels. 2.1.1 h.264 encoder nxp h.264 encoder is compliant with h. 264/mpeg-4 avc (iso/iec 14496-10) video coding standard.the h.264 encoder su pports the following features: ? h.264/mpeg-4 avc baseline profile, main prof ile (i, p frame coding only), and high profile (i, p frame coding only) @ level 4.1 ? cavlc and cabac entropy coding tools ? full search quality motion estimation ? up to 2 reference frames motion estimation ? 16*16, 16*8, 8*16, 8*8, 8*4, 4*8, and 4*4 motion estimation block size ? integer, half and quarter pixel precision motion estimation ? constant bitrate (cbr) and variable bitrate (vbr) or constant quality ? encoding capability up to d1 @ 240 fps or full hd 1080p @ 45 fps ? supports all intra prediction modes for 4 4, 8 8 and 16 16 block sizes ? supports in-loop deblocking filter ? forces intra mb insertion into inter-frames to maintain video quality for large i-frame interval ? cb and cr qp can be different to y ? supports intra prediction in inter frames using 128 or reconstruction pixels 2.1.2 mpeg-4 encoder nxp mpeg-4 encoder is compliant with mpeg-4 part 2 (iso/iec 14496-2) video coding standard. the mpeg-4 encoder supports the following features: ? mpeg-4 part 2 simple profile ? error resilience tools (video packet re-synchronization) ? full search quality motion estimation ? 16*16 and 8*8 motion estimation block size ? integer and half pixel precision motion estimation ? constant bit-rate (cbr) and variable bit-rate (vbr)/constant quality ? encoding capability up to d1 @ 80 fps or full hd 720p @ 30 fps (share the bandwidth with h.264 encoder) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 3 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 2.1.3 jpeg encoder nxp jpeg encoder is compliant with jpeg (iso/iec is 10918-1 | itu-t recommendation t.81) image coding standard. the jpeg encoder supports the following features: ? baseline jpeg with jfif support ? ycbcr 4:4:4, 4:2:2, and 4:2:0 input format ? custom defined quality table and content adaptive huffman table ? encoding capability up to 80 megapi xel/sec or full hd 1080p @ 40 fps 2.2 flexible platform the on-chip arm926ej processor and easy -to-use video media library (vml) api ensure highest flexibility for system design. th e highly integrated soc platform provides a glueless interface to cmos sensor, video decoder,video encoder, lcd module, hdmi transmitter, serial flash, nand flash, ddr- ii/iii sdram, gigabit ethernet phy, audio codec and camera control. usb 2.0 otg and pc ie 1.1 interfaces are also available for wireless lan connection, mass storag e devices and other peripherals. 2.2.1 video/sensor interface support various video/sensor input interfaces and rich functions on the captured frame ? . ? support 2-channel 8-bit ycbcr 4:2:2 ccir-656 progressive or interlace format ? support 2-channel 8-bit ycbcr 4:2:2 format with separate sync signals ? support 1-channel 16-bit ycbcr 4:2:2 format with separate or embedded sync signals ? support 2-channel 2-to-1 time-multiplexed cc ir-656 8-bit ycbcr 4:2:2 progressive or interlace format ? support 2-channel 4-to-1 time-multiplexed cc ir-656 8-bit ycbcr 4:2:2 progressive or interlace format ? support 1-channel bayer pattern (bayer rgb or cmyg) raw data format up to 16-bit. ? capture up to 8-channel video data simultaneously ? image front-end processing (color filter array, auto white balance, auto exposure, and auto focus, color correction, gamma correction) ? tone mapping that can provide wide dynamic range (wdr) image quality ? automatic contrast enhancement that can im prove the image quality in high contrast environment ? photometric and geometric lens distortion correction ? color adjustment (saturation, brightness, and contract control) ? image cropping, mirror, and flip free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 4 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 2.2.2 audio interface support i2s format and there are four stereo input channels and one full-duplex stereo channel. 2.2.3 image processing rich image processing functions are included. ? motion adaptive interlacing ? arbitrary image resizing and scaling ratio (scaling using bi cubic 4 tap filter) ? spatial (2d) noise reduction (g aussian, impulse, false color) ? edge enhancement ? frame difference motion detection with 16 arbitrary sized rectangular windows ? privacy mask with arbitrary shape and grid size 2.2.4 data encryption ? des, tdes, aes,sha-1 ? sha-224, sha-256, sha-384, sha-512 2.2.5 host controller arm926ej is integrated with 16kb instruction cache and 16kb data cache. the operating frequency is up to 600 mhz on linux 2.6x. 2.2.6 external memory interface there are several interfaces built in for the external memory devices. ? two 16-bit ddr-ii/iii 800 sdram channels t hat can support up to 1gb ddr-iii per channel or up to 512mb ddr-ii per channel for asc8848/49/50 m2 version and ASC8851. 1 ? two high-speed spi interface to support serial flash ? two nand flash memory interface 2.2.7 peripherals high-speed peripheral interfaces are built in for the application needs ? usb 2.0 otg (host/device) interface ? pcie x1 1.1 dual mode (root complex/end point) interface ? 10/100/1000 ethernet mac low-speed peripherals include: ? two mmc/sd/sdio interfaces ? four uarts (2 full functionality / 2 simple uarts (vpl uartc)) ? one irda interf ace (vpl irdac) ? 20-bit gpios ? 8 programmable timers (vpl tmrc) ? 1 watchdog timer (vpl wdtc) ? 1 64-bit system timer (vpl sysc) ? interface support for wlan, bluetooth, wusb 1. refer to table 2 for asc8848/49/50 m1 version free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 5 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 3. ordering information table 1. ordering information type number package name description version asc8848et tfbga484 thin profile fine -pitch ball grid array; 484 balls - asc8849et tfbga484 thin profile fine -pitch ball grid array; 484 balls - asc8850et tfbga484 thin profile fine -pitch ball grid array; 484 balls - table 2. comparison of asc8848/49/50 m1 and asc8848/49/50/51 m2 features feature version asc8848 asc8849 asc8850 ASC8851 max. sensor resolution asc8848/49/50 m1 1.3m 5m 12m na asc8848/49/50/51 m2 5m 5m 12m 12m max number of input bits asc8848/49/50 m1 10 bits 16 bits 16 bits na asc8848/49/50/51 m2 12 bits 16 bits 16 bits 16 bits max. number of input channels asc8848/49/50 m1 3 4 6 na asc8848/49/50/51 m2 3 4 6 8 max voc bits asc8848/49/50 m1 8 24 24 na asc8848/49/50/51 m2 8 24 24 24 max hdmi output asc8848/49/50 m1 not supported 720p @ 60 fps 1080p @ 30 fps na asc8848/49/50/51 m2 not supported 720p @ 60 fps 1080p @ 60 fps 1080p @ 60 fps bt1120 output support asc8848/49/50 m1 no no no na asc8848/49/50/51 m2 no yes yes yes arm frequency asc8848/49/50 m1 400 mhz 450 mhz 600 mhz na asc8848/49/50/51 m2 400 mhz 500 mhz 600 mhz 600 mhz h264 maximum performance asc8848/49/50 m1 720p @ 30 fps sxga @ 30 fps 1080p @ 30 fps na asc8848/49/50/51 m2 720p @ 45 fps sxga @ 40 fps 1080p @ 30 fps 1080p @ 45 fps ddr support asc8848/49/50 m1 1-ch 16 b ddr-ii, 266 mhz up to 512 mb per channel 2-ch 16 b ddr-ii, 300 mhz up to 512 mb per channel 2-ch 16 b ddr-ii, 400 mhz upto 512 mb per channel na asc8848/49/50/51 m2 1-ch 16 b @266 mhz up to 1 gb ddr-iii or 512 mb ddr-ii per channel 2-ch 16 b @333 mhz up to 1 gb ddr-iii or 512 mb ddr-ii per channel 2-ch 16 b @400 mhz up to 1 gb ddr-iii or 512 mb ddr-ii per channel 2-ch 16 b @400 mhz up to 1 gb ddr-iii or 512 mb ddr-ii per channel table 3. comparison of asc8848, as c8849, asc8850 & ASC8851 peripherals feature asc8848 asc8849 asc8850 ASC8851 ddr- ii/iii channels [1] 12 2 2 i2s channels 1 5 5 5 ethernet mii rgmii/gmii/mii rgmii/gmii/mii rgmii/ gmii/mii spi interface 1 2 2 2 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 6 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] ddr-ii/iii is supported only for asc8848/49/50 m2 version and ASC8851 for asc8848/49/50 m1 version only ddr-ii is supported. sd interface 1 2 2 2 uarts 2 4 4 4 nand flash 1 2 2 2 table 3. comparison of asc8848, as c8849, asc8850 & ASC8851 peripherals feature asc8848 asc8849 asc8850 ASC8851 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 7 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 4. functional diagram fig 1. functional blocks 001aam933 gigabit ethernet phy 10/100/1000 ethernet mac mass storage device usb 2.0 otg i/f pc pciex1 i/f wireless ethernet card sdio i/f sd card sdio i/f ddr-ii sdram ddr-ii sdram i/f image scaling image enhancement video/sensor i/f audio processing jpeg encoder h.264/mpeg-4 video encoder ccd/cmos sensor ddr-ii sdram ddr-ii sdram i/f data encryption dma spi i 2 s gpio irda pll intc wdt tmr uart nand flash nand flash controller arm926ej free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 8 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 5. pinning information 5.1 pinning all asc8849/50/51 soc signals are listed in table 6 and asc8848 soc signals are listed in ta b l e 8 . asc8848/49/50 soc has input pins (i), outpu t pins (o), bi-directional pins (i/o), power pins (p), and ground pins (g). some functional pins have built-in functions as specified at ta b l e 6 . ta b l e 4 explains each i/o functions used in ta b l e 6 . the ball map is split to four quadrants as shown in figure 2 to figure 5 . remark: pin assignment is for the m2 versi on. for the m1 version refer to table 6 fig 2. top left view of an asc8849 / 8850 / 8851 tfbga-484 pin assignment a 1234567891011 uartc_0 _i_sda uartc_0 _o_sda uartc_0 _io_ndtr gmac_i _rxd[6] gmac_i _rx_clk gmac_i_ rxd[2] gmac_i_ tx_clk gmac_o _txd[5] gmac_o _tx_clk gmac_o _txd[0] vssio_ 2_5_3_3 sys_i_ osc_1_ clk uartc_0 _i_ndcd uartc_0 _i_ncts gmac_i_ rxd[7] gmac_i_ rxd[5] gmac_i_ rxd[3] gmac_i_ rxd[0] gmac_o _txd[6] gmac_o _txd[3] gmac_o _txd[1] sys_o_ mon_ clk[1] sys_o_ osc_1_ febclk uartc_0 _i_nri uartc_0 _i_ndsr uartc_0 _io_nrts gmac_i_ crs gmac_i_ rxd[4] gmac_i_ rxd[1] gmac_o _txd[7] gmac_o _txd[4] gmac_o _txd[2] sys_o_ mon_ clk[0] uartc_2 _o_sda uartc_2 _i_sda uartc_1 _i_sda uartc_1 _io_ndtr gmac_i_ col gmac_io _md gmac_o _mdc gmac_i_ rxdv gmac_i_ rxer gmac_o _txer gmac_o _txen vssio_ 2_5_3_3 uartc_1 _i_ndsr uartc_1 _o_sda uartc_1 _i_ndcd vddio_ 3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 3_3 usbc_io _phy_dm uartc_1 _i_nri uartc_1 _i_ncts uartc_1 _io_nrts vddio_ 3_3 vssio_ 2_5_3_3 pllc_i_ pll_2_ pwr_ vssa_2_5 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vddio_ 3_3 usbc_io _phy_dp usbc_io _phy_ atest usbc_o _drv_ vbus uartc_3 _i_sda usbc_io _phy_ pwr_ vdda _3_3 usbc_io_ phy_pwr _vssa_ 2_5_3_3 pllc_i_ pll_2_ pwr_ vdda_2_5 vddio_ 3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 usbc_io _phy_ vbus usbc_i_ phy_id uartc_3 _o_sda usbc_io _phy_ pwr_ vddc_1_0 usbc_io_ phy_pwr _vssa_ 2_5_3_3 vddio_ 3_3 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 i2ssc_0_ i_bclk i2ssc_0_ i_ws i2ssc_0_ o_txd usbc_io_ phy_rext rkelvin usbc_io _phy_ pwr_ vdda _2_5 usbc_io_ phy_pwr _vssc_ 1_0 vssio_ 2_5_3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 i2ssc_1_ i_ws i2ssc_1_ i_bclk i2ssc_0_ i_rxd sys_i_ boot_ mode_ sel[0] reserved reserved vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 i2ssc_o_ tx_mclk i2ssc_2_ i_ws i2ssc_1_ i_rxd sys_i_ boot_ mode_ sel[1] reserved reserved vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 b c d e f g h j k l 001aam935 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 9 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc remark: pin assignment is for the m2 versi on. for the m1 version refer to table 6 fig 3. top right view of an asc8849 / 8850/ 8851 tfbga-484 pin assignment free datasheet http://
draft draft d raft dr draft d raft draft draf draft draft draft draft draft d draft draft draft draft draft draft d ra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 10 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc remark: pin assignment is for m2version. for m1 version refer to ta b l e 6 fig 4. bottom left view of an asc8849 / 8850/ 8851 tfbga-484 pin assignment 001aam937 m 1234567891011 i2ssc_ o_rx_ mclk i2ssc_ 2_i_ rxd i2ssc_ 2_i_ bclk sys_i_ nrst vssio_ 2_5_3_3 reserved vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 i2ssc_ 3_i_ rxd i2ssc_ 3_i_ ws i2ssc_ 3_i_ bclk vssio_ 2_5_3_3 reserved reserved vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 i2ssc_ 4_i_ rxd i2ssc_ 4_i_ ws i2ssc_ 4_i_ bclk vssc_ 1_0 reserved vssio_ 2_5_3_3 vssio_ 2_5_3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 ssic_i_ rxd ssic_o_ bclk wdtc_o _nrst ddr32 sdmc_io_ pwr_vssio _1_8 reserved ddr32 sdmc_io_ pwr_vssio _1_8 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 ssic_o_ nsel[0] ssic_o_ txd irdac_ i_sda ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ phy_pwr_ vssa_2_5 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ssic_o_ nsel[1] ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 dmc_o_ nrst ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vref _0_9 ddr32 sdmc_io_ pwr_vref _0_9 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 dmc _o_ addr[15] ddr32 sdmc_ 0_o_ dm[1] ddr32 sdmc_ 0_io_ dq[13] ddr32 sdmc_ i_ cali ddr32 sdmc_ 0_io_ dq[7] ddr32 sdmc_ 0_io_ dq[5] ddr32 sdmc_o_ phy_ atest ddr32 sdmc _o_ addr[2] ddr32 sdmc _o_ addr[4] ddr32 sdmc _o_ addr[8] ddr32 sdmc _o_ addr[6] ddr32 sdmc _o_ addr[14] ddr32 sdmc_ 0_io_ dq[15] ddr32 sdmc_ 0_io_ dq[8] ddr32 sdmc_ 0_io_ dq[10] ddr32 sdmc_ 0_io_ dq[0] ddr32 sdmc_ 0_io_ dq[2] ddr32 sdmc_ 0_o_ dm[0] ddr32 sdmc _o_ ba[2] ddr32 sdmc _o_ ba[0] ddr32 sdmc _o_ addr[0] ddr32 sdmc _o_ addr[5] ddr32 sdmc _o_ addr[1] ddr32 sdmc_ 0_io_ dq[9] ddr32 sdmc_ 0_io_ dq[11] ddr32 sdmc_ 0_io_ dq[12] ddr32 sdmc_ 0_io_ dq[6] ddr32 sdmc_ 0_io_ dq[1] ddr32 sdmc_ 0_io_ dq[3] ddr32 sdmc _o_ ba[1] ddr32 sdmc _o_nras ddr32 sdmc _o_ncas ddr32 sdmc _o_ addr[10] ddr32 sdmc _o_nwe ddr32 sdmc_ 0_io_ dq[14] ddr32 sdmc_ 0_io_ dqs[1] ddr32 sdmc_ 0_io_ ndqs[1] ddr32 sdmc_ 0_io_ dq[4] ddr32 sdmc_ 0_io_ dqs[0] ddr32 sdmc_ 0_io_ ndqs[0] ddr32 sdmc_ 0_o_ ncs ddr32 sdmc_ 0_o_ odt ddr32 sdmc_ 0_o_ cke ddr2 sdmc _o_clk ddr2 sdmc _o_nclk n p r t u v w y aa ab free datasheet http://
draft draft d raft dr draft d raft draft draf draft draft draft draft draft d draft draft draft draft draft draft d ra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 11 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc remark: pin assignment is for m2 vers ion. for m1 version refer table 6 fig 5. bottom right view of an asc8849 / 8850/ 8851 tfbga-484 pin assignment free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 12 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc the ball map of asc8848 is split into four quadrants as shown in figure 6 to figure 9 . remark: pin assignment is for asc8848/49/50/51 m2 version. for asc8848/49/50 m1 version refer table 8 fig 6. top left view of an asc8848 tfbga- 484 pin assignment 001aan243 a 1234567891011 uartc_0 _i_sda uartc_0 _o_sda uartc_0 _io_ndtr reserved/ nc mac_i _rx_clk mac_i_ rxd[2] mac_i_ tx_clk reserved/ nc reserved/ nc mac_o _txd[0] vssio_ 2_5_3_3 sys_i_ osc_1_ clk uartc_0 _i_ndcd uartc_0 _i_ncts reserved/ nc reserved/ nc reserved/ nc mac_i_ rxd[3] mac_i_ rxd[0] reserved/ nc mac_o _txd[3] mac_o _txd[1] sys_o_ osc_1_ febclk uartc_0 _i_nri uartc_0 _i_ndsr uartc_0 _io_nrts mac_i_ crs reserved/ nc mac_i_ rxd[1] reserved/ nc reserved/ nc mac_o _txd[2] sys_o_ mon_ clk[0] reserved/ nc reserved/ nc or vssio_ 2_5_3_3 uartc_1 _i_sda reserved/ nc mac_i_ col mac_io _md mac_o _mdc mac_i_ rxdv mac_i_ rxer mac_o _txer mac_o _txen vssio_ 2_5_3_3 reserved/ nc uartc_1 _o_sda reserved/ nc vddio_ 3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 2_5_3_3 vddio_ 3_3 usbc_io _phy_dm reserved/ nc reserved/ nc reserved/ nc vddio_ 3_3 vssio_ 2_5_3_3 pllc_i_ pll_2_ pwr_ vssa_2_5 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vddio_ 3_3 usbc_io _phy_dp usbc_io _phy_ atest usbc_o _drv_ vbus reserved/ nc or vssio_ 2_5_3_3 usbc_io _phy_ pwr_ vdda _3_3 usbc_io_ phy_pwr _vssa _ 2_5_3_3 pllc_i_ pll_2_ pwr_ vdda_2_5 vddio_ 3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 usbc_io _phy_ vbus usbc_i_ phy_id reserved/ nc usbc_io _phy_ pwr_ vddc_1_0 usbc_io_ phy_pwr _vssa_ 2_5_3_3 vddio_ 3_3 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 i2ssc_0_ i_bclk i2ssc_0_ i_ws i2ssc_0_ o_txd usbc_io_ phy_rext rkelvin usbc_io _phy_ pwr_ vdda _2_5 usbc_io_ phy_pwr _vssc_ 1_0 vssio_ 2_5_3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 reserved/ nc or vssio_ 2_5_3_3 reserved/ nc or vssio_ 2_5_3_3 i2ssc_0_ i_rxd sys_i_ boot_ mode_ sel[0] reserved/ nc reserved/ nc vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 i2ssc_o_ tx_mclk reserved/ nc or vssio_ 2_5_3_3 reserved/ nc or vssio_ 2_5_3_3 sys_i_ boot_ mode_ sel[1] reserved/ nc reserved/ nc vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 b c d e f g h j k l free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 13 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc remark: pin assignment is for asc8848/49/50/51 m2 version. for asc8848/49/50 m1 version refer table 8 fig 7. top right view of an asc8848 tfbga - 484 pin assignment 001aan244 a 12 13 14 15 16 17 18 19 20 21 22 pciec_o _phy_ tx_p pciec_i _phy_ refclk _p reserved/ nc reserved/ nc mshc_0_ io_ data[2] mshc_0_ io_ data[0] sys_o_ osc_0_ febclk sys_i_ osc_0_ clk reserved/ nc nfc_o nce[0] nfc_o _ale pciec_o _phy_ tx_m pciec_i _phy_ refclk _m mshc_0_ io_ data[3] mshc_0_ io_ data[1] mshc_0 _i_ ndetect nfc_o _nwe nfc_o _nre reserved/ nc reserved/ nc nfc_io_ data[7] nfc_io_ data[6] pciec_i _phy_ rx_p pciec_o_ phy_ resref mshc_0_ o_tx_ cclk mshc_0 io_cmd reserved/ nc nfc_i_ nrb nfc_io_ data[5] nfc_io_ data[4] reserved/ nc reserved/ nc nfc_io_ data[3] pciec_i _phy_ rx_m mshc_0_ i_write_ protect mshc_0_ i_rx_ cclk nfc_o _cle nfc_o _nwp[0] nfc_io_ data[2] reserved/ nc reserved/ nc reserved/ nc nfc_io_ data[1] nfc_io_ data[0] pciec_i_ phy_pwr _vssa_ 1_0_2_5 pciec_i_ phy_pwr _vssa_ 1_0_2_5 pllc_i_ pll_1_ pwr_ vdda_2_5 vddio_ 3_3 vddio_ 3_3 gpioc_ io_ data[19] gpioc_ io_ data[17] gpioc_ io_ data[15] gpioc_ io_ data[14] gpioc_ io_ data[13] gpioc_ io_ data[12] pciec_i_ phy_pwr _vdda_ 2_5 pciec_i_ phy_pwr _vdda_ 1_0 pllc_i_ pll_1_ pwr_ vssa_2_5 vddio_ 3_3 reserved/ nc reserved/ nc reserved/ nc pllc_i_ pll_0_ pwr_ vssa_2_5 pllc_i_ pll_0_ pwr_ vdda_2_5 gpioc_ io_ data[18] gpioc_ io_ data[16] pciec_i_ phy_pwr _vssa_ 1_0_2_5 pciec_i_ phy_pwr _vssa_ 1_0_2_5 vssio_ 2_5_3_3 vssio_ 2_5_3_3 vssio_ 2_5_3_3 hostc_i _dbg_ yms vssio_ 2_5_3_3 reserved/ nc reserved/ nc reserved/ nc reserved/ nc vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vssio_ 2_5_3_3 vddio_ sensor hostc_i _dbg_ ntrst reserved/ nc vic_i_ dev_0_ data[9] vic_i_ dev_0_ data[8] reserved/ nc vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 vddc_ 1_0 vssio_ 2_5_3_3 usbc_ io_phy_ pwr_ vssc_1_0 reserved/ nc hostc_ o_dbg_ tdo vic_i_ dev_0 _data[7] vic_i_ dev_0 _data[6] vic_i_ dev_0 _data[5] vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 vddc_ 1_0 vssio_ 2_5_3_3 vddio_ 3_3 hostc_i _dbg_ tck vic_i_ dev_0 _data[4] vic_i_ dev_0 _data[3] vic_i_ dev_0 _vsync vic_i_ dev_0 _pclk vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 vddc_ 1_0 vssio_ 2_5_3_3 vddio_ 3_3 hostc_i _dbg_ tdi vic_i_ dev_0 _data[2] vic_i_ dev_0 _data[1] vic_i_ dev_0 _data[0] vic_i_ dev_0 _hsync b c d e f g h j k l free datasheet http://
draft draft d raft dr draft d raft draft draf draft draft draft draft draft d draft draft draft draft draft draft d ra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 14 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc remark: remark: pin assignment is for asc8848/49/50/51 m2 version. for asc8848/49/50 m1 version refer table 8 fig 8. bottom left view of an as c8848 tfbga- 484 pin assignment 001aan245 m 1234567891011 vssio_ 2_5_3_3 vssio_ 2_5_3_3 sys_i_ nrst vssio_ 2_5_3_3 vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 reserved/ nc reserved/ nc vssc_ 1_0 reserved/ nc reserved/ nc reserved/ nc vssio_ 2_5_3_3 reserved/ nc reserved/ nc vddio_ 3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 reserved/ nc reserved/ nc reserved/ nc vssc_ 1_0 reserved/ nc vssio_ 2_5_3_3 vssio_ 2_5_3_3 vddc_ 1_0 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 ssic_i_ rxd ssic_o_ bclk wdtc_o _nrst ddr32 sdmc_io_ pwr_vssio _1_8 reserved/ nc ddr32 sdmc_io_ pwr_vssio _1_8 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 ssic_o_ nsel[0] ssic_o_ txd irdac_ i_sda ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ phy_pwr_ vssa_2_5 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 reserved/ nc ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 dmc_o_ nrst ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_ i_ cali ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vref _0_9 ddr32 sdmc_io_ pwr_vref _0_9 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 dmc _o_ addr[15] reserved/ nc ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_ i_ cali ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_o_ phy_ atest ddr32 sdmc _o_ addr[2] ddr32 sdmc _o_ addr[4] ddr32 sdmc _o_ addr[8] ddr32 sdmc _o_ addr[6] ddr32 sdmc _o_ addr[14] ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 reserved/ nc ddr32 sdmc _o_ ba[2] ddr32 sdmc _o_ ba[0] ddr32 sdmc _o_ addr[0] ddr32 sdmc _o_ addr[5] ddr32 sdmc _o_ addr[1] ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc _o_ ba[1] ddr32 sdmc _o_nras ddr32 sdmc _o_ncas ddr32 sdmc _o_ addr[10] ddr32 sdmc _o_nwe ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 reserved/ nc reserved/ nc reserved/ nc ddr32 sdmc _o_clk ddr32 sdmc _o_nclk n p r t u v w y aa ab free datasheet http://
draft draft d raft dr draft d raft draft draf draft draft draft draft draft d draft draft draft draft draft draft d ra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 15 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc remark: pin assignment is for asc8848/49/50/51 m2 version. for asc8848/49/50 m1 version refer table 8 fig 9. bottom right view of an asc8848 tfbga- 484 pin assignment m 12 13 14 15 16 17 18 19 20 21 22 vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 vddc_ 1_0 vssio_ 2_5_3_3 vddio_ 3_3 hostc_ o_dbg_ rtck reserved/ nc reserved/ nc reserved/ nc vic_i_ dev_0_ fsync vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 vddc_ 1_0 vssio_ 2_5_3_3 voc_ i_clk vddio_ 3_3 reserved/ nc reserved/ nc reserved/ nc reserved/ nc vssc_ 1_0 vssc_ 1_0 vssc_ 1_0 vddc_ 1_0 vssio_ 2_5_3_3 pllc_i_ pll_3_pwr _vssa_ 2_5 pllc_i_ pll_3_pwr _vdda_ 2_5 reserved/ nc reserved/ nc reserved/ nc reserved/ nc vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 vddc_ 1_0 gpioc_ io_ data[6] gpioc_ io_ data[7] gpioc_ io_ data[11] reserved/ nc reserved/ nc reserved/ nc reserved/ nc ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ phy_pwr_ vssa_2_5 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 gpioc_ io_ data[9] gpioc_ io_ data[8] gpioc_ io_ data[10] reserved/ nc voc_o_ data[7] voc_o_ data[6] voc_o_ pclk ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ phy_pwr_ vdda_2_5 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 voc_o_ data[5] voc_o_ data[4] voc_o_ data[3] voc_o_ data[2] ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vref _0_9 ddr32 sdmc_io_ pwr_vref _0_9 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vddio _1_8 ddr32 sdmc_io_ pwr_vssio _1_8 voc_o_ blank voc_o_ data[1] voc_o_ data[0] ddr32 sdmc _o_ addr[9] ddr32 sdmc _o_ addr[13] ddr32 sdmc _o_ addr[11] ddr32 sdmc_ 1_io_ dq[3] ddr32 sdmc_ 1_io_ dq[0] ddr32 sdmc_io_ phy_pwr_ vdda_2_5 ddr32 sdmc_ 1_io_ dq[11] ddr32 sdmc_ 1_o_ dm[1] ddr32 sdmc_io_ pwr_vssio _1_8 voc_o_ hsync w22 voc_o_ vsync ddr32 sdmc _o_ addr[3] ddr32 sdmc _o_ addr[7] ddr32 sdmc_ 1_io_ dq[7] ddr32 sdmc_ 1_io_ dq[5] ddr32 sdmc_ 1_o_ dm[0] ddr32 sdmc_ 1_io_ dq[15] ddr32 sdmc_ 1_io_ dq[9] ddr32 sdmc_ 1_io_ dq[10] gpioc_ io_ data[4] gpioc_ io_ data[5] sys_o_ osc_2_ febclk ddr32 sdmc _o_ addr[12] ddr32 sdmc_ 1_o_ ncs ddr32 sdmc_ 1_io_ dq[6] ddr32 sdmc_ 1_io_ dq[4] ddr32 sdmc_ 1_io_ dq[1] ddr32 sdmc_ 1_io_ dq[14] ddr32 sdmc_ 1_io_ dq[13] ddr32 sdmc_ 1_io_ dq[8] gpioc_ io_ data[3] gpioc_ io_ data[2] sys_i_ osc_2_ clk ddr32 sdmc_ 1_o_ odt ddr32 sdmc_ 1_o_ cke ddr32 sdmc_ 1_io_ ndqs[0] ddr32 sdmc_ 1_io_ dqs[0] ddr32 sdmc_ 1_io_ dq[2] ddr32 sdmc_ 1_io_ dq[12] ddr32 sdmc_ 1_io_ ndqs[1] ddr32 sdmc_ 1_io_ dqs[1] ddr32 sdmc_io_ pwr_vssio _1_8 gpioc_ io_ data[1] gpioc_ io_ data[0] n p r t u v w y aa ab free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 16 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 5.2 pin description [1] refer to table 7 for change table 4. i/o functions i/o function description 5vt 5 v - tolerant i/o smt schmitt trigger i2p default 2 ma driving capability and can be programmed to 2 ma, 4 ma, 8 ma and 12 ma i4p default 4 ma driving capability and can be programmed to 2 ma, 4 ma, 8 ma and 12 ma i8p default 8ma driving capability and can be programmed to 2 ma, 4 ma, 8 ma and 12 ma pd pulled down and can not be programmed. pudp pull-up disabled and can be programmed puep pull-up enabled and can be programmed pddp pull-down disabled and can be programmed pdep pull-down enabled and can be programmed oedp output enable disabled and can be programmed oeep output enable enabled and can be programmed ieep input enable enabled and can be programmed fsrp fast slew rate and can be programmed to slow table 5. overview of ball map updates fo r asc8848/49/50/51 m2 version and ASC8851 ball asc8848/49/50 m1 version asc8848/49/50 m2 version and ASC8851 p4 sys_i_gmac_mode_sel vssc_1_0 r4 reserved ddr32sdm c_io_pwr_vssio_1_8 m5 sys_i_gmac_tx_clk_dir vssio_2_5_3_3 w6 ddr2sdmc_i_cmd_cali ddr32sdmc_o_phy_atest w17 ddr2sdmc_i_data_1_cali ddr32sdmc_io_phy_pwr_vdda_2_5 w3 ddr2sdmc_i_data_0_cali ddr32sdmc_i_cali r7 ddr2sdmc_io_phy_pwr_vddc_1_0 vddc_1_0 t7 ddr2sdmc_io_phy_pwr_vssc_1_0 ddr32sdmc_io_phy_pwr_vssa_2_5 h6 usbc_io_phy_pwr_vssc_1_0 usbc_io_phy_pwr_vssa_2_5_3_3 j6 usbc_io_phy_pwr_vssa_2_5_3_3 usbc_io_phy_pwr_vssc_1_0 b11 sys_o_mon_clk[1] [1] sys_o_mon_clk[1] [1] v11 ddr2dmc_o_phy_atest ddr32dmc_o_addr[15] u6 ddr2sdmc_io_pwr_vssio_1_8 ddr32dmc_o_nrst n17 vssio_2_5_3_3 voc_i_clk h17 vddio_3_3 vddio_sensor free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 17 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc table 6. asc8849/50/51 so c signal descriptions pin name bga ball type function descriptions global signals sys_i_osc_0_clk a19 i - system clock 0 from oscillator or crystal (25 mhz). the feedback resistor, rf is built in and no external resistor is required. sys_i_osc_1_clk b1 i - system clock 1 from oscillator or crystal. (18.432 mhz) sys_i_osc_2_clk aa22 i - system clock 2 from oscillator or crystal. (24 mhz) the feedback resistor, rf, is built in and no external resistor is required. sys_i_nrst m4 i - active-low gl obal reset input signal. sys_i_boot_mode_sel[0] k4 i - boot mode select. refer to section boot modes 6.2. sys_i_boot_mode_sel[1] l4 i - boot mode select. refer to section boot modes 6.2. sys_i_gmac_mode_sel p4 i - asc8849/50 m1 version: rgmii/gmii mode select. 1: 2.5 v rgmii mode. 0: 3.3 v gmii mode. vssc_1_0 i - asc8849/50 m2 ve rsion and 8 851: core ground supply sys_i_gmac_tx_clk_dir m5 i - asc8849/50 m1 version: et hernet mac tx clock direction. 1: input from the external ethernet phy. 0: output to the ex ternal ethernet phy. vssio_2_5_3_3 i - asc8849/50 m2 version and 8851: i/o ground supply sys_o_osc_0_febclk a18 o - feedback crystal output of system clock 0. sys_o_osc_1_febclk c1 o - feedback crystal output of system clock 1. sys_o_osc_2_febclk y22 o - feedback crystal output of system clock 2. sys_o_mon_clk[0] c11 o oeep, i2p ? monitor clock 0. ? connect to mshc_0_i_rx_cclk if mshc 0 interface is enabled. sys_o_mon_clk[1] b11 o - asc8849/50 m1 version: monitor clock 1. connect to mshc_1_i_rx_cclk if mshc 1 interface is enabled or use 90 rotated gmac_o_tx_clk o - asc8849/50 m2 version and 8851: monitor clock 1. connect to mshc_1_i_rx_cclk wdtc_o_nrst r3 o oeep, puep, i4p system output reset. ddr-ii/iii sdram interface ddr32sdmc_o_clk ab10 o - ddr-ii/iii sdram common output clock. ddr32sdmc_o_nclk ab11 o - ddr-ii/iii sdram common complementary output clock. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 18 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr32sdmc_io_pwr_vssio_1_8 u6 g - asc8849/50 m1 version: ddr-ii/iii sdram i/o ground supply. ddr32dmc_o_nrst g - asc8849/50 m2 version and 8851: ddr-iii sdram reset. for ddr-ii could be left floating ddr32sdmc_o_nras aa8 o - active-low ddr-ii/iii sdram common row address strobe signal. ddr32sdmc_o_ncas aa9 o - active-low ddr-ii/iii sdram common column address strobe signal. ddr32sdmc_o_nwe aa11 o - active-low ddr-ii/iii sdram common write enable signal. ddr32sdmc_o_addr[0] y9 o - ddr-ii/iii sdram common address bus. ddr32sdmc_o_addr[1] y11 o - - ddr32sdmc_o_addr[2] w7 o - - ddr32sdmc_o_addr[3] y12 o - - ddr32sdmc_o_addr[4] w8 o - - ddr32sdmc_o_addr[5] y10 o - - ddr32sdmc_o_addr[6] w10 o - - ddr32sdmc_o_addr[7] y13 o - - ddr32sdmc_o_addr[8] w9 o - - ddr32sdmc_o_addr[9] w12 o - - ddr32sdmc_o_addr[10] aa10 o - - ddr32sdmc_o_addr[11] w14 o - - ddr32sdmc_o_addr[12] aa12 o - - ddr32sdmc_o_addr[13] w13 o - - ddr32sdmc_o_addr[14] w11 o - - ddr2sdmc_o_phy_atest v11 o - asc8849/50 m1 version: pll analog test output. ddr32sdmc_o_addr[15] o - asc8849/50 m2 version and 8851: ddr-ii/iii sdram common address bus bit15. allows connecting higher capacity dram compared to m1 version otherwise could be left floating ddr32sdmc_io_pwr_vddio_1_8 u7, u8, u9, u10, u11, u12, v2, v3, v4, v7 v8, v9, v10, v12, , v16, v17, v18 p - ddr-ii/iii sdram i/o power supply (1.8/1.5 v). ddr32sdmc_o_ba[0] y8 o - ddr-ii/iii sdram common internal bank select signals. ddr32sdmc_o_ba[1] aa7 o - - ddr32sdmc_o_ba[2] y7 o - - table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 19 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr2sdmc_i_cmd_cali w6 i - asc8849/50 m1 version: pvt calibration for ddr-ii sdram common command signal. connected through an external resistor, 240 (1 %), to 1.8 v. ddr32sdmc_o_phy_atest o - asc8849/50 m2 version and 8851: pll analog test output. ddr2sdmc_i_data_0_cali w3 i - asc8849/50 m1 version: pvt calibration for ddr-ii sdram 0 data bus. connected through an external resistor, 240 (1 %), to 1.8 v ddr32sdmc_i_cali - - asc8849/50 m2 version and 8851: pvt calibration for ddr-ii/iii data and command. connected through an external resistor, 240 (1 %) to ground ddr2sdmc_i_data_1_cali w17 i - asc8849/50 m1 version: pvt calibration for ddr-ii i sdram 1 data bus. connected through an external resistor, 240 (1 %), to 1.8 v ddr32sdmc_io_phy_pwr_vdda_2_5 i - asc8849/50 m2 version and 8851: ddr-ii/iii phy analog power supply (2.5 v). ddr32sdmc_0_io_dq[0] y4 i/o - ddr-ii/iii sdram 0 read/write data bus. ddr32sdmc_0_io_dq[1] aa5 i/o - - ddr32sdmc_0_io_dq[2] y5 i/o - - ddr32sdmc_0_io_dq[3] aa6 i/o - - ddr32sdmc_0_io_dq[4] ab4 i/o - - ddr32sdmc_0_io_dq[5] w5 i/o - - ddr32sdmc_0_io_dq[6] aa4 i/o - - ddr32sdmc_0_io_dq[7] w4 i/o - - ddr32sdmc_0_io_dq[8] y2 i/o - - ddr32sdmc_0_io_dq[9] aa1 i/o - - ddr32sdmc_0_io_dq[10] y3 i/o - - ddr32sdmc_0_io_dq[11] aa2 i/o - - ddr32sdmc_0_io_dq[12] aa3 i/o - - ddr32sdmc_0_io_dq[13] w2 i/o - - ddr32sdmc_0_io_dq[14] ab1 i/o - - ddr32sdmc_0_io_dq[15] y1 i/o - - ddr32sdmc_0_io_dqs[0] ab5 i/o - ddr-ii/iii s dram 0 data strobe signals. it is edge-aligned with write data and centered in read data. it must be connected on the board to a pull-down resistor, 430 to 560 (5 %). the resistor must be placed on the board within 0.3 inches of the soc. dqs[0]: for dq[7:0] dqs[1]: for dq[15:8] ddr32sdmc_0_io_dqs[1] ab2 i/o - table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 20 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr32sdmc_0_io_ndqs[0] ab6 i/o - ddr-ii/iii sdram 0 complementary data strobe signals for each byte of the data bus. it must be connected on the board to a pull-up resistor, 430 to 560 (5 %). the resistor must be placed on the board within 0.3 inches of the soc ndqs[0]: for dq[7:0] ndqs[1]: for dq[15:8] ddr32sdmc_0_io_ndqs[1] ab3 i/o - ddr32sdmc_0_o_dm[0] y6 o - ddr-ii/iii sdram 0 output data mask signals. dm[0]: for dq[7:0] dm[1]: for dq[15:8]. ddr32sdmc_0_o_dm[1] w1 o - - ddr32sdmc_0_o_cke ab9 o - ddr-ii/iii sdram clock enable signal. ddr32sdmc_0_o_ncs ab7 o - active-low ddr-ii sdram 0 chip select signal. ddr32sdmc_0_o_odt ab8 o - ddr-ii/iii sdram 0 on-die termination signal. ddr32sdmc_1_io_dq[0] w16 i/o - ddr-ii/iii sdram 1 read/write data bus. ddr32sdmc_1_io_dq[1] aa16 i/o - - ddr32sdmc_1_io_dq[2] ab16 i/o - - ddr32sdmc_1_io_dq[3] w15 i/o - - ddr32sdmc_1_io_dq[4] aa15 i/o - - ddr32sdmc_1_io_dq[5] y15 i/o - - ddr32sdmc_1_io_dq[6] aa14 i/o - - ddr32sdmc_1_io_dq[7] y14 i/o - - ddr32sdmc_1_io_dq[8] aa19 i/o - - ddr32sdmc_1_io_dq[9] y18 i/o - - ddr32sdmc_1_io_dq[10] y19 i/o - - ddr32sdmc_1_io_dq[11] w18 i/o - - ddr32sdmc_1_io_dq[12] ab17 i/o - - ddr32sdmc_1_io_dq[13] aa18 i/o - - ddr32sdmc_1_io_dq[14] aa17 i/o - - ddr32sdmc_1_io_dq[15] y17 i/o - - ddr32sdmc_1_io_dqs[0] ab15 i/o - ddr- ii/ddrddr-ii/iii-iii sdram 1 data strobe signals. it is edge-aligned with write data and centered in read data. it must be connected on the board to a pull-down resistor, 430~560? (?15%). the resistor must be placed on the board within 0.3 inches of the soc. dqs[0]: for dq[7:0] dqs[1]: for dq[15:8] - ddr32sdmc_1_io_dqs[1] ab19 - table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 21 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr32sdmc_1_io_ndqs[0] ab14 i/o - ddr-ii/iii sdram 1 complementary data strobe signals. it is edge-aligned with write data and centered in read data. it must be connected on the board to a pull-down resistor, 430~560? (?15%). the resistor must be placed on the board within 0.3 inches of the soc. ndqs[0]: for dq[7:0] ndqs[1]: for dq[15:8] - ddr32sdmc_1_io_ndqs[1] ab18 i/o - ddr32sdmc_1_o_dm[0] y16 o - ddr-ii/iii sdram 1 output data mask signals. dm[0]: for dq[7:0] dm[1]: for dq[15:8]. ddr32sdmc_1_o_dm[1] w19 o - - ddr32sdmc_1_o_cke ab13 o - ddr-ii/iii sdram 1 clock enable signal. ddr32sdmc_1_o_ncs aa13 o - active-low ddr-ii/iii 1 sdram chip select signal. ddr32sdmc_1_o_odt ab12 o - ddr-ii/iii sdram 1 on-die termination signal. gpio interface gpioc_io_data[0] ab22 i/o smt, i8p, pudp, pddp, oeep general-purpose i/o data signals. upon reset, gpioc_io_data[7:0] is set output mode and drives low; gpioc_io_data[19:8] is set input mode. gpioc_io_data[1] ab21 i/o - gpioc_io_data[2] aa21 i/o - gpioc_io_data[3] aa20 i/o - gpioc_io_data[4] y20 i/o - gpioc_io_data[5] y21 i/o - - gpioc_io_data[6] r16 i/o - - gpioc_io_data[7] r17 i/o - - gpioc_io_data[8] t17 i/o smt, i8p, pudp, pddp, oedp - gpioc_io_data[9] t16 i/o - - gpioc_io_data[10] t18 i/o - - gpioc_io_data[11] r18 i/o - - gpioc_io_data[12] e22 i/o - - gpioc_io_data[13] e21 i/o - - gpioc_io_data[14] e20 i/o - - gpioc_io_data[15] e19 i/o - - gpioc_io_data[16] f19 i/o - - gpioc_io_data[17] e18 i/o - - gpioc_io_data[18] f18 i/o - - table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 22 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc gpioc_io_data[19] e17 i/o - - jtag interface (arm926ej) hostc_i_dbg_ntrst h18 i smt, puep active low reset for internal synchronizer. hostc_i_dbg_tck k18 i smt, ieep, puep jtag clock input. hostc_i_dbg_tms g17 i smt, puep jtag mode selection input signal. hostc_i_dbg_tdi l18 i - jtag data input signal. hostc_o_dbg_rtck m18 o oeep, pdep, i4p jtag output clock signal. hostc_o_dbg_tdo j18 o oedp, puep, i4p jtag data output signal. irda interface irdac_i_sda t3 i - irda input. i2s interface i2ssc_0_i_bclk j1 i ieep, smt i 2 s serial clock. i2ssc_0_i_rxd k3 i - i 2 s receive data input signal. i2ssc_0_i_ws j2 i - i 2 s frame synchronization signal. i2ssc_0_o_txd j3 o oeep, i4p i 2 s transmit data output signal. i2ssc_1_i_bclk k2 i ieep, smt i 2 s serial clock. i2ssc_1_i_rxd l3 i - i 2 s receive data input signal. i2ssc_1_i_ws k1 i - i 2 s frame synchronization signal. i2ssc_2_i_bclk m3 i ieep, smt i 2 s serial clock. i2ssc_2_i_rxd m2 i - i 2 s receive data input signal. i2ssc_2_i_ws l2 i - i 2 s frame synchronization signal. i2ssc_3_i_bclk n3 i ieep, smt i 2 s serial clock. i2ssc_3_i_rxd n1 i - i 2 s receive data input signal. i2ssc_3_i_ws n2 i - i 2 s frame synchronization signal. i2ssc_4_i_bclk p3 i ieep, smt i 2 s serial clock. i2ssc_4_i_rxd p1 i - i 2 s receive data input signal. i2ssc_4_i_ws p2 i - i 2 s frame synchronization signal. i2ssc_o_rx_mclk m1 o oeep, i4p i 2 s master clock output. i2ssc_o_tx_mclk l1 o - i 2 s master clock output. 10/100/1000 ethernet mac interface gmac_i_rx_clk a5 i - receive clock signal. gmac_i_tx_clk a7 i - miii input transmit clock signal. gmac_i_rxdv d8 i - mii/gmii: receive data valid signal. rgmii: receive control signal. gmac_i_rxer d9 i - mii/gmii receive error signal. gmac_i_rxd[0] b7 i - receive data bus. gmac_i_rxd[1] c7 i - mii/rgmii: [3:0] table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 23 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc gmac_i_rxd[2] a6 i - gmii: [7:0] gmac_i_rxd[3] b6 i - - gmac_i_rxd[4] c6 i - - gmac_i_rxd[5] b5 i - - gmac_i_rxd[6] a4 i - - gmac_i_rxd[7] b4 i - - gmac_i_crs c5 i - mii/gmiii carrier sense signal. gmac_i_col d5 i - mii/gmii collision detected signal. gmac_io_md d6 i/o oedp, fsrp management data. gmac_o_tx_clk a9 o fsrp gmii/rgmii ou tput transmit clock signal. this clock is used only when tx clock is an input signal to the phy. gmac_o_mdc d7 o oeep, fsrp management data clock signal. gmac_o_txen d11 o - gmii: transmit data enable signal. rgmii: transmit control signal gmac_o_txer d10 o - mgi/gmii transmit error signal. gmac_o_txd[0] a10 o - transmit data bus. gmac_o_txd[1] b10 o - mii/rgmii: [3:0] gmac_o_txd[2] c10 o - gmii: [7:0] gmac_o_txd[3] b9 o - - gmac_o_txd[4] c9 o - - gmac_o_txd[5] a8 o - - gmac_o_txd[6] b8 o - - gmac_o_txd[7] c8 o - - synchronous serial interface ssic_i_rxd r1 i - ssi receive data signal. ssic_o_bclk r2 o oeep, i4p ssi serial clock output. ssic_o_txd t2 o oedp, i4p ssi transmit data signal. ssic_o_nsel[0] t1 o oeep, i4p, puep ssi slave selection signal. ssic_o_nsel[1] u1 o - - mobile storage host control interface mshc_0_i_ndetect b18 i puep card detect signal. mshc_0_i_rx_cclk d17 i ieep card input sampling clock. mshc_0_i_write_protect d16 i puep card write protect signal. mshc_0_io_cmd c17 i/o oedp, smt, puep, i8p card command signal. mshc_0_io_data[0] a17 i/o - card data signals. mshc_0_io_data[1] b17 i/o - - mshc_0_io_data[2] a16 i/o - - table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 24 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc mshc_0_io_data[3] b16 i/o - - mshc_0_o_tx_cclk c16 o oeep, i8p card clock. mshc_1_i_ndetect c14 i puep card detect signal. mshc_1_i_rx_cclk d14 i ieep card input sampling clock. mshc_1_i_write_protect d13 i puep card write protect signal. mshc_1_io_cmd d15 i/o oedp, smt, puep, i8p card command signal. mshc_1_io_data[0] a15 i/o - card data signals. mshc_1_io_data[1] a14 i/o - - mshc_1_io_data[2] b15 i/o - - mshc_1_io_data[3] b14 i/o - - mshc_1_o_tx_cclk c15 o oeep, i8p card clock. nand flash interface nfc_i_nrb c19 i smt, puep nand flash read/busy signal. nfc_io_data[0] d22 i/o oedp, smt, puep nand flash data signals. nfc_io_data[1] d21 i/o - - nfc_io_data[2] d20 i/o - - nfc_io_data[3] c22 i/o - - nfc_io_data[4] c21 i/o - - nfc_io_data[5] c20 i/o - - nfc_io_data[6] b22 i/o - - nfc_io_data[7] b21 i/o - - nfc_o_ale a22 o oeep, i4p nand flash address latch enable signal. nfc_o_cle d18 o nand flash command latch enable signal. nfc_o_nce[0] a21 o oeep, puep, i4p nand flash chip enable signals. nfc_o_nce[1] a20 o - - nfc_o_nre b20 o nand flash read enable signal. nfc_o_nwe b19 o nand flash write enable signal. nfc_o_nwp[0] d19 o nand flash write protect signals. nfc_o_nwp[1] c18 o - - uart (modem control) interface uartc_0_i_sda a1 i - serial data input for uart0. uartc_0_i_ncts b3 i - clear to send signal for uart0. uartc_0_i_ndsr c3 i - data set ready signal for uart0. uartc_0_i_nri c2 i - ring indicator signal for uart0. uartc_0_i_ndcd b2 i - data carrier detect signal for uart0. uartc_0_io_nrts c4 i/o oedp, smt, i8p request to send signal for uart0. table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 25 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc uartc_0_io_ndtr a3 i/o oedp, smt, i8p data terminal ready signal for uart0. uartc_0_o_sda a2 o oedp, puep, i8p serial data output for uart0. uartc_1_i_sda d3 i - serial data input for uart1. uartc_1_i_ncts f3 i - clear to send signal for uart1. uartc_1_i_ndsr e2 i - data set ready signal for uart1. uartc_1_i_nri f2 i - ring indicator signal for uart1. uartc_1_i_ndcd e4 i - data carrier detect signal for uart1. uartc_1_io_nrts f4 i/o oedp, smt, i8p request to send signal for uart1. uartc_1_io_ndtr d4 i/o oedp, smt, i8p data terminal ready signal for uart1. uartc_1_o_sda e3 o oedp, puep, i8p serial data output for uart1. uartc_2_i_sda d2 i - serial data input for uart2. uartc_2_o_sda d1 o oeep, puep, i8p serial data output for uart2. uartc_3_i_sda g4 i - serial data input for uart3. uartc_3_o_sda h4 o oeep, puep, i8p serial data output for uart3. video input interface vic_i_dev_0_pclk k22 i ieep, smt device 0 pixel clock input. vic_i_dev_0_hsync l22 i smt device 0 horizontal synchronization (line valid) signal. vic_i_dev_0_vsync k21 i - device 0 ve rtical synchronization (frame valid) signal. vic_i_dev_0_fsync m22 i - device 0 field signal. vic_i_dev_0_data[0] l21 i - device 0 video input data bus. vic_i_dev_0_data[1] l20 i - - vic_i_dev_0_data[2] l19 i - - vic_i_dev_0_data[3] k20 i - - vic_i_dev_0_data[4] k19 i - - vic_i_dev_0_data[5] j22 i - - vic_i_dev_0_data[6] j21 i - - vic_i_dev_0_data[7] j20 i - - vic_i_dev_1_pclk f22 i ieep, smt device 1 pixel clock input. unused when configured as one 16-bit device. vic_i_dev_1_hsync g22 i smt device 1 horizontal synchronization (line valid) signal. unused when configured as one 16-bit device. vic_i_dev_1_vsync g21 i - device 1 ve rtical synchronization (frame valid) signal. unused when configured as one 16-bit device. table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 26 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc vic_i_dev_1_fsync h22 i - device 1 field signal. unused when configured as one 16-bit device. vic_i_dev_1_data[0] / vic_i_dev_0_data[8] h21 i - device 0 video input data bus [15:8] when configured as one 16-bit device. device 1 video input data bus when configured as two 8-bit devices. vic_i_dev_1_data[1]/ vic_i_dev_0_data[9] h20 i - vic_i_dev_1_data[2]/ vic_i_dev_0_data[10] j19 i - vic_i_dev_1_data[3]/ vic_i_dev_0_data[11] h19 i - vic_i_dev_1_data[4]/ vic_i_dev_0_data[12] g20 i - vic_i_dev_1_data[5]/ vic_i_dev_0_data[13] g19 i - vic_i_dev_1_data[6]/ vic_i_dev_0_data[14] f21 i - vic_i_dev_1_data[7]/ vic_i_dev_0_data[15] f20 i - - video output interface voc_o_pclk t22 o oeep, fsrp, i8p pixel clock output. vssio_2_5_3_3 n17 - - asc8849/50 m1 version: i/o ground supply voc_i_clk - - asc8849/50 m2 version and 8851: optional alternate clock source for voc pll voc_o_vsync w22 o - vertical synchr onization (frame valid) signal. voc_o_hsync w21 o - horizontal synchronization (line valid) signal. voc_o_blank v20 o - blanking signal or data enable (de) signal. voc_o_data[0] v22 o - video output data bus voc_o_data[1] v21 o - - voc_o_data[2] u22 o - - voc_o_data[3] u21 o - - voc_o_data[4] u20 o - - voc_o_data[5] u19 o - - voc_o_data[6] t21 o - - voc_o_data[7] t20 o - - voc_o_data[8] t19 o - - voc_o_data[9] r22 o - - voc_o_data[10] r21 o - - voc_o_data[11] r20 o - - voc_o_data[12] r19 o - - voc_o_data[13] p22 o - - voc_o_data[14] p21 o - - voc_o_data[15] p20 o - - voc_o_data[16] p19 o - - table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 27 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc voc_o_data[17] n22 o - - voc_o_data[18] n21 o - - voc_o_data[19] n20 o - - voc_o_data[20] n19 o - - voc_o_data[21] m21 o - - voc_o_data[22] m20 o - - voc_o_data[23] m19 o - - universal serial bus (usb) interface usbc_i_phy_id h3 i - usb mini-rec eptacle identifier. the id detection circuitry can differentiate the following conditions: id pin floating (>100 k ) id pin shorted to ground (<10 ) usbc_io_phy_dp g1 i/o 5vt usb differential data signal, d+. usbc_io_phy_dm f1 i/o 5vt usb differential data signal, d-. usbc_io_phy_rext_rkelvin j4 i/o - usb external resistor 43.2 (1 %) connection to ground for bias current in usb 2.0 phy. usbc_io_phy_vbus h2 i/o 5vt usb 5v power supply pin. usbc_io_phy_atest g2 i/o - analog test point for internal analog voltage level measurement. usbc_o_drv_vbus g3 o oeep, i4p control off- chip charge pump. 0: do not drive vbus 1: drive vbuspci express x1 interface pci express x1 interface pciec_i_phy_refclk_m b13 i - differential reference clock input, 100 mhz. pciec_i_phy_refclk_p a13 i - differential reference clock input, 100 mhz. pciec_i_phy_rx_m d12 i - high-speed differential receive pair. pciec_i_phy_rx_p c12 i - high-speed differential receive pair. pciec_o_phy_tx_m b12 o - high-speed differential transmit pair. pciec_o_phy_tx_p a12 o - high-speed differential transmit pair. pciec_o_phy_resref c13 o - reference resistor connection, 191 (1 %) to ground. power / ground ddr32sdmc_io_phy_pwr_vdda_2_5 u13 p - ddr-ii phy pll power supply (2.5 v). ddr32sdmc_io_phy_pwr_vddc_1_0 r7 p - asc884 9/50 m1 version: ddr-ii phy core power supply (1.0 v). vddc_1_0 p - asc8849/50 m2 version and 8851: core power supply(1.0 v) ddr32sdmc_io_phy_pwr_vssa_2_5 t13 g - ddr-ii/iii phy pll ground supply. ddr32sdmc_io_phy_pwr_vssc_1_0 t7 g - asc8849/50 m1 version: ddr-ii/iii phy core ground supply. ddr32sdmc_io_phy_pwr_vssa_2_5 g - asc8849/50 m2 vers ion and 8851: ddr-ii/iii phy analog ground supply. table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 28 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr32sdmc_io_pwr_vddio_1_8 u7, u8, u9, u10, u11, u12, v2, v3, v4, v7 v8, v9, v10, v12, v13, v16, v17, v18 p - ddr-ii/iii sdram i/o power supply (1.8/1.5 v). ddr32sdmc_io_pwr_vref_0_9 v5, v6, v14, v15 p - ddr-ii/iii sdram reference power supply (0.9 v). ddr32sdmc_io_pwr_vssio_1_8 r6, t4, t5, t6, t8, t9, t10, t11, t12 t14, t15 u2, u3, u4, u5, u14, u15, u16, u17, u18, v1, v19, w20, ab20 g - ddr-ii/iii sdram i/o ground supply. pciec_i_phy_pwr_vdda_1_0 f13 p - pci express phy low-voltage power supply (1.0 v). pciec_i_phy_pwr_vdda_2_5 f12 p - pci express phy high-voltage power supply (2.5 v). pciec_i_phy_pwr_vssa_ 1_0_2_5 e12, e13 g12, g13 g - pci express phy ground supply. pllc_i_pll_0_pwr_vdda_2_5 f17 p - pll0 analog power supply (2.5 v). pllc_i_pll_0_pwr_vssa_2_5 f16 g - pll0 analog ground supply. pllc_i_pll_1_pwr_vdda_2_5 e14 p - pll1 analog power supply (2.5 v). pllc_i_pll_1_pwr_vssa_2_5 f14 g - pll1 analog ground supply. pllc_i_pll_2_pwr_vdda_2_5 g7 p - pll2 analog power supply (2.5 v). pllc_i_pll_2_pwr_vssa_2_5 f7 g - pll2 analog ground supply. pllc_i_pll_3_pwr_vdda_2_5 p18 p - pll3 analog power supply (2.5 v). pllc_i_pll_3_pwr_vssa_2_5 p17 g - pll3 analog ground supply. usbc_io_phy_pwr_vddc_1_0 h5 p - usbphy digital power supply (1.0 v). usbc_io_phy_pwr_vssc_1_0 h6 g - asc8849/ 50 m1 version: usbphy digital ground supply. usbc_io_phy_pwr_vssa_2_5_3_3 g - asc8849/50 m2 version and 8851: usbphy analog ground supply. usbc_io_phy_pwr_vdda_2_5 j5 p - usbphy analog power supply (2.5 v). usbc_io_phy_pwr_vdda_3_3 g5 p - usbphy analog power supply (3.3 v). usbc_io_phy_pwr_vssa_2_5_3_3 g6 g - usbphy analog ground supply. usbc_io_phy_pwr_vssa_2_5_3_3 j6 - - asc8849/50 m1 version: usbphy analog ground supply. usbc_io_phy_pwr_vssc_1_0 - - asc8849/50 m2 version and 8851:usbphy digital ground supply. table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 29 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc vddc_1_0 h8, h9, h10, h11, h12, h13, h14, h15, j8, j15, k8, k15, l8, l15, m8, m15, n8, n15, p8, p15, r8, r9, r10, r11, r12, r13, r14, r15 p - core power supply (1.0 v). vssc_1_0 j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n9, n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14 g - core ground supply. vddio_2_5_3_3 e6, e7, e8, e9, e10 p - mii/gmii (3.3 v) / rgmii (2.5 v) i/o power supply. vddio_3_3 e5, e11, e15, e16, f5, f11, f15, g8, h7, j17, k7, k17, l7, l17, m7, m17, n7, n18 p - i/o power supply (3.3 v). vddio_3_3 h17 - - asc8849/50 m1 version: i/o power supply (3.3 v). vddio_sensor - - asc8849/50 m2 version and 8851: sensor power supply if the level-shifters between sensor and this chip are removed table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 30 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc table 7 shows the reference voltages for each i/o. those signals not listed below all reference vddio_3_3 (3.3 v). vssio_2_5_3_3 a11, e1, f6, f8, f9, f10, g9, g10, g11, g14, g15, g16 g18, h1, h16, j7, j16, k16, l16, m16, n4, n16, p6, p7, p16 g - i/o ground supply. reserved k5, k6, l5, l6, m6, n5, n6, p5, r5 -- - reserved r4 - - asc8849/50 m1 version: left floating for normal operation ddr32sdmc_io_pwr_vssio_1_8 - - asc 8849/50 m2 vers ion and 8851: ddr-ii/iii sdram i/o ground supply. table 6. asc8849/50/51 so c signal descriptions ?continued pin name bga ball type function descriptions table 7. asc8849/asc8850/ASC8851 soc pin reference voltage special i/o 1.0v1 1.8 v 2.5v or 3.3v video in i/o usbc_i_phy_id sys_i_osc_0_clk ddr32sdmc_o_clk gmac_i_rx_clk vic_i_dev_0_pclk usbc_io_phy_dp sys_i_osc_1_clk ddr32sdmc_o_nclk gmac_i_tx_clk vic_i_dev_0_hsync usbc_io_phy_dm sys_i_osc_2_clk ddr32sdmc_o_nras gmac_i_rxdv vic_i_dev_0_vsync usbc_io_phy_rext_rk elvin ddr32sdmc_o_ncas gmac_i_rxer vic_i_dev_0_fsync usbc_io_phy_vbus ddr32sdmc_o_nwe gma c_i_rxd[7:0] vic_i_dev_0_data[0] usbc_io_phy_atest ddr32sdmc_o_addr [14:0] gmac_i_crs vic_i_dev_0_data[1] pciec_i_phy_refclk_ m ddr32sdmc_o_ba[2: 0] gmac_i_col vic_i_dev_0_data[2] pciec_i_phy_refclk_p ddr32sdmc_o_phy_ atest gmac_io_md vic_i_dev_0_data[3] pciec_i_phy_rx_m ddr32sdmc_i_cali gmac_o_tx_clk vic_i_dev_0_data[4] pciec_i_phy_rx_p ddr32sdmc_0_io_d q[15:0] gmac_o_mdc vic_i_dev_0_data[5] pciec_o_phy_tx_m ddr32sdmc_0_io_d qs[1:0] gmac_o_txen vic_i_dev_0_data[6] pciec_o_phy_tx_p ddr32sdmc_0_io_nd qs[1:0] gmac_o_txer vic_i_dev_0_data[7] pciec_o_phy_resref ddr32sdmc_0_o_dm [1:0] gmac_o_txd[7:0] v ic_i_dev_1_pclk ddr32sdmc_0_o_ck e vic_i_dev_1_hsync free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 31 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr32sdmc_0_o_nc s vic_i_dev_1_vsync ddr32sdmc_0_o_od t vic_i_dev_1_fsync ddr32sdmc_1_io_d q[15:0] vic_i_dev_0_data[8] ddr32sdmc_1_io_d qs[1:0] vic_i_dev_0_data[9] ddr32sdmc_1_io_nd qs[1:0] vic_i_dev_0_data[1 0] ddr32sdmc_1_o_dm [1:0] vic_i_dev_0_data[1 1] ddr32sdmc_1_o_ck e vic_i_dev_0_data[1 2] ddr32sdmc_1_o_nc s vic_i_dev_0_data[1 3] ddr32sdmc_1_o_od t vic_i_dev_0_data[1 4] vic_i_dev_0_data[1 5] table 7. asc8849/asc8850/ASC8851 soc pin reference voltage special i/o 1.0v1 1.8 v 2.5v or 3.3v video in i/o table 8. asc8848 soc signal descriptions pin name bga ball type function description global signals sys_i_osc_0_clk a19 i - system clock 0 from oscillator or crystal. (25 mhz). the feedback resistor, rf, is built in and no external resistor is required. sys_i_osc_1_clk b1 i - system clock 1 from oscillator or crystal. (18.432 mhz). the feedback resistor, rf, is built in and no external resistor is required. sys_i_osc_2_clk aa22 i - system clock 2 from oscillator or crystal. (24 mhz). the feedback resistor, rf, is built in and no external resistor is required. sys_i_nrst m4 i - active-low global reset input signal. sys_i_boot_mode_sel[0] k4 i - boot mode select. refer to section boot modes 4.2. sys_i_boot_mode_sel[1] l4 i - boot mode select. refer to section boot modes 4.2. sys_i_gmac_mode_sel p4 i - asc8848 m1 version: rgmii/gmii mode select. 1: 2.5 v rgmii model. 0: 3.3 v gmii mode. vssc_1_0 i - asc8848 m2: core ground supply free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 32 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc sys_i_gmac_tx_clk_dir m5 i - asc8848 m1 version: ethernet mac tx clock direction. 1: input from the ex ternal ethernet phy. 0: output to the external ethernet phy. vssio_2_5_3_3 i - asc8848 m2: i/o ground supply sys_o_osc_0_febclk a18 o - feedback crystal output of system clock 0. sys_o_osc_1_febclk c1 o - feedback crystal output of system clock 1. sys_o_osc_2_febclk y22 o - feedback crystal output of system clock 2. sys_o_mon_clk[0] c11 o oeep , i2p 1. monitor clock 0 2. connect to mshc_0_i_rx_cclk if mshc 0 interface is enabled wdtc_o_nrst r3 o oeep, puep, i4p system output reset. ddr-ii/iii sdram interface ddr32sdmc_o_clk ab10 o - ddr-ii/iii sdram common output clock. ddr32sdmc_o_nclk ab11 o - ddr-ii/iii sdram common complementary output clock. ddr2sdmc_io_pwr_vssio_1_8 u6 g - asc88 48 m1 version: ddr-ii/iii sdram i/o ground supply. ddr32dmc_o_nrst g - asc8848 m2: ddr-iii sdram reset. for ddr-ii could be left floating ddr32sdmc_o_nras aa8 o - active-low ddr-ii/iii sdram common row address strobe signal. ddr32sdmc_o_ncas aa9 o - active-low ddr-ii/iii sdram common column address strobe signal. ddr32sdmc_o_nwe aa11 o - active-low ddr-ii/iii sdram common write enable signal. ddr32sdmc_o_addr[0] y9 o - ddr-ii/ iii sdram common address bus. ddr32sdmc_o_addr[1] y11 o - - ddr32sdmc_o_addr[2] w7 o - - ddr32sdmc_o_addr[3] y12 o - - ddr32sdmc_o_addr[4] w8 o - - ddr32sdmc_o_addr[5] y10 o - - ddr32sdmc_o_addr[6] w10 o - - ddr32sdmc_o_addr[7] y13 o - - ddr32sdmc_o_addr[8] w9 o - - ddr32sdmc_o_addr[9] w12 o - - ddr32sdmc_o_addr[10] aa10 o - - ddr32sdmc_o_addr[11] w14 o - - ddr32sdmc_o_addr[12] aa12 o - - ddr32sdmc_o_addr[13] w13 o - - ddr32sdmc_o_addr[14] w11 o - table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 33 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr2sdmc_o_phy_atest v11 o - asc8848 m1 version: pll analog test output. ddr32sdmc_o_addr[15] o - asc8848 m2: ddr-ii/iii sdram common address bus bit15. allows connecting higher capacity dram compared to m1 version otherwise could be left floating. ddr32sdmc_o_ba[0] y8 o - ddr-ii/iii sdram common internal bank select signals. ddr32sdmc_o_ba[1] aa7 o - - ddr32sdmc_o_ba[2] y7 o - - ddr2sdmc_i_cmd_cali w6 i - asc8848 m1 version: pvt calibration for ddr-ii sdram common command signal. connected through an external resistor, 240 (1 %), to 1.8 v. ddr32sdmc_o_phy_atest - - asc8848 m2: pll analog test output. ddr2sdmc_i_data_1_cali w17 i - asc8848 m1 version: pvt calibration for ddr-ii sdram 1 data bus. connected through an external resistor, 240 (1 %), to 1.8 v ddr32sdmc_io_phy_pwr_vdda _2_5 - - asc8848 m2: ddr-ii/iii phy analog power supply (2.5 v). ddr32sdmc_1_io_dq[0] w16 i/o - ddr- ii/iii sdram 1 read/write data bus. ddr32sdmc_1_io_dq[1] aa16 i/o - - ddr32sdmc_1_io_dq[2] ab16 i/o - - ddr32sdmc_1_io_dq[3] w15 i/o - - ddr32sdmc_1_io_dq[4] aa15 i/o - - ddr32sdmc_1_io_dq[5] y15 i/o - - ddr32sdmc_1_io_dq[6] aa14 i/o - - ddr32sdmc_1_io_dq[7] y14 i/o - - ddr32sdmc_1_io_dq[8] aa19 i/o - - ddr32sdmc_1_io_dq[9] y18 i/o - - ddr32sdmc_1_io_dq[10] y19 i/o - - ddr32sdmc_1_io_dq[11] w18 i/o - - ddr32sdmc_1_io_dq[12] ab17 i/o - - ddr32sdmc_1_io_dq[13] aa18 i/o - - ddr32sdmc_1_io_dq[14] aa17 i/o - - ddr32sdmc_1_io_dq[15] y17 i/o - - table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 34 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr32sdmc_1_io_dqs[0] ab15 i/o - ddr-ii/iii sdram 1 data strobe signals. it is edge-aligned with write data and centered in read data. it must be connected on the board to a pull-down resistor, 430~560? (?15%). the resistor must be placed on the board within 0.3 inches of the soc. dqs[0]: for dq[7:0] dqs[1]: for dq[15:8]- ddr32sdmc_1_io_dqs[1] ab19 i/o - ddr32sdmc_1_io_ndqs[0] ab14 i/o - ddr-ii/iii sdram 1 complementary data strobe signals. it is edge-aligned with write data and centered in read data. it must be connected on the board to a pull-down resistor, 430~560? (?15%). the resistor must be placed on the board within 0.3 inches of the soc. ndqs[0]: for dq[7:0] ndqs[1]: for dq[15:8]- ddr32sdmc_1_io_ndqs[1] ab18 i/o - ddr32sdmc_1_o_dm[0] y1 6 o - ddr-ii/iii sdram 1 output data mask signals. dm[0]: for dq[7:0] dm[1]: for dq[15:8]. ddr32sdmc_1_o_dm[1] w19 o - ddr32sdmc_1_o_cke ab13 o - ddr-ii/ iii sdram 1 clock enable signal. ddr32sdmc_1_o_ncs aa13 o - active- low ddr-ii/iii 1 sdram chip select signal. ddr32sdmc_1_o_odt ab12 o - ddr-ii/ iii sdram 1 on-die termination signal. gpio interface gpioc_io_data[0] ab22 i/o smt, i8p, pudp, pddp, oeep general-purpose i/o data signals. upon reset, gpioc_io_data[7:0] is set output mode and drives low; gpioc_io_data[19:8] is set input mode. gpioc_io_data[1] ab21 i/o - gpioc_io_data[2] aa21 i/o - gpioc_io_data[3] aa20 i/o - gpioc_io_data[4] y20 i/o - gpioc_io_data[5] y21 i/o - - gpioc_io_data[6] r16 i/o - - gpioc_io_data[7] r17 i/o - - gpioc_io_data[8] t17 i/o smt, i8p, pudp, pddp, oedp - gpioc_io_data[9] t16 i/o - - gpioc_io_data[10] t18 i/o - - gpioc_io_data[11] r18 i/o - - gpioc_io_data[12] e22 i/o - - table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 35 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc gpioc_io_data[13] e21 i/o - - gpioc_io_data[14] e20 i/o - - gpioc_io_data[15] e19 i/o - - gpioc_io_data[16] f19 i/o - - gpioc_io_data[17] e18 i/o - - gpioc_io_data[18] f18 i/o - - gpioc_io_data[19] e17 i/o - - jtag interface (arm926ej) hostc_i_dbg_ntrst h18 i smt, puep active low reset for internal synchronizer. hostc_i_dbg_tck k18 i smt, ieep, puep jtag clock input. hostc_i_dbg_tms g17 i smt, puep jtag mode selection input signal. hostc_i_dbg_tdi l18 i - jtag data input signal. hostc_o_dbg_rtck m18 o oeep, pdep, i4p jtag output clock signal. hostc_o_dbg_tdo j18 o oedp, puep, i4p jtag data output signal. irda interface irdac_i_sda t3 i - irda input. i2s interface i2ssc_0_i_bclk j1 i ieep, smt i 2 s serial clock. i2ssc_0_i_rxd k3 i - i 2 s receive data input signal. i2ssc_0_i_ws j2 i - i 2 s frame synchronization signal. i2ssc_0_o_txd j3 o oeep, i4p i 2 s transmit data output signal. i2ssc_o_tx_mclk l1 o - i 2 s master clock output. 10/100 ethernet mac interface gmac_i_rx_clk a5 i - receive clock signal. gmac_i_tx_clk a7 i - input transmit clock signal. gmac_i_rxdv d8 i - receive data valid signal. rgmii: receive control signal. gmac_i_rxer d9 i - receive error signal. gmac_i_rxd[0] b7 i - receive data bus. gmac_i_rxd[1] c7 i - - gmac_i_rxd[2] a6 i - - gmac_i_rxd[3] b6 i - - gmac_i_crs c5 i - carrier sense signal. gmac_i_col d5 i - collision detected signal. gmac_io_md d6 i/o oedp, fsrp management data. table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 36 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc gmac_o_tx_clk a9 o fsrp gmii/rgmii output transmit clock signal. this clock is used only when tx clock is an input signal to the phy. gmac_o_mdc d7 o oeep, fsrp management data clock signal. gmac_o_txen d11 o - transmit data enable signal. gmac_o_txer d10 o - transmit error signal. gmac_o_txd[0] a10 o - transmit data bus. gmac_o_txd[1] b10 o - - gmac_o_txd[2] c10 o - - gmac_o_txd[3] b9 o - - synchronous serial interface ssic_i_rxd r1 i - ssi receive data signal. ssic_o_bclk r2 o oeep, i4p ssi serial clock output. ssic_o_txd t2 o oedp, i4p ssi transmit data signal. ssic_o_nsel[0] t1 o oeep, i4p, puep ssi slave selection signal. mobile storage host control interface mshc_0_i_ndetect b18 i puep card detect signal. mshc_0_i_rx_cclk d17 i ieep card input sampling clock. mshc_0_i_write_protect d16 i puep card write protect signal. mshc_0_io_cmd c17 i/o oedp, smt, puep, i8p card command signal. mshc_0_io_data[0] a17 i/o card data signals. mshc_0_io_data[1] b17 i/o - - mshc_0_io_data[2] a16 i/o - - mshc_0_io_data[3] b16 i/o - - mshc_0_o_tx_cclk c16 o oeep, i8p card clock. nand flash interface nfc_i_nrb c19 i smt, puep nand flash read/busy signal. nfc_io_data[0] d22 i/o oedp, smt, puep nand flash data signals. nfc_io_data[1] d21 i/o - - nfc_io_data[2] d20 i/o - - nfc_io_data[3] c22 i/o - - nfc_io_data[4] c21 i/o - - nfc_io_data[5] c20 i/o - - nfc_io_data[6] b22 i/o - - nfc_io_data[7] b21 i/o - - table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 37 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc nfc_o_ale a22 o oeep, i4p nand flash address latch enable signal. nfc_o_cle d18 o - nand flash command latch enable signal. nfc_o_nce[0] a21 o oeep, puep, i4p nand flash chip enable signals. nfc_o_nre b20 o - nand flash read enable signal. nfc_o_nwe b19 o - nand flash write enable signal. nfc_o_nwp[0] d19 o - nand flash write protect signals. uart (modem control) interface uartc_0_i_sda a1 i - serial data input for uart0. uartc_0_i_ncts b3 i - clear to send signal for uart0. uartc_0_i_ndsr c3 i - data set ready signal for uart0. uartc_0_i_nri c2 i - ring indicator signal for uart0. uartc_0_i_ndcd b2 i - data carrier detect signal for uart0. uartc_0_io_nrts c4 i/o oedp, smt, i8p request to send signal for uart0. uartc_0_io_ndtr a3 i/o oedp, smt, i8p data terminal ready signal for uart0. uartc_0_o_sda a2 o oedp, puep, i8p serial data output for uart0. uartc_1_i_ndcd d3 i - data carrier detect signal for uart1. uartc_1_o_sda e3 o oedp, puep, i8p serial data output for uart1. video input interface vic_i_dev_0_pclk k22 i ieep, smt device 0 pixel clock input. vic_i_dev_0_hsync l22 i smt device 0 horizontal synchronization (line valid) signal. vic_i_dev_0_vsync k21 i - device 0 ve rtical synchronization (frame valid) signal. vic_i_dev_0_fsync m22 i - device 0 field signal. table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 38 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc vic_i_dev_0_data[0] l21 i - device 0 video input data bus. vic_i_dev_0_data[1] l20 i - vic_i_dev_0_data[2] l19 i - vic_i_dev_0_data[3] k20 i - vic_i_dev_0_data[4] k19 i - vic_i_dev_0_data[5] j22 i - vic_i_dev_0_data[6] j21 i - vic_i_dev_0_data[7] j20 i - vic_i_dev_0_data[8] h21 i - vic_i_dev_0_data[9] h20 i - vic_i_dev_0_data[10] j19 i vic_i_dev_0_data[11] h19 i video output interface voc_o_pclk t22 o oeep, fsrp, i8p pixel clock output. vssio_2_5_3_3 n17 - - asc8848 m1 version: i/o ground supply voc_i_clk - - asc8848 m2 optional: alternate clock sour ce for voc pll voc_o_vsync w22 o - vertical synch ronization (frame valid) signal. voc_o_hsync w21 o - horizontal synchronization (line valid) signal. voc_o_blank v20 o - blanking signal or data enable (de) signal. voc_o_data[0] v22 o - video output data bus voc_o_data[1] v21 o - - voc_o_data[2] u22 o - - voc_o_data[3] u21 o - - voc_o_data[4] u20 o - - voc_o_data[5] u19 o - - voc_o_data[6] t21 o - - voc_o_data[7] t20 o - - universal serial bus (usb) interface usbc_i_phy_id h3 i - usb mini-receptacle identifier. the id detection circuitry can differentiate the following conditions: id pin floating (>100 k ) id pin shorted to ground (<10 ) usbc_io_phy_dp g1 i/o 5vt usb differential data signal, d+. usbc_io_phy_dm f1 i/o 5vt usb differential data signal, d-. usbc_io_phy_rext_rkelvin j4 i/o - usb external resistor 43.2 (1 %) connection to ground for bias current in usb 2.0 phy. usbc_io_phy_vbus h2 i/o 5vt usb 5 v power supply pin. table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 39 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc usbc_io_phy_atest g2 i/o - analog test point for internal analog voltage level measurement. usbc_o_drv_vbus g3 o oeep, i4p control off-chip charge pump. 0: do not drive vbus 1: drive vbuspci express x1 interface pci express x1 interface pciec_i_phy_refclk_m b13 i - differential reference clock input, 100 mhz. pciec_i_phy_refclk_p a13 i - differential reference clock input, 100 mhz. pciec_i_phy_rx_m d12 i - high-speed differential receive pair. pciec_i_phy_rx_p c12 i - high-speed differential receive pair. pciec_o_phy_tx_m b12 o - high-speed differential transmit pair. pciec_o_phy_tx_p a12 o - high-speed differential transmit pair. pciec_o_phy_resref c13 o - reference resistor connection, 191 (1 %) to ground. power / ground ddr32sdmc_io_phy_pwr_vdda _2_5 u13 p - ddr-ii/iii phy pll power supply (2.5 v). ddr32sdmc_io_phy_pwr_vddc _1_0 r7 p - asc8848 m1 version: ddr-ii/iii phy core power supply (1.0 v). vddc_1_0 p - asc8848 m2: core power supply(1.0 v) ddr32sdmc_io_phy_pwr_vssa _2_5 t13 g - ddr-ii/iii phy pll ground supply. ddr32sdmc_io_phy_pwr_vssc _1_0 t7 g - asc8848 m1 version: ddr-ii/iii phy core ground supply. ddr32sdmc_io_phy_pwr_vssa _2_5 g - asc8848 m2: ddr-ii/iii phy analog ground supply. ddr32sdmc_io_pwr_vddio_1_8 u7,u8, u9, u10, u11, u12, v2 , v3, v4, v7, v8, v9, v10, v12, v13, v16 , v17, v18 p - ddr-ii/iii sdram i/o power supply (1.8/1.5 v). ddr32sdmc_io_pwr_vref_0_9 v5 , v6, v14, v15 p - ddr-ii/iii sdram reference power supply (0.9 v). table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 40 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ddr32sdmc_io_pwr_vssio_ 1_8 r6, t4 , t5, t6, t8 ,t9, t10, t11, t12, t14, t15, u2,u3, u4, u5, u14 , u15, u16, u17, u18, v1, v19, w2, w4, w5, w20, y1,y2, y3, y4 y5, aa1 , aa2, aa3, aa4, aa5, aa6, ab1,ab2, ab3, ab4, ab5, ab6, ab20 g - ddr-ii/iii sdram i/o ground supply. ddr2sdmc_i_data_0_cali w3 i - asc8848 m1 version: pvt calibration for ddr-ii sdram 0 data bus. connected through an external resistor, 240 (1 %), to 1.8 v ddr32sdmc_i_cali i - asc8848 m2: pvt calibration for ddr-ii/iii data and command. connected through an external resistor, 240 (1 %) to gnd pciec_i_phy_pwr_vdda_1_0 f13 p - pci express phy low-voltage power supply (1.0 v). pciec_i_phy_pwr_vdda_2_5 f12 p - pci express phy high-voltage power supply (2.5 v). pciec_i_phy_ pwr_vssa_1_0_2_ 5 e12, e13, g12, g13 g - pci express phy ground supply. pllc_i_pll_0_pwr_vdda_2_5 f17 p - pll0 analog power supply (2.5 v). pllc_i_pll_0_pwr_vssa_2_5 f16 g - pll0 analog ground supply. pllc_i_pll_1_pwr_vdda_2_5 e14 p - pll1 analog power supply (2.5 v). pllc_i_pll_1_pwr_vssa_2_5 f14 g - pll1 analog ground supply. pllc_i_pll_2_pwr_vdda_2_5 g7 p - pll2 analog power supply (2.5 v). pllc_i_pll_2_pwr_vssa_2_5 f7 g - pll2 analog ground supply. pllc_i_pll_3_pwr_vdda_2_5 p18 p - pll3 analog power supply (2.5 v). pllc_i_pll_3_pwr_vssa_2_5 p17 g - pll3 analog ground supply. usbc_io_phy_pwr_vddc_1_0 h5 p - usbphy digital power supply (1.0 v). usbc_io_phy_pwr_vssc_1_0 h6 g - asc88 48 m1 version: usbphy digital ground supply. usbc_io_phy_pwr_vssa_2_5_3 _3 g asc8848 m2: usbphy analog ground supply. usbc_io_phy_pwr_vdda_2_5 j5 p - usbphy analog power supply (2.5 v). usbc_io_phy_pwr_vdda_3_3 g5 p - usbphy analog power supply (3.3 v). usbc_io_phy_pwr_vssa_2_5_3 _3 g6 g - usbphy analog ground supply. table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 41 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc usbc_io_phy_pwr_vssa_2_5_3 _3 j6 - - asc8848 m1 version: usbphy analog ground supply. usbc_io_phy_pwr_vssc_1_0 - - asc8848 m2: usbphy digital ground supply. vddc_1_0 h8, h9, h10, h11, h12, h13, h14, h15, j8, j15, k8, k15, l8, l15, m8, m15, n8, n15, p8, p15, r8 to r15 p - core power supply (1.0 v). vssc_1_0 j9 , j10, j11, j12, j13, j14, k9 , k10, k11, k12, k13, k14, l9 , l10, l11, l12, l13, l14, m9 , m10, m11, m12, m13, m14, n9 , n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14 g - core ground supply. vddio_2_5_3_3 e6 , e7, e8, e9, e10 p - mii i/o power supply. should be connected to 3.3v. vddio_3_3 e5, e11, e15, e16, f5, f11, f15, g8, h7, j17, k7, k17, l7, l17, m7, m17, n7, n18 p - i/o power supply (3.3 v) vddio_3_3 h17 - - asc8848 m1 version: i/o power supply (3.3 v) vddio_sensor - - asc8848 m2: sensor power supply if the level-shifters between sensor and this chip are removed vssio_2_5_3_3 a11, d2, e1, e2, f6, f8 , f9, f10, g4, g9,g10, g11, g14 , g15, g16, g18 h1, h16, j7, j16, k1, k2, k16, l2, l3, l16, m2, m3, m16, n4, n16, p6, p7, p16 g - i/o ground supply. table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 42 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc reserved a14, a15, a20, a4, a8, b14, b15, b4, b5, b8, c14, c15, c18, c6, c8, c9, d1, d13, d14, d3, d4, e4, f2, f20, f21, f22, f4, g19,g20, g21, g22, , h22, h4, , k5, k6, l5, l6, m1, m6, m19 , m20, m21, n1, n2, n19 to n22, n3, n5, n6, p1,p2, p3, p5, p19 , p20, p21, r5, t19, v1, v20, w1, w21, y6, ab7 to ab9 - - left floating for normal operation sys_o_mon_clk[1] b11 o - asc8848 m1 version: monitor clock 1. connect to mshc_1_i_rx_cclk if mshc 1 interface is enabled or use 90 rotated gmac_o_tx_clk - - asc8848 m2: monitor clock 1. connect to mshc_1_i_rx_cclk reserved r4 - - asc8848 m1 version: left floating for normal operation ddr32sdmc_io_pwr_vssio_1_8 - - asc 8848 m2: ddr-ii/iii sdram i/o ground supply. table 8. asc8848 soc signal descriptions ?continued pin name bga ball type function description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 43 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc ta b l e 9 shows the reference voltages for each i/o. those signals not listed below all reference vddio_3_3 (3.3 v). table 9. reference voltage for i/o special i/o 1.0v1 1.8 v video in i/o usbc_i_phy_id sys_i_osc_0_clk ddr32sdmc_o_clk vic_i_pclk usbc_io_phy_dp sys_i_osc_1_clk ddr32sdmc_o_nclk vic_i_hsync usbc_io_phy_dm sys_i_osc_2_clk ddr32sdmc_o_nras vic_i_vsync usbc_io_phy_rext_rkelvin ddr3 2sdmc_o_ncas vic_i_fsync usbc_io_phy_vbus ddr32sdmc_o_nwe vic_i_data[0] usbc_io_phy_atest ddr32sdmc_ o_addr[14:0] vic_i_data[1] pciec_i_phy_refclk_m ddr32sdmc_o_ba[2:0] vic_i_data[2] pciec_i_phy_refclk_p ddr32sdmc_o_phy_ates t vic_i_data[3] pciec_i_phy_rx_m ddr32sdmc_i_cali vic_i_data[4] pciec_i_phy_rx_p ddr32sdmc_ io_dq[15:0] vic_i_data[5] pciec_o_phy_tx_m ddr32sdmc_io_dqs[1:0] vic_i_data[6] pciec_o_phy_tx_p ddr32sdmc_io_ndqs[1:0] vic_i_data[7] pciec_o_phy_resref ddr32sdmc_o_dm[1:0] vic_i_data[8] ddr32sdmc_o_cke vic_i_data[9] ddr32sdmc_o_ncs vic_i_data[10] ddr32sdmc_o_odt vic_i_data[11] free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 44 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6. functional description memory map: asc8848/49/50/51 soc has a 32-bit address bus and is capable of addressing up to 4 gb address space. ta b l e 1 0 shows the memory mapped address and its size for each device on amba ahb bus. ta b l e 11 shows the memory mapped address and its size for each device on amba apb 2.0 bus. table 12 shows the memory mapped address and its size for each device on amba apb 3.0 bus. the start address and size are power-on def ault values and users could configure the memory space based on their own requirements. the overlapping of memory space is forbidden and must be taken care of. figure 10 illustrates the whole memory map. 6.1 function selection table 10. memory mapped address on amba ahb bus. start address size (mb) description 0x00000000 256 internal boot rom / external ddr-ii/iii sdram 0 0x10000000 256 external ddr-ii/iii sdram 1 0x40000000 256 apb 2.0 devices 0x50000000 256 apb 3.0 devices 0x60000000 256 pcie devices 0x80000000 1 usb 2.0 host controller (usbc) 0x84000000 1 pcie dual mode controller (pciec) 0x90000000 1 mobile storage controller 0 (mshc) 0x94000000 1 mobile storage controller 1 (mshc) 0x98000000 1 giga-bit ethernet mac (gmac) 0xa0000000 1 nand flash controller (nfc) 0xc0000000 1 amba ahb controller 0 (ahbc) 0xc1000000 1 amba ahb controller 1 (ahbc) 0xc2000000 1 amba ahb controller 2 (ahbc) 0xc4000000 1 ddr-ii/iii sdram memory controller 0 (ddr32sdmc ) 0xc5000000 1 ddr-ii/iii sdram memory controller 1 (ddr32sdmc ) 0xc7000000 1 interrupt controller (intc) 0xc8000000 1 ahb-to-apb bridge (apbc) 0xc9000000 1 direct memory access controller (dmac) 0xca000000 1 video input controller (vic) 0xcc000000 1 video output controller (voc) 0xd0000000 1 data crypto engine (dce) 0xd1000000 1 deinterlacing engine (die) 0xd2000000 1 image back-en d processing engine (ibpe) 0xd3000000 1 resize engine (ire) 0xd7000000 1 mpeg-4 enco der audio engine (meae) 0xd8000000 1 jpeg encoder engine (jebe) 0xdc000000 1 h.264/mpeg-4 encoder engine (h4ee) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 45 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc table 11. memory mapped address on amba apb 2.0 bus start address size (mb) description 0x40800000 8 synchronous serial interface controller (ssic) 0x41800000 8 inter-ic sound controller 0 (i2sc) 0x42000000 8 inter-ic sound controller 1 (i2sc) 0x42800000 8 inter-ic sound controller 2 (i2sc) 0x43000000 8 inter-ic sound controller 3 (i2sc) 0x43800000 8 inter-ic sound controller 4 (i2sc) 0x47000000 8 usb 2.0 host controller (usbssc) 0x47800000 8 pcie dual mode controller (pciessc) 0x48000000 8 timer controller (tmrc) 0x48800000 8 watchdog timer (wdt) 0x49000000 8 general purpose inpu t/output controller (gpioc) 0x49800000 8 advanced general purpos e output controller (agpoc) 0x4a000000 8 universal asynchronous receiver/transmitter controller 0 (uartc) 0x4a800000 8 universal asynchronous receiver/transmitter controller 1 (uartc) 0x4b000000 8 universal asynchronous receiver/transmitter controller 2 (uartc) 0x4b800000 8 universal asynchronous receiver/transmitter controller 3 (uartc) 0x4c000000 8 irda controller (irdac) 0x4f000000 8 pll controller (pllc) 0x4f800000 8 system controller (sysc) table 12. memory mapped address on amba apb 3.0 bus (for asc8848/49/50 m1 version) start address size (mb) description 0x50000000 1 ddr-ii i/o data bus 0 impedance control block 0x50100000 1 ddr-ii i/o data bus 1 impedance control block 0x50800000 1 ddr-ii i/o command bus impedance control block 0x51000000 1 ddr-ii data bus 0 lane 0 configuration 0x51100000 1 ddr-ii data bus 0 lane 1 configuration 0x51200000 1 ddr-ii data bus 1 lane 0 configuration 0x51300000 1 ddr-ii data bus 1 lane 1 configuration 0x51800000 1 ddr-ii command bus configuration table 13. memory mapped address on amba apb 3.0 bus for asc8848/49/50 m2 version and ASC8851 start address size (mb) description 0x50000000 1m ddr-ii/iii pub configuration block free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 46 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.2 boot modes if the sd/sdhc memory card is present, the system will always boot from the memory card. if the sd card boot flow fails or the sd memory card is not present. the boot modes are decided by sys_i_boot_mode_sel [1 :0]. therefore pull- up and pull-down resistors or jumpers should be placed on the system board in order to select the desired mode. these pins must be maintained in the same states after power-on. the different boot modes are described as follows. fig 10. illustration of memory ma p in asc8848/49/50 m1 version soc 0 x00000000 0 x10000000 0xc0000000 0xc4000000 0 x40000000 boot r om / dd r- ii sdr am 0 (256 mb) d dr-i i sd ram 1 (256 mb) apb 2.0 devi ces (size: 8mb) dd r- ii sdr am mem ory c ontr oll er 0 (1 mb) apb 2. 0 d evices ( 256m b) 0xc1000000 amba ahb c ontr oll er 1 (1m b) dd r- ii sdr am mem ory c ontr oll er 1 (1 mb) 0xc5000000 i nter rupt contr oll er (1 mb) 0xc7000000 dei nterl acing engine (1mb) 0xd1000000 i mage back -end processi ng engi ne (1m b) 0xd2000000 0xd8000000 h. 264 / mpeg -4 encoder engine (1mb) m peg -4 encoder audi o engi ne (1 mb) 0xd7000000 resi ze engi ne ( 1mb) 0xd3000000 jpeg encoder engi ne (1mb) 0xdc 000000 d ata crypt o engi ne (1m b) 0xd0000000 a h b -t o - a pb br i d g e ( 1 m b) 0xc8000000 video out put cont roll er ( 1mb) 0xcc 000000 di rect mem ory access controll er (1 mb) 0xc9000000 amba ahb c ontr oll er 0 (1m b) apb 3. 0 d evices ( 256m b) 0 x50000000 pc ie devi ces (256 mb) 0 x60000000 u sb 2 . 0 h ost cont roll er (1m b) 0 x80000000 pc ie dual mode cont rol ler (1mb) 0 x84000000 mobil e sot rage c ontr oll er 0 (1mb) 0 x90000000 mobil e sot rage c ontr oll er 1 (1mb) 0 x94000000 g iga -bit ethernet m ac (1 mb) 0 x98000000 nand f l ash c ontrol ler (1mb) 0xa0000000 uart controller 3 0x4b800000 irda controller 0x4c000000 pll controller 0x4f000000 system controller 0x4f800000 agpo controller 0x49800000 uart controller 0 0x4a000000 uart controller 1 0x4a800000 uart controller 2 0x4b000000 pcie controller 0x47800000 t im e r co n t ro l le r 0x48000000 watchdog tim er 0x48800000 gpio controller 0x49000000 i 2 s controller 2 0x42800000 i 2 s controller 3 0x43000000 i 2 s controller 4 0x43800000 usb controller 0x47000000 ssi controller 0x40800000 i 2 s controller 0 0x41800000 i 2 s controller 1 0x42000000 apb 3.0 devi ces (size: 1mb) bus 0 lane 1 configuration 0x51100000 bus 1 lane 0 configuration 0x51200000 bus 1 lane 1 configuration 0x51300000 com mand bus configuration 0x51800000 da t a bu s 0 z ou t control 0x50000000 da t a bu s 1 z ou t control 0x50100000 com mand bus z out control 0x50800000 bus 0 lane 0 configuration 0x51000000 0xc2000000 amba ahb c ontr oll er 2 (1m b) video input c ontr oll er (1m b) 0xca 000000 table 14. boot modes boot_mode[1:0] descriptions 0x0 boot from serial flash through spi interface 0. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 47 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 0x1 reserved. 0x2 boot from nand flash interface 0 with 4 address cycles. 0x3 boot from nand flash interface 0 with 5 address cycles. table 14. boot modes boot_mode[1:0] descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 48 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.3 boot flow 6.3.1 sd card boot flow fig 11. sd card boot flow 001aam940 yes yes yes yes yes yes no no no no no no no yes boot by sd card initialize mshc configure sd card ocr sd card power on? sd card go to transfer state reset clk to 25 mhz read sd card blk 0 magic num 0 correct? power-on timeout? check 0x4f80034[1] = 1? boot by serial flash boot by nand flash send multiple- block-read cmd data transfer over? rx fifo data ready? read data read the residual data in rx fifo magic num 1 correct? read loader from sd card to sram jump to loader 1. reset controller 2. power on controller 3. set clk to 400 khz 4. set timeout to the max value 5. set card-type to 1 bit 6. clear raw interrupt status 1. send cmd0: go to idle 2. send cmd8: identify sdhc 3. send acmd41: config ocr 1. send cmd2: go to ident state 2. send cmd3: get sd card rca 3. send cmd7: go to transfer state free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 49 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.3.2 serial flash boot flow fig 12. serial flash boot flow 001aam941 yes yes yes no no no boot by serial flash initialize ssic read from serial flash address 0 magic num 0 correct? 1. set baud-rate devisor to 0xf 2. set transfer mode to eeprom read 3. set dfs to 8 bit 4. set transfer number of data to 4 5. enable controller jump to loader check the next 32 kb general configuration read loader from serial flash to sram magic num 1 correct? general config over? free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 50 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.3.3 nand flash boot flow 6.4 boot image boot image for boot rom code contains boot parameters, and loader code. boot parameters are read by boot rom code to check magic numbers and get loader information. magic number#0 and magic number#1 are "0x82451282" and "0x28791166" for all three boot device images. if magic numbers are both correct, loader code would be transferred to sram. wh en loader is transferred over, programming counter is set to the base address of loader in sram and starts to execute loader. fig 13. nand flash boot flow 001aam942 yes yes yes no no no yes no boot by nand flash initialize nfc read from nand flash page 0 magic num 0 correct? 1. set timing parameters 2. set pagesize to 2 kb 3. set nand flash chip address cycle by 0x4f80034[0] (5 address cycles when 0x4f80034[0] is set read one page: jump to loader check the next 64 kb general configuration read loader from nand flash to sram magic num 1 correct? yes yes sram switch to nfc fsm busy? rnb_st = 1? send pageread cmd rnb edge = 1? clear rnb edge sram switch to nfc fsm busy? general config over? no no yes free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 51 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.4.1 sd card boot image magic numbers, loader address, loader size are sd card boot parameters. they have to be placed on the first block of the sd card. magic number#0 should be written on address 0x0. magic number#1, loader address, and loader size are at address 0x4, 0x8 and 0xc respectively. 6.4.2 serial flash boot image magic numbers, loader address header (pointer of loader address value), loader size header (pointer of loader size value), and gen eral configuration header (pointer of general configuration section) are serial flash boot parameters. they should be placed on the same sector. sector that contains boot parameters is the boot parameter sector. magic number#0 should be written on the base address of boot parameter sector. magic number#1 should be written on boot parameter sector base address + 0x4. loader address header should be written on boot parameter sector base address + 0x8. general configuration header should be written on boot parameter sector base address + 0xc. loader size header should be written on boot parameter sector base address + 0x10. fig 14. sd card boot image format 001aam943 magic number#0 magic number#1 loader address loader size 0x00 0x04 0x08 0x0c boot parameters loader loader size loader address block 0 block 1 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 52 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.4.3 nand flash boot image magic numbers, loader address header (pointer of loader address value), and general configuration header (pointer of general configuration section) are nand flash boot parameters. they should be placed on th e same block. block that contains boot parameters is the boot parameter block. m agic number#0 should be written on the base address of boot parameter block. magic number#1 should be written on boot parameter block base address + 0x4. loader address header should be written on boot parameter block base address + 0x8. general configur ation header should be written on boot parameter block base address + 0xc. loader size is fixed to be 2 kb. fig 15. serial flash boot image 001aam944 magic number#0 magic number#1 loader address header general configuration header sector_nbase + 0x00 sector_nbase + 0x04 sector_nbase + 0x08 sector_nbase + 0x0c sector_nbase + 0x10 loader loader size loader address loader size header loader size header loader address header sector 0 boot parameters loader address general configuration loader size sector n sector 1 loader size header free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 53 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.5 limitations 6.5.1 sd card boot code 1. sd / sdhc cards are both compatible with this boot rom code. because command parameter register in mshc is 32 bit width, the maximum size of supported sd memory card should be 32 gb. if loader is wr itten at the address higher than 32 gb in sd memory card, it couldn't be co rrectly accessed by boot rom code. 2. sd card ocr configuration has a time-out mechanism. after 1000 times failure to check power-on, sd card boot terminates a nd serial flash boot or nand flash boot is displaced. 3. boot parameters have to be written into the first block in sd card. if the magic numbers are incorrect in the first block, sd card boot terminates and serial flash boot or nand flash boot is displaced. 4. sd card loader is transferred by block. if loader starts from block#2 and ends to block#4, block#2-block#4 are all transferred into sram. base address of loader is allowed to be unaligned to 512b (block size). though there is an offset from sram base address to loader base address, it would be skipped when the program starts to execute loader in sram. the maximum loader size is the size of sram, 4608 b (equal to 9 blocks). fig 16. nand flash boot image 001aam945 magic number#0 magic number#1 loader address header general configuration header block_nbase + 0x00 block_nbase + 0x04 block_nbase + 0x08 block_nbase + 0x0c loader loader address loader size header loader address header block 0 boot parameters loader address general configuration block n block 1 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 54 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc fig 17. read boot parameter block 001aam946 sd card sram boot parameters loader blk0 blk1 blk2 blk3 blk4 sd card sram boot parameters loader blk0 blk1 blk2 blk3 blk4 blk0 fig 18. read loader 001aam947 sd card sram boot parameters loader blk0 blk1 blk2 blk3 blk4 sd card sram boot parameters loader base address loader blk0 blk1 blk2 blk3 blk4 blk0 blk2 blk3 blk4 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 55 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 6.5.2 serial flash boot code because there are 3 address cycles sent to seri al flash, supported serial flash chip has a size limit of 16 mb. if boot parameters or loader is programmed to address higher than 16 mb in serial flash, it couldn't be correctly accessed by boot rom code. boot parameters can be programmed at any sector of serial flash which has a size smaller than 16 mb. serial flash is infinitely scanned by 32 kb until magic numbers are hit. serial flash loader has a size limit of 4068 b (size of sram). 6.5.3 nand flash boot code address of nand flash chips is defined to be a 32 bits data in this boot rom code. a relationship between nand flash address bytes and the 32 bits data is shown in figure 19 (nand flash byte address). because there are 20 bits of column address, maximum page number of nand flash chip is 1048576. therefore, the maximum size of nand flash chip is 16 gb or 32 gb according to th e page size (2 kb page size or 4 kb page size) of nand flash chips. if boot parameters or loader code is programmed at address higher than the size limit, it cannot be correctly accessed. for the row address has only 12 bits, spare area could not be accessed in 4 kb page. loader base address shouldn't be at the spare area in 4 kb page or it cannot be correctly accessed. page read operation is only executed once when transferring loader from nand flash to sram, hence nand flash loader cannot be programmed across pages and size cannot be greater than (2 k+64) bytes on 2 kb page size chips or (4 k+128) bytes on 4 kb page size chips. boot parameters can be programmed at any page of nand flash. nand flash is infinitely scanned by 64 kb until magic numbers are correct. fig 19. address codes 001aan675 address cycle i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle addr_reg[31:0] : a0-a31 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ?0? ?0? ?0? ?0? a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 ?0? ?0? ?0? ?0? row address column address free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 56 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc fig 20. nand flash boot procedure: read boot parameter page 001aam948 nand flash sram boot parameters boot parameters loader pg0 pg1 pg2 pg3 pg4 nand flash sram boot parameters loader pg0 pg1 pg2 pg3 pg4 pg2 fig 21. nand flash boot procedure: read loader 001aam949 nand flash sram boot parameters loader pg0 pg1 pg2 pg3 pg4 nand flash sram boot parameters loader pg0 pg1 pg2 pg3 pg4 pg4 loader base address free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 57 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7. system controller , resets and clocks this chapter describes the detailed func tions of asc8848/49/50/51 soc system controller. the system controlle r provides an interface to configure the system level parameters through memory map register settings. it is also used to generate some system level clocks and reset signals. in the end of this chapter, the asc8848/49/50/51 soc clock and reset schemes are also described. 7.1 features 7.1.1 clock generation the system controller generates clock signals for all ip modules used in asc8848/49/50/51 project from the internal plls and the external clock signals. it also provides gated-clock control over individual modules. 7.1.2 reset signal generation the system controller also generates rese t signals for all ip modules used in asc8848/49/50/51 project from the external reset signal. 7.1.3 i/o pad control the system controller can cont rol output pad driving capabilit y and input pad pull-up of asc8848/49/50/51 chip 7.2 memory map register 7.2.1 sysc_version (0x00000000) 7.2.2 reserved (0x00000004) 7.2.3 sysc_chip_id_0 (0x00000008) 7.2.4 sysc_chip_id_1 (0x0000000c) table 15. sysc_version name bit default r/w description major_version 31 - 24 0x08 r major version number. minor_version 23 - 16 0x01 r minor version number. build_version 15 - 08 0x00 r asc8848/49/50 m1 : build version number. 0x0c asc8848/49/50/51 m2 : build version revision 07 - 00 0x02 r revision number. table 16. chip id information register 0 name bit default r/w description chip_id_0 31 - 00 0x415a4f4d r chip id 0. table 17. chip id information register 1. name bit default r/w description chip_id_1 31 - 00 0x00005452 r chip id 1. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 58 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.5 sysc_chip_id_2 (0x00000010) 7.2.6 sysc_chip_version (0x00000014) chip version info rmation register. 7.2.7 sysc_cnt_ctrl (0x00000018) 7.2.8 sysc_cnt_low (0x0000001c) embedded 64-bit counter low 32-bit value register. 7.2.9 sysc_cnt_high (0x00000020) embedded 64-bit counter high 32-bit value register. table 18. chip id information register 1. name bit default r/w description chip_id_2 31 - 00 0x00000000 r chip id 2. table 19. chip version information register name bit default r/w description chip_version 31 - 00 0x01000000 r asc8848/49/50 m1 : chip version chip_version 31 - 00 0x01000000 r asc8848/49/50/51 m2: chip version table 20. embedded 64-bit counter control register. name bit default r/w description cnt_clear 31 - 31 n/a w write only embedded 64-bit counter clear control. 1?b0: do nothing. 1?b1: clear 64-bit embedded counter. 30 - 28 0x0 r reserved. cnt_div 27 - 00 0x0 r/w 64-bit counter clock frequency divider or precision multiplier. this value is used to determine the period per tick. period per tick in the 64-bit counter = apb clock period x (cnt_div+1) table 21. embedded 64-bit counter low 32-bit value register name bit default r/w description cnt_low 31 - 00 0x0 r low 32-bit value of the embedded 64-bit counter. table 22. embedded 64-bit counte r high 32-bit value register. name bit default r/w description cnt_high 31 - 00 0x0 r high 32-bit valu e of the embedded 64-bit counter. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 59 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.10 sysc_clk_en_ctrl_0 (0x00000024) internal module clock enable control register 0. for reserved fields, write the default value. table 23. internal module clo ck enable control register 0 name bit default r/w description ssic_clk_en 31-31 0x1 r/w ssic module clock enable control. 1?b0: disable apb clock for ssic module. 1?b1: enable apb clock for ssic module. pllc_clk_en 30 - 30 0x1 r/w pllc module clock enable control. 1?b0: disable apb clock for pllc module. 1?b1: enable apb clock for pllc module. pciec_clk_en 29 - 29 0x1 r/w pciec module clock enable control. 1?b0: disable ahb and pciec clocks for pciec module. 1?b1: enable ahb and pciec clocks for pciec module. nfc_clk_en 28 - 28 0x1 r/w nfc module clock enable control. 1?b0: disable ahb clock for nfc module. 1?b1: enable ahb clock for nfc module. mshc_1_clk_en 27 - 27 0x1 r/w mshc 1 module clock enable control. 1?b0: disable ahb and mshc clocks for mshc 1 module. 1?b1: enable ahb and mshc clocks for mshc 1 module. mshc_0_clk_en 26 - 26 0x1 r/w mshc 0 module clock enable control. 1?b0: disable ahb and mshc clocks for mshc 0 module. 1?b1: enable ahb and mshc clocks for mshc 0 module. meae_clk_en 25 - 25 0x1 r/w meae module clock enable control. 1?b0: disable ahb clock for meae module. 1?b1: enable ahb clock for meae module. jebe_clk_en 24 - 24 0x1 r/w jebe module clock enable control. 1?b0: disable ahb clock for jebe module. 1?b1: enable ahb clock for jebe module. ire_clk_en 23 - 23 0x1 r/w ire module clock enable control. 1?b0: disable ahb clock for ire module. 1?b1: enable ahb clock for ire module. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 60 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc irdac_clk_en 22 - 22 0x1 r/w irdac module clock enable control. 1?b0: disable apb clock for irdac module. 1?b1: enable apb clock for irdac module. intc_clk_en 21 - 21 0x1 r/w intc module clock enable control. 1?b0: disable ahb clock for intc module. 1?b1: enable ahb clock for intc module. ibpe_clk_en 20 - 20 0x1 r/w ibpe mo dule clock enable control. 1?b0: disable ahb clock for ibpe module. 1?b1: enable ahb clock for ibpe module. i2ssc_4_clk_en 19 - 19 0x1 r/w i2ssc 4 module clock enable control. 1?b0: disable apb and i2ssc clocks for i2ssc 4 module. 1?b1: enable apb and i2ssc clocks for i2ssc 4 module. i2ssc_3_clk_en 18 - 18 0x1 r/w i2ssc 3 module clock enable control. 1?b0: disable apb and i2ssc clocks for i2ssc 3 module. 1?b1: enable apb and i2ssc clocks for i2ssc 3 module. i2ssc_2_clk_en 17 - 17 0x1 r/w i2ssc 2 module clock enable control. 1?b0: disable apb and i2ssc clocks for i2ssc 2 module. 1?b1: enable apb and i2ssc clocks for i2ssc 2 module. i2ssc_1_clk_en 16 - 16 0x1 r/w i2ssc 1 module clock enable control. 1?b0: disable apb and i2ssc clocks for i2ssc 1 module. 1?b1: enable apb and i2ssc clocks for i2ssc 1 module. i2ssc_0_clk_en 15 - 15 0x1 r/w i2ssc 0 module clock enable control. 1?b0: disable apb and i2ssc clocks for i2ssc 0 module. 1?b1: enable apb and i2ssc clocks for i2ssc 0 module. 14 - 14 0x1 r/w reserved. h4ee_clk_en 13 - 13 0x1 r/w h4ee mo dule clock ena ble control. 1?b0: disable ahb and h4ee clocks for h4ee module. 1?b1: enable ahb and h4ee clocks for h4ee module. gpioc_clk_en 12 - 12 0x1 r/w gpioc module clock enable control. 1?b0: disable apb clock for gpioc module. 1?b1: enable apb clock for gpioc module. table 23. internal module clo ck enable control register 0 name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 61 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.11 sysc_clk_en_ctrl_1 (0x00000028) internal module clock enable control register 1. for reserved fields, write the default value. gmac_clk_en 11 - 11 0x1 r/w gmac module clock enable control. 1?b0: disable ahb and gmac clocks for gmac module. 1?b1: enable ahb and gmac clocks for gmac module. dmac_clk_en 10 - 10 0x1 r/w dmac module clock enable control. 1?b0: disable ahb clock for dmac module. 1?b1: enable ahb clock for dmac module. die_clk_en 09 - 09 0x1 r/w die module clock enable control. 1?b0: disable ahb clock for die module. 1?b1: enable ahb clock for die module. 08 - 08 0x1 r/w reserved. dce_clk_en 07 - 07 0x1 r/w dce module clock enable control. 1?b0: disable ahb clock for dce module. 1?b1: enable ahb clock for dce module. brc_clk_en 06 - 06 0x1 r/w brc module clock enable control. 1?b0: disable ahb clock for brc module. 1?b1: enable ahb clock for brc module. 05 - 05 0x1 r/w reserved. apb3c_clk_en 04 - 04 0x1 r/w apb3c m odule clock enable control. 1?b0: disable ahb clock for apb3c module. 1?b1: enable ahb clock for apb3c module. 03 - 01 0x7 r/w reserved. agpoc_clk_en 00 - 00 0x1 r/w agpoc module clock enable control. 1?b0: disable apb clock for agpoc module. 1?b1: enable apb clock for agpoc module. table 23. internal module clo ck enable control register 0 name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 62 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc table 24. internal module clo ck enable control register 1 name bit default r/w description 31 - 13 0x0 r reserved. i2ssc_rx_clk_en 12 - 12 0x1 r/w i2ssc_o_rx_mclk output enable control. 1?b0: disable clock output on i2ssc_o_rx_mclk pad. 1?b1: enable clock output on i2ssc_o_rx_mclk pad. i2ssc_tx_clk_en 11 - 11 0x1 r/w i2ssc_o_t x_mclk output enable control. 1?b0: disable clock output on i2ssc_o_tx_mclk pad. 1?b1: enable clock output on i2ssc_o_tx_mclk pad. wdtc_clk_en 10 - 10 0x1 r/w wdtc module clock enable control. 1?b0: disable apb clock for wdtc module. 1?b1: enable apb clock for wdtc module. voc_clk_en 09 - 09 0x1 r/w voc module clock enable control. 1?b0: disable ahb and voc clocks for voc module. 1?b1: enable ahb and voc clocks for voc module. vic_ clk_en 08 - 07 0x3 r/w vic module clock enable control. 2?b00: disable ahb an d vic clocks for vic module. 2?b01: enable ahb and vic device 0 clocks and disable vic device 1 clock for vic module. 2?b10: enable ahb and vic device 1 clocks and disable vic device 0 clock for vic module. 2?b11: enable ahb an d vic clocks for vic module. usbc_clk_en 06 - 06 0x1 r/w usbc module clock enable control. 1?b0: disable ahb and usbc clocks for usbc module. 1?b1: enable ahb and usbc clocks for usbc module. uartc_3_clk_en 05 - 05 0x1 r/w uartc 3 module clock enable control. 1?b0: disable apb and uartc clocks for uartc 3 module. 1?b1: enable apb and uartc clocks for uartc 3 module. uartc_2_clk_en 04 - 04 0x1 r/w uartc 2 module clock enable control. 1?b0: disable apb and uartc clocks for uartc 2 module. 1?b1: enable apb and uartc clocks for uartc 2 module. uartc_1_clk_en 03 - 03 0x1 r/w uartc 1 module clock enable control. 1?b0: disable apb and uartc clocks for uartc 1 module. 1?b1: enable apb and uartc clocks for uartc 1 module. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 63 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.12 sysc_clk_gen_cfg (0x0000002c) internal clock speed control register. uartc_0_clk_en 02 - 02 0x1 r/w uartc 0 module clock enable control. 1?b0: disable apb and uartc clocks for uartc 0 module. 1?b1: enable apb and uartc clocks for uartc 0 module. tmrc_clk_en 01 - 01 0x1 r/w tmrc module clock enable control. 1?b0: disable apb clo ck for tmrc module. 1?b1: enable apb clock for tmrc module. 00 - 00 0x1 r/w table 24. internal module clo ck enable control register 1 ?continued name bit default r/w description table 25. internal clock speed control register name bit default r/w description gmac_tx_clk_cfg 31 - 30 0x0 r/w gmac tx clock speed selection. 2?b00: 125mhz (rgmii). 2?b01: 125mhz (gmii). 2?b10: 25mhz. 2?b11: 2.5mhz. mshc_1_clk_cfg 29 - 29 0x0 r/w mshc 1 clock speed selection. 1?b0: 25mhz. 1?b1: 19.23mhz. mshc_0_clk_cfg 28 - 28 0x0 r/w mshc 0 clock speed selection. 1?b0: 25mhz (for sd/sdio). 1?b1: 19.23mhz (for mmc). vic_dev_1_clk_cfg 27 - 26 0x0 r/w vic device 1 clock speed selection. 2?b00: full speed. 2?b01: half speed. 2?b10: quarter speed. vic_dev_0_clk_cfg 25 - 24 0x0 r/w vic device 0 clock speed selection. 2?b00: full speed. 2?b01: half speed. 2?b10: quarter speed. gmac_reduced_mode _en 23-23 0x0 r asc8848/49/50 m1 - reserved asc8848/49/50/51 m2 - gmac reduced mode enable selection. it controls the output gmac tx phase. 1'b0: shift 180 degrees. 1'b1: shift 90 degrees voc_pll_ref_sel 22 - 22 0x0 r asc8848/49/50 m1 - reserved asc8848/49/50/51 m2 - voc pll reference clock selection. 1'b0: 24mhz crystal input (sys_i_osc_2_clk). 1'b1: 27mhz oscillator input (voc_i_clk) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 64 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.13 sysc_mon_clk_sel (0x00000030) monitor clock selection register. voc_clk_div 21 - 16 0x02 r/w voc pixel clock divider. voc pixel clock frequency = pll 3 clock frequency/voc_clk_div i2ssc_rx_mclk_div 15 - 08 0x10 r/w i 2 ssc rx device master clock divider. i 2 ssc rx master clock frequency = 270.336mhz/i2ssc_rx_mclk_div i2ssc_tx_mclk_div 07 - 00 0x10 r/w i 2 ssc tx device master clock divider. i 2 ssc tx master clock frequency = 270.336mhz/i2ssc_tx_mclk_div table 25. internal clock speed control register ?continued name bit default r/w description table 26. monitor clock selection register name bit default r/w description 31 - 14 0x0 r reserved. mon_clk_1_sel 13 - 08 0x15 r/w monit or clock 1 selection control. 6?h00: ahb clock. 6?h01: apb clock. 6?h02: gmac tx positive clock. 6?h03: gmac tx negative clock. 6?h04: gmac rx positive clock. 6?h05: gmac rx negative clock. 6?h06: h4ee clock. 6?h07: hostc clock. 6?h08: i2ssc 0 positive bit clock. 6?h09: i2ssc 0 negative bit clock. 6?h0a: i2ssc 1 posi tive bit clock. 6?h0b: i2ssc 1 negative bit clock. 6?h0c: i2ssc 2 posi tive bit clock. 6?h0d: i2ssc 2 negative bit clock. 6?h0e: i2ssc 3 posi tive bit clock. 6?h0f: i2ssc 3 negative bit clock. 6?h10: i2ssc 4 positive bit clock. 6?h11: i2ssc 4 negative bit clock. mon_clk_1_sel 13 - 08 0x15 r/w 6?h1a: usbc core clock. 6?h1b: usbc phy clock. 6?h1c: vic device 0 pixel clock. 6?h1d: vic device 0 divided pixel clock. 6?h1e: vic device 1 pixel clock. 6?h1f: vic device 1 divided pixel clock. 6?h20: voc pixel clock. 6?h21-6?h3f: 1?b0. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 65 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 07 - 06 0x0 r reserved. mon_clk_0_sel 05 - 00 0x12 r/w monit or clock 1 selection control. 6?h00: ahb clock. 6?h01: apb clock. 6?h02: gmac tx positive clock. 6?h03: gmac tx negative clock. 6?h04: gmac rx positive clock. 6?h05: gmac rx negative clock. 6?h06: h4ee clock. 6?h07: hostc clock. 6?h08: i2ssc 0 positive bit clock. 6?h09: i2ssc 0 negative bit clock. 6?h0a: i2ssc 1 posi tive bit clock. 6?h0b: i2ssc 1 negative bit clock. 6?h0c: i2ssc 2 posi tive bit clock. 6?h0d: i2ssc 2 negative bit clock. 6?h0e: i2ssc 3 posi tive bit clock. 6?h0f: i2ssc 3 negative bit clock. mon_clk_0_sel 05 - 00 0x12 r/w 6?h10 : i2ssc 4 positive bit clock. 6?h11: i2ssc 4 negative bit clock. 6?h12: mshc 0 positive card clock. 6?h13: mshc 0 negative card clock. 6?h14: mshc 0 rx card clock. 6?h15: mshc 1 positive card clock. 6?h16: mshc 1 negative card clock. 6?h17: mshc 1 rx card clock. 6?h18: pciec core clock. 6?h19: uartc clock. 6?h1a: usbc core clock. 6?h1b: usbc phy clock. 6?h1c: vic device 0 pixel clock. 6?h1d: vic device 0 divided pixel clock. 6?h1e: vic device 1 pixel clock. 6?h1f: vic device 1 divided pixel clock. 6?h20: voc pixel clock. 6?h21-6?h3f: 1?b0. table 26. monitor clock selection register ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 66 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.14 sysc_sys_info (0x00000034) system information register. 7.2.15 reserved (0x00000038~0x00000040) 7.2.16 sysc_pad_en_ctrl (0x00000044) pad enable control register. table 27. system information register name bit default r/w description 31 - 06 0x0 r reserved. gmac_tx_dir 05 - 05 0x0 r gmac tx clock direction information. 1?b0: internal generated clock. 1?b1: external clock source. gmac_speed_info 04 - 03 0x0 r gmac speed information. 2?b0x: 1000mbps. 2?b10: 10mbps. 2?b11: 100mbps. gmac_io_info 02 - 02 0x0 r gmac interface voltage information. 1?b0: gmii/mii interface, 3.3v. 1?b1: rgmii interface, 2.5v. boot_mode_info 01 - 00 0x0 r boot mode information. 2?b00: boot from serial flash through spi interface 0. 2?b01: reserved. 2?b10: boot from nand flash interface 0 with 4 address cycles. 2?b11: boot from nand flash interface 0 with 5 address cycles. table 28. pad enable control register name bit default r/w description 31 - 28 0x0 r reserved. wdtc_pad_en 27 0x1 r/w wdtc interface pad enable control. voc_pad_en 26 - 24 0x7 r/w voc inte rface pad enable control. bit 0: byte 0 output pad enable control. bit 1: byte 1 output pad enable control. bit 2: byte 2 output pad enable control. 23 - 21 0x0 r reserved. vic_dev_1_pad_en 20 0x1 r/w vic device 1 interface pad enable control. vic_dev_0_pad_en 19 0x1 r/w vic device 0 interface pad enable control. usbc_pad_en 18 0x1 r/w usbc interface pad enable control. uartc_3_pad_en 17 0x1 r/w uartc 3 interface pad enable control. uartc_2_pad_en 16 0x1 r/w uartc 2 interface pad enable control. uartc_1_pad_en 15 0x0 r/w uartc 1 interface pad enable control. uartc_0_pad_en 14 0x0 r/w uartc 0 interface pad enable control. ssic_pad_en 13 0x1 r/w ssic interface pad enable control. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 67 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.17 sysc_if_ctrl (0x00000048) 7.2.18 sysc_slew_ctrl (0x0000004c) output pads slew rate control register. nfc_pad_en 12 0x1 r/w nfc interface pad enable control. mshc_1_pad_en 11 0x1 r/w mshc 1 interface pad enable control. mshc_0_pad_en 10 0x1 r/w mshc 0 interface pad enable control. i2ssc_4_pad_en 09 0x1 r/w i2ssc 4 interface pad enable control. i2ssc_3_pad_en 08 0x1 r/w i2ssc 3 interface pad enable control. i2ssc_2_pad_en 07 0x1 r/w i2ssc 2 interface pad enable control. i2ssc_1_pad_en 06 0x1 r/w i2ssc 1 interface pad enable control. i2ssc_0_pad_en 05 0x1 r/w i2ssc 0 interface pad enable control. hostc_pad_en 04 0x1 r/w hostc interface pad enable control. 03 0x0 r reserved. gmac_pad_en 02 0x1 r/w gmac interface pad enable control. 01 - 00 0x0 r reserved. table 28. pad enable control register ?continued name bit default r/w description table 29. interface control register name bit default r/w description 31-04 0x1042020 r reserved vic_if_pwr_level 03-03 0x0 r/w asc8848/49/50 m1 - reserved asc8848/49/50/51 m2 - vic io pad voltage level selection. 1'b0: 2.5~3.3v. 1'b1: 1.8v. gmac_if_pwr_level 02-02 0x0 r /w asc8848/49/50 m1 -reserved asc8848/49/50/51 m2 - gmac io pad voltage level selection. 1'b0: 3.3v. 1'b1: 2.5v. gmac_tx_clk_dir 01-01 0x0 r/w asc8848/49/50 m1 - reserved asc8848/49/50/51 m2 - gmac tx clock direction selection. 1'b0: internal tx clock source (pll 1). 1'b1: external ethernet phy tx clock source 00 - 00 0x0 reserved free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 68 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.19 sysc_pull_ctrl (0x00000050) output and bidirectional pads pull up and pull down control register. table 30. output pads slew rate control register name bit default r/w description 31 - 02 0x0 r reserved. voc_slew_rate_ctrl 01 0x1 r/w voc output pads slew rate control. 1?b0: slow. 1?b1: fast. gmac_slew_rate_ctrl 00 0x1 r/w gmac output pads slew rate control. 1?b0: slow. 1?b1: fast. table 31. output and bidirectional pads pull up and pull down control register name bit default r/w description - 31 - 16 0x0 r reserved. wdtc_cmd_pup_en 15 0x1 r/w wdtc_o_nrst pad pull up enable control. uartc_3_sda_pup_en 14 0x1 r/w uartc_3_o_sda pad pull up enable control. uartc_2_sda_pup_en 13 0x1 r/w uartc_2_o_sda pad pull up enable control. uartc_1_sda_pup_en 12 0x1 r/w uartc_1_o_sda pad pull up enable control. uartc_0_sda_pup_en 11 0x1 r/w uartc_0_o_sda pad pull up enable control. ssic_sel_pup_en 10 0x1 r/w ssic_o_nsel pads pull up enable control. nfc_data_pup_en 09 0x1 r/w nfc_io_data pads pull up enable control. nfc_busy_pup_en 08 0x1 r/w nfc_i_nrb pad pull up enable control. nfc_com_pup_en 07 0x1 r/w nfc common pads pull up enable control. mshc_1_data_pup_en 06 0x1 r/w mshc_1_io_data pads pull up enable control. mshc_1_cmd_pup_en 05 0x1 r/w mshc_1_io_cmd pad pull up enable control. mshc_1_com_pup_en 04 0x1 r/w mshc 1 common pads pull up enable control. mshc_0_data_pup_en 03 0x1 r/w mshc_0_io_data pads pull up enable control. mshc_0_cmd_pup_en 02 0x1 r/w mshc_0_io_cmd pad pull up enable control. mshc_0_com_pup_en 01 0x1 r/w mshc 0 common pads pull up enable control. hostc_com_pup_pdn_en 00 0x1 r/w hostc common pads pull up and pull down enable control. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 69 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.20 sysc_drv_strength_ctrl_0 (0x00000054) output and bidirectional pads driv ing strength control register 0. 7.2.21 sysc_drv_strength_ctrl_1 (0x00000058) output and bidirectional pads driv ing strength control register 1. 7.2.22 sysc_drv_strength_ctrl_2 (0x0000005c) output and bidirectional pads driv ing strength control register 2. table 32. output and bidirectional pads driving strength control register 0 name bit default r/w description - 31 - 20 0x0 r reserved. agpoc_gpioc_drv_str 19 - 00 0x0 r /w agpoc/gpioc interface output driving strength control bit 0, which are combined with agpoc_gpioc_drv_str_1. 2'b00: 2ma 2'b01: 4ma 2'b10: 8ma 2'b11: 12ma table 33. output and bidirectional pads driving strength control register 1 name bit default r/w description - 31 - 20 0x0 r reserved. agpoc_gpioc_drv_str 19 - 00 0xfffff r/w agpoc/gpioc interface output driving strength control bit 1. table 34. output and bidirectional pads driving strength control register 2 name bit default r/w description - 31 - 28 0x0 r reserved. sysc_drv_str 27 - 26 0x0 r/w sysc interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma wdtc_drv_str 25 - 24 0x1 r/w wdtc interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma voc_drv_str 23 - 22 0x2 r/w voc inte rface output stre ngth control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma usbc_drv_str 21 - 20 0x1 r/w usbc interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 70 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc uartc_3_drv_str 19 - 18 0x2 r/w uartc 3 interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma uartc_2_drv_str 17 - 16 0x2 r/w uartc 2 interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma uartc_1_drv_str 15 - 14 0x2 r/w uartc 1 interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma uartc_0_drv_str 13 - 12 0x2 r/w uartc 0 interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma ssic_drv_str 11 - 10 0x1 r/w ssic inte rface output stre ngth control. 2?b00: 2ma. 2?b01: 4ma. 2?b10: 8ma. 2?b11: 12ma. nfc_drv_str 09 - 08 0x1 r/w nfc inte rface output st rength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma mshc_1_drv_str 07 - 06 0x2 r/w mshc 1 in terface output st rength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma mshc_0_drv_str 05 - 04 0x2 r/w mshc 0 in terface output st rength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma i2ssc_drv_str 03 - 02 0x1 r/w i2ssc interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma hsotc_drv_str 01 - 00 0x1 r/w hostc interface output strength control. 2?b00: 2ma 2?b01: 4ma 2?b10: 8ma 2?b11: 12ma table 34. output and bidirectional pads driving strength control register 2 ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 71 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.3 clock signal distributions 7.3.1 system clocks the host processor, ahb and apb clocks are g enerated by pl l 0 and the clock ratio is 6:2:1. the pll ratio is not configurable. refer to section 13.3 for the pll ratio of asc8848/49/50/51. 7.3.2 giga-bit ethernet mac for the giga-bit ethernet applications, th ere are two kinds of the transmitter clock (tx_clk), tx_clk from phy and tx_clk from mac. mmr_i_gmac_tx_clk_dir from mmr (sys_i_gmac_tx_cl k_dir for asc8848/49/50 m1 version) is used to control the tx_clk direction. mmr_i_gm ac_tx_clk_cfg[1:0] from mmr is used to select the speed mode if tx_clk is gen erated by mac. 2.5/ 25/125mhz clocks are generated from pll 1. the pll ratio is not configurable because the clock rates for 10/100/1000 are well defined. to support rgmii in asc8849/50 m2 version and ASC8851, the output tx_clk could be 90 degr ees phase shift on-chip to maximize the phy sampling window through mmr_i_gmac_reduced_mode_en." fig 22. system clock scheme 001aan237 pll 0 (64/4, 400 mhz to 48/2, 600 mhz) pll_0_clk 1/6 100/83/66 mhz (apb_o_clk_p for all amba apb devices) 1/3 200/166/133 mhz (ahb_o_clk_p for all amba ahb devices) 600 m/500/400 mhz (hostc_o_clk_p) sys_i_osc_0_clk (25 mhz) sys_o_osc_0_febclk 25 mhz sys_osc_0_clk fig 23. gigabit ethernet clock scheme (for asc8850/49/48 m1) 001aam950 01 10 0 1 11 ? 1/2 pll 1 40/4, 250 mhz pll_1_div_2_shift_clk pll_1_clk 1/100 pll_1_div_100_clk 1/10 pll_1_div_10_clk 1/2 pll_1_div_2_clk gmac_o_tx_clk (2.5 mhz, 25 mhz or 125 mhz) 2.5/25/125 mhz (gmac_o_tx_clk_n) 2.5/25/125 mhz (gmac_o_tx_clk_p) gmac_tx_clk (5 mhz, 25 mhz or 125 mhz) gmac_tx_clk_cfg [1:0] (mmr) sys_i_osc_clk (25 mhz) sys_osc_clk sys_o_osc_0_febclk 25 mhz 00 2.5/25/125 mhz (gmac_o_rx_clk_n) 2.5/25/125 mhz (gmac_o_rx_clk_p) sys_i_gmac_tx_clk_dir gmac_i_rx_clk (2.5 mhz, 25 mhz or 125 mhz) gmac_rx_clk gmac_tx_clk 01 10 11 00 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 72 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.3.3 mobile storage controller there are two clocks for the mobile storage controller. they are generated from pll 1. the 19.23 mhz clock is for mmc cards while 25 mhz clock is for sd or sdio cards. the clock rate is chose by mshc_0_clk _cfg and mshc_1_clk_cfg from mmr. 7.3.4 i 2 s and uart the 18.432 mhz system clock (sys_i_osc_ 1_clk) is directly used for i 2 s and uart. the default settings of pll 2 and a divide-by-3 divider will generate 270. 336 mhz clock i 2 s master clock is generated by dividing this clock by i2ssc_rx_mclk_div and i2ssc_tx_mclk_div. since we have five i 2 s controllers, four for rx-only and one for rx and tx, we could set different master clocks for rx-only and full-duplex i 2 s controllers respectively. to configure the pll for other settings, please refer to chapter 10. fig 24. mobile storage controller clock scheme 001aam951 1 0 1/13 pll 1 (40/4, 250 mhz) pll_1_div_13_clk pll_1_clk 1/10 pll_1_div_10_clk mshc_1_ clk_cfg (mmr) mshc_1_i_rx_cclk (17.857 mhz or 25 mhz) 19.23/25 mhz (msh c_0 _o _cclk_p) sys_i_osc_0_clk (25 mhz) sys_o_osc_0_febclk 25 mhz sys_osc_0_clk 1 0 19.23/25 mhz (msh c_0 _o _cclk_n) 1 0 19.23/25 mhz (msh c_1 _o _cclk_p) 1 0 19.23/25 mhz (msh c_1 _o _cclk_n) 19.23/25 mhz (msh c_1 _o_rx _cclk_p) mshc_0_i_rx_cclk (17.857 mhz or 25 mhz) mshc_0_rx_cclk mshc_1_rx_cclk 19.23/25 mhz (msh c_0 _o_rx _cclk_p) mshc_0_ clk_cfg (mmr) fig 25. i 2 s and uart clock scheme 001aam952 1/3 pll 2 (88/2, 811.008 mhz) pll_2_clk pll_2_div_3_clk 1/6 to 1/132 i2ssc_tx_mclk i2ssc_o_tx_mclk (2.048 mhz to 45.056 mhz) 1/6 to 1/132 i2ssc_rx_mclk i2ssc_o_rx_mclk (2.048 mhz to 45.056 mhz) 18.432 mhz (uartc_[0/1/2/3]_o_clk_p) sys_i_osc_1_clk ( 18.432 mhz) sys_o_osc_1_febclk 18.432 mhz sys_osc_1_clk free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 73 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc the relationship between the master clock and the audio sample rate is either 256 fs or 384 fs depending on the settings on the audio codec chips. 7.3.5 video output controller pll 3 is dedicated for the video display pixel clock generation. the default setting of pll 3 and the divider will generate 27mhz clock for tv applications. it could be configured up to 180mhz for lcd panel output or 148.5m hz bt.1120p (in case of asc8848/49/50 m1 version it is limited to 125 mhz). to configure the pll for other settings, please refer to chapter 10. the reference cl ock is selectable from vo c_i_clk or sys_i_osc_2_clk through mmr_i_voc_pll_src_sel (sysc_c lk_gen_cfg[22]) fo r asc8848/49/50 m2 version and ASC8851. 7.3.6 usb if usb function is required, sys_i_osc_2_clk must be fed with 24mhz clock. pll inside usb phy will generate 30 mhz clock for internal utmi bus and 480mhz clock for usb bus communication. table 35. relationship between master clock and audio sample sample rate (khz) 256 fs 384 fs master clock (mhz) mclk_div master clock (mhz) mclk_div 8 2.048 132 3.072 88 16 4.096 66 6.144 44 32 8.192 33 12.288 22 44 11.264 24 16.896 16 48 12.288 22 18.432 n/a fig 26. video output controller clock scheme 001aam953 pll 3 (72/32, 54 mhz to 61/2, 732 mhz or 60/2, 720 mhz ) pll_3_clk 1/2 to 1/48 or 1/4 voc_clk 24 mhz to 125 mhz (voc_o_clk_p) sys_i_osc_2_clk ( 24 mhz) sys_o_osc_2_febclk 24 mhz sys_osc_2_clk fig 27. usb clock scheme 001aam954 usbphy (20/16, 30 mhz) usbc_core_clk 30 mhz (usbc_o_core_clk _p) sys_i_osc_2_clk ( 24 mhz) sys_o_osc_2_febclk 24 mhz sys_osc_2_clk free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 74 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 7.3.7 video input controller there are two physical capture devices in asc8848/49/50/51 soc. each one needs two clocks, pclk and div_pclk. if the video sour ce is a multi-channel video decoder, which means video channels are time-division-mult iplexed into one video stream, div_pclk must be set to 27 mhz through vic_dev_0_clk_cfg and vic_dev_1_clk_cfg. if the video source is a single-channel video decoder or a cmos sensor, pclk and div_pclk must be the same. 7.3.8 pci express the pci express controller needs a differen tial 100 mhz clock on board fed into pciec_i_refclk_p and pciec_i_refclk_m. through the internal pll in pcie phy, 125 mhz clock is generated for the pci express controller. 7.4 reset signal generation asc8848/49/50/51 soc use low active reset signal in the input system reset signal, sys_i_nrst. figure 30 shows the reset signal genera tion in asc8848/49/50/51 soc. usually an external reset ic is used on board to generate the power-on reset for the whole system. in addition, the reset ic could also receive the external trigger to assert the system reset. if the system is no t responding within a specific period, the watchdog timer inside asc8848/49/50/5 1 soc will trigger wdtc_o_nrst (a ctive-low) and the external reset ic will reboot the whole system to make the system back to alive. fig 28. video input controller clock scheme 001aam955 1/2 vic_dev_1_div_2_clk 1/4 vic_dev_1_div_4_clk vic_dev_1_pclk 24 mhz to 180 mhz (vic_o_dev_1_div_pclk_p) 24 mhz to 180 mhz (vic_o_dev_1_pclk_p) vic_dev_1_clk_cfg [1:0] (mmr) vic_i_dev_1_pclk ( 24 mhz to 180 mhz) 00 01 10 1/2 vic_dev_0_div_2_clk 1/4 vic_dev_0_div_4_clk vic_dev_0_pclk 24 mhz to 180 mhz (vic_o_dev_0_div_pclk_p) 24 mhz to 180 mhz (vic_o_dev_0_pclk_p) vic_dev_0_clk_cfg [1:0] (mmr) vic_i_dev_0_pclk ( 24 mhz to 180 mhz) 00 01 10 fig 29. pci express clock scheme 001aam956 pciec_i_refclk_p pciec_core_clk 125 mhz pciephy (514, 125 mhz) pciec_i_refclk_m free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 75 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 8. boot rom 8.1 general description the boot rom contains the boot codes to perform the boot sequence and load the boot program from different devices, such as sd card, serial flash memory or nand flash memory. there is a sram inside the boot rom controller for the system applications. 8.2 features 8.2.1 read only memory (rom) support 2048 byte read only memory for boot codes. 8.2.2 static random access memory (sram) support 4608 byte static random access memory for the system applications. this memory is shared with the internal buffer of the nand flash controller. 8.3 memory map register 8.3.1 rom block (0x00000000~0x000007ff) 8.3.2 ram block (0x00001000~0x000021ff) 8.3.3 brc_version (0x00004000) version information register. fig 30. reset signal generation 001aam957 asc8850 reset sync watchdog timer to other modules wdtc_o_nrst reset ic sys_i_nrst table 36. version information register name bit default r/w description major_version 31 - 24 0x03 r major version number. minor_version 23 - 16 0x02 r minor version number. build_version 15 - 08 0x00 r build version number. revision 07 - 00 0x09 r revision number. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 76 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 8.3.4 brc_ctrl (0x00004004) control register. 9. ddr-ii sdram controller (for asc8848/49/50 m1 version only) 2 9.1 features there are two ddr-ii sdram controllers (ddr2sdmc) inasc8848/49/50m1 version soc. each one provides an interface be tween amba ahb bus and external ddr-ii sdram. they can receive amba ahb requests, encode them into ddr-ii sdram standard commands and then send them to external ddr-ii sdram. it also has an 8-entry write queue to fulfill zero-wait-state amba ahb write access. 9.1.1 data width supports 16-bit data width on external ddr-ii sdram interface. 9.1.2 external bank supports only 1 external bank number. 9.1.3 memory size supports 32 mb, 64 mb, 128 mb, 256 mb, 512 mb and 1 gb external memory sizes. 9.1.4 data type supports 8-bit, 16-bit, 32-bit, and 64-bit data access on amba ahb bus. 9.1.5 page number supports 8192, 16384, or 32768 page numbers. 9.1.6 bank number supports 4 or 8 internal banks. table 37. control register name bit default r/w description - 31 - 01 0x0 - reserved. data_dir 00 0x0 r/w internal sram buffer access direction. 1?b0: access through ahb (from the host processor). 1?b1: access through external sram interface (from the nand flash controller). 2. remark: for asc8848/49/50 m2 version and ASC8851 sdram controller, refer to chapter 10 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 77 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 9.1.7 burst type for data writing, the controller can support ze ro-wait-state random data write crossing at least two different pages. for data reading, an y kind of burst type is supported without any latency after the first data is ready. 9.2 memory map register all timing parameters are in dram clcock cycles. calculate them based on dram databook. 9.2.1 ddr2sdmc_version (0x00000000) version information register. 9.2.2 ddr2sdmc_ctrl (0x00000004) main control register. table 38. version information register name bit default r/w description major_version 31 - 24 0x08 r major version number. minor_version 23 - 16 0x00 r minor version number. build_version 15 - 08 0x00 r build version number. revision 07 - 00 0x02 r revision number. table 39. main control register name bit default r/w description - 31 - 10 0x0 - reserved. dynamic_odt_ctrl 09 - 09 0x1 r/w dynamic odt control. 1?b0: disable dynamic odt control. 1?b1: enable dynamic odt control. pll_test_sel 08 - 07 0x0 r/w phy pll test signal selection. 2?b00: disable phy pll test signal output. 2?b10: select phyac digital output. 2?b11: select phydatx8 digital output. phy_update_en 06 - 06 0x0 r/w phy pvt auto-update indicator. 1?b0: disable phy pvt auto-update mechanism. 1?b1: enable phy pvt auto-update mechanism. pad_ update_ctrl 05 - 04 0x0 r/w pad pvt auto-update control. 2?b00: disable all pad pvt auto-update. 2?b01: enable pad pvt auto-update mechanism in data lanes. 2?b10: enable pad pvt auto-update mechanism in command lane. 2?b11: enable all pad pvt auto-update mechanism fast_setting_en 03 - 03 0x0 r/w fast setting indicator for mode registers. 1?b0: all fields in mode registers are programmable. 1?b1: only some specific fields in mode registers are programmable. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 78 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 9.2.3 reserved (0x00000008) 9.2.4 ddr2sdmc_size_cfg (0x0000000c) size configuration register. 9.2.5 ddr2sdmc_load_mode_0_1_cfg (0x00000010) load mode register 0 and 1 configuration register. 9.2.6 ddr2sdmc_load_mode_2_3_cfg (0x00000014) load mode register 2 and 3 configuration register. pwr_on 02 - 02 0x0 r once the ddr2sdmc is enabled by setting ddr2sdmc_ctrl bit 0 to 1, the ddr2sdmc can?t issue any command until this bit is 1. 1?b0: ddr2sdmc is not ready to issue command and in the power on state. 1?b1: ddr2sdmc is ready to issue command fast_pwr_ctrl 01 - 01 0x0 r/w fast power on control. 1?b0: normal power on sequence. 1?b1: fast power on sequence, the sstl i/o calibration status will be ignored. for simulation only. en 00 - 00 0x0 r/w 0: disable ddr2sdmc. 1: enable ddr2sdmc. table 39. main control register ?continued name bit default r/w description table 40. size configuration register name bit default r/w description base_addr 31 - 24 0x0 r/w ddr-ii sdram base address (amba ahb slave address 31 to 24). 23 - 10 0x0 reserved. bank_num 09 - 08 0x0 r/w ddr-ii sdram internal bank number. 2?b01: 4 internal banks. 2?b10: 8 internal banks. row_addr_bit_width 07 - 04 0x0 r/w ddr-ii sdram row address bit width (13~15). col_addr_bit_width 03 - 00 0x0 r/w ddr-ii sdram column address bit width (9~11). table 41. load mode register 0 and 1 configuration register name bit default r/w description - 31 0x0 - reserved. ext_mode_reg_data 30 - 16 0x0 r/w ddr-ii sdram extended mode register data. - 15 0x0 - reserved. mode_reg_data 14 - 00 0x0 r/w ddr-ii sdram mode register data. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 79 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 9.2.7 ddr2sdmc_timing_cfg_0 (0x00000018) timing configuration register 0. unit: ahb cycle. 9.2.8 ddr2sdmc_timing _cfg_1 (0x0000001c) timing configuration register 1. unit: ahb cycle. 9.2.9 ddr2sdmc_timing_cfg_2 (0x00000020) timing configuration register 2. unit: ahb cycle. 9.2.10 ddr2sdmc_timing_cfg_3 (0x00000024) timing configuration register 3. unit: ahb cycle. table 42. load mode register 2 and 3 configuration register name bit default r/w description - 31 0x0 - reserved. ext_mode_reg_3_data 30 - 16 0x0 r/w ddr-ii sdram extended mode register 3 data. - 15 0x0 - reserved. ext_mode_reg_2_data 14 - 00 0x0 r/w ddr-ii sdram extended mode register 2 data. table 43. timing configuration register name bit default r/w description - 31 - 24 0x0 - reserved. t_wtr 23 - 20 0x0 r/w minimum internal write-to-read command delay. t_rtp 19 - 16 0x0 r/w minimum internal read-to-precharge command delay. t_rcd 15 - 12 0x0 r/w minimum active-to-read or write delay. t_rrd 11 - 08 0x0 r/w minimum active-to-active command at different bank interval. t_mrd 07 - 04 0x0 r/w minimum load mode command cycle time. t_rp 03 - 00 0x0 r/w minimum precharge command period. table 44. timing configuration register 1 name bit default r/w description t_rfc 31 - 24 0x0 r/w minimum refresh-to-active or refresh-to-refresh command interval. t_faw 23 - 16 0x0 r/w minimum 4-bank activate period. t_rc 15 - 08 0x0 r/w minimum active-to-active command at the same bank interval. t_ras 07 - 00 0x0 r/w minimum active-to-precharge command interval. table 45. timing configuration register 2 name bit default r/w description t_idle 31 - 16 0x0 r/w minimum clock cycles between the first nop command and the precharge command. t_ref 15 - 00 0x0 r/w maximum pe riodic refresh interval. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 80 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc table 46. timing configuration register 3 name bit default r/w description t_dllrst 31 - 20 0x0 r/w minimum clock cycles for ddr-ii sdram internal dll reset to stable t_pwron 19 - 00 0x0 r/w minimum clock cycles for ddr-ii sdram power-up. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 81 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10. ddr-ii/iii sdram controller (for asc8848/49/50 m2 version and ASC8851) 10.1 features there are two ddr-ii/iii sdram controllers (ddr32sdmc) in asc88xx soc. it provides an interface between amba ahb bus and external ddr-ii/iii sdram. it can receive amba ahb requests, encode them into ddr-ii/iii sdram standard commands, and then send them to external ddr- ii/iii sdram. it also has an 8-entry write queue to fulfill zero-wait-state amba ahb write access. 10.1.1 data width supports 16-bit data width on exte rnal ddr-ii/iii sdram interface. 10.1.2 external bank supports only 1 external bank number 10.1.3 memory size ddr-ii: supports 256 mb, 512 mb, 1 gb, 2 gb, 4 gb ddr-iii: supports 512 mb, 1 gb, 2 gb, 4 gb or 8 gb 10.1.4 data type supports 8-bit, 16-bit, 32-bit, and 64-bit data access on amba ahb bus 10.1.5 page number ddr-ii: supports 32768, 65536, 131072 or 262144 page number ddr-iii: supports 32768, 65536, 131072, 262144 or 524288 page numbers 10.1.6 bank number ddr-ii: supports 4 or 8 internal banks ddr-iii: supports 8 internal banks 10.1.7 column latency ddr-ii: supports cl=4~7 ddr-iii: supports cl=5~11 10.1.8 burst type ddr-ii: supports burst length 4 ddr-iii: supports fixed burst length 8 and on-the-fly burst 10.2 memory map register all timing parameters are in dram clo ck cycles. calculate them based on dram databook. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 82 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.1 ddr32sdmc_version (0x00000000) version information register 10.2.1.1 ddr32sdmc_ctrl (0x00000004) main control register table 47. version control register name bit default r/w description major_version 31 - 24 0x0c r major version number minor_version 23 - 16 0x00 r minor version number build_version 15 - 08 0x00 r build version number revision 07 - 00 0x03 r revision number table 48. main control register name bit default r/w description fixed_write_as_bl8 19-19 0x0 r/w fixed write operation as burst length 8 in on-the-fly mode. 1'b0: write operation is on-the-fly mode 1'b1: write operation is burst-length 8 mode fixed_read_as_bl8 18-18 0x0 r/w fixed read operation as burst length 8 in on-the-fly mode. 1'b0: read operation is on-the-fly mode 1'b1: read operation is burst-length 8 mode slave_core_sync_en 17-17 0x0 r/w slave core synchronization enable 1'b0: disable slave core synchronization 1'b1: enable slave core synchronization mci_iophy_update_ack_en 16-16 0x0 r/w mci-initiate vt update acknowledge enable control. 1'b0: ignore phy acknowledge signal 1'b1: wait phy acknowledge signal mci_iophy_update_period 15-12 0x0 r/w mci-initiate vt update period 4'b0000: 1 cycle. ? 4'b1111: 16 cycles bpss_pub_en 11-11 0x0 r/w bypass pub enable 1'b0: controller access phy through pub with dfi 1'b1: controller access phy directly ddr_mode 10-10 0x0 r/w ddr-ii/iii mode selection 1'b0: ddr-ii mode 1'b1: ddr-iii mode dynamic_odt_en 09-09 0x1 r/w dynamic odt control enable. 1'b0: disable dynamic odt control. 1'b1: enable dynamic odt control phy_pll_dto_en 08-08 0x0 r/w phy pll digital test signal output enables. 1'b0: disable phy pll digital test signal output 1'b1: enable phy pll digital test signal output 07-07 0x0 reserved free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 83 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.2 reserved (0x00000008) 10.2.3 ddr32sdmc_size_cfg (0x0000000c) size configuration register 10.2.4 ddr32sdmc_load_mode_0_1_cfg (0x00000010) load mode register 0 and 1 configuration register mci_iophy_update_en 06-06 0x0 r/w phy vt update control selection. 1'b0: phy-initiate vt update mechanism. 1'b1: mci-initiate vt update mechanism 05-04 0x0 reserved fast_setting_en 03-03 0x0 r/w fast setting for mode registers 1'b0: all fields in mode registers are programmable. 1'b1: only some specific fields in mode registers are programmable pwr_on 02-02 0x0 r power-on status bit. once the ddr32sdmc is enabled by setting ddr32sdmc_ctrl bit 0 to 1, the ddr32sdmc can't issue any command until this bit is 1. 1'b0: ddr32sdmc is not ready to issue command and in the power on state. 1'b1: ddr32sdmc is ready to issue command 01-01 0x0 reserved en 00-00 0x0 r/w ddr-ii/iii sdram controller enable 1'b0: disable ddr32sdmc. 1'b1: enable ddr32sdmc table 48. main control register name bit default r/w description table 49. size configuration register name bit default r/w description base_addr 31-24 0x0 r/w ddr-ii/iii sdram base address (amba ahb slave address 31 to 24). 23-10 0x0 reserved bank_num 09-08 0x0 r/w ddr-ii/iii sdram internal bank number. 2'b01: 4 internal banks. 2'b10: 8 internal banks row_addr_bit_width 07-04 0x0 r/w ddr-ii/iii sdram row address bit width (13 15) col_addr_bit_width 03-00 0x0 r/w ddr-ii/iii sdram column address bit width (9 11) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 84 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.5 ddr32sdmc_load_mode_2_3_cfg (0x00000014) load mode register 2 and 3 configuration register. 10.2.6 ddr32sdmc_timing_cfg_0 (0x00000018) timing configuration register 0 10.2.7 ddr32sdmc_timing_cfg_1 (0x0000001c) timing configuration register 1 table 50. load mode register 0 and 1 configuration register name bit default r/w description 31-31 0x0 reserved ext_mode_reg_data 30-16 0x0 r/w ddr-ii/iii sdram extended mode register data. 15-15 0x0 reserved mode_reg_data 14-00 0x0 r/w ddr-ii/iii sdram mode register data. table 51. load mode register 2 and 3 configuration register name bit default r/w description 31-31 0x0 reserved ext_mode_reg_3_data 30-16 0x0 r/w ddr-ii/iii sdram extended mode register data. 15-15 0x0 reserved ext_mode_reg_2_data 14-00 0x0 r/w ddr- ii/iii sdram mode register data. table 52. timing configuration register 0 name bit default r/w description t_mod 27-24 0x0 r/w minimum mrs update time. (ddr-iii only) t_wtr 23-20 0x0 r/w minimum internal write-to-read command delay. t_rtp 19-16 0x0 r/w minimum internal read-to-precharge command delay. t_rcd 15-12 0x0 r/w minimum active-to-read or write delay. t_rrd 11-08 0x0 r/w minimum active-to-active command at different bank interval. t_mrd 07-04 0x0 r/w minimum load mode command cycle time. t_rp 03-00 0x0 r/w minimum precharge command period. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 85 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.8 ddr32sdmc_timing_cfg_2 (0x00000020) timing configuration register 2 10.2.9 ddr32sdmc_timing_cfg_3 (0x00000024) timing configuration register 3 10.2.10 ddr32sdmc_zq_ctrl (0x00000028) output impedance contro l configuration register table 53. timing configuration register 1 name bit default r/w description t_rfc 31-24 0x0 r/w minimum refresh-to-active or refresh-to-refresh command interval. t_faw 23-16 0x0 r/w minimum 4-bank activate period. t_rc 15-08 0x0 r/w minimum active-to-active command at the same bank interval. t_ras 07-00 0x0 r/w minimum active-to-precharge command interval. table 54. timing configuration register 2 name bit default r/w description t_idle 31-16 0x0 r/w ddr-ii:minim um clock cycles between the first nop command and the precharge command. ddr-iii: minimum clock cycles between the first nop command and the emr2 command t_ref 15-00 0x0 r/w maximum periodic refresh interval. table 55. timing configuration register 3 name bit default r/w description t_dllrst 31-20 0x0 r/w ddr-ii: minimum clock cycles for ddr-ii sdram internal dll reset to stable ddr-iii: minimum clock cycles for ddr-iii sdram (trst2cke >> 8). t_pwron 19-00 0x0 r/w ddr-ii:mi nimum clock cycles for ddr-ii/iii sdram power-up. ddr-iii: minimum clock cycles for ddr-iii sdram reset time free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 86 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.11 ddr32sdmc_powr_down_mode_ctrl (0x0000002c) power down mode control register table 56. output impedance control configuration name bit default r/w description 31-28 0x0 reserved zqcl_interval 27-20 0x0 r/w issue zqcl command every (256*zqcl_interval) zqcs_interval 19-08 0x0 r/w i ssue zqcs command every (16*zqcs_interval) 07-05 0x0 reserved t_zq_extend_en 04-04 0x0 r/w extend tzqinit, tzqoper and tzqcs two cycles more. 1'b0: disable. 1'b1: enable 03-03 0x0 reserved zqc_force_en 02-02 0x0 r/w zqcs/zqcl command execution control. 1'b0: drop zqcl/zqcs command if there are other pending dram commands. 1'b1: always execute zqcl/zqcs command zqcl_en 01-01 0x0 r/w zqcl command enable control. 1'b0: disable 1'b1: enable zqcs_en 00-00 0x0 r/w zqcs command enable control. 1'b0: disable 1'b1: enable table 57. power down mode control register name bit default r/w description precharged_dll_of f_pd_cycle 31:24:00 0x0 r/w auto-refresh count before entry pre-charged power down mode with dll off. precharged_dll_on _pd_cycle 23:16 0x0 r/w auto-refresh count before entry pre-charged power down mode with dll on. active_pd_cycle 15-08 0x0 r/w cycle count before entry active power down mode. 07-03 0x0 reserved precharged_dll_of f_pd_en 02-02 0x0 r/w pre-charged power down mode with dll off enable. 1'b0: disable 1'b1: enable precharged_dll_on _pd_en 01-01 0x0 r/w pre-charged power down mode with dll on enable 1'b0: disable 1'b1: enable active_pd_en 00-00 0x0 r/w active power down enable 1'b0: disable. 1'b1: enable free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 87 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.12 ddr32sdmc_self_refresh_mode_ctrl (0x00000030) self refresh mode control configuration register 10.2.13 7.2.4.ddr32sdmc_powr_down _and_self_refresh_mode_timing (0x00000034) power down and self refresh mode timing register 10.2.14 ddr32sdmc_io_dynamic_ctrl (0x00000038) io dynamic control register table 58. generic table (5col) name bit default r/w description dll_off_srf_cycle 31:24 0x0 r/w au to-refresh count before entry self refresh mode with dll off. dll_on_srf_cycle 23:16 0x0 r/w au to-refresh count before entry self refresh mode with dll on. 15-03 0x0 reserved dll_off_srf_en 13-03 0x0 r/w self refresh mode with dll off enable. dll_on_srf_en 01-01 0x0 r/w self refresh mode with dll on enable. 00-00 0x0 reserved table 59. power down and self refresh mode timing register name bit default r/w description 31-29 0x0 reserved t_xpdll 28-24 0x0 r/w exit pre-charge power down with dll frozen to commands requiring a locked dll. t_dllk_extend 23-23 0x0 r/w extend tdllk and txsdll two cycles more 1'b0: disable. 1'b1: enable t_xp 22-20 0x0 r/w exit power down with dll on to any valid command; exit per-charge power down with dll frozen to commands not requiring a locked dll. t_pd 18-16 0x0 r/w power down entry to exit timing. t_xs 15:08 0x0 r/w exit self refresh to commands not requiring a locked dll. 07-07 0x0 reserved t_cksrex 06-04 0x0 r/w valid clock requirement after self refresh entry (sre) or power down entry (pde) valid clock requirement before self refresh exit (srx) or power down exit (pdx) or reset exit t_ckesr 02-00 0x0 r/w minimum cke low width for self refresh entry to exit timing. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 88 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.15 ddr32sdmc_io_bit_enable (0x0000003c) io bit enable register table 60. io dynamic control register name bit default r/w description 31-09 0x0 reserved dynamic_dq_dqs_rcv_en 08-08 0x0 r/w dm[3:0], dq[15:0] and dqs[ 3:0] io receiving dynamic power down control 1'b0: disable 1'b1: enable dynamic_dm_dq_dqs_drv_en 07-07 0x0 r/w dm[3: 0], dq[15:0] and dq s[3:0] io driving dynamic power down control 1'b0: disable. 1'b1: enable dynamic_addr_drv_en 06-06 0x0 r/w addr[15:0] io driving dynamic power down control 1'b0: disable. 1'b1: enable dynamic_cmd_drv_en 05-05 0x0 r/w nras, ncas, nwe and ba[2:0] io driving dynamic power down control 1'b0: disable. 1'b1: enable dynamic_clk_drv_en 04-04 0x0 r/w clk io driving dynamic power down control 1'b0: disable. 1'b1: enable nop_ac_oe_disable 0 3-03 0x0 r/w ac output di sable control in nop 1'b0: disable. 1'b1: enable dynamic_addr_oe_en 02-02 0x0 r/w addr[15:0] io output enable dynamic control. dynamic_cmd_oe_en 01-01 0x0 r/w nras, ncas, nwe and ba[2:0] io output enable dynamic control 1'b0: disable. 1'b1: enable dynamic_clk_oe_en 00-00 0x0 r/w clk io output enable dynamic control. table 61. io bit enable register name bit default r/w description 31-19 0x0 reserved cke_bit_en 18-18 0x1 r/w cke output enable control 1'b0: disable 1'b1: enable free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 89 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 10.2.16 ddr32sdmc_dfi_ctrl (0x00000040) dfi control register 10.2.17 ddr32sdmc_load_mode_ctrl (0x00000044) load mode control register odt_bit_en 17-17 0x1 r/w odt output enable control 1'b0: disable 1'b1: enable cs_n_bit_en 16-16 0x1 r/w ncs output enable control 1'b0: disable 1'b1: enable addr_bit_en 15-00 0xffff r/w addr[ 15:0] output enable control 1'b0: disable 1'b1: enable table 61. io bit enable register name bit default r/w description table 62. dfi control register name bit default r/w description 31-12 0x0 reserved dfi_lp_wakeup 11-08 0x0 r/w dfi low power wake up time. (please check pub databook for details) 07-07 0x0 reserved dfi_lp_ack 06-06 0x0 r dfi low power acknowledge. dfi_lp_req 05-05 0x0 r/w dfi low power request. dfi_init_complete 04-04 0x0 r dfi initialization complete. dfi_dram_clk_disable 03-03 0x0 r /w dfi disable dram clock. dfi_data_halfwordlan e_disable 02-01 0x0 r/w dfi data half word l ane disable. dfi_init_start 00-00 0x0 r/w dfi initialization start. table 63. load mode control register name bit default r/w description 31-06 0x0 reserved lode_mode_idx 05-04 0x0 r/w lmr command id. 2'b00: mr0 2'b01: mr1 2'b10: mr2 2'b11: mr3 03-01 0x0 reserved load_mode_op_en 00-00 0x0 r/w launch lmr command. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 90 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 11. interrupt controller 11.1 general description asc8848/49/50/51 soc interrupt controller supports 64 interrupt sources but only 44 of them are connected internally. it provides one output to the host processor. the interrupt sources could be configured as edge-triggered or level-triggered with positive polarity. 11.2 features 11.2.1 interrupt number supports 44 independent interrupt signals. 11.2.2 interrupt source provides both edge and level-triggered interrupt sources with positive polarity. 11.2.3 interrupt map the interrupt controller will inte rrupt host processo r whenever one of the 44 in terrupt sources is asserted. th e host processor will read the stat us of the interr upt controller and decide which interrupt source is to be serviced first. this procedure will not stop until all interrupts are serviced. refer to ta b l e 6 4 for the interrupt number assignment. table 64. interrupt number assignment number source type descriptions 0 tmrc 0 edge timer 0 1 apbc level apb dma controller 2 vic level video input controller 3 voc level video output controller 4 dmac level dma controller 5 gmac level giga-bit ethernet mac 6 mshc 0 level mobile storage controller 0 7 mshc 1 level mobile storage controller 1 8 usbc level usb 2.0 otg controller 9 pcie_lvl level pcie controller level interrupt 10 nfc level nand flash controller 11 dce level data crypto engine 12 h4ee level h.264 encoder engine 13 jebe level jpeg encoder engine 14 ibpe level image back-end processing engine 15 die level deinterlacing engine 16 ire level resize engine 17 meae level mpeg-4 audio engine 18 ssic level synchronous serial interface 19 i2ssc 0 level i2s slave controller 0 20 i2ssc 1 level i2s slave controller 1 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 91 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 11.3 memory map register 11.3.1 intc_version (0x00000000) version information register. 21 i2ssc 2 level i2s slave controller 2 22 i2ssc 3 level i2s slave controller 3 23 i2ssc 4 level i2s slave controller 4 24 wdtc edge watchdog 25 uartc 0 level uart device 0 26 uartc 1 level uart device 1 27 uartc 2 level uart device 2 28 uartc 3 level uart device 3 29 agpoc level advanced general purpose output 30 gpioc level general purpose i/o 31 irdac level irda controller 32 tmrc 1 edge timer 1 33 tmrc 2 edge timer 2 34 tmrc 3 edge timer 3 35 pcie_edge edge pcie controller edge interrupt 36 pcie msi 7 edge pcie msi 7 interrupt for asc8848/49/50 m1 version vic dev 0 edge vic device 0 vsync signal for asc8848/49/50 m2 version and ASC8851 37 pcie msi 6 edge pcie msi 6 interrupt for asc8848/49/50 m1 version vic dev 1 edge vic device 1 vsync signal for asc8848/49/50 m2 version and ASC8851 38 pcie msi 5 edge pcie msi 5 interrupt for asc8848/49/50 m1 version - - reserved for asc8848/49/50 m2 version and ASC8851 39 pcie msi 4 edge pcie msi 4 interrupt for asc8848/49/50 m1 version - - reserved for asc8848/49/50 m2 version and ASC8851 40 pcie dev 4 edge pcie device 4 msi 41 pcie dev 5 edge pcie device 5 msi 42 pcie dev 6 edge pcie device 6 msi 43 pcie dev 7 edge pcie device 7 msi table 64. interrupt number assignment ?continued number source type descriptions free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 92 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 11.3.2 intc_src_lo (0x00000004) low 32-bit irq source register. 11.3.3 intc_src_hi (0x00000008) high 32-bit irq source register. 11.3.4 intc_stat_lo (0x0000000c) low 32-bit masked ir q source register. 11.3.5 intc_stat_hi (0x00000010) high 32-bit masked ir q source register. 11.3.6 intc_mask_lo (0x00000014) low 32-bit mask register. 11.3.7 intc_mask_hi (0x00000018) high 32-bit mask register. table 65. version information register name bit default r/w description major_version 31 - 24 0x01 r major version number. minor_version 23 - 16 0x01 r minor version number. build_version 15 - 08 0x00 r build version number. revision 07 - 00 0x00 r revision number. table 66. low 32-bit irq source register name bit default r/w description src_lo 31 - 00 0x0 r irq source bit 0~31. table 67. high 32-bit irq source register name bit default r/w description src_hi 31 - 00 0x0 r irq source bit 32~63. table 68. low 32-bit masked irq source register name bit default r/w description stat_lo 31 - 00 0x0 r irq masked source bit 0~31. table 69. high 32-bit masked irq source register name bit default r/w description stat_hi 31 - 00 0x0 r irq masked source bit 32~63. table 70. low 32-bit mask register name bit default r/w description mask_lo 31 - 00 0x0 r/w mask control bit 0~31. 1?b0: irq masked. 1?b1: irq enabled. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 93 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 11.3.8 intc_clear_lo (0x0000001c) low 32-bit status clear register. 11.3.9 intc_clear_hi (0x00000020) high 32-bit status clear register. 11.3.10 intc_trigger_mode_lo (0x00000024) low 32-bit irq trigger mode register. 11.3.11 intc_trigger_mode_hi (0x00000028) high 32-bit irq trigger mode register. 11.3.12 intc_set_lo (0x0000002c) low 32-bit irq software set register. table 71. high 32-bit mask register name bit default r/w description mask_hi 31 - 00 0x0 r/w mask control bit 32~63. 1?b0: irq masked. 1?b1: irq enabled. table 72. low 32-bit status clear register name bit default r/w description clear_lo 31 - 00 0x0 w status clear control bit 0~31. this register is self cleared. 1?b0: do nothing. 1?b1: clear irq. table 73. high 32-bit status clear register name bit default r/w description clear_hi 31 - 00 0x0 w status clear control bit 32~63. this register is self cleared. 1?b0: do nothing. 1?b1: clear irq. table 74. low 32-bit irq trigger mode register name bit default r/w description trigger_mode_lo 31 - 00 0x0 r/w trigger mode control bit 0~31. 1?b0: level triggered. 1?b1: edge triggered. table 75. high 32-bit irq trigger mode register name bit default r/w description trigger_mode_hi 31 - 00 0x0 r/w trigger mode control bit 32~63. 1?b0: level triggered. 1?b1: edge triggered. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 94 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 11.3.13 intc_set_hi (0x00000030) high 32-bit irq software set register. 12. timer controller 12.1 general description asc8848/49/50/51 soc provides four independent se ts of 32-bit timers. apb clock is used to clock each timer. each timer could be configured to increment or decrement its value at each clock rising edge. there is one match register for each timer. when the value of the timer is equal to the match regi ster, an interrupt is asserted. auto-reload register is incorporated to generate regular ticks for software scheduling. 12.2 features 12.2.1 interrupt mode each timer has a match register. when the value of match register is equal to the timer, the interrupt is triggered immediately. furthermore, the interrupt can be asserted wh en the timer is overflowed or underflowed. users can disable the interrupt by tm(0~3 )_of_en and tm(0~3)_match_en bits in timer control resister. 12.2.2 counting direction each timer can increment or decrement its value. users can customize the counting direction of each timer by tm(0~3)_cnt_dir bit in the control register. 12.2.3 auto-reload value no matter tm(0~3)_of_en bit in the timer control register is enabled or disabled, tm(0~3)_load value will be auto matically loaded in to the counter re gister when the counter overflows or underflows. users c an use tm(0~3)_load to set the period between two counter overflows. table 76. low 32-bit irq software set register name bit default r/w description trigger_mode_lo 31 - 00 0x0 w software set control bit 0~31. this register is self cleared. 1?b0: do nothing. 1?b1: set irq. table 77. high 32-bit irq software set register name bit default r/w description trigger_mode_hi 31 - 00 0x0 w software set control bit 32~63. this register is self cleared. 1?b0: do nothing. 1?b1: set irq. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 95 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 12.2.4 memory map register 12.2.4.1 tmrc_version (0x00000000) version information register. 12.2.4.2 tmrc_ctrl (0x00000004) control register of four independent timers. table 78. version information register name bit default r/w description major_version 31 - 24 0x03 r major version number. minor_version 23 - 16 0x00 r minor version number. build_version 15 - 08 0x00 r build version number. revision 07 - 00 0x03 r revision number. table 79. control register of four independent timers name bit default r/w description -31 - 16--reserved tm3_ cnt_dir 15 0x0 r/w timer3 counting direction 0: incrementing 1: decrementing tm3_match_en 14 0x0 r/w timer3 match interrupt enable bit 0: disable 1: enable tm3_of_en 13 0x0 r/w timer3 overflow/underflow interrupt enable bit 0: disable 1: enable tm3_en 12 0x0 r/w timer3 enable bit 0: disable 1:enable tm2_ cnt_dir 11 0x0 r/w timer2 counting direction 0: incrementing 1: decrementing tm2_match_en 10 0x0 r/w timer2 match interrupt enable bit 0: disable 1: enable tm2_of_en 09 0x0 r/w timer2 overflow/underflow interrupt enable bit 0: disable 1: enable tm2_en 08 0x0 r/w timer2 enable bit 0: disable 1:enable free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 96 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 12.2.4.3 reserved (0x00000008) 12.2.4.4 tmrc_timer0_counter (0x0000000c) timer0 counter register. 12.2.4.5 tmrc_timer0_auto_reload_value (0x00000010) timer0 auto-reload register. 12.2.4.6 tmrc_timer0_match_value (0x00000014) timer0 match value register. tm1_ cnt_dir 07 0x0 r/w timer1 counting direction 0: incrementing 1: decrementing tm1_match_en 06 0x0 r/w timer1 match interrupt enable bit 0: disable 1: enable tm1_of_en 05 0x0 r/w timer1 overflow/underflow interrupt enable bit 0: disable 1: enable tm1_en 04 0x0 r/w timer1 enable bit 0: disable 1:enable tm0_ cnt_dir 03 0x0 r/w timer0 counting direction 0: incrementing 1: decrementing tm0_match_en 02 0x0 r/w timer0 match interrupt enable bit 0: disable 1: enable tm0_of_en 01 0x0 r/w timer0 overflow/underflow interrupt enable bit 0: disable 1: enable tm0_en 00 0x0 r/w timer0 enable bit 0: disable 1:enable table 79. control register of four independent timers ?continued name bit default r/w description table 80. timer0 counter register name bit default r/w description tm0_cnt 31 - 00 0x0 r/w timer0 counter. the r/w status is as follows. tm0_en=1?b0: r/w tm0_en=1?b1: ro table 81. timer0 auto-reload register name bit default r/w description tm0_load 31 - 00 0x0 r/w timer0 auto reload value free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 97 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 12.2.4.7 tmrc_timer1_counter (0x00000018) timer1 counter register. 12.2.4.8 tmrc_timer1_auto_reload_value (0x0000001c) timer1 auto-reload register. 12.2.4.9 tmrc_timer1_match_value (0x00000020) timer1 match value register. 12.2.4.10 tmrc_timer2_counter (0x00000024) timer2 counter register. 12.2.4.11 tmrc_timer2_auto_reload_value (0x00000028) timer2 auto-reload register. 12.2.4.12 tmrc_timer2_match_value (0x0000002c) timer2 match value register. table 82. timer0 match value register name bit default r/w description tm0_match_val 31 - 00 0x0 r/w timer0 match value table 83. timer1 counter register name bit default r/w description tm1_cnt 31 - 00 0x0 r/w timer1 counter. the r/w status is as follows. tm1_en=1?b0: r/w tm1_en=1?b1: ro table 84. timer1 auto-reload register name bit default r/w description tm1_load 31 - 00 0x0 r/w timer1 auto reload value table 85. timer1 match value register name bit default r/w description tm1_match_val 31 - 00 0x0 r/w timer1 match value table 86. timer2 counter register name bit default r/w description tm2_cnt 31 - 00 0x0 r/w timer2 counter. the r/w status is as follows. tm2_en=1?b0: r/w tm2_en=1?b1: ro table 87. timer2 auto-reload register name bit default r/w description tm2_load 31 - 00 0x0 r/w timer2 auto reload value free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 98 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 12.2.4.13 tmrc_timer3_counter (0x00000030) timer3 counter register. 12.2.4.14 tmrc_timer3_auto_reload_value (0x00000034) timer3 auto-reload register. 12.2.4.15 tmrc_timer3_match_value (0x00000038) timer3 match value register. table 88. timer2 match value register name bit default r/w description tm2_match_val 31 - 00 0x0 r/w timer2 match value table 89. timer3 counter register name bit default r/w description tm3_cnt 31 - 00 0x0 r/w timer3 counter. the r/w status is as follows. tm3_en=1?b0: r/w tm3_en=1?b1: ro table 90. timer3 auto-reload register name bit default r/w description tm3_load 31 - 00 0x0 r/w timer3 auto reload value table 91. timer3 match value registers name bit default r/w description tm3_match_val 31 - 00 0x0 r/w timer3 match value free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 99 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 13. phase lock loop controller 13.1 general description asc8848/49/50/51 soc provides four plls to generate all clocks. pll. pll 0 is for system use including ahb/apb/dra m clocks; pll 1 is for giga -bit ethernet mac; pll 2 is for i 2 s master clock generation; pll 3 is for the video display pixel clock generation. only pll 2 and pll 3 could be configured depending on the desired sample rate and the output resolution. 13.2 features the asc8848/49/50/51 supports: ? four plls, which are built-in for various applications ? two plls, which are programmable through the register settings 13.3 memory map register 13.3.1 pllc_version (0x00000000) version information register. 13.3.2 pllc_ctrl_0 (0x00000004) control register 0. do not disable this pll. table 92. version information register name bit default r/w description major_version 31 - 24 0x03 r major version number. minor_version 23 - 16 0x00 r minor version number. build_version 15 - 08 0x00 r build version number. revision 07 - 00 0x04 r revision number. table 93. control register 0 name bit default r/w description - 31 - 03 0x0 - reserved. pll_lock 02 0x0 r pll lock indicator. pll_clk_en 01 0x1 r/w pll function clock output enable. 1'b0: disable 1'b1: enable pll_pwr_on 00 0x1 r/w pll power on control. 1'b0: pll power down 1'b1: pll power on free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 100 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 13.3.3 pllc_ratio_0 (0x00000008) ratio register 0. this register value depends on different models. 13.3.4 pllc_ctrl_1(0x0000000c) control register 1. table 94. ratio register 0 name bit default r/w description - - 31 - 27 0x0 - reserved. filter_range 26 - 24 0x2 r this sets the pll loop filter to work with the post-reference divider frequency. choose the highest valid range for best jitter performance. 3'b000: reserved. 3'b001: 10 mhz to 16 mhz 3'b010: 16 mhz to 26 mhz 3'b011: 26 mhz to 42 mhz 3'b100: 42 mhz to 65 mhz 3'b101: 65 mhz to 104 mhz 3'b110: 104 mhz to 166 mhz 3'b111: 166 mhz to 200 mhz 23 - 19 0x0 reserved. div_out ASC8851 asc8850 asc8849 asc8848 18 - 16 0x1 0x1 0x2 0x2 r r r output divider value 15 - 14 0x0 reserved. div_ref 13 - 08 0x0 r reference divider value div_fb ASC8851 asc8850 asc8849 asc8848 07 - 00 0x2f 0x2f 0x47 0x3f r r feedback divider value table 95. control register 1 name bit default r/w description - 31 - 03 0x0 - reserved. pll_lock 02 0x0 r pll lock indicator. pll_clk_en 01 0x1 r/w pll function clock output enable. 1'b0: disable 1'b1: enable pll_pwr_on 00 0x1 r/w pll power on control. 1'b0: pll power down 1'b1: pll power on free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 101 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 13.3.5 pllc_ratio_1 (0x00000010) ratio register 1. 13.3.6 pllc_ctrl_2 (0x00000014) control register 2. table 96. ratio register 1 name bit default r/w description - 31 - 27 0x0 - reserved. filter_range 26 - 24 0x2 r this sets the pll loop filter to work with the post-reference divider frequency. choose the highest valid range for best jitter performance. 3'b000: reserved. 3'b001: 10 to 16mhz 3'b010: 16 to 26mhz 3'b011: 26 to 42mhz 3'b100: 42 to 65mhz 3'b101: 65 to 104mhz 3'b110: 104 to 166mhz 3'b111: 166 to 200mhz - 23 - 19 0x0 - reserved. div_out 18 - 16 0x1 r output divider value. - 15 - 14 0x0 - reserved. div_ref 13 - 08 0x0 r reference divider value. div_fb 07 - 00 0x27 r feedback divider value. table 97. control-register 2 name bit default r/w description - 31 - 04 0x0 - reserved. pll_adjust_en 03 0x0 r/w pll adjustment control. 1'b0: disable 1'b1: enable pll_lock 02 0x0 r pll lock indicator. pll_clk_en 01 0x1 r/w pll functi on clock output enable. 1'b0: disable 1'b1: enable pll_pwr_on 00 0x1 r/w pll power on control. 1'b0: pll power down 1'b1: pll power on free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 102 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 13.3.7 pllc_ratio_2 (0x00000018) ratio register 2. 13.3.8 pllc_ctrl_3 (0x0000001c) control register 3. table 98. ratio register 2 name bit default r/w description 31 - 27 0x0 reserved. filter_range 26 - 24 0x2 r/w this sets the pll loop filter to work with the post-reference divider frequency. choose the highest valid range for best jitter performance. 3'b000: reserved. 3'b001: 10 to 16mhz 3'b010: 16 to 26mhz 3'b011: 26 to 42mhz 3'b100: 42 to 65mhz 3'b101: 65 to 104mhz 3'b110: 104 to 166mhz 3'b111: 166 to 200mhz 23 - 19 0x0 reserved. div_out 18 - 16 0x1 r/w output divider value. 15 - 14 0x0 reserved. div_ref 13 - 08 0x0 r/w reference divider value. div_fb 07 - 00 0x57 r/w feedback divider value. table 99. control register 3 name bit default r/w description 31 - 04 0x0 reserved. pll_adjust_en 03 0x0 r/w pll adjustment control. 1'b0: disable 1'b1: enable pll_lock 02 0x0 r pll lock indicator. pll_clk_en 01 0x1 r/w pll function clock output enable. 1'b0: disable 1'b1: enable pll_pwr_on 00 0x1 r/w pll power on control. 1'b0: pll power down 1'b1: pll power on free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 103 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 13.3.9 pllc_ratio_3 (0x00000020) ratio register 3. 13.4 block diagram figure 31 shows the block diagram of the pll. m is (div_fb+1); n is (div_ref+1); div is 2 div_out . the formula is: pllout freq = f refq x m/n x 1/div. the operation limits of the pll are listed below. div_out, div_ref, div_fb, and filter_range must be within the operation limits. table 100. ratio register 3 name bit default r/w description - 31 - 27 0x0 - reserved. filter_range 26 - 24 0x2 r/w this sets the pll loop filter to work with th e post-reference divider frequency. choose the highest valid range for best jitter performance. 3'b000: reserved. 3'b001: 10 mhz to 16 mhz 3'b010: 16 mhz to 26 mhz 3'b011: 26 mhz to 42 mhz 3'b100: 42 mhz to 65 mhz 3'b101: 65 mhz to 104 mhz 3'b110: 104 mhz to 166 mhz 3'b111: 166 mhz to 200 mhz - 23 - 19 0x0 - reserved. div_out 18 - 16 0x5 r/w output divider value. - 15 - 14 0x0 - reserved. div_ref 13 - 08 0x0 r/w reference divider value. div_fb 07 - 00 0x47 r/w feedback divider value. fig 31. the block diagram of pll 001aam958 pll lock 1 / div pwr_on pllout vco pfd 1 / n ref pwr_on 1 / m table 101. operation limits of pll symbol description conditions min. type. max. units f i(ref) input reference frequency - 10 - 800 mhz f ref(pd) reference frequency. post-divide 10 - 200 mhz 1 output frequency for divided outputs. 10 - 1000 mhz f ref(vco ) vco reference frequency. - 1000 - 2000 mhz o output duty cycle for divided outputs. 45 - 55 % e ?( stat) static phase error. - ? 50 +/-25 50 ps ltj maximum long term jitter for post-divide reference period. +/-1 % - - ccj maximum cycle-to-cycle jitter for the output period. +/-1 % - - free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 104 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 13.5 programming to change the pll 2/3 output frequency, perform the following steps: 1. set pwr_on and pll_clk_en to 1?b0 and pll_adjust_en to 1?b1. 2. change div_out, div_ref, div_fb, an d filter_range corresponding to the desired frequency. 3. set pwr_on to 1?b1 and pll_adjust_en to 1?b0. 4. wait until pll_lock to become 1?b1 and then set pll_clk_en to 1?b1. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 105 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14. video input controller 14.1 features 14.1.1 input formats ? support 1-channel 16-bit ycbcr 4:2:2 format with separate or embedded sync signals. ? support 1-channel bayer pattern (bayer rgb or cmyg) raw data format up to 16-bit. ? support 2-channel standard ccir-656 8-bit ycbcr 4:2:2 progressive or interlace format. ? support 2-channel 8-bit ycbcr 4:2:2 format with separate sync signals. ? support 2-channel 2-to-1 time-multiplexed cc ir-656 8-bit ycbcr 4:2:2 progressive or interlace format. ? support 2-channel 4-to-1 time-multiplexed cc ir-656 8-bit ycbcr 4:2:2 progressive or interlace format. ? capture up to 8-channel video data simultaneously. 14.1.2 image cropping specify the region of interest to be captured. four parameters are required, the starting coordinate and the width and height of the cropped image. 14.1.3 image adjustment support saturation, brightness and cont rast adjustment. the advanced contrast enhancement that can improve the image quality in high co ntrast environment. 14.1.4 photometric lens distortion correction photometric lens distortion correction can calibrate the photometric distortion which causes the dark corners. 14.1.5 image front-end processing support cfa, 3a statistics, colo r correction, gamma correction. 14.1.6 wide dynamic range (wdr) support tone mapping that can provide wide dynamic range image quality. 14.1.7 output modes ? mirror (reverse the horizontal order) ? flip (reverse the vertical order) ? field mode (save two fields in an inte rleaved frame or two separate fields) 14.1.8 output formats support ycbcr 4:2:2 and ycbcr 4:2:0 formats. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 106 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.1.9 horizontal blanking interval the horizontal blanking interval should be at least 2.5us. 14.2 memory map register the memory mapped registers of vic can be accessed via amba ahb slave interface. note that registers with * are only updated at each frame end, the others are updated at once. the hierarchy of the register map is as follows. for those registers without n, m postfix, they are global registers or dedicated for the bayer format. vic could be configured as one 16-bit device or two 8-bit devices. when configured as one 16-bit device, it could accept the bayer format up to 16-bit data, bt.1120 and 16-bit ycbcr 4:2:2 with separate sync signals. a lways use channel 0 for the 16-bit device. when configured as two 8-bit devices, th e supported formats and channels for each device are listed in table 102 . the two 8-bit devices should have the same input format, like bt.656 or time-multiplexed bt.656 or 8-bit ycbcr 4:2:2 with separate sync signals. be careful not to let af/ae windows exceed the input frame/field. [1] 1. a 27 mhz 1-channel bt.656 or an 8 b video stream w/ sync signals. 2. always use channel 0 with or without chid. [2] 1. 54mhz 2-channel time-multiplexed bt.656. 2. w/ chid: always use chid 0 and 2 for two video streams. 3. w/ chid: channels are dispatched according to chid [3] 1. 108mhz 4-channel time-multiplexed bt.656. 2. w/o chid: dispatch video streams to channel 0,1,2,3 depending on the order of the sync codes of the individual channel in the video stream detected. 3. w/ chid: channels are dispatched according to chid. fig 32. the hierarchy of the register map table 102. configuration for a 8-bit device edge type channel number pclk (mhz) div_pclk (mhz) support channel mmr table notes w/o chid w/ chid single edge 1 24 - 180 24 - 180 yes 0 0 [1] 2 54 27 partial n/a 0,2 [2] 4 108 27 yes 0,1,2,3 chid [3] double edge 1 n/a n/a n/a n/a n/a n/a 22727 yes0,20,2 [4] 45427 non/an/a [5] 001aam959 device 0 (16-bit) or vic channel 0 device 0 (8-bit) vic channel 0 channel 1 channel 2 channel 3 device 0 (8-bit) channel 0 channel 1 channel 2 channel 3 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 107 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [4] 1. 27 mhz 2-channel time-multiplexed bt.656. 2. w/o chid: ch0 is the video stream at the ri sing edge; ch1 is the video stream at the falling. 3. w/ chid: always use chid 0 and 2 for two video streams. 4. w/ chid: channels are dispatched according to chid [5] 1. 54 mhz 4-channel time-multiplexed bt.656. 14.2.1 vic_version (0x00000000) version information register. 14.2.2 vic_ctrl (0x00000004) the global control register. table 103. version information register name bit default r/w description major_version 31 - 24 0x08 r major version number. minor_version 23 - 16 0x00 r minor version number. build_version 15 - 08 0x00 r build version number. revision 07 - 00 0x0d r revision number. table 104. global control register name bit default r/w description clear 31 0x0 r/w write 1?b1 to clear maximum request-to-grant interval. hardware will automatically clear this bit. clock_rate 30 - 08 0x0 r/w number of ahb cycles for one tick. - 07 - 06 0x0 - reserved. header_ref 05 0x0 r/w sync code detection scheme for bt.1120 mode 1?b0: the chroma channel uses the sync codes in itself. 1?b1: the chroma channel uses the sync codes from the luma channel. in_format* 04 - 02 0x0 r/w input formats. 3?b000: 8-bits input data with separate sync signals. 3?b001: 16-bits input data separate sync signals. 3?b010: 8-bit input data with sync codes (bt.656 input) 3?b011: 16-bit input data with sync codes (bt. 1120 input) 3?b100: bayer data input. - 01 0x0 - reserved. vic_en 00 0x0 r/w vic enable control. 1?b0: disable the vic module. 1?b1: enable the vic module. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 108 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.3 vic_ctrl_device_n (0x00000008+n*4) control register for device n (n=0,1). 14.2.4 vic_ctrl_ channel_n_m (0x00000010+(n*4+m)*4) video input controller control register for channel_n_m (n=0,1; m=0,1,2,3). the maximum number of channel supported in ASC8851 / 8850 / 8849 / 8848 is 8 / 6 / 4 / 3 respectively. table 105. control register for device n name bit default r/w description - 31 - 09 0x0 - reserved. ccir656_chid_type_n 08 - 07 0x0 r/w select the chan nel id format for time-multiplexed output. 2?b00: no channel id. 2?b01: chid with the specific itu-r bt.656 sync code. 2?b10: chid with the specific horizontal blanking code. 2?b11: chid with both the specific itu-r bt.656 sync and horizontal blanking code. ccir656_mux_n 06 - 05 0x0 r/w number of channels of bt.656 data in vic device_n. 2?b00: 1 channel. 2?b01: 2 channels. 2?b10: 4 channels. 2?b11: 0 channel (disable this device). ccir656_edge_n 04 0x0 r/w specify the type of clock edge used to sample the bt.656 data in vic device_n 1?b0: single edge. 1?b1: double edge (both rising edge and falling edge). - 03 0x0 - reserved. raw_field_mode_en_n* 02 0x0 r/w using separa te sync signals, the field pin control. 1?b0: disable the field pin. 1?b1: enable the field pin to determine the input field. hsync_trg_n* 01 0x0 r/w vic_i_hsync_n trigger 1?b0: rising edge. 1?b1: falling edge. vsync_trg_n* 00 0x0 r/w vic_i_vsync_n trigger 1?b0: rising edge. 1?b1: falling edge. table 106. video input controller control register name bit default r/w description - 31 - 29 0x0 - reserved. int_rem_line_n_m* 28 - 24 0x0 r/w gener ate interrupt when the remaining number of lines is equal to int_rem_line_n_m. - 23 - 19 0x0 - reserved. field_invert_n_m* 18 0x0 r/w field bit control. 1?b0: field bit 0 is top field. 1?b1: field bit 1 is top field. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 109 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc field_mode_n_m* 17 0x0 r/w output field mode control. 1?b0: write two single fields in sdram. 1?b1: write one interleaved field in sdram. out_format_n_m* 16 0x0 r/w output image format. 1?b0: ycb cr 4: 2: 2 1?b1: ycb cr 4: 2:0. eccfvh_n* 15 0x0 r/w error detection using fvh field. 1?b1: enable fvh error detection. 1?b0: disable fvh error detection. mirror_n_m* 14 0x0 r/w mirror frame before writing to sdram 1?b0: don?t mirror. 1?b1: mirror. flip_n_m* 13 0x0 r/w flip frame before writing to sdram 1?b0: don?t flip. 1?b1: flip. ccir656_p_n_m* 12 0x0 r/w progressive bt.656 input 1?b0: interlaced bt.656 input. 1?b1: progressive bt.656 input. 11 0x0 reserved. nosig_clear_n_m 10 0x0 r/w no-signal counter enable control. 1?b0: disable and clear no-signal counter. 1?b1: enable no-signal counter. update_mmr_n_m 09 0x0 r/w force update mmr immediately when set to 1. this bit will clear itself after updating mmr. this bit is used for the first time when vic is initializ ed. registers with * are updated through this bit. out_en_n_m* 08 0x0 r/w enable data write to sdram when set to 1 int_en_n_m 07 0x0 r/w interrupt generation control. 1?b0: disable. 1?b1: enable. fifo_full_out_en_n_m 06 0x0 r/w fifo full output enable control. 1'b0: disable data write out when fifo full occurs.1'b1: enable data write out when fifo full occurs. this bit must be set to 1?b1 for asc8848/49/50 m1 version nosig_err_ack_en_n_m 05 0x0 r/w nosig_err_ack_n_m enable control. 1?b0: disable. 1?b1: enable. fifo_full_ack_en_n_m 04 0x0 r/w fif o_full_ack_n_m enable control. 1?b0: disable. 1?b1: enable. table 106. video input controller control register ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 110 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.5 vic_stat_0 (0x00000030) video input controller status register for channel_0_m (m = 0,1,2,3) op_cmpt_ack_en_n_m 03 0x0 r/w op_cmpt_ack_n_m enable control. 1?b0: disable. 1?b1: enable. nosig_err_ack_n_m 02 0x0 r/w set when no-signal error occurs and nosig_err_ack_en_n_m is 1?b1. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_ack_n_m 01 0x0 r/w set when fifo full occurs and fifo_full_ack_n_m is 1?b1. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_ack_n_m 00 0x0 r/w set when vic operation is complete and op_cmpt_ack_en_n_m is 1?b1. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. table 106. video input controller control register ?continued name bit default r/w description table 107. video input controller status register name bit default r/w description - 31 - 30 0x0 - reserved. buf_0_3 29 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_0_3 28 0x0 r frame error status. 1?b1: error found when capturing. 1?b0: no error occurred. field_0_3 27 0x0 r field information. 1?b0: top field. 1?b1: bottom field. nosig_err_0_3 26 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_0_3 25 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_0_3 24 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. - 23 - 22 0x0 - reserved. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 111 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc buf_0_2 21 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_0_2 20 0x0 r frame status. 1?b1: error found when capturing. 1?b0: no error occurred. field_0_2 19 0x0 r field status. 1?b0: top field. 1?b1: bottom field. nosig_err_0_2 18 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_0_2 17 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_0_2 16 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. - 15 - 14 0x0 - reserved. buf_0_1 13 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_0_1 12 0x0 r frame status. 1?b1: error found when capturing. 1?b0: no error occurred. field_0_1 11 0x0 r field status. 1?b0: top field. 1?b1: bottom field. nosig_err_0_1 10 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_0_1 09 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_0_1 08 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. - 07 0x1 - reserved. load_cmpt_0_0 06 0x0 r set when vic completes loading gamma table. 1?b0: vic gamma table loading is not complete. 1?b1: vic gamma table loading is complete. table 107. video input controller status register ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 112 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.6 vic_stat_1 (0x00000034) video input controller status register for channel_n_m (n=0,1; m=0,1,2,3). buf_0_0 05 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_0_0 04 0x0 r frame status. 1?b1: error found when capturing. 1?b0: no error occurred. field_0_0 03 0x0 r field status. 1?b0: top field. 1?b1: bottom field. nosig_err_0_0 02 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_0_0 01 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_0_0 00 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. table 107. video input controller status register ?continued name bit default r/w description table 108. video input controller status register for channel_n_m name bit default r/w description 31 - 24 - - reserved. buf_1_3 23 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_1_3 22 0x0 r frame error status. 1?b1: error found when capturing. 1?b0: no error occurred. field_1_3 21 0x0 r field information. 1?b0: top field. 1?b1: bottom field. nosig_err_1_3 20 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_1_3 19 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 113 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc op_cmpt_1_3 18 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. buf_1_2 17 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_1_2 16 0x0 r frame status. 1?b1: error found when capturing. 1?b0: no error occurred. field_1_2 15 0x0 r field status. 1?b0: top field. 1?b1: bottom field. nosig_err_1_2 14 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_1_2 13 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_1_2 12 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. buf_1_1 11 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_1_1 10 0x0 r frame status. 1?b1: error found when capturing. 1?b0: no error occurred. field_1_1 09 0x0 r field status. 1?b0: top field. 1?b1: bottom field. nosig_err_1_1 08 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_1_1 07 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_1_1 06 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. table 108. video input controller status register for channel_n_m ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 114 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc buf_1_0 05 0x0 r the buffer which is being written (occupied) by the channel. 1?b0: buffer0 is being used by vic. 1?b1: buffer1 is being used by vic. ferr_1_0 04 0x0 r frame status. 1?b1: error found when capturing. 1?b0: no error occurred. field_1_0 03 0x0 r field status. 1?b0: top field. 1?b1: bottom field. nosig_err_1_0 02 0x0 r set when no-signal error occurs. 1?b0: no no-signal error occurs. 1?b1: no-signal error occurs. fifo_full_1_0 01 0x0 r set when fifo full occurs. 1?b0: no fifo full occurs. 1?b1: fifo full occurs. op_cmpt_1_0 00 0x0 r set when vic operation is complete. 1?b0: vic operation is not complete. 1?b1: vic operation is complete. table 108. video input controller status register for channel_n_m ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 115 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.7 vic_sync_delay_n (0x00000038+n*4) this register provides the vic module to accept shifted hsync signal for device_n (n = 0,1). supports up to 4096 pixel clocks delay. 14.2.8 vic_milli_second_n_m (0x00000040+n*0xe0+m*0x38) this register contains the tick information. 14.2.9 vic_addr group1 (0x00000044+n*0xe0+m80x38~0x0000004c+n*0xe0+m*0x38) these registers specify the 1st output buff er addresses for channel_n_m (n = 0,1; m = 0, 1, 2, 3). fig 33. vic sync delay 001aam960 set sync_delay_s to 0x01 set sync_delay_e to 0x03 x pclk sync data valid valid valid valid valid valid valid valid valid x x table 109. vic sync delay name bit default r/w description sync_delay_s_n* 31 - 16 0x0 r/w hsync start point delay cycle. sync_delay_e_n* 15 - 00 0x0 r/w hsync end point delay cycle. table 110. vic milli second name bit default r/w description milli_second 31 - 00 0x0 r the number of ticks after vic initialized. this could be used as the hardware timestamp for one captured frame. it could represent 1ms or 1us depending on clock_rate register in vic_ctrl. table 111. vic_addr group1 name bit default r/w description y_addr_buf0_n_m* (0x00000044 + n*0xe0 + m*0x38) 31 - 00 0x0 r/w starting address of the first buffer of y-component. cb_addr_buf0_n_m* (0x00000048 + n*0xe0 + m*0x38) 31 - 00 0x0 r/w starting address of the first buffer of cb-component. cr_addr_buf0_n_m* (0x0000004c + n*0xe0 + m*0x38) 31 - 00 0x0 r/w starting address of the first buffer of cr-component. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 116 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.10 vic_addr group2 (0x00000050+n*0xe0+m*038~0x00000058 +n*0xe0+m*0x38) these registers specify the 2nd output buffer addresses for channel_n_m (n=0,1; m=0,1,2,3). 14.2.11 vic_in_size_n_m (0x0000005c+ n*0xe0+m*0x38) this register specifies the input frame/field width and height for channel_n_m (n=0,1;m=0,1,2,3). the number of pixels per line supported in asc8848/49/50/51 is 2560/2560/4096/4096 respectively. 14.2.12 vic_cap_h_n_m (0x00000060+n*0xe0+m*0x38) this register specifies the horizontal capturing parameters for channel_n_m (n=0,1; m=0,1,2,3). support up to 4096 pixels per line. 14.2.13 vic_cap_v_n_m (0x00000064+ n*0xe0+m*0x38) this register specifies the vertical capturing parameters for channel_n_m (n = 0,1; m = 0, 1, 2, 3). supports up to 4096 lines per frame. table 112. vic_addr group2 name bit default r/w description y_addr_buf1_n_m* (0x00000050+ n*0xe0+m*0x38) 31-00 0x0 r/w starting address of the second buffer of y component. cb_addr_buf1_n_m* (0x00000054+ n*0xe0+m*0x38) 31-00 0x0 r/w starting address of the second buffer of cb component. cr_addr_buf1_n_m* (0x00000058+ n*0xe0+m*0x38) 31-00 0x0 r/w starting address of the second buffer of cr component. table 113. vic input size n_m name bit default r/w description height_n_m* 31 - 16 0x0 r/w input frame/field height. width_n_m* 15 - 00 0x0 r/w input frame/field height table 114. horizontal capturing parameters name bit default r/w description nph_n_m* 31-16 0x0 r/w number of capturing pixels per line in horizontal direction. this register must be multiple of 16. sph_n_m* 15-00 0x0 r/w start capturing pixel ho rizontal. this register must be even. table 115. vertical capturing parameters name bit default r/w description nlv_n_m* 31 - 16 0x0 r/w number of capturing lines vert ical for one progressive frame or two interlaced fields. this register must be even. slv_n_m* 15 - 00 0x0 r/w start capturing line vertical for one progressive frame or two interlaced fields. this register must be even. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 117 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.14 vic_stride_n_m (0x00000068+ n*0xe0+m*0x38) this register specifies the capturing strides for channel_n_m (n = 0,1; m = 0, 1, 2, 3). supports up to 4096. 14.2.15 vic_sbc_n_m (0x0000006c+ n*0xe0+m*0x38) this register specifies saturation, brightness and contrast adjustments for channel_n_m (n=0,1;m=0,1,2,3). 14.2.16 vic_ce_ctrl_n_m (0x0000070+n*0xe0+m*0x38) contrast enhancement control register. 14.2.17 vic_ce_tbl_addr_n_m (0x00000074+n*0xe0+m*0x38) contrast enhancement table address. table 116. capturing strides for channel n_m name bit default r/w description - 31 - 16 0x0 - reserved stride_n_m* 15 - 00 0x0 r/w stride for y component. the stride for cb/cr component is half the value. table 117. saturation, brightness and contrast adjustments for channel n_m name bit default r/w description - 31 - 25 0x0 - reserved saturation_n_m* 24 - 16 0x0 r/w the saturation control on the output chrominance. (0~511, 128: off) brightness_n_m* 15 - 08 0x0 r/w the bright ness control on the output luminance. (-128~127, 0: off) contrast_n_m* 07 - 00 0x0 r/w the contra st control on the output luminance (-128~127, 0: off) table 118. contrast enhancement control register name bit default r/w description - 31 - 07 0x0 - reserved ce_load_tbl_cmpt 06 0x0 r/w load contrast enhance table complete signal. this register will be set by vic and cleared by sw. ce_load_tbl_en 05 0x0 r/w load contrast enhanc e table enable signal. write 1?b1 to enable and this register will be cleared by vic. ce_brightness 04 - 01 0x0 r/w brightness control signal ce_en 00 0x0 r/w contrast enhan cement enable control. 1?b0: disable. 1?b1: enable. table 119. contrast enhancement table address name bit default r/w description ce_tbl_addr_n_m 31 - 00 0x0 r/w contrast enhancement free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 118 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.18 vic_no_signal (0x00000200) this register specifies the no-signal in terrupt generation period of the vic module. 14.2.19 vic_cmos_ctrl (0x00000204) this register configures the cmos control register for device 0. table 120. no signal interrupt generation name bit default r/w description no_signal 31 - 00 0x0 r/w number of ahb cycles to generate no-signa l interrupt. if no sync code has been found for no_signal cycles, mmr; ferr will be set to high and the interrupt will be asserted. table 121. configuration of cmos control register name bit default r/w description - 31 - 30 0x0 - reserved clamp 29 - 22 0x0 r/w black clamp value in signed-magnitude format. if the msb is 0, this value is for subtraction. if the msb is 1, it is for addition. additional_pad_en 21 0x0 r/w support two additional padding rows and columns for cmyg or bilinear interpolation. 1?b0: disable. 1?b1: enable. bayer_bitwidth 20 - 16 0xa r/w the bit width of the bayer pattern. blank 15 - 04 0x0 r/w internal horizontal blanking when input external hsync is not present. it is recommended to set the same as the input external hsync. (unit: pixel clock) load_tbl_en 03 0x0 r/w write 1?b1 to this register to start loading the gamma table. this register will clear itself. denoise_en* 02 0x0 r/w the de-impulse noise removal enable control (only for pcci cfa method). 1?b0: disable. 1?b1: enable cfa_mode* 01 - 00 0x0 r/w the cfa method. 2?b00: bilinear interpolation (bayer format). 2?b01: primary consistent color interpolation (bayer format). 2?b10: cymgyeg interpolation. 2?b11: reserved. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 119 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.20 vic_rgb2ycbcr_coeff_0 (0x00000208) rgb to ycbcr conversion matrix: this register configures the coefficien ts for rgb to ycbcr conversion matrix. 14.2.21 vic_rgb2ycbcr_coeff_1 (0x0000020c) this register configures the coefficien ts for rgb to ycbcr conversion matrix. 14.2.22 vic_rgb2ycbcr_coeff_2 (0x00000210) this register configures the coefficients fo r rgb to ycbcr conversion matrix and the y killer function. 14.2.23 vic_denoise_threshold (0x00000214) this register configures the th reshold for impulse noise removal. ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? 128 128 256 8 7 6 5 4 3 2 1 0 offset b g r coeff coeff coeff coeff coeff coeff coeff coeff coeff cr cb y table 122. rgb to ycbcr conversion matrix name bit default r/w description coeff3 31 - 24 0x2c r/w rgb2ycbcr coefficient 3. coeff2 23 - 16 0x1d r/w rgb2ycbcr coefficient 2. coeff1 15 - 08 0x96 r/w rgb2ycbcr coefficient 1. coeff0 07 - 00 0x4d r/w rgb2ycbcr coefficient 0. table 123. rgb to ycbcr conversion matrix name bit default r/w description coeff7 31 - 24 0x6e r/w rgb2ycbcr coefficient 7. coeff6 23 - 16 0x83 r/w rgb2ycbcr coefficient 6. coeff5 15 - 08 0x83 r/w rgb2ycbcr coefficient 5. coeff4 07 - 00 0x57 r/w rgb2ycbcr coefficient 5. table 124. rgb to ycbcr conversion matrix name bit default r/w description - 31 - 21 0x0 - reserved. y_killer 20 - 13 0xff r/w cb/cr is set to zero if y is larger than y_killer. offset 12 - 08 0x0 r/w rgb2ycbcr offset for y. coeff8 07 - 00 0x15 r/w rgb2ycbcr coefficient 8. table 125. impulse noise removal name bit default r/w description road_thr 31 - 16 0x0 r/w road threshold. 0xfa is recommended. neighbor_thr 15 - 00 0x0 r/w neighbor threshold. 0x28 is recommended. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 120 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.24 vic_awb_ctrl (0x00000218) this register configures the configuration for awb. 14.2.25 vic_awb_ threshold (0x0000021c) this register configures th e threshold values in awb. table 126. configuration for awb name bit default r/w description cbcr_max 31 - 24 0x0 r/w cb and cr maximum threshold. it indicates the cb or cr value is ignored for averaging when it is larger than this threshold value. cbcr_min 23 - 16 0x0 r/w cb and cr minimum threshold. it indicates the cb or cr value is ignored for averaging when it is smaller than this threshold value. - 15 - 14 0x0 - reserved. 13 0x0 asc8848/49/50 m1 version : reserved asc8848/49/50 m2 version and ASC8851 : awb tuning position 1?b0: awb tuning after cfa. 1?b1: awb tuning before cfa. awb_after_cc* 12 0x0 r/w awb measurement control. 1?b0: awb measurement is before color correction. 1?b1: awb measurement is after color correction. manual_wb_en 11 0x0 r/w manual white balance control enable. 1?b0: enable auto white balance. 1?b1: enable manual white balance. max_step 10 - 07 0x1 r/w r/b gain adjustment maximum step size. min_step 06 - 03 0x1 r/w r/b gain adjustment minimum step size. - 02 - 01 0x0 r/w reserved. wb_en 00 0x0 r/w wb control enable. 1'b0: disable wb. 1'b1: enable wb. table 127. threshold values in awb name bit default r/w description cb_upper_bond 31 - 24 0x0 r/w cb upper bond threshold. it indicates the blue or red component of the frame is to o deep when it exceeds this threshold value. cb_lower_bond 23 - 16 0x0 r/w cb lower bond threshold. it indicates the blue or red component of the frame is to o weak when it doesn?t exceed this threshold value. cr_upper_bond 15 - 08 0x0 r/w cr upper bond threshold. it indicates the blue or red component of the frame is to o deep when it exceeds this threshold value. cr_lower_bond 07 - 00 0x0 r/w cr lower bond threshold. it indicates the blue or red component of the frame is to o weak when it doesn?t exceed this threshold value. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 121 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.26 vic_ae_src_sel (0x00000220) 14.2.27 reserved (0x00000224~0x0000022c) table 128. generic name bit default r/w description 31-01 0x0 reserved ae_src_sel 00-00 0x0 asc8848/49/50 m1 version : reserved r/w asc8848/49/50 m2 version and ASC8851 : ae luminance source selection 1?b0: after gamma correction. 1?b1: before gamma correction. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 122 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.28 vic_awb_manual_gain (0x00000230) user defined r/b gain when manual wb is enabled. 14.2.29 vic_colorcrt_coeff_r (0x00000234) color correction matrix: this register configures the coeffi cients for color correction matrix. 14.2.30 vic_colorcrt_coeff_g (0x00000238) this register configures the coeffi cients for color correction matrix. 14.2.31 vic_colorcrt_coeff_b (0x0000023c) this register configures the coeffi cients for color correction matrix. table 129. user defined r/b gain name bit default r/w description gain_upper_bond 31 - 24 0x0 r/w awb gain upper bond. gain_lower_bond 23 - 16 0x0 r/w awb gain lower bond. manual_r_gain 15 - 08 0x0 r/w user defined r gain (manual_r_gain/64) when manual wb is enabled. internal r gain when auto wb is enabled for asc8848/49/50 m2 version and ASC8851 only manual_b_gain 07 - 00 0x0 r/w user defined b gain (manual_b_gain/64) when manual wb is enabled. internal b gain when auto wb is enabled for asc8848/49/50 m2 version and ASC8851 only ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? offset offset offset in in in out out out b g r b g r bb coeff gb coeff rb coeff bg coeff gg coeff rg coeff br coeff gr coeff rr coeff b g r 128 _ _ _ _ _ _ _ _ _ table 130. coefficients for color correction name bit default r/w description coeff_r_of fset 31 - 28 0x0 - reserved for asc8848/49/50 m1 version r/w coefficient r offset, in range 0~15 for asc8848/49/50 m2 version and ASC8851 coeff_rr 27 - 18 0x0 r/w coefficient rr, in range -511~511. (first bit means sign-bit) coeff_gr 17 - 09 0x0 r/w coefficient gr, in range -255~255. (first bit means sign-bit) coeff_br 08 - 00 0x0 r/w coefficient br, in range -255~255. (first bit means sign-bit) table 131. coefficients for color correction matrix name bit default r/w description coeff_g_of fset 31 - 28 0x0 - reserved for asc8848/49/50 m1 version r/w coefficient goffset, in range 0~15. coeff_rg 27 - 19 0x0 r/w coefficient rg, in range -255~255. (first bit means sign-bit) coeff_gg 18 - 09 0x0 r/w coefficient gg, in range -511~511. (first bit means sign-bit) coeff_bg 08 - 00 0x0 r/w coefficient bg, in range -255~255. (first bit means sign-bit) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 123 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.32 vic_gamma_tbl_addr (0x00000240) this register specifies the gamma table address. 14.2.33 vic_af_ctrl0 (0x00000244) this register specifies the control register 0 for af. 14.2.34 vic_af_window_start_position (0x00000248) this register specified the starting position of af window. 14.2.35 vic_af_window_size (0x0000024c) this register specifies the size of af window. table 132. color correction matrix name bit default r/w description coeff_b_offse t 31 - 28 0x0 - reserved for asc8848/49/50 m1 version r/w coefficient boffset, in range 0~15 for asc8848/49/50 m2 version and ASC8851 coeff_rb 27 - 19 0x0 r/w coefficient rb, in range -255~255. (first bit means sign-bit) coeff_gb 18 - 10 0x0 r/w coefficient gb, in range -255~255. (first bit means sign-bit) coeff_bb 09 - 00 0x0 r/w coefficient bb, in range -511~511. (first bit means sign-bit) table 133. gamma table address name bit default r/w function gamma_tbl_addr 31 - 00 0x0 r/w gamma table address. table 134. control register 0 for af name bit default r/w description - 31 - 24 0x0 r/w reserved af_en 23 0x0 r/w enable auto-focus statistics output. 1?b0: disable, 1?b1: enable - 27 - 00 0x0 r/w reserved table 135. starting position of af window name bit default r/w description - 31 - 29 0x0 - reserved. af_window_start_pos_x 28 - 16 0x0 r/w the x coordinate of af window upper-left corner. - 15 - 13 0x0 - reserved. af_window_start_pos_y 12 - 00 0x0 r/w the y coordinate of af window upper-left corner. table 136. af window size name bit default r/w description - 31 - 29 0x0 - reserved. af_window_width 28 - 16 0x0 r/w af window width. - 15 - 13 0x0 - reserved. af_window_height 12 - 00 0x0 r/w af window height. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 124 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.36 vic_af_focus_value_high (0x00000250) this register records the focus value of af. table 137. af high focus value name bit default r/w description - 31 - 15 0x0 - reserved. af_focus_value_high 14 - 00 0x0 r focus value higher 15 bits. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 125 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.37 vic_af_focus_value_low (0x00000254) this register records the focus value of af. 14.2.38 vic_ae_window0_start (0x0000025c) this register specified the starting position of ae window 0. 14.2.39 vic_ae_window0_range (0x00000260) this register specified the size of ae window 0. 14.2.40 vic_ae_window1_start (0x00000264) this register specified the starting position of ae window 1. 14.2.41 vic_ae_window1_range (0x00000268) this register specified the size of ae window 1. the window width is up to 4096 pixels. table 138. low focus value of af name bit default r/w description af_focus_value_low 31 - 00 0x0 r focus value lower 32 bits. table 139. starting position of ae window name bit default r/w description - 31 - 29 0x0 - reserved. ae_win0_ver_start 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner. - 15 - 13 0x0 - reserved. ae_win0_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper-left corner. table 140. size of ae window name bit default r/w description - 31 - 29 0x0 - reserved. ae_win0_height 28 - 16 0x0 r/w ae window height. - 15 - 13 0x0 - reserved. ae_win0_width 12 - 00 0x0 r/w ae window width. table 141. starting position of ae window name bit default r/w description - 31 - 29 0x0 - reserved. ae_win1_ver_start 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner. - 15 - 13 0x0 - reserved. ae_win1_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper-left corner. table 142. ae window1 range name bit default r/w description - 31 - 29 0x0 - reserved. ae_win1_height 28 - 16 0x0 r/w ae window height. - 15 - 13 0x0 - reserved. ae_win1_width 12 - 00 0x0 r/w ae window width. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 126 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.42 vic_ae_window2_start (0x0000026c) this register specified the starting position of ae window 2. 14.2.43 vic_ae_window2_range (0x00000270) this register specified the size of ae window 2. the window width is up to 4096 pixels. 14.2.44 vic_ae_window3_start (0x00000274) this register specified the starting position of ae window 3. 14.2.45 vic_ae_window3_range (0x00000278) this register specified the size of ae window 3. the window width is up to 4096 pixels. table 143. starting position of ae window2 name bit default r/w description - 31 - 29 0x0 - reserved. ae_win2_ver_start 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner. - 15 - 13 0x0 - reserved. ae_win2_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper-left corner. table 144. ae window2 range name bit default r/w description - 31 - 29 0x0 - reserved. ae_win2_height 28 - 16 0x0 r/w ae window height. - 15 - 13 0x0 - reserved. ae_win2_width 12 - 00 0x0 r/w ae window width. table 145. starting position of ae window 3 name bit default r/w description - 31 - 29 0x0 - reserved ae_win3_ver_start 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner - 15 - 13 0x0 - reserved ae_win3_hor_start 12 - 00 0x0 r/w the x co-ordinate of ae window upper-left corner table 146. ae window3 range name bit default r/w description - 31 - 29 0x0 - reserved ae_win3_height 28 - 16 0x0 r/w ae window height - 15 - 13 0x0 - reserved ae_win3_width 12 - 00 0x0 r/w ae window width free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 127 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.46 vic_ae_window4_start (0x0000027c) this register specified the starting position of ae window 4. 14.2.47 vic_ae_window4_range (0x00000280) this register specified the size of ae window 4. 14.2.48 vic_ae_window5_start (0x00000284) this register specified the starting position of ae window 5. 14.2.49 vic_ae_window5_range (0x00000288) this register specified the size of ae window 5. table 147. starting position of ae name bit default r/w description - 31 - 29 0x0 - reserved ae_win4_ver_start 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner - 15 - 13 0x0 - reserved ae_win4_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper-left corner table 148. size of ae window4 name bit default r/w description - 31 - 29 0x0 - reserved ae_win4_height 28 - 16 0x0 r/w ae window height - 15 - 13 0x0 - reserved ae_win4_width 12 - 00 0x0 r/w ae window width table 149. starting position of ae window name bit default r/w description - 31 - 29 0x0 - reserved ae_win5_ver_start 28 - 16 0x0 r/w the y co-ordinate of ae window upper-left corner - 15 - 13 0x0 - reserved ae_win5_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper left corner table 150. size of ae window 5 name bit default r/w description - 31 - 29 0x0 - reserved ae_win5_height 28 - 16 0x0 r/w ae window height - 15 - 13 0x0 - reserved ae_win5_width 12 - 00 0x0 r/w ae window width free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 128 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.50 vic_ae_window6_start (0x0000028c) this register specified the starting position of ae window 6. 14.2.51 vic_ae_window6_range (0x00000290) this register specified the size of ae window 6. the window width is up to 4096 pixels. 14.2.52 vic_ae_window7_start (0x00000294) this register specified the starting position of ae window 7. 14.2.53 vic_ae_window7_range (0x00000298) this register specified the size of ae window 7. the window width is up to 4096 pixels. table 151. starting position of ae window 6 name bit default r/w description - 31 - 29 0x0 - reserved ae_win6_ver_start 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner - 15 - 13 0x0 - reserved ae_win6_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper-left corner table 152. size of ae window6 name bit default r/w description - 31 - 29 0x0 - reserved ae_win6_height 28 - 16 0x0 r/w ae window height - 15 - 13 0x0 - reserved ae_win6_width 12 - 00 0x0 r/w ae window width table 153. starting position of ae window 7 name bit default r/w description - 31 - 29 0x0 - reserved ae_win7_ver_stat 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner - 15 - 13 0x0 - reserved ae_win7_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper left corner table 154. ae window7 range name bit default r/w description - 31 - 29 0x0 - reserved ae_win7_height 28 - 16 0x0 r/w ae window height - 15 - 13 0x0 - reserved ae_win7_width 12 - 00 0x0 r/w ae window width free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 129 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.54 vic_ae_window8_start (0x0000029c) this register specified the starting position of ae window 8. 14.2.55 vic_ae_window8_range (0x000002a0) this register specified the size of ae window 8. the window width is up to 4096 pixels. 14.2.56 vic_ae_window0_luminance (0x000002a4) window 0 luminance value measured by ae. 14.2.57 vic_ae_window1_luminance (0x000002a8) window 1 luminance value measured by ae. 14.2.58 vic_ae_window2_luminance (0x000002ac) window 2 luminance value measured by ae. 14.2.59 vic_ae_window3_luminance (0x000002b0) window 3 luminance value measured by ae. table 155. starting position of ae window8 name bit default r/w description - 31 - 29 0x0 - reserved ae_win8_ver_start 28 - 16 0x0 r/w the y coordinate of ae window upper-left corner - 15 - 13 0x0 - reserved ae_win8_hor_start 12 - 00 0x0 r/w the x coordinate of ae window upper-left corner table 156. size of ae window8 name bit default r/w description - 31 - 29 0x0 - reserved ae_win8_height 28 - 16 0x0 r/w ae window height - 15 - 13 0x0 - reserved ae_win8_width 12 - 00 0x0 r/w ae window width table 157. luminance value measurement name bit default r/w description ae_win0_lum 31 - 00 0x0 r total luminance in ae window table 158. window1 luminance value name bit default r/w description ae_win1_lum 31 - 00 0x0 r total luminance in ae window table 159. window 2 luminance measurement name bit default r/w description ae_win1_lum 31 - 00 0x0 r total luminance in ae window table 160. window 3 luminance measurement name bit default r/w description ae_win3_lum 31 - 00 0x0 r total luminance in ae window free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 130 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.60 vic_ycbcr_clip (0x000002b4) clip value for ycbcr. 14.2.61 vic_cmyg_ctrl0 (0x000002b8) configuration for cmyg sensors. usin g pattern_vshift and patter_hshift to make the bayer rgb or cmyg pattern like below to be correctly cfa-interpolated. 14.2.62 vic_cmyg_ctrl1 (0x000002bc) configuration for cmyg sensors. table 161. clip value for ycbcr name bit default r/w description clip_y_upper 31 - 24 0xff r/w upper bound for y clip_y_lower 23 - 16 0x0 r/w lower bound for y clip_cbcr_upper 15 - 08 0xff r/w upper bound for cb/cr clip_cbcr_lower 07 - 00 0x0 r/w lower bound for cb/cr g r b g g r b g g r b g g r b g cy ye g mg cy ye g mg cy ye g mg cy ye g mg table 162. configuration for cmyg sensors name bit default r/w description is_edge_thrd 31 - 22 0x0 r/w sobel gradient threshold for distinguishing if the operation pixel has an edge - 21 - 04 0x0 - reserved pattern_vshift 03 - 02 0x0 r/w pattern vertical shif ting number (for bayer rgb and cmyg sensor) pattern_hshift 01 - 00 0x0 r/w pattern horizontal sh ifting number (for bayer rgb and cmyg sensor) table 163. cmyg_ctrl1 name bit default r/w description - 31 - 29 - - reserved attenuate_met hod 28 - 26 0x0 r/w 3?b000: 1/2 3?b001: 1/4 3?b010: left pixel 3?b011: set 0 3?b100: set 4095 others: reserved dir_edge_dif_thrd 25 - 16 0x0 r/w threshold for distin guishing if the operating pixel has a strong edge chroma_dif_thrd 15 - 00 0x0 r/w threshold for attenuating chroma signals free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 131 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.63 vic_ae_window4_luminance (0x000002c0) window 4 luminance value measured by ae. 14.2.64 vic_ae_window5_luminance (0x000002c4) window 5 luminance value measured by ae. 14.2.65 vic_ae_window6_luminance (0x000002c8) window 6 luminance value measured by ae. 14.2.66 vic_ae_window7_luminance (0x000002cc) window 7 luminance value measured by ae. 14.2.67 vic_tm_ctrl (0x000002d0) tone mapping control signals table 164. window4 luminance name bit default r/w description ae_win4_lum 31 - 00 0x0 r total luminance in ae window table 165. window 5 luminance name bit default r/w description ae_win5_lum 31 - 00 0x0 r total luminance in ae window table 166. window 6 luminance name bit default r/w description ae_win6_lum 31 - 00 0x0 r total luminance in ae window table 167. window 7 luminance name bit default r/w description ae_win7_lum 31 - 00 0x0 r total luminance in ae window table 168. tone mapping control signals name bit default r/w description gamma_overflow _slope 31-28 0x0 reserved for asc8848/49/50 m1 version. r/w slope for r/g/b greater than 256 to do gamma mapping for asc8848/49/50 m2 version and ASC8851 0: clip to 255 1:01 2:02 3:03 4:04 5:16 6:32 7.64 8.128 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 132 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.68 vic_awb_exclude_hori_window (0x000002d4) awb exclude horizontal window. 14.2.69 vic_awb_exclude_vert_window (0x000002d8) awb exclude horizontal window. 14.2.70 vic_awb_cb_sum (0x000002dc) awb statistics: sum of cb component. 14.2.71 vic_awb_cr_sum (0x000002e0) awb statistics: sum of cr component. 14.2.72 vic_ae_window8_luminance (0x000002e4) window 8 luminance value measured by ae. 27-04 0x0 reserved tm_blend_value 03 - 01 0x0 r/w the blending value of alpha=0.7 and alpha=1. tm_en 00 - 00 0x0 r/w enable signal for tone mapping function 1?b0: disable 1?b1: enable table 168. tone mapping control signals name bit default r/w description table 169. awb exclude horizontal window name bit default r/w description awb_exclude_x_start 31 - 16 0x0 r/w the x c oordinate of the exclusive awb window upper-left corner awb_exclude_x_end 15 - 00 0x0 r/w the x c oordinate of the exclusive awb window lower-right corner table 170. awb exclude vertical window name bit default r/w description awb_exclude_y_start 31-16 0x0 r/w the y coordinate of the exclusive awb window upper-left corner awb_exclude_y_end 15-00 0x0 r/w the y coordinates of the exclusive awb window lower-right corner table 171. sum of cb component name bit default r/w description awb_cb_sum 31 - 00 0x0 r sum of cb components of the whole frame except the exclusive awb window table 172. sum of cr components name bit default r/w description awb_cr_sum 31 - 00 0x0 r sum of cr components of the whole frame except the exclusive awb window free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 133 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.73 vic_ae_windows_msb_luminance (0x000002e8) this register specifies the control signals for ae. 14.2.74 vic_af_ctrl1 (0x000002ec) this register specifies the control register 1 for af. 14.2.75 vic_photo_ldc_ctrl (0x000002f0) photometric lens distortion co rrection control register. table 173. window 8 luminance value measurement name bit default r/w description ae_win8_lum 31 - 00 0x0 r total luminance in ae window table 174. windows msb luminance name bit default r/w description - 31 - 18 0x0 - reserved ae_win8_msb_lum 17 - 16 0x0 r msb 2bits of the total luminance in ae widow 8 ae_win7_msb_lum 15 - 14 0x0 r msb 2bits of the total luminance in ae widow 7 ae_win6_msb_lum 13 - 12 0x0 r msb 2bits of the total luminance in ae widow 6 ae_win5_msb_lum 11 - 10 0x0 r msb 2bits of the total luminance in ae widow 5 ae_win4_msb_lum 09 - 08 0x0 r msb 2bits of the total luminance in ae widow 4 ae_win3_msb_lum 07 - 06 0x0 r msb 2bits of the total luminance in ae widow 3 ae_win2_msb_lum 05 - 04 0x0 r msb 2bits of the total luminance in ae widow 2 ae_win1_msb_lum 03 - 02 0x0 r msb 2bits of the total luminance in ae widow 1 ae_win0_msb_lum 01 - 00 0x0 r msb 2bits of the total luminance in ae widow 0 table 175. windows msb luminance name bit default r/w description - 31 - 08 0x0 - reserved af_frame_intv 07 - 00 0x0 r/w calculate the focus value every af_frame_intv frame table 176. photometric lens distor tion correction control register name bit default r/w description - 31 - 03 0x0 - reserved photo_ldc_load_tbl_cmpt 02 0x0 r/w photometric lens distortion correction table loading complete indication. this bit is set by vic and cleared by sw. 1?b0 still loading 1?b1: loading complete photo_ldc_first_load_tbl_en 01 0x0 r/w enable signal of the first time table loading for photometric lens distorti on correction function. this bit should be sent to 1?b1 at the initialization of vic and then be cleared to 0 by vic. 1?b0: disable 1?b1: enable photo_ldc_en* 00 0x0 r/w enable signal for photometric lens distortion correction function 1?b0: disable 1?b1:enable free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 134 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.76 vic_photo_ldc_tbl_addr (0x000002f4) photometric lens distortion correction table address. 14.2.77 vic_awb_red_sum (0x000002f8) awb statistics: sum of r component. 14.2.78 vic_awb_green_sum (0x000002fc) awb statistics: sum of g component. 14.2.79 vic_awb_blue_sum (0x00000300) awb statistics: sum of b component. 14.2.80 vic_cmos_hor_penalty_thr (0x00000304) horizontal penalty threshold for cfa pcci edg e detector. it makes cfa pcci more easily to use vertical interpolation. 14.2.81 vic_cmos_ver_penalty_thr (0x00000308) vertical penalty threshold for cfa pcci edge detector. it makes cfa pcci more easily to use horizontal interpolation. table 177. photometric lens dist ortion correction table address name bit default r/w description photo_ldc_tbl_addr 31 - 00 0x0 r/w photometric lens distortion correction table address table 178. sum of r component name bit default r/w description awb_red_sum 31 - 00 0x0 r sum of r components of the whole frame except the exclusive awb window table 179. sum of g component name bit default r/w description awb_green_sum 31 - 00 0x0 r sum of g components of the whole frame except the exclusive awb window. table 180. sum of b component name bit default r/w description awb_blue_sum 31 - 00 0x0 r sum of b components of the whole frame except the exclusive awb window table 181. horizontal penalty thr eshold for cfa pcci edge detector name bit default r/w description - 31 - 18 0x0 - reserved cfa_pcci_hor_pen_thr 17 - 00 0x0 r/w horizontal penalty threshold for cfa pcci edge detector table 182. vertical penalty threshold name bit default r/w description - 31 - 18 0x0 - reserved cfa_pcci_ver_pen_thr 17 - 00 0x0 r/w vertical p enalty threshold for cfa pcci edge detector free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 135 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.3 block diagram the ic can be configured either as one 16-bit device or as two 8-bit devices. 14.3.1 16-bit device when it is configured as a 16-bit device, the vic accepts bayer rgb, cmyg or bt.1120 input formats. in this configuration, the pixel clock is up to 180mhz. 14.3.2 8-bit device when vic is configured as two 8-bit devices, it can accept single-channel video stream, two-channel time-multiplexed video stream, or four-channel time-multiplexed video stream. the supported clock frequency is specified in table 103 . 14.4 input formats there are various kinds of video stream form ats supported in the vi c. to support sd/hd video decoders or cmos sensors, bt.656, bt .1120, 8-/16-bit ycbcr 4:2:2 with separate sync signals is to be used. to suppor t multiple channel applications, the time-division-multiplexed bt. 656 video stream is used. 14.4.1 16-bit device 14.4.1.1 bayer rgb and cmyg in bayer/cmyg format, the vsync blanki ng must be at least 3 line periods. for asc8848/49/50 m1 version additional requirements are * vsync must be asserted before the first active video of hsync at least one pixel clock. fig 34. block diagram of a 16-bit device 001aam961 black clamping bayer format cpa/color correction/awb/ae/ gamma correction/tone mapping rgb format color transforms auto focus brightness/contrast/ saturation/ contrast enhancement ycbcr format ccir.656/ ccir.501 parser fig 35. block diagram of an 8-bit device 001aam962 brightness/contrast/ saturation/ contrast enhancement ccir.656 parser ccir.656 parser brightness/contrast/ saturation/ contrast enhancement ccir.656 parser ccir.656 parser demux pclk div_pclk pclk free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 136 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc * if hsync will be toggling in vsync blanking, the de-assertion of h sync must be prior to vsync assertion at le ast one pixel clock.. 14.4.1.2 ycbcr there are two kinds of video streams supporte d in this configuration, bt.1120 and ycbcr 4:2:2 with seperate sync signals. bt.1120 format has embedded sync codes in the data pins. the high byte of the 16-bit data is cb/cr component while the low byte is the y component. the video format timing is up to 1080p60@148.5mhz. figure 37 provides a typical timing diagram for bt.1120. figure 38 shows the typical timing of 16-bit ycbcr supported by most hdmi receivers. fig 36. timing diagram of bayer rgb and cmyg format 001aam963 vsync hsync g0 or c0 r0 or m0 g1 or c1 r1 or m1 fig 37. timing diagram of bt1120 fig 38. timing diagram of 16-bit ycbcr with seperate sync signals 001aam964 data[15:8] pclk ff 00 00 xy .... cb0 cr0 cb1 cr1 data[7:0] ff 00 00 xy .... y0 y1 y2 y3 001aao103 cb0 y0 hsync vsync data[7:0] data[15:8] pclk cr0 y1 cb1 y2 cr0 y3 ... ... free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 137 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.4.2 8-bit device 14.4.2.1 single-channel video stream there are two kinds of video streams supporte d in this configuration, bt.656 and ycbcr 4:2:2 with separate sync signals. figure 39 is a typical timing diagram of video decoders. figure 40 shows the typical timing diagram of cmos smart sensors. 14.4.2.2 2-channel video stream with single-edge clocking the 2-channel time-multiplexed video stream must be specified with the channel id (chid) either in the sync codes or the ho rizontal blanking code. chid[1:0] must be 2?b00 and 2?b10. the video st ream will be de-multiplexed in vic into ch0 and ch2 according to the channel id. fig 39. timing diagram of single-channel bt656 video stream fig 40. timing diagram of single-channel vi deo stream with separate sync signals. 001aam965 data[7:0] pclk ff 00 00 xy .... cb0 y0 cr0 y1 001aam966 vsync hsync cb0 y0 cr0 y1 .... fig 41. timing diagram of two-channel video stream with single-edge clocking 001aam967 ff cb28 cb28 ff multiplexed 54 mhz ch2 ch0 y56 00 cr28 00 y57 xy cb29 cb0 y58 y0 cr29 cr0 y59 y1 00 y56 00 cr28 xy y57 cb0 cb29 y0 y58 cr0 cr29 y1 y59 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 138 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.4.2.3 2-channel video stream with double-edge clocking the 2-channel time-multiplex ed video stream will be de-multiplexed in vic into ch0 (rising edge) and ch2 (falling edg e) if no chid is specified. if the channel id is added, chid[1:0] must be 2?b00 and 2?b10 and then the video stre am will be de-multiplexed in vic into ch0 and ch2 according to the channel id. 14.4.2.4 4-channel video stream with single-edge clocking the 4-channel time-multiplexed video stream will be de-multipl exed in vic into ch0, ch1, ch2, and ch3 depending on the order of the syn c codes of the individual channel in the video stream detected if no chid is specified. if the channe l id is added, chid[1:0] must be 2?b00, 2?b01, 2?b10, and 2?b11 and then th e video stream will be de-multiplexed in vic into ch0, ch1, ch2, and ch3 according to the channel id. fig 42. timing diagram of two-channel video stream with double-edge clocking 001aam968 ff cb28 cb28 ff multiplexed 27 mhz ch2 ch0 y56 00 cr28 00 y57 xy cb29 cb0 y58 y0 cr29 cr0 y59 y1 00 y56 00 cr28 xy y57 cb0 cb29 y0 y58 cr0 cr29 y1 y59 fig 43. timing diagram of four-channel video stream with single-edge clocking 001aan235 ff cb28 cb11 y66 multiplexed 108 mhz ch3 ch2 cb28 ff ch1 ch0 y22 cb33 y56 00 cr11 y67 cr28 00 y23 cr34 y57 xy y66 cb11 00 y56 cb33 y22 00 cr28 y67 cr11 xy y57 cr34 y23 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 139 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.4.2.5 channel id format there are two kinds of channel id formats s upported in vic to identify the individual channel in the time-multiplexed video stream. first, the channel id is inserted in the sync codes as shown in ta b l e 1 8 3 . second, the channel id is inserted in t he horizontal blanking code as shown in table 184 table 183. channel id format for 4-channel time-multiplexed video stream (sync codes) bt.656 timing reference signal description first second third fourth ch0 ch1 ch2 ch3 ff 00 00 80 81 82 83 field 1, active, sav ff 00 00 90 91 92 93 field 1, active, eav ff 00 00 a0 a1 a2 a3 field 1, blanking, sav ff 00 00 b0 b1 b2 b3 field 1, blanking, eav ff 00 00 c0 c1 c2 c3 field 2, active, sav ff 00 00 d0 d1 d2 d3 field 2, active eav ff 00 00 e0 d1 d2 d3 field 2, blanking, sav ff 00 00 f0 f1 f2 f3 field 2, blanking, eav table 184. channel id format for 4-channel time-multiplexed video stream (horizontal blanking code) ch0 ch1 ch2 ch3 y10111213 cb/cr80818283 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 140 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 14.4.3 interrupt generation vic supports up to 8 channels and all channels share one common interrupt. this sections shows how to distinguish which device issues the interrupts and how the interrupt is generated. each channel has its own stat and ctrl mmr. table 185 shows all conditions possibly encountered during the video capture. op_cmpt_ack_en, fifo_full_ack_en a nd nosig_err_ack_en decides which kind of interrupt will be asserted. since all interrupts are ored together, after the host receives the interrupt signal, it should check the stat for ferr, op_cmpt, fifo_f ull, and nosig_err of all channels to know which channel asserts the interrupt and what type of conditions occurred. remember to clear the corresponding ack bits in ctrl mmr in order to de-assert the interrupt. table 185. video capture status descriptions condition associate knowledge and status signals stat ctrl frame capture without errors: 1.op_cmpt_ack_en = 1. 2.frame header found (bt.656). 3.int_rem_line meet op_cmpt = 1 ferr = 0 op_cmpt_ack = 1 input parsing error: 1.op_cmpt_ack_en = 1 2.parsing error due to invalid frame header (bt.656) or input width mismatch. ferr = 1 op_cmpt_ack = 1 fifo full error: 1.fifo_full_ ack_en = 1 2.output fifo is full and the pixels are dropped. fifo_full = 1 ferr = 1 fifo_full_ack = 1 no signal error: 1.nosig_err_ack_en = 1 2.next frame header or frame sync is not detected after a given period. nosig_err = 1 ferr = 1 nosig_err_ack = 1 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 141 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 15. general purpose i/o 15.1 general description asc8848/49/50/51 soc provides 20 general-purpose i/o (gpio). each gpio can be configured as input or output independently. some of the gpio signals are shared with other signals. see ta b l e 1 8 6 for details. for mult i-function pins, make sure only one function is enabled at one time. gpio must be to set input direction to disable it so as not to interfere with the advanced general purpose output function. 15.2 features 15.2.1 i/o pins up to 20 independent bi-directional i/o pins. 15.2.2 pull mode each pin can be configured pull-high or pull-low independently. 15.2.3 interrupt mode each pin can be configured to high-level, low-level, positive-edge, negative-edge, or both-edge trigger mode separately to trigger the gpio interrupt signal. the gpio interrupt signal is level-triggered to th e interrupt controller. when one gpio is level-triggered, the application needs to clear the external interrup t source to make the gpio interrupt signal de-asserted. when one gpio is edge-triggered , the application needs to clear the gpio interrupt signal through gp ioc_intr_cleaer register. 15.2.4 de-bounce mode when the de-bounce mode is enabled, each pin can be de-bounced to filter out the unexpected noise from the data input pin if the noise period is less than the de-bouncing period. table 186. gpio signals name description gpio[19:8] dedicated for gpio. gpio[7:0] 1. gpio[7:0]. agpo[7:0] must be disabled first (enabled by default and disabled by setting agpoc_dft_data_oe_n to 32?h000000ff). 2. agpo[7:0] controlled by the advan ced general purpose output controller. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 142 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 15.3 memory map registers 15.3.1 gpioc_version (0x00000000) version information register. 15.3.2 gpioc_data_out (0x00000004) output data register. 15.3.3 gpioc_data_in (0x00000008) input data register. 15.3.4 gpioc_pin_dir (0x0000000c) pin direction register. 15.3.5 reserved (0x00000010) 15.3.6 gpioc_data_set (0x00000014) output data set register. table 187. version information register name bit default r/w description major_version 31 - 24 0x03 r major version number minor_version 23 - 16 0x00 r minor version number build_version 15 - 08 0x00 r build version number revision 07 - 00 0x08 r revision number table 188. output data register name bit default r/w description data_out 19 - 00 0x0 r/w if the direction is output, write this register to control the output logic level. table 189. input data register name bit default r/w description data_in 19-00 0x0 r this register shows the logic level on the gpio table 190. pin direction register name bit default r/w description pin_dir 19-00 0x0 r/w 1? b0: input 1?b1:output table 191. output data set register name bit default r/w description data_set 19-00 0x0 w when writing 1?b1 to some bits in this register, the corresponding bits on the gpio will be set to 1?b1. this register is self cleared. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 143 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 15.3.7 gpioc_data_clear (0x00000018) output data clear register. 15.3.8 gpioc_pin_pull_enable (0x0000001c) pull mode enable register. 15.3.9 gpioc_pin_pull_type (0x00000020) pull type register. 15.3.10 gpioc_intr_enable (0x00000024) interrupt enab le register. 15.3.11 gpioc_intr_raw_state (0x00000028) interrupt raw state register. 15.3.12 gpoic_intr_mask_state (0x0000002c) masked interrupt state register. table 192. output data clear register name bit default r/w description data_clr 19 - 00 0x0 w when writing 1?b1 to some bits in this register, the correspondent bits on the gpio will be set to 1?b0. this register is self cleared. table 193. pull mode enable register name bit default r/w description pin_pull_en 19 - 00 0x0 r/w control t he pull-up or pull-down function of the gpio 1?b0: disable 1?b1: enable table 194. interrupt enable register name bit default r/w description intr_en 19 - 00 0x0 r/w it is a mask of interrupt detection logic. when the pin direction is set to input and the interrupt detection is enabled, the interrupt detection logic can accept interrupt from the output port of the bidirectional i/o pad. table 195. interrupt raw state register name bit default r/w description intr_raw_state 19 - 00 0x0 r when the corresponding intr_en bit is high, this register shows the state of the external interrupt sources. table 196. masked interrupt state register name bit default r/w description intr_mask_state 19 - 00 0x0 r when the corresponding intr_en bit is high, this register shows masked external interrupt sources. gpioc?s interrupt pin will be asserted once this register is not zero. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 144 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 15.3.13 gpioc_intr_mask (0x00000030) interrupt mask register. 15.3.14 gpioc_intr_clear (0x00000034) interrupt state clear register. 15.3.15 gpioc_intr_trigger_type (0x00000038) interrupt triggered method register. 15.3.16 gpioc_intr_both (0x0000003c) edge triggered mode register. 15.3.17 gpioc_intr_dir (0x00000040) interrupt direction register. 15.3.18 gpioc_debo unce_enable (0x00000044) de-bounce enable register. table 197. interrupt mask register name bit default r/w description intr_mask 19 - 00 0x0 r/w interrupt mask control bits. 1?b0: external interrupt is enabled 1?b1: external interrupt is masked. table 198. interrupt state clear register name bit default r/w description intr_clr 19 - 00 0x0 w when writing 1?b1 to this register, the correspondent bit of the interrupt state register is cleared. this register is self cleared. table 199. interrupt triggered method register name bit default r/w description intr_trig_type 19 - 00 0x0 r/w 1?b0: edge-triggered type 1?b1: level-triggered type table 200. edge triggered mode register name bit default r/w description intr_both 19 - 00 0x0 r/w this register is only meaningful if the interrupt type is set to edge trigger type. table 201. interrupt direction register name bit default r/w description intr_dir 19 - 00 0x0 r/w 1?b0: positive edge or high level trigger 1?b1: negative edge or low level trigger table 202. de-bounce enable register name bit default r/w description debounce_en 19 - 00 0x0 r/w 1?b?0: disable de-bounce capability 1?b1: enable de-bounce capability free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 145 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 15.3.19 gpioc_debounce _period (0x00000048) de-bounce cycle register. table 203. de-bounce cycle register name bit default r/w description - 31 - 24 - - reserved debounce_period 23 - 00 0x0 r/w minimum de-bounce period in apb clock cycle. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 146 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 16. usb 2.0 16.1 general description there is a one-port usb2.0 in asc8848/49 /50/51 soc. it is compliant with usb specification 2.0 and otg supplement to the u sb 2.0 specification revi sion 1.0a. it also supports session request protocol (srp) and host negotiation protocol (hnp). usb 2.0 test modes are implemented to fa cilitate the compliance testing. acting as a host controller, 5 v vbus c ould be removed if it is not required. 16.2 features the usb 2.0 provides the following features. ? supports 480 mbps high-speed, 12 mbps full-speed, and 1.5 mbps low-speed (host mode only) data transmission rates ? supports a generic root hub ? implements a 4kb fifo and dynamic fifo sizing ? includes a dma controller to support tx and rx transfers ? supports off-chip charge pump regulator to generate 5 v for vbus ? supports session request protocol (srp) ? supports host negotiation protocol (hnp) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 147 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17. inter-ic soun d slave controller 17.1 general description the inter-ic sound (i2s) bus is a simple three-wire serial bus protocol developed by philips to transfer stereo audio data. the bus only handles the transfer of audio data; hence control and subcoding signals need to be transferred separately using a different bus protocol (such as i2c). the i2s contro ller in asc8848/49/50/51 soc only supports slave mode which means the bit-clock (bclk) a nd word select (ws) must be provided by the external audio codec. the master clock (mclk) which might be 256fs or 384fs could be provided by asc8848/49/50/51 soc through the system controller ( section 7.2.12 and ta b l e 2 5 ). 17.2 features ? supports i2s slave mode ? full duplex communication due to the independence of transmitter and receiver ? audio data resolutions up to 32 bits ? programmable thresholds of rx and tx fifos ? support external dma inte rface to request apbc to move data from/to i2ssc ? independent rx and tx fifos ? independent 8-entry left and right fifos for rx and tx fifos ? four rx-only and one full-duplex i2ssc controllers 17.3 memory map register 17.3.1 ier (0x00000000) this register acts as a global enable/disable control for i2ssc. 17.3.2 irer (0x00000004) this register acts as an enable/disable for the i2ssc receiver block. table 204. ier name bit default r/w description - 31 - 01 0x0 - reserved ien 00 - 00 0x0 r/w i2ssc enable control 1?b0: disable 1?b1: enable table 205. irer name bit default r/w description - 31 - 01 0x0 - reserved rxen 00 - 00 0x0 r/w received block enable control 1?b0: disable 1?b1: enable free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 148 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.3 iter (0x00000008) this register acts as an enable/disable for the i2ssc transmitter block. 17.3.4 cer (0x0000000c) this register acts as an enable/disab le for the i2ssc clock generation block. 17.3.5 reserved (0x00000010) 17.3.6 rxffr (0x00000014) receiver block fifo reset register. 17.3.7 txffr (0x00000018) transmitter block fifo reset register. table 206. iter name bit default r/w description - 31 - 01 0x0 - reserved txen 00 - 00 0x0 r/w transmitter block enable control 1?b0: disable 1?b1: enable table 207. cer name bit default r/w description - 31 - 01 0x0 - reserved clken 00 - 00 0x0 r/w clock generation block enable control 1?b0: disable 1?b1: enable table 208. receiver block fifi reset register name bit default r/w description - 31 - 01 0x0 - reserved rxffr 00 - 00 0x0 w receiver fifo reset. writing a 1 to this register flushes all the rx fifos (this is a self clearing bit). the receiver block must be disabled prior to writing this bit. table 209. transmitted bloc k fifo reset register name bit default r/w description - 31 - 01 0x0 - reserved txffr 00 - 00 0x0 w transmitter fifo reset. writing a 1 to this register flushes all the tx fifos (this is a self cl earing bit). the transmitter block must be disabled prior to writing this bit. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 149 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.8 lrbr (0x00000020) left receive buffer register. 17.3.9 lthr (0x00000020) left transmit holding register. 17.3.10 rrbr (0x00000024) right receive buffer register. table 210. left receive buffer register name bit default r/w description lrbr 31 - 00 0x0 r the left stereo data received serially from the receiver channel input is read through this register. if the rx fifo is full and the two-stage read operation (for instance, a read from lrbr followed by a read from rrbr) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (data already in the rx fifo is preserved) table 211. lthr name bit default r/w description lthr 31 - 00 0x0 w the left stereo data to be transmitted serially through the transmit channel output is written through this register. writing is a two-stage process.(1) a write to this register passes the left stereo sample to the transmitte r (2) this must be followed by writing the right stereo sample to the rthr register. data should only be written to the fifo when it is not full. any attempt to write to a full fifo results in that data being lost and an overrun interrupt being generated. table 212. right receive buffer register name bit default r/w description rrbr 31 - 00 0x0 r the right stereo data rece ived serially from the receive channel input is read through this register . if the rx fifo is full and the two-stage read operation (for inst ance, read from lrbr followed by a read from rrbr) is not per formed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (data already in the rx fifo is preserved) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 150 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.11 rthr (0x00000024) right transmit holding register. 17.3.12 rer (0x00000028) receive enable register. 17.3.13 ter (0x0000002c) transmit enable register. table 213. right transmit holding register name bit default r/w description rthr 31 - 00 0x0 w the right stereo data to be transmitted serially through the transmit channel output is written th rough this register. writing is a two stage process. (1) a left stereo sample must first be written to the lthr register. (2) a write to this register passes the right stereo sample to the transmitter.must first be written to the lthr register. (2) a write to this register passes the right stereo sample to the transmitter. data should only be written to the fifo when it is not full. any attempt to write to a full fifo re sults in that data being lost and an overrun interrupt being generated. table 214. receive enable register name bit default r/w description - 31 - 00 0x0 - reserved rxchen 00 - 00 0x1 r/w receive channel enable. this bit enables/disables a receive channel. on enable, the channel begins receiving on the next left stereo cycle. a global disable of i2s (ier[0] = 0) or the receiver block (irer[0] = 0) overrides this value. 1?b1: enable.receiving on the next left st ereo cycle. a global disable of i2s (ier[0] = 0) or the receiver block (irer[0] = 0) overrides this value. 1?b1: enable. 1?b0: disable. table 215. transmit enable register name bit default r/w description - 31 - 00 0x0 - reserved txchen 00 - 00 0x1 r/w transmit channel enable. this bit enables/ disables a transmit channel. on enable, the channel begins transmitting on the next left stereo cycle. a global disable of i2s (i er[0] = 0) or transmitter block (iter[0] = 0) overrides this value. 1?b0: disable. 1?b1: enable. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 151 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.14 rcr (0x00000030) receive configuration register. 17.3.15 tcr (0x00000034) transmit configuration register. table 216. receive configuration register name bit default r/w description - 31 - 03 0x0 - reserved wlen 02 - 00 0x5 r/w these bits are used to program the desired data resolution of the receiver and enables the lsb of the incoming left (or right) word to be placed in the lsb of the lrbr (or rrbr) register. 3?b000: ignore word length. 3?b001: 12 bit resolution. 3?b010: 16 bit resolution. 3?b011: 20 bit resolution. 3?b100: 24 bit resolution. 3?b101: 32 bit resolution. the channel must be disabled prior to any changes in this value (rer[0] = 0) table 217. transmit configuration register name bit default r/w description - 31 - 03 0x0 - reserved wlen 02 - 00 0x5 r/w these bits are used to program the data resolution of the transmitter and ensures the msb of the data is transmitted first. 3?b000: ignore word length. 3?b001: 12 bit resolution. 3?b010: 16 bit resolution. 3?b011: 20 bit resolution. 3?b100: 24 bit resolution. 3?b101: 32 bit resolution. the channel must be disabled prior to any changes in this value (ter[0] = 0). free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 152 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.16 isr (0x00000038) interrupt status register. 17.3.17 imr (0x0000003c) interrupt mask register. table 218. interrupt status register name bit default r/w description - 31 - 06 0x0 - reserved txfo 05 0x0 r status of data overrun inte rrupt for the tx channel. attempt to write to full tx fifo. 1?b0: tx fifo write valid. 1?b1: tx fifo write overrun. txfe 04 0x1 r status of transmit empty trigger interrupt. tx fifo is empty. 1?b1: trigger level reached. 1?b0: trigger level not reached. 03 - 02 0x0 reserved rxfo 01 0x0 r status of data overrun interrupt for the rx channel. incoming data lost due to a full rx fifo. 1?b0: rx fifo write valid. 1?b1: rx fifo write overrun. rxda 00 0x0 r status of receive data available interrupt. rx fifo data available. 1?b1: trigger level reached. 1?b0: trigger level not reached. table 219. interrupt mask register name bit default r/w description 31 - 06 0x0 reserved txfom 05 0x1 r/w masks tx fifo overrun interrupt. 1?b1: masks interrupt. 1?b0: unmasks interrupt. txfem 04 0x1 r/w masks tx fifo empty interrupt. 1?b1: masks interrupt. 1?b0: unmasks interrupt. 03 - 02 0x0 reserved rxfom 01 0x1 r/w masks rx fi fo overrun interrupt. 1?b1: masks interrupt. 1?b0: unmasks interrupt. rxdam 00 0x1 r/w masks rx fifo data available interrupt. 1?b1: masks interrupt. 1?b0: unmasks interrupt. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 153 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.18 ror (0x00000040) receive overrun register. 17.3.19 tor (0x00000044) transmit overrun register. 17.3.20 rfcr (0x00000048) receive fifo configuration register. 17.3.21 tfcr (0x0000004c) transmit fifo configuration register. table 220. receive overrun register name bit default r/w description - 31 - 01 0x0 - reserved rxcho 00 - 00 0x0 r read this bit to clear he rx fifo data overrun interrupt. 1?b0: rx fifo write valid. 1?b1: rx fifo write overrun. table 221. transmit overrun register name bit default r/w description - 31 - 01 0x0 - reserved txcho 00 - 00 0x0 r read this bit to clear the tx fifo data overrun interrupt. 1?b0: tx fifo write valid. 1?b1: tx fifo write overrun. table 222. receive fifo configuration register name bit default r/w description - 31 - 04 0x0 - reserved rxchdt 03 - 00 0x1 r/w these bits program the trigger level in the rx fifo at which the received data available interrupt is generated. trigger level = programmed value + 1 the channel must be disabled prior to any changes in this value (that is, rer[0] = 0). table 223. transmit fifo configuration register name bit default r/w description - 31 - 04 0x0 - reserved txchet 03 - 00 0x1 r/w transmit channel em pty trigger. these bits program the trigger level in the tx fifo at which the empty threshold reached interrupt is generated. trigger level = txchet the channel must be disabled prior to any changes in this value (that is, ter[0] = 0) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 154 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.22 rff (0x00000050) receive fifo flush register. 17.3.23 tff (0x00000054) transmit fifo flush register. 17.3.24 rxdma (0x000001c0) receiver block dma register. the rxdma regi ster allows access to enabled receive channel via a single point rather than throu gh the lrbr and rrbr registers. the receive channels takes two reads to read stereo data pairs. the order of returned data is left data first and then right data. 17.3.25 rrxdma (0x000001c4) reset receiver block dma register. [1] writing to this register has no effect if the comp onent is performing a stereo pair read (such as, when left stereo data has been read but not right stereo data). table 224. receive fi fo flush register name bit default r/w description - 31 - 01 0x0 - reserved rxchfr 00 0x0 w receive channel fifo rese t. writing a 1 to this register flushes an individual rx fifo. (this is a self clearing bit.) rx channel or block must be disabled prior to writing to this bit. table 225. transmit fifo flush register name bit default r/w description - 31 - 01 0x0 - reserved txchfr 00 0x0 w transmit channel fifo reset. writing a 1 to this register flushes channel?s tx fifo. (this is a self clearing bit.) tx channel or block must be disabled prior to writing to this bit. table 226. rxdma name bit default r/w description rxdma 31 - 00 0x0 r receiver block dma register. used to cycle repeatedly through the enabled receive channel, reading stereo data pairs. table 227. reset receiv er block dma register name bit default r/w description - 31 - 01 0x0 - reserved rrxdma [1] 00 0x0 w reset receiver block dma register. writing a 1 to this self-clearing register re sets the rxdma register. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 155 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 17.3.26 txdma (0x000001c8) transmitter block dma register. the txdma register functions similar to the rxdma register and allows write accesses via a single point rather than through the lthr and rthr registers. [1] used to cycle repeatedly through the enabled tr ansmit channel, writing stereo data pairs. 17.3.27 rtxdma (0x000001cc) reset receiver block dma register. [1] this register has no effect in the middle of a stereo pair write (such as, when left stereo data has been written but not right stereo data). table 228. txdma name bit default r/w description txdma [1] 31 - 00 0x0 w transmitter block dma register. table 229. rtxdma name bit default r/w description - 31 - 01 0x00 - reserved rtxdma [1] 00 0x00 w reset transmitter block dma register. writing a 1 to this self-clearing register resets the txdma register. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 156 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 18. ethernet mac controller 18.1 general description the ethernet mac 10/100/1000 controller in asc8848/49/50/51 soc enables a host to transmit and receive data over ethernet in complia nce with the ieee 802.3-2002 standard. it supports gigabit media indepe ndent interface (gmii) / media independent interface (mii) defined in the ieee 802.3 specificat ions. it also supports the industry standard, reduced gigabit media independent interface (rgmii). 18.2 features the ethernet mac 10/100/1000 contro ller provides the following features. ? supports ieee 802.3-2002 fo r ethernet mac and gmii ? supports rgmii specificati on from hp/marvell for rgmii ? checksum of load engine to ease the system loading (not for jumbo ethernet frames) ? independent tx and rx fifo for the internal dma engine ? programmable frame length to support standard or jumbo ethernet frames with sizes up to 16 kb ? 64-bit hash filter for multicast addresses ? supports only full-duplex operation free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 157 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19. synchronous serial interface controller 19.1 features the synchronous serial interface (ssi ) controller has the following features. ? programmable signal polarity ? programmable serial bit clock phase and frequency ? programmable serial bit data sequence ? programmable threshold interrupt of rx and tx fifos ? programmable interrupt enable/disable ? support external dma inte rface to request apbc to move data from/to ssic ? independent 32-entry rx and tx fifos 19.2 memory map register 19.2.1 ctrlr0 (0x00000000) this register controls the serial data transfer. table 230. ctrlr0 name bit default r/w description - 31 - 16 0x0 - reserved cfs 15 - 12 0x0 r/w selects the length of the control word for the microwire frame format. 0000: 1-bit control word 0001: 2-bit control word 0010: 3-bit control word 0011: 4-bit control word 0100: 5-bit control word 0101: 6-bit control word 0110: 7-bit control word 0111: 8-bit control word 1000: 9-bit control word 1001: 10-bit control word 1010: 11-bit control word 1011: 12-bit control word 1100: 13-bit control word 1101: 14-bit control word 1110: 15-bit control word 1111: 16-bit control word srl [1] 11 0x0 r/w used for testing purposes only. 0: normal mode operation 1: test mode operation - 10 0x0 - reserved free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 158 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] when internally active, connects the transmit shift r egister output to the receive shift register input: [2] this field does not affect the transfe r duplicity. only indicates whether t he receive or transmit data are valid. in transmit-only mode, data received from the external device is not valid and is not stored in the receive fifo memory; it is overwritten on the next transfer . in receive-only mode, transmitted data are not valid. after the first write to the transmit fifo, the same word is retransmitted for the duration of the transfer. in transmit-and-receive mode, both transmit and receive data are valid. the transfer continues until the transmit fifo is empty. data received from the exte rnal device are stored into the receive fifo memory, where it can be accessed by the host processor. in eeprom-read mode, receive data is not valid while control data is being transmitted. when all control data is sent to the eeprom, receive data becomes valid and transmit data becomes invalid. all data in the trans mit fifo is considered c ontrol data in this mode. [3] valid when the frame format (frf) is set to motorola spi. used to select the polarity of the inactive serial clock, which is held inactive when the ssi master is not actively transferring data on the serial bus. [4] valid when the frame format (frf) is set to motorola spi. the serial clock phase selects the relationship of the serial clock with the slave se lect signal. when scph = 0, data are captured on the first edge of the serial clock. when scph =1, the serial clock starts toggl ing one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 19.2.2 ctrlr1 (0x00000004) this register controls the end of serial transfers when in rece ive-only mode. it is impossible to write to this register when the ssi controller is enabled. the ssi controller is enabled and disabled by writing to the ssienr register. [1] when tmod = 10 or tmod = 11, this register fiel d sets the number of data frames to be continuously received by the ssi controller. the ssi controller cont inues to receive serial data until the number of data frames received is equal to this register value plus 1, which enables you to receive up to 64 kb of data in a continuous transfer. tmod [2] 09-08 0x0 r/w selects the mode of transfer for serial communication. 00: transmit & receive 01: transmit only 10: receive only 11: eeprom read scpol [3] 07 0x0 r/w 0: inactive state of serial clock is low 1: inactive state of serial clock is high scph [4] 06 0x0 r/w 0: serial clock toggles in middle of first data bit 1: serial clock toggles at start of first data bit frf 05 - 04 0x0 r/w selects which serial protocol transfers the data: 00 ?- motorola spi 01 ?- texas instruments ssp 10 ?- national semiconductors microwire 11 ?- reserve table 230. ctrlr0 ?continued name bit default r/w description table 231. ctrlr1 name bit default r/w description - 31 - 16 0x0 - reserved ndf [1] 15 - 00 0x0 r/w number of data frames. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 159 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.2.3 ssienr (0x00000008) this register enables and disables the ssi controller. [1] when disabled, all serial transfers are halted imm ediately. transmit and receive fifo buffers are cleared when the device is disabled. it is impossible to program some of the ssi control registers when enabled. 19.2.4 mwcr (0x0000000c) this register controls the direction of the da ta word for the half-duplex microwire serial protocol. [1] when enabled, the ssi controller checks for a ready stat us from the target slave, after the transfer of the last data/control bit, before clearing the busy status in the sr register: [2] when this bit is set to 0, the data word is received by the ssi macrocell from t he external serial device. when this bit is set to 1, the data word is transmitted from the ssi macrocell to the external serial device. [3] when sequential mode is used, only one control word is needed to transmit or receive a block of data words. when non-sequential mode is used, there must be a control word for each data word that is transmitted or received. table 232. ssienr name bit default r/w description - 31 - 01 0x0 - reserved ssi_en [1] 00 0x0 r/w enables and disables all ssi operations. table 233. mwcr name bit default r/w description - 31 - 03 0x0 - reserved mhs [1] 02 0x0 r/w used to enable and disable the ?busy/ready? handshaking interface for the microwire protocol. 0: handshaking interface is disabled 1: handshaking interface is enabled mdd [2] 01 0x0 r/w defines the direction of the data word when the microwire serial protocol is used. mwmod [3] 00 0x0 r/w defines whether the microwire transfer is sequential or non-sequential. 0: non-sequential transfer 1: sequential transfer free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 160 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.2.5 ser (0x00000010) the register enables the individual slave select output lines. up to 2 slave-select output signals are available on the ssi controller. you cannot write to this register when the ssi controller is busy. [1] when a bit in this register is set (1), the co rresponding slave select line from the master is activated when a serial transfer begins. it should be noted that setting or clearing bits in this register have no effect on the corresponding slav e select outputs until a transfer is started. before beginning a transfer, you should enable the bit in this register that corresponds to the slave device with which the master wants to communicate. when not operating in broadcast mode, only one bit in this field should be set. 19.2.6 baudr (0x00000014) the register derives the frequency of the serial clock that regulates the data transfer. the 16-bit field in this register defines the serial clock divider value. it is impossible to write to this register when the ssi controller is enabled. [1] the lsb for this field is always set to 0 and is una ffected by a write operation, which ensures an even value is held in this register. if the value is 0, the serial output clock (sclk_out) is disabled. the frequency of the sclk_out is derived from the following equation. (1) where sckdv is any even value betwe en 2 and 65534. for example, if fapb_clk = 100 mhz and sckdv = 4, then: (2) table 234. save-select output signals name bit default r/w description - 31 - 02 0x0 - reserved ser [1] 01 - 00 0x0 r/w each bit in this register corresponds to a slave select line (ss_x_n]) from the ssi master. 1: selected 0: not selected table 235. baudr name bit default r/w description - 31 - 16 0x0 - reserved sckdv [1] 15 - 00 0x0 r/w serial clock divider f sclk _out fapb _clk sckdv ------------------------------ - = f sclk _out 100 4 -------- - 25 mhz = = free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 161 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.2.7 txftlr (0x00000018) this register controls the threshold value for the transmit fifo memory. it is impossible to write to this register when the ssi controller is enabled. [1] controls the level of entries (or below) at which the transmit fifo controller triggers an interrupt. the fifo depth is 32. if you attempt to set this value greater t han or equal to the depth of the fifo, this field is not written and retains its current value. when the number of transmit fifo entries is le ss than or equal to this value, the transmit fifo empty interrupt is triggered. table 236. txftlr name bit default r/w description - 31 - 05 0x0 - reserved tft [1] 04 - 00 0x0 r/w 0000_0000: ssi_txe_intr is asserted when 0 data entries are present in transmit fifo 0000_0001: ssi_txe_intr is asserted when 1 or less data entry is present in transmit fifo 0000_0010: ssi_txe_intr is assert ed when 2 or less data entries are present in transmit fifo 0000_0011: ssi_txe_intr is asserted when 3 or less data entries are present in transmit fifo ? 1111_1100: ssi_txe_intr is asserted when 252 or less data entries are present in transmit fifo 1111_1101: ssi_txe_intr is asserted when 253 or less data entries are present in transmit fifo 1111_1110: ssi_txe_intr is asserted when 254 or less data entries are present in transmit fifo 1111_1111: ssi_txe_intr is asserted when 255 or less data entries are present in transmit fifo free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 162 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.2.8 rxftlr (0x0000001c) this register controls the threshold value for the receive fifo memory. it is impossible to write to this register when the ssi controller is enabled. [1] controls the level of entries (or above) at which the receive fifo controller tri ggers an interrupt. the fifo depth is configurable in the range 32. if you attempt to se t this value greater than the depth of the fifo, this field is not written and retains its current value. when the number of receive fifo entries is greater than or equal to this value + 1, the receive fifo full interrupt is triggered. 19.2.9 txflr (0x00000020) transmit fifo level register. 19.2.10 rxflr (0x00000024) receive fifo level register. table 237. rxftlr name bit default r/w description - 31 - 05 0x0 - reserved rft [1] 04 - 00 0x0 r/w 0000_0000: ssi_rxf_intr is asserted when 1 or more data entry is present in receive fifo 0000_0001: ssi_rxf_intr is asserted when 2 or more data entries are present in receive fifo 0000_0010: ssi_rxf_intr is asserted when 3 or more data entries are present in receive fifo 0000_0011: ssi_rxf_intr is asserted when 4 or more data entries are present in receive fifo ? 1111_1100: ssi_rxf_intr is asserted when 253 or more data entries are present in receive fifo 1111_1101: ssi_rxf_intr is asserted when 254 or more data entries are present in receive fifo 1111_1110: ssi_rxf_intr is asserted when 255 or more data entries are present in receive fifo 1111_1111: ssi_rxf_intr is asserted when 256 data entries are present in receive fifo table 238. transmit fifo level register name bit default r/w description - 31 - 06 0x0 - reserved txtft 05 - 00 0x0 r contains the number of va lid data entries in the transmit fifo table 239. rxflr name bit default r/w description - 31 - 06 0x0 - reserved rxtft 05 - 00 0x0 r contains the number of valid data entries in the receive fifo. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 163 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.2.11 sr(0x00000028) this is a read-only register used to indicate the current transfer status, fifo status, and any transmission/reception errors that may have occurred. the status register may be read at any time. none of the bits in this register request an interrupt. [1] this bit is set if the ssi master is actively transmi tting when another master selects this device as a slave. this informs the processor that the last data transfer was halted before completion: [2] set if the transmit fifo is empty when a transfer is started. this bit can be set only when the ssi controller is configured as a slave device. data from the previous transmiss ion is resent on the txe line: [3] when the receive fifo is completely full, this bit is set. when the receive fifo contains one or more empty location, this bit is cleared: 19.2.12 imr (0x0000002c) interrupt mask register. 19.2.13 isr (0x00000030) interrupt status register. 19.2.14 risr (0x00000034) raw interrupt status register. table 240. sr name bit default r/w description - 31 - 07 0x0 - reserved dcol [1] 06 0x0 rsr 0: no error 1: transmit data collision error txe [2] 05 0x0 r 0: no error 1: transmission error rff [3] 04 0x0 r 0: receive fifo is not full 1: receive fifo is full table 241. interrupt mask register name bit default r/w description - 31 - 06 0x0 - reserved mstim 05 0x1 r/w 0: ssi_mst_intr interrupt is masked 1: ssi_mst_intr interrupt is not masked rxfim 04 0x1 r/w 0: ssi_rxf_i ntr interrupt is masked 1: ssi_rxf_intr interrupt is not masked rxoim 03 0x1 r/w 0: ssi_rxo_intr interrupt is masked 1: ssi_rxo_intr interrupt is not masked table 242. raw interrupt name bit default r/w description - 31 - 06 0x0 - reserved mstir 05 0x0 r 0: ssi_mst_intr interrupt is not active prior to masking 1: ssi_mst_intr interrupt is active prior masking rxfir 04 0x0 r 0:ssi_rxf_intr interrupt is not active prior to masking 1: ssi_rxf_intr interrupt is active prior to masking free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 164 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.2.15 txoicr (0x00000038) transmit fifo overflow interrupt clear register. [1] a read from this register clears the ssi_t xo_intr interrupt; writing has no effect. 19.2.16 rxoicr (0x0000003c) receive fifo overflow interrupt clear register. [1] a read from this register clears the ss i_rxo_intr interrupt; writing has no effect. 19.2.17 rxuicr (0x00000040) receive fifo underflow interrupt clear register. [1] a read from this register clears the ss i_rxu_intr interrupt; writing has no effect. 19.2.18 msticr (0x00000044) multi-master interrupt clear register. [1] a read from this register clears the ssi_mst_intr interrupt; writing has no effect. rxoir 03 0x0 r 0: ssi_rxo_intr interrupt is not active prior to masking 1: ssi_rxo_intr interrupt is active prior masking rxuir 02 0x0 r 0:ssi_rxu_intr interrupt is not active prior to masking 1: ssi_rxu_intr interrupt is active prior to masking txoir 01 0x0 r 0: ssi_txo_intr interrupt is not active prior to masking 1: ssi_txo_intr interrupt is active prior masking txeir 00 0x0 r 0: ssi_txe_intr interrupt is not active prior to masking 1: ssi_txe_intr interrupt is active prior masking table 242. raw interrupt ?continued name bit default r/w description table 243. transmit fifo overfl ow interrupt clear register name bit default r/w description - 31 - 01 0x0 - reserved txoicr [1] 00 0x0 r this register reflects the status of the interrupt. table 244. receive fifo overfl ow interrupt clear register name bit default r/w description - 31 - 01 0x0 - reserved rxoicr [1] 00 0x0 r this register reflects the status of the interrupt. table 245. receive fifo underf low interrupt clear register name bit default r/w description - 31 - 01 0x0 - reserved rxoicr [1] 00 0x0 r this register reflects the status of the interrupt. table 246. multi-master interrupt clear register name bit default r/w description - 31 - 01 0x0 - reserved msticr [1] 00 0x0 r this register reflects the status of the interrupt. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 165 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.2.19 icr (0x00000048) interrupt clear register. [1] a read clears the ssi_txo_intr, ssi_ rxu_intr, ssi_rxo_intr, and the ssi_mst_ intr interrupts. writing to this register has no effect. 19.2.20 dmacr (0x0000004c) dma control register. 19.2.21 dmatdlr (0x00000050) dma transmit data level register. table 247. interrupt clear register name bit default r/w description - 31 - 01 0x0 - reserved icr [1] 00 0x0 r this register is set if any of the interrupts below are active. table 248. dma control register name bit default r/w description - 31 - 02 0x0 - reserved tdmae 01 0x0 r/w this bit enables/disables the transmit fifo dma channel: 0: transmit dma disabled 1: transmit dma enabled rdmae 00 0x0 r/w this bit enables/disables the receive fifo dma channel: 0: receive dma disabled 1: receive dma enabled table 249. dma transmit data level register name bit default r/w description - 31 - 05 0x0 - reserved tdmae [1] 04 - 00 0x0 r/w 0000_0000: dma_tx_req is asserted when 0 data entries are present in the receive fifo 0000_0001: dma_tx_req is asserted when 1 or less data entry is present in the receive fifo 0000_0010: dma_tx_req is asserted when 2 or less data entries are present in the receive fifo 0000_0011: dma_tx_req is asserted when 3 or less data entries are present in the receive fifo ? 1111_1100: dma_tx_req is asserted when 252 or less data entries are present in the receive fifo 1111_1101: dma_tx_req is asserted when 253 or less data entries are present in the receive fifo 1111_1110: dma_tx_req is asserted when 254 or less data entries are present in the receive fifo 1111_1111: dma_tx_req is asserted when 255 or less data entries are present in the receive fifo free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 166 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] this bit field controls the level at which a dma re quest is made by the transmit logic. it is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit fifo is equal to or belo w this field value, and tdmae = 1. 19.2.22 dmardlr (0x00000054) dma receive data level register. [1] this bit field controls the level at which a dma reques t is made by the receive logic. the watermark level = dmardl+1; that is, dma_rx_req is generated when the num ber of valid data entries in the receive fifo is equal to or above this field value + 1, and rdmae=1. 19.2.23 reserved (0x00000058~0x0000005c) 19.2.24 dr (0x00000060 to 0x0000009c) the ssi data register is a 16-bit read/write buff er for the transmit/rec eive fifos. when the register is read, data in the receive fifo buffer is accessed. when it is written to, data are moved into the transmit fifo buffer; a writ e can occur only when ssi_en = 1. fifos are reset when ssi_en = 0. table 250. dma receive data level register name bit default r/w description - 31 - 05 0x0 - reserved rdmae [1] 04 - 00 0x0 r/w 0000_0000: dma_rx_req is asserted when 1 or more data entries are present in the receive fifo 0000_0001: dma_rx_req is asserted when 2 or more data entries are present in the receive fifo 0000_0010: dma_rx_req is asserted when 3 or more data entries are present in the receive fifo 0000_0011: dma_rx_req is asserted when 4 or more valid data entries are present in the receive fifo ? 1111_1100: dma_rx_req is asserted when 253 or more data entries are present in the receive fifo 1111_1101: dma_rx_req is asserted when 254 or more data entries are present in the receive fifo 1111_1110: dma_rx_req is asserted when 255 or more data entries are present in the receive fifo 1111_1111: dma_rx_req is asserted when 256 data entries are present in the receive fifo table 251. data register name bit default r/w description - 31 - 16 0x0 - reserved dr 15 - 00 0x0 r/w when writing to this regi ster, the data must be right-justified. read data is automatical ly right-justified. read: receive fifo buffer write: transmit fifo buffer free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 167 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 19.3 i/o timing table 252. i/o timing signal symbol min max unit ssic_i_rxd t setup --ns ssic_i_rxd t hold --ns free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 168 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 20. advanced gene ral purpose output the advanced general purpose output controller provides a 128-bit pattern buffer per port to output a series of user-defined bits for any protocol such as i2c, spi. there are up to 8 output ports which are shared with gpio[7:0]. please refer to table 186 . 20.1 features to be defined. 20.1.1 port control type there are two port control types, data contro l and data output enable control. it needs external pull-up or pull-down resistors when using data output enable control type. 20.1.2 pattern repeat the pattern repeat function is used to send the same pattern with a specific number of times up to 409 times. this could ease the host processor loading. 20.1.3 non-stop pattern to output non-stop pattern, configure the repeat time to 0xfff and the data pattern will be output continuously until it is disabled. 20.2 memory map register 20.2.1 agpoc_version (0x00000000) version information register. 20.2.2 agpoc_ctrl(0x00000004) control register. table 253. version information register name bit default r/w description major_version 31 - 24 0x01 r major version number minor_version 23 - 16 0x00 r minor version number build_version 15 - 08 0x00 r build version number revision 07 - 00 0x05 r revision number table 254. control register name bit default r/w description - 31 - 08 0x0 - reserved enable 07 - 00 0x0 r/w 1?b0: disable and clear status register. 1?b1: start to output the data pattern. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 169 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 20.2.3 agpoc_status(0x00000008) status register. 20.2.4 agpoc_intr_mask (0x0000000c) interrupt mask register. 20.2.5 agpoc_dft_data_oe_n (0x00000010) default data output enable_n port register. 20.2.6 agpoc_dft_data (0x00000014) default data port value register. 20.2.7 agpoc_ctrl_port_sel (0x00000018) control port selection register. table 255. status register name bit default r/w description - 31 - 08 0x0 - reserved op_compt 07 - 00 0x0 r/w operation complete status. write enable register with 1?b0 to clear this register. table 256. interrupt mask register name bit default r/w description - 31 - 08 0x0 - reserved intr_mask 07 - 00 0x0 r/w interrupt mask control bit. 1?b0: enable interrupt 1?b1: disable interrupt table 257. default data output enable_n port register name bit default r/w description - 31 - 08 0x0 - reserved dft_data_oe_n 07 - 00 0x0 r/w default value for data output enable_n port. 1?b0: enable output 1?b1: disable output table 258. default data port value register. name bit default r/w description - 31 - 08 0x0 - reserved dft_data 07 - 00 0x0 r/w default value for data port table 259. control port selection register name bit default r/w description - 31 - 08 0x0 - reserved ctrl_port_sel 07 - 00 0x0 r/w control port selection free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 170 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 20.2.8 agpoc_bit_n_pattern _0 (0x0000001c + n*28) port n pattern 0 register, n = 0~7. 20.2.9 agpoc_bit_n_pattern _1 (0x00000020 + n*28) port n pattern 1 register, n = 0~7. 20.2.10 agpoc_bit_n_pattern_2 (0x00000024 + n*28) port n pattern 2 register, n = 0~7. 20.2.11 agpoc_bit_n_ pattern _3 (0x00000028 + n*28) port n pattern 3 register, n = 0~7. 20.2.12 agpoc_bit_n_period (0x0000002c +n*28) port n period register, n = 0~7. 20.2.13 agpoc_bit_n_length (0x00000030) port n length register, n = 0~7. table 260. port n pattern 0 register name bit default r/w description pattern_0 31 - 00 0x0 r/w data pattern [31:0] table 261. port n pattern 1 register name bit default r/w description pattern_1 31 - 00 0x0 r/w data pattern [63:32] table 262. port n pattern 2 register name bit default r/w description pattern_2 31 - 00 0x0 r/w data pattern [95:64] table 263. port n pattern 3 register name bit default r/w description pattern_3 31 - 00 0x0 r/w data pattern [127:96] table 264. port n period register name bit default r/w description period 31 - 00 0x0 r/w output data period. unit apb cycles. table 265. port n length register name bit default r/w description - 31 - 07 0x0 - reserved length 06 - 00 0x0 r/w output (length+1) bits in the 128-bit pattern register free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 171 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 20.2.14 agpoc_bit_n_intvrepeat (0x00000034 + n*28) port n repeat and interval register, n = 0~7. 20.2.15 port control type there are two types of port control mechanism depicted below. it needs external pull-up or pull-down resistors when ctrl_port_sel is 1?b1. 20.3 programming figure 45 shows the timing representation of each parameter such as period, length, interval, repeat registers. the repeat function is used to s end a pattern repeatedly in a single operation. after (lengt h+1) bits are sent, the outp ut will be kept in the default state, dft_data or dft_data_oe_n depe nding on the ctrl_port_sel until next operation or repeat pr evious operation again if repeat is not zero. use i 2 c protocol as an example. the pattern register is shifted out from lsb to msb. this example shows only 32-bit pattern registers. it is a read operation to the device address 7?b1100111. since there is ack or nack from the device, it had better to make the output table 266. port n repeat and interval register name bit default r/w description repeat 31 - 20 0x0 r/w repeat times for the same data pattern. (repeat+1) times will be executed in one operation. when this value is set to 0xfff, the repeat time will be infinite. interval 19 - 00 0x0 r/w the interval for one complete data pattern. unit: bit time. must be larger or equal to length register. fig 44. illustration of the port control types 001aam970 agpoc_dft_data[n] register ctrl_port_sel[n] = 1'b1 port n port n 128-bit pattern register agpoc_dft_data_oe_n[n] register ctrl_port_sel[n] = 1'b0 port n port n 128-bit pattern register fig 45. timing representation of each parameter 001aam971 1 length interval repeat 0 001 period repeat 1 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 172 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc tri-state at those cycles. but it is unable to know if ack or nack is received because apgoc does not handle the input data. after fini shing the register sett ings, write 1?b1 to the enable bit of the related ports and the operation is started. the interrupt could be used to notify the host processor when the operation is completed. to de-assert the interrupt, the host processor needs to write 1?b0 to the enable bit of the related ports to clear the interrupt. port 0: used as scl pattern register 0 = 0100_1001_0010_0100_1001_0010_0000_1111 ctrl_port_sel = 1?b1 agpoc_dft_data = 1?b0 a pull-up resistor is placed at the output port 0. port 1: used as sda pattern register 0 = 0001_1111_1111_0000_0011_1111_0000_0011 ctrl_port_sel = 1?b1 agpoc_dft_data = 1?b0 a pull-up resistor is placed at the output port 1. fig 46. example of the i 2 c protocol 001aam972 port 0 (scl) start driven by the pull-up resistor device address: 7'b1100111 r/w port 1 (sda) driven by the output port free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 173 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 21. irda 21.1 general description the irda controller is designed for receiving irda commands from the consumer remote controller. it receives the signal from the external irda demodulator and the decoded data is sent to the application through apb interfac e. a variety of remote control protocols are supported such as nec, toshiba, matsus hita, philips rc5, sharp and sony sirc protocols. 21.2 features the irda controller su pports the following: ? bi-phase modulation, pulse distance modulation, and pulse width modulation. ? de-bounce function for the input irda signal. 21.2.1 modulation type supports bi-phase modulation, pulse distance modulation and pulse width modulation 21.2.2 de-bounce supports be-bounce function for the input irda signal. 21.3 memory map register 21.3.1 irdac version (0x00000000) version information register. 21.3.2 irdac_ctrl (0x00000004) control register. table 267. version information register name bit default r/w description major revision 31 - 24 0x04 r major version number minor_revision 23 - 16 0x01 r minor version number build version 15 - 08 0x00 r build version number revision 07 - 00 0x04 r revision number table 268. control register name bit default r/w description - 31 - 22 0x0 - reserved data_num 21 - 16 0x0 r/w data number, number of bits in one data real data number = data_num + 1 - 15 - 12 0x0 - reserved free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 174 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 21.3.3 irdac_stat (0x00000008) status register. 21.3.4 irdac_rbr_lo (0x0000000c) lower bits of the received data. [1] users can read this register to get low 32-bit data latched in the fifo. 21.3.5 irdac_rbr_hi (0x00000010) higher bits of the received data. [1] users can read this register to ge t high 32-bit data latched in the fifo. table 269. status register name bit default r/w description - 31 - 12 0x0 - reserved err_bit 11 - 07 0x0 r the bit number of the a command sequence where a error occurs (or does not correspond to a specific protocol) err_state 06 - 04 0x0 r the state where a error occurs (or does not correspond to a specific protocol) 3?b000: no error 3?b001: reserved 3?b010: error occurs in burst_len 3?b011: error occurs in silen_len 3?b100: error occurs in repeat_len 3?b101: error occurs in modu_len 3?b110: error occurs in logic_len 3?b111: reserved repeat 03 0x0 r repeat flag fifo_full 02 0x0 r ifo full flag 1?b0: fifo is not full 1?b1: fifo is full fifo_not_empty 01 0x0 r fifo not empty flag 1?b0: fifo is empty 1?b1: fifo is not empty op_cmpt 00 0x0 r set when irdac operation is complete. 1?b0: irdac is busy or idle. 1?b1: irdac operation is complete. table 270. lower bits of received data name bit default r/w description rbr_lo [1] 31 - 00 0x0 r read port of fifo. table 271. higher bits of the received data name bit default r/w description rbr_hi [1] 31 - 00 0x0 r read port of fifo. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 175 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 21.3.6 irdac_timing (0x00000014) timing register. 21.3.7 irdac_timing_ext(0x00000018) extended timing register. 21.3.8 irdac_interval_freq_div (0x0000001c) frequency divisor and the repeat code interval. [1] frequency = frequency of apb_clk / (freq_div+1). [2] interval = (repeat_interval ir sampling time) table 272. timing register name bit default r/w description - 31 - 24 0x00 - reserved modu_len 23 - 16 0x00 r/w modulation length. time of modulation = (mo du_len ir sampling time) zero_len 15 - 08 0x00 r/w logic zero length. time of logic zero = (zer o_len ir sampling time) one_len 07 - 00 0x00 r/w logic one length. time of logic one = (one_len ir sampling time) table 273. extended timing register name bit default r/w description - 31 - 28 0x0 - reserved debounce 27 - 24 0x0 r/w de-bounce length. time of repeat = (debo unceir sampling time) repeat_len 23 - 16 0x00 r/w repeat length. time of repeat = (repeat_lenir sampling time) silen_len 15 - 08 0x00 r/w silence length. time of silence = (silen_lenir sampling time2) burst_len 07 - 00 0x00 r/w burst length. time of start = (burst_len ir sampling time 4) table 274. frequency divisor and repeat code interval name bit default r/w description freq_div 31 - 16 0x0000 r/w the frequency divisor that generates the ir sampling frequency. repeat_interval 15 - 00 0x0000 r/ w defined as the interval from the last bit of the previous command and the first bit of the next repeated command interval of two consecutive data package. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 176 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 21.4 programming the sampling clock of irda si gnal is derived from the inpu t apb clock. the frequency of sampling clock, which is denoted as fs, is equal to the frequency of fapb_clk/(freq_div+1). th e sampling time ts is defined by 1/ fs. figure 47 illustrates the timing definition of data bi ts in three kinds of modulation. in all types of modulation, the field modu_len, wh ich means the length of modulation time, must be filled. modu_len is defined by td/ts, where td is time of modulation shown in figure 47 . note that the definition of modulation ti me is different in three modulations. td is the interval of ?mark? part (low level) in pulse distance modulation, whereas td is the interval of ?space? part (high level) in pulse width modulation. in bi-phase modulation, td is half of the bit time. since the logical one an d zero are defined by the phase of the signal in the bi-phase modulation, it does not ne ed to define the logical one/zero length. on the other hand, the time of logical one to and logical zero tz should be defined in the other two modulations. sim ilar to definition of modu_l en, one_len is defined by to/ts, and zero_len is defined by tz/ts. also note that the definitions of the interval of logical one/zero are different in pulse dist ance modulation and pulse width modulation. see figure 47 for details. fig 47. timing definition of data bits in three kinds of modulation (a) pulse distance modulation (b) pulse width modula tion (c) bi-phase modulation. 001aam973 (a) (b) (c) logic "1" logic "0" logic "1" logic "0" logic "0" t m t m t m t m t m t m t 0 t 0 t z t z free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 177 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc in nec and sony sirc protocol, there is the start code, and burst_mode_en should be enabled. once burst_mode_en is enabl ed, the irda controlle r will be idle until the start code with correct timing comes. for the start code, it has two parts: one is burst part and one is silent part. the burst part is low level at the receiver side and burst_len is defined by tb/4ts, where tb is the burst time . (9ms for nec protocol and 2.4ms for sony sirc protocol) the silent part, which follows the burst part, is high level and silen_len is defined by tl/2ts, where tl is the silent time. (4.5ms for nec protocol and 600ms for sony sirc protocol) figure 48 shows the timing definition of start code. in nec protocol, the repeat code is transmi tted for as long as the key remains down. let the time of silent part of the repeat code be tr, then repeat_len is defined by tr/2ts. the timing definition of repe at code is illustrated in figure 49 . in addition, repeat_interval can be set for the interv al of two consecut ive commands when the key on the remote control is held down. as long as the interval of two consecutive commands meets the repeat interval, or repeat code occurs, the repeat flag in register irdac_stat will be 1. fig 48. timing definition of start and repeat code 001aam974 start code repeat code t b t b t l t r (a) (b) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 178 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22. mobile storage host controller 22.1 general description the mobile storage host contro ller (mshc) is a secure digita l multimedia card controller, which simultaneously supports secure digi tal memory (sd mem), secure digital i/o (sdio), and multimedia cards (mmc). 22.2 features ? supports secure digital memory version 2.0 protocol commands ? supports secure digital i/o version 2.0 protocol commands ? supports multimedia card version 4.3 protocol commands ? supports half-duplex internal dma block with descriptor-based linked list ? supports combined 16-entry tx/rx fifo 22.3 memory map register 22.3.1 ctrl (0x00000000) control register. table 275. control register name bit default r/w description - 31 - 26 - - reserved use_internal_dmac 25 0x0 r/w use internal dma engine. 1?b0: the host performs data transfers through the slave interface. 1?b1: internal dmac us ed for data transfer. enable_od_pullup 24 0x1 r/w external cmd open-drain pull-up 1?b0: disable. 1?b1: enable. - 23 - 12 - - reserved ceata_device_interrupt_status [1] 11 0x0 r/w 1'b0: interrupts not enabled in ce-ata device (nien = 1 in ata control register). 1'b1: interrupts are enabled in ce-ata device (nien = 0 in ata control register). send_auto_stop_ccsd [2] 10 0x0 r/w 1'b0: clear bit if mshc does not reset the bit. 1'b1: send internally generated stop after sending ccsd to ce-ata device. send_ccsd [3] 09 0x0 r/w 1'b0: clear bit if mshc does not reset the bit. 1'b1: send command completion signal disable (ccsd) to ce-ata device. abort_read_data [4] 08 0x0 r/w 1'b0: no change. 1'b1: abort read send_irq_response [5] 07 0x0 r/w 1'b0: no change. 1'b1: send auto irq response. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 179 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] software should appropriately write to this bit after power-on reset or any other reset to ce-ata device. after reset, usual ly ce-ata device interrupt is disabled (nien = 1). if the host enables ce-ata device interrupt, then so ftware should set this bit [2] note: always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. when set, mshc automatically s ends internally generated stop command (c md12) to ce-ata device. after sending internally-generated stop command, auto command done (acd) bit in rintsts is set and generates interrupt to host if auto command done interrupt is not masked. after sending the ccsd, mshc automatically cl ears send_auto_stop_ccsd bit. [3] when set, mshc sends ccsd to ce-ata device. software sets th is bit only if current command is expecting ccs (that is, rw_blk ) and interrupts are enabled in ce-ata device. once the ccsd pattern is sent to device, mshc au tomatically clear s send_ccsd bit. it also sets command done (cd) bit in rintsts register and generates interrupt to host if command done interrupt is not masked. no te that once the send_ccsd bit is set, it takes two card clock cyc les to drive the ccsd on the cmd line. due to this, during the b oundary conditions it may happen that ccsd is sent to the ce-ata device, even if the device signalled ccs. [4] after suspend command is issued during read-transfer, softwa re polls card to find when suspend happened. once suspend occurs , software sets bit to reset data state-machine, which is wait ing for next block of data. bit automatically clears once data stat e machine resets to idle. used in sdio card suspend sequence. [5] bit automatically clears once response is sent. to wait for mmc card interrupts, host issues cmd40, and mshc waits for inter rupt response from mmc card(s). in meantime, if host wants mshc to ex it waiting for interrupt state, it can set this bit, at which t ime mshc command state-machine sends cmd40 res ponse on bus and returns to idle state. [6] valid only if mshc configured for external dma interface. even when dma mode is enabled, host can still push/pop data into o r from fifo; this should not happen during the normal operation. if ther e is simultaneous fifo access from host/dma, the data coherenc y is lost. also, there is no arbitration inside ms hc to prioritize simultaneous host/dma access. [7] the int port is 1 only when this bit is 1 and one or more unmasked interrupts are set. [8] to reset dma interface, firmware should set bit to 1. this bit is auto-cleared after two ahb clocks. [9] to reset fifo, firmware should set bit to 1. this bit is auto-cleared after completion of reset operation. [10] to reset controller, firmware should set bit to 1. this bit is auto-cleared after two ahb and two cclk_in clock cycles. this resets: * card interface state machines * abort_read_data, send_irq_response, and read_wait bits of ctrl register * start_cmd bit of cmd register does not affect any registers or dma interface, or fifo or host interrupts 22.3.2 reserved (0x00000004) this register is reserved. read_wait 06 0x0 r/w 1'b0: clear read wait. 1'b1: assert read wait. for sending read-wait to sdio cards. dma_enable [6] 05 0x0 r/w 1'b0: disable dma transfer mode. 1'b1: enable dma transfer mode. int_enable [7] 04 0x0 r/w global interrupt enable/disable bit: 1'b0: disable interrupts. 1'b1: enable interrupts. 03 0x0 r/w reserved dma_reset [8] 02 0x0 r/w 1'b0: no change. 1'b1: reset internal dma interface control logic fifo_reset [9] 01 0x0 r/w 1'b0: no change. 1'b1: reset to data fifo to reset fifo pointers controller_reset [10] 00 0x0 r/w 1'b0: no change. 1'b1: reset mshc. table 275. control register ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 180 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.3 clkdiv (0x00000008) clock divider register. [1] clock division is 2*n. for example, value of 0 me ans divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ?f f? means divide by 2*255 = 510, and so on. 22.3.4 reserved (0x0000000c) this register is reset to 0x0 and should not be altered. 22.3.5 clkena (0x00000010) clock enable register [1] stops clock when card in idle (should be normally set to only mmc and sd memory cards; for sdio cards, if interrupts must be detected, clock should not be stopped). [2] up to 16 sd card clocks and one mmc card clock supported. 22.3.6 tmout (0x00000014) timeout register. [1] the same value also used for data starvation by host timeout. value is in number of card output clocks. [2] value is in number of card output clocks. table 276. clock divider register name bit default r/w description - 31 - 08 - - reserved clk_divider [1] 07 - 00 0x0 r/w clock divider value. table 277. clock enable register name bit default r/w description - 31 - 17 - - reserved cclk_low_power 16 0x0 r/w low-power control for sd card clock and mmc card clock. 1'b0: non-low-power mode 1'b1: low-power mode [1] 15 - 01 0x0 reserved cclk_enable [2] 00 0x0 r/w clock-enable control. 1'b0: clock disabled 1'b1: clock enabled table 278. timeout register name bit default r/w description data_timeout [1] 31 - 08 0xffffff r/w value for card data read timeout. response_timeout [2] 07 - 00 0x40 r/w response timeout value. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 181 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.7 ctype (0x00000018) card type register. 22.3.8 blksiz (0x0000001c) block size register 22.3.9 bytcnt (0x00000020) byte count register. [1] integer multiple of block size for block transfers. fo r undefined number of byte transfers, byte count should be set to 0. when byte count is set to 0, it is res ponsibility of host to explicit ly send stop/abort command to terminate data transfer. table 279. card type register name bit default r/w description - 31 - 01 0x0 - reserved card_width 00 0x0 r/w indicates if card is 1-bit or 4-bit: 1'b0: 1-bit mode. 1'b1: 4-bit mode table 280. block size register name bit default r/w description - 31 - 16 - - reserved block_size 15 - 00 0x200 r/w block size table 281. byte count register name bit default r/w description byte_count [1] 31 - 00 0x200 r/w number of bytes to be transferred. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 182 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.10 intmask (0x00000024) interrupt ma sk register. 22.3.11 cmdarg (0x00000028) command argument register. table 282. interrupt mask register name bit default r/w description - 31 - 17 - - reserved sdio_int_mask 16 0x0 r/w mask sdio interrupts when masked, sdio interrupt detection for that card is disabled. 1'b0: mask the interrupt. 1'b1: enable the interrupt. int_mask 15 - 00 0x0 r/w bits used to mask unwanted interrupts. 1'b0: mask the interrupt. 1'b1: enable the interrupt. bit 15 ? end-bit error (r ead)/write no crc (ebe) bit 14 ? auto command done (acd) bit 13 ? start-bit error (sbe) bit 12 ? hardware locked write error (hle) bit 11 ? fifo underrun/overrun error (frun) bit 10 ? data starvati on-by-host timeout (hto) bit 9 ? data read timeout (drto) bit 8 ? response timeout (rto) bit 7 ? data crc error (dcrc) bit 6 ? response crc error (rcrc) bit 5 ? receive fifo data request (rxdr) bit 4 ? transmit fifo data request (txdr) bit 3 ? data transfer over (dto) bit 2 ? command done (cd) bit 1 ? response error (re) bit 0 ? card detect (cd) table 283. command argument register name bit default r/w description cmd_arg 31 - 00 0x0 r/w value indicates command argument to be passed to card free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 183 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.12 cmd (0x0000002c) command register. table 284. command register name bit default r/w description start_cmd [1] 31 0x0 r/w start command. 30 - 28 - - reserved boot_mode 27 0x0 r/w boot mode 1'b0: mandatory boot operation 1'b1: alternate boot operation disable_boot [2] 26 0x0 r/w disable boot. expect_boot_ack [3] 25 0x0 r/w expect boot acknowledge. enable_boot [4] 24 0x0 r/w enable boot ccs_expected [5] 23 0x0 r/w 1'b0: interrupts are not enabled in ce-ata device (nien = 1 in ata control register), or command does not expect ccs from device 1'b1: interrupts are enabled in ce-ata device (nien = 0), and rw_blk command expects command completion signal from ce-ata device read_ceata_device [6] 22 0x0 r/w 1'b0: host is not performing read access (rw_reg or rw_blk) towards ce-ata device 1'b1: host is performing read access (rw_reg or rw_blk) towards ce-ata device update_clock_registers_only [7] 21 0x0 r/w 1'b0: normal command sequence. 1'b1: do not send commands, just update clock register value into card clock domain. card_number 20 - 16 0x0 r/w must be 0x0 send_initialization [8] 15 0x0 r/w 1'b0: do not send initialization sequence (80 clocks of 1) before sending this command. 1'b1: send initialization sequence before sending this command. stop_abort_cmd 14 0x0 r/w 1'b0: neither stop nor abort command. [9] 1'b1: stop or abort command intended to stop current data transfer in progress. [10] wait_prvdata_complete [11] 13 0x0 r/w the wait_prvdata_complete = 0 option send_auto_stop [12] 12 0x0 r/w 1'b0: no stop command sent at end of data transfer. 1'b1: send stop command at end of data transfer. transfer_mode 11 0x0 r/w 1'b0: block data transfer command 1'b1: stream data transfer command don?t care if no data expected. read/write 10 0x0 r/w 1'b0: read from card 1'b1: write to card don?t care if no data expected from card. data_expected 09 0x0 r/w 1'b0: no data transfer expected (read/write). 1'b1: data transfer expected (read/write). check_response_crc [13] 08 0x0 r/w 1'b0: do not check response crc. 1'b1: check response crc. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 184 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] once command is taken by ciu, bit is cl eared. when bit is set, host should not attempt to write to any command registers. if write is attempted, hardware lock error is set in raw interrupt register . once command is sent and response is received from sd_mmc_ceat a cards, command done bit is set in raw interrupt register. [2] when software sets this bit along with start_cmd, ciu terminates the boot operation. do not set disable_boot and enable_boot together. [3] when software sets this bit along with enable_cmd, ciu expects a boot acknowledge start pattern of "0-1-0" from the selected card. [4] this bit should be set only for mandatory boot mode. when softwa re sets this bit along with start_cmd, ciu starts the boot s equence for the corresponding card by asserting the cmd line low. do not set disable_boot and enable_boot together. [5] if the command expects command completion signal (ccs) from t he ce-ata device, the software should set this control bit. msh c sets data transfer over (dto) bit in rintsts register and generates interrupt to host if data transfer over interrupt is not ma sked. [6] software should set this bit to indicate that ce-ata device is being accessed for read transfer. this bit is used to disable read data timeout indication while performing ce-ata read transfers. maximum value of i/o tr ansmission delay can be no less than 10 secon ds. mshc should not indicate read data timeout while waiting for data from ce-ata device [7] changes card clocks; provided in order to change clock frequency or st op clock without having to send command to cards. when bit is set, there are no command done interrupts because no command is sent to sd_mmc_ceata cards. [8] after power on, 80 clocks must be sent to card for init ialization before sending any commands to card. bit should be set whi le sending first command to card so that controller will initialize cloc ks before sending command to card. this bit should not be set for either of the boot modes (alternate or mandatory). [9] to stop current data transfer in progress. if abort is sent to function-number currently selected or not in data-transfer mo de, then bit should be set to 0. [10] when open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bi t should be set so that command/data state-machines of ciu can return correc tly to idle state. this is also applicable for boot mode transf ers. to abort boot mode, this bit should be set along with cmd[26] = disable_boot. [11] this is typically used to quer y status of card during data transfer or to stop current data transfer; card_number should be same as in previous command. [12] when set, mshc sends stop command to sd_mmc_ceata cards at end of data transfer. refer to table 212 auto-stop generation to determine: * when send_auto_stop bit should be set, since so me data transfers do not need explicit stop commands * open-ended transfers that software should explicitly send to stop command additionally, when ?resume? is sent to resume ? suspended memory access of sd-combo card ? bit should be set correctly if suspended data transfer needs send_auto_stop. don't care if no data expected from card [13] some of command responses do not return valid crc bits. so ftware should disable crc checks for those commands in order to disable crc checking by controller. 22.3.13 resp0 (0x00000030) response register 0. response_length 07 0x0 r/w 1'b0: short response expected from card. 1'b1: long response expected from card. response_expect 06 0x0 r/w 1'b0: no response expected from card. 1'b1: response expected from card. cmd_index 05 - 00 0x0 r/w command index table 284. command register ?continued name bit default r/w description table 285. response register 0 name bit default r/w description response_0 31 - 00 0x0 r bi t[31:0] of response free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 185 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.14 resp0 (0x00000030) response register 0. 22.3.15 resp1 (0x00000034) response register 1. [1] when ciu sends auto-stop command, then response is saved in register . response for previous command sent by host is still preserved in response 0 register. 22.3.16 resp2 (0x00000038) response register 2. 22.3.17 resp3 (0x0000003c) response register 3. table 286. response name bit default r/w description response_0 31 - 00 0x0 r bit[31:0] of response table 287. response register 1 name bit default r/w description response_1 [1] 31 - 00 0x0 r register represents bit[63:32] of long response. table 288. response register 2 name bit default r/w description response_2 31 - 00 0x0 r bit[95: 65] of long response table 289. response register 3 name bit default r/w description response_3 31 - 00 0x0 r bit[127:96] of long response free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 186 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.18 mintsts (0x00000040) masked interrupt status register. table 290. masked interrupt status register name bit default r/w description - 31 - 17 - - reserved sdio_interrupt 16 0x0 r inte rrupt from sdio card. sdio interrupt for card enabled only if corresponding sdio_int_mask bit is set in interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). 1'b0: no sdio interrupt from card 1'b1: sdio interrupt from card in mmc-ver3.3-only mode, bits always 0. int_status 15 - 00 0x0 r interrupt enabled only if co rresponding bit in interrupt mask register is set. bit 15 ? end-bit error (r ead)/write no crc (ebe) bit 14 ? auto command done (acd) bit 13 ? start-bit error (sbe) bit 12 ? hardware locke d write error (hle) bit 11 ? fifo underrun/overrun error (frun) bit 10 ? data starvation by host timeout (hto) bit 9 ? data read timeout (drto) bit 8 ? response timeout (rto) bit 7 ? data crc error (dcrc) bit 6 ? response crc error (rcrc) bit 5 ? receive fifo data request (rxdr) bit 4 ? transmit fifo data request (txdr) bit 3 ? data transfer over (dto) bit 2 ? command done (cd) bit 1 ? response error (re) bit 0 ? card detect (cd) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 187 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.19 rintsts (0x00000044) interrupt status register. table 291. interrupt status register name bit default r/w description -31 - 17--reserved sdio_interrupt 16 0x0 r/w interrupt from sdio card. writes to these bits clear them. value of 1 clears bit and 0 leaves bit intact. 1'b0: no sdio interrupt from card 1'b1: sdio interrupt from card in mmc-ver3.3-only mode, bits always 0. bits are logged regardless of interrupt-mask status. int_status 15 - 00 0x0 r/w writes to bits clear status bit. value of 1 clears status bit, and value of 0 leaves bit intact. bits are logged regardless of interrupt mask status. bit 15 ? end-bit error (r ead)/write no crc (ebe) bit 14 ? auto command done (acd) bit 13 ? start-bit error (sbe) bit 12 ? hardware locked write error (hle) bit 11 ? fifo underrun/overrun error (frun) bit 10 ? data starvation-by-host timeout (hto) bit 9 ? data read timeout (drto)/boot data start (bds) bit 8 ? response timeout (rto)/boot ack received (bar) bit 7 ? data crc error (dcrc) bit 6 ? response crc error (rcrc) bit 5 ? receive fifo data request (rxdr) bit 4 ? transmit fifo data request (txdr) bit 3 ? data transfer over (dto) bit 2 ? command done (cd) bit 1 ? response error (re) bit 0 ? card detect (cd) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 188 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.20 status (0x00000048) status register. [1] note there are 19 command fsm states. the status register (7:4) has 4 bits to represent the command fsm states, so status 0 represents four states. table 292. status register name bit default r/w description - 31 - 30 - - reserved fifo_count 29 - 17 0x0 r fifo count ? nu mber of filled locations in fifo. response_index 16 - 11 0x0 r index of previous resp onse, including any auto-stop sent by core. data_state_mc_busy 10 0x0 r data transmit or receive state-machine is busy. data_busy 09 - r inverted version of raw selected card_data[0]. 1'b0: card data not busy. 1'b1: card data busy data_3_status 08 - r raw selected card_dat a[3]; checks whether card is present. 1'b0: card not present. 1'b1: card present. command_fsm_states [1] 07 - 04 0x0 r command fsm states: 4'b0000 ? idle/wait for ccs/send ccsd/boot mode 4'b0001 ? send init sequence 4'b0010 ? tx cmd start bit 4'b0011 ? tx cmd tx bit 4'b0100 ? tx cmd index + arg 4'b0101 ? tx cmd crc7 4'b0110 ? tx cmd end bit 4'b0111 ? rx resp start bit 4'b1000 ? rx resp irq response 4'b1001 ? rx resp tx bit 4'b1010 ? rx resp cmd idx 4'b1011 ? rx resp data 4'b1100 ? rx resp crc7 4'b1101 ? rx resp end bit 4'b1110 ? cmd path wait ncc 4'b1111 ? wait; cmd-to-response turnaround fifo_full 03 0x0 r fifo is full status fifo_empty 02 0x0 r fifo is empty status fifo_tx_watermark 01 0x1 r fifo reached transmit watermark level; not qualified with data transfer fifo_rx-watermark 00 0x1 r fifo reached receiv e watermark level; not qualified with data transfer. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 189 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.21 fifoth (0x0000004c) fifo threshold watermark register. [1] in non-dma mode, when receiver fifo threshold (rxdr) inte rrupt is enabled, then interrupt is generated instead of dma reques t. during end of packet, interrupt is not generated if threshold pr ogramming is larger than any rema ining data. it is responsibili ty of host to read remaining bytes on seeing data transfer done interrupt. in dm a mode, at end of packet, even if remaining bytes are less th an threshold, dma request does single transfers to flush out any remaining bytes before data transfer done interrupt is set. rx_wmark<=14, 7 is recommended. note that in dma mode during ccs time-out, the dma does not generate the request at the end of packet, even if remaining bytes are less than threshold. in th is case, there will be some data left in the fifo. it is the r esponsibility of the application to reset the fifo after the ccs timeout [2] in non-dma mode, when transmit fifo threshold (txdr) inte rrupt is enabled, then interrupt is generated instead of dma reques t. during end of packet, on last interrupt, host is responsible for filling fifo with only required remaining bytes (not before fi fo is full or after ciu completes data transfers, because fifo may not be empty). in dma mode, at end of packet, if last transfer is less tha n burst size, dma controller does single cyc les until required bytes are transferre d. tx_wmark >= 1, 8 is recommended. 22.3.22 cdetect (0x00000050) card detect register. 22.3.23 wrtprt (0x00000054) receive fifo configuration register. table 293. fifo threshold watermark register name bit default r/w description - 31 - 31 - - reserved dw_dma_multiple_ transaction_size 30 - 28 0x0 r/w burst size of multiple transaction. 8 transfers recommended. 3'b000: 1 transfer 3'b001: 4 transfers 3'b010: 8 transfers 3'b011: 16 transfers 3'b100: 32 transfers 3'b101: 64 transfers 3'b110: 128 transfers 3'b111: 256 transfers rx_wmark [1] 21 - 16 0xf r/w fifo threshold watermark level when receiving data to card. - 15 - 12 - - reserved tx_wmark [2] 11 - 00 0x0 r/w fifo threshold watermark level when transmitting data to card. table 294. card detect register name bit default r/w description - 31-01 - - reserved card_detect_n 00-00 - r value on card_detect_n input ports; read-only bits. 1?b0 represents presence of card table 295. receive fifo configuration register name bit default r/w description - 31 - 01 - - reserved write_project 00 - r value on card_write_prt inpu t ports; 1'b1 represents write protection. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 190 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.24 reserved (0x00000058) this register is reserved. 22.3.25 tcbcnt (0x0000005c) transferred ciu card byte count register. 22.3.26 tbbcnt (0x00000060) transferred host to biu-fi fo byte count register. 22.3.27 debnce (0x00000064) transferred host to biu-fi fo byte count register. 22.3.28 usrid (0x00000068) user id register. 22.3.29 verid (0x0000006c) version id register. 22.3.30 reserved (0x00000070~0x0000007c) this register is reserved. table 296. transferred ciu card byte count register name bit default r/w description trans_card_byte_count 31 - 00 0x0 r number of bytes transferred by ciu unit to card. table 297. transferred host name bit default r/w description trans_fifo_byte_count 31 - 00 0x0 r number of bytes transferred between host/dma memory and biu fifo. table 298. transferred host to biu-fifo byte count register name bit default r/w description - 31 - 24 - - reserved debounce_count 23 - 00 0xffffff r/w number of host clocks (ahb clock) used by debounce filter logic; typical debounce time is 5-25 ms. table 299. user id register name bit default r/w description usrid 31 - 00 0x7967797 r user identification register, value set by user. can also be used as scratch pad register by user table 300. version id register name bit default r/w description verid 31 - 00 0x5342210a r version identification register free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 191 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.31 bmod (0x00000080) bus mode register. [1] these bits indicate the maximum number of beats to be performed in one internal dma controller (idmac) transaction. the idmac will always a ttempt to burst as specified in pbl each time it starts a burst transfer on the host bus. the permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. this value is the mirror of msize of fifoth register. in order to change this va lue, write the required value to fifoth register. [2] specifies the number of 32-bit word to skip betw een two unchained descriptors. this is applicable only for dual buffer structure. [3] controls whether the ahb master interface performs fixed burst transfers or not. when set, the ahb will use only single, incr4, incr8 or incr16 during start of normal burst transfers. when reset, the ahb will use single and incr burst transfer operations. [4] when set, the dma controller resets all its internal r egisters. it is automatically cleared after 1 clock cycle. 22.3.32 pldmnd (0x00000084) poll demand register. [1] if the own bit of a descriptor is not set, the fsm goes to the suspend state. the host needs to write any value into this register for the idmac fsm to resume normal descriptor fetch operat ion. this is a write only register. 22.3.33 dbaddr (0x00000088) descriptor list base address register. [1] contains the base address of the first descriptor. the lsb bits [1:0] are ignored and taken as all-zero by the idmac internally. hence these lsb bits are read-only. table 301. bus mode register name bit default r/w description - 31 - 11 - - reserved pbl [1] 10 - 08 0x0 r programmable burst length. the encode value is as follows: 3'b000: 1 transfer 3'b001: 4 transfers 3'b010: 8 transfers 3'b011: 16 transfers 3'b100: 32 transfers 3'b101: 64 transfers 3'b110: 128 transfers 3'b111: 256 transfers de 07 0x0 r/w idmac enable. when set, the idmac is enabled. dsl [2] 06 - 02 0x0 r/w descriptor skip length. fb [3] 01 0x0 r/w fixed burst. swr [4] 00 0x0 r/w software reset. table 302. poll demand register name bit default r/w description pd [1] 31 - 00 - w poll demand. table 303. descriptor list base address register name bit default r/w description sdl [1] 31 - 00 0x0 r/w start of descriptor list. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 192 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.34 idsts (0x0000008c) internal dmac status register. [1] indicates the type of error that caused a bus error. va lid only with fatal bus error bit (idsts[2]) set. this field does not generate an interrupt. table 304. internal dmac status register name bit default r/w description - 31 - 17 - - reserved fsm 16 - 13 0x0 r dmac fsm present state. 4'b0000: dma_idle 4'b0001: dma_suspend 4'b0010: desc_rd 4'b0011: desc_chk 4'b0100: dma_rd_req_wait 4'b0101: dma_wr_req_wait 4'b0110: dma_rd 4'b0111: dma_wr 4'b1000: desc_close eb [1] 12 - 10 0x0 r error bits. 3?b001 ? host abort received during transmission 3?b010 ? host abort received during reception others: reserved ais [2] 09 0x0 r/w abnormal interrupt summary. logical or of the following: idsts[2] ? fatal bus interrupt idsts[4] ? du bit interrupt idsts[5] ? card e rror summary interrupt only unmasked bits affect this bit. nis [3] 08 0x0 r/w normal interrupt summary. logical or of the following: idsts[0] ? transmit interrupt idsts[1] ? receive interrupt only unmasked bits affect this bit. - 07 - 06 - - reserved ces [4] 05 0x0 r/w card error summary. indicates the logical or of the following bits: ebe ? end bit error rto ? response timeout/boot ack timeout rcrc ? response crc sbe ? start bit error drto ? data read timeout/bds timeout dcrc ? data crc for receive re ? response error du [5] 04 0x0 r/w descriptor unavailable interrupt. - 03 - - reserved fbe [6] 02 0x0 r/w fatal bus error interrupt. r1 [7] 01 0x0 r/w receive interrupt. t1 [8] 00 0x0 r/w transmit interrupt. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 193 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [2] this is a sticky bit and must be cleared each time a corresponding bit that causes ais to be set is cleared. writing a 1 clears this bit [3] this is a sticky bit and must be cleared each time a corresponding bit that causes nis to be set is cleared. writing a 1 clears this bit. [4] indicates the status of the transaction to/from the card ; also present in rintsts. writing a 1 clears this bit. [5] this bit is set when the descriptor is unavailable due to own bit = 0 (des0 [31] =0). writing a 1 clears this bit. [6] indicates that a bus error occurred (idsts[12:10]). when this bit is set, the dma disables all its bus accesses. writing a 1 clears this bit. [7] indicates the completion of data reception fo r a descriptor. writing a 1 clears this bit. [8] indicates that data transmission is finished for a descriptor. writing a ?1? clears this bit 22.3.35 idinten (0x00000090) internal dmac interrupt enable register. [1] when set, an abnormal interrupt is enabled. [2] enable. when set, a normal interrupt is enabled. when reset, a normal interrupt is disabled. [3] when set, it enables the card interrupt summary. [4] when set along with abnormal interrupt summary enable, the du interrupt is enabled. [5] when set with abnormal summary enable, the fatal bus error interrupt is enabled. when reset, fatal bus error enable interrupt is disabled. [6] when set with normal interrupt summary enable, receive interrupt is enabled. when reset, receive interrupt is disabled. [7] when set with normal interrupt summary enable, tr ansmit interrupt is enabled. when reset, transmit interrupt is disabled. table 305. internal dmac interrupt enable register name bit default r/w description - 31 - 10 - - reserved ai [1] 09 0x0 r/w abnormal interrupt summary enable. this bit enables the following bits: idinten[2] ? fatal bus error interrupt. idinten[4] ? du interrupt. idinten[5] ? card e rror summary interrupt. ni [2] 08 0x0 r/w normal interrupt summary this bit enables the following bits: idinten[0] ? transmit interrupt. idinten[1] ? re ceive interrupt. - 07 - 06 - - reserved ces [3] 05 0x0 r/w card error summary interrupt enable. du [4] 04 0x0 r/w descriptor unavailable interrupt. 03 reserved fbe [5] 02 0x0 r/w fatal bus error enable. ri [6] 01 0x0 r/w receive interrupt enable. ti [7] 00 0x0 r/w transmit interrupt enable. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 194 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.3.36 dscaddr (0x00000094) current host descriptor address register. [1] cleared on reset. pointer updated by idmac during operation. this register points to the start address of the current descriptor read by the idmac. 22.3.37 bufaddr (0x00000098) current buffer descriptor address register. [1] cleared on reset. pointer updated by idmac during oper ation. this register points to the current data buffer address being accessed by the idmac. 22.3.38 reserved (0x0000009c~0x000000fc) data (0x00000100~0x00000140) data fifo read/write. table 306. current host descriptor address register name bit default r/w description hda [1] 31 - 00 0x0 r host descriptor address pointer. table 307. current buffer descriptor address register name bit default r/w description hba [1] 31 - 00 0x0 r host buffer address pointer. table 308. data fifo read/write name bit default r/w description fifo 31 - 00 - r/w if address offset is equal or greater than 0x100, then fifo is selected free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 195 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 22.4 auto stop the mshc internally generates a stop command and is loaded in the command path when the send_auto_stop bit is set in the command register. the auto-stop command helps to send an exact number of data bytes using a stream read or write for the mmc, and a multiple-block re ad or write for sd memory transfer for sd cards. the software should set the send_auto_stop bit according to details listed in table 212 . [1] the condition under which the transfer mode is set to block transfer and byte_count is equal to block size is treated as a single-block data transfer co mmand for both mmc and sd cards. if byte_count = n*block_size (n = 2, 3, ?), the condition is treated as a predefined multiple-block data transfer command. in the case of an mmc card, the host software can perform a predefined data transfer in two ways: 1) issue the cmd23 command before issuing cmd18/cmd25 commands to the card ? in this case, issue cmd18/cmd25 commands without setting t he send_auto_stop bit. 2) issue cmd18/cmd25 commands without issuing cmd23 command to the card, with the send_auto_stop bit set. in this case, the multiple-block data transfer is terminated by an internally-generated auto-stop command after the programmed byte count. 22.5 descriptors the idmac uses these types of descriptor structures: ? dual-buffer structure: the distance between two descriptors is determined by the skip length value programmed in the descri ptor skip length (dsl) field of the bus mode register (bmod @0x80). ? chain structure: each descriptor points to a unique buffer and the next descriptor. figure 48 illustrates the idmac dual-buff er descriptor structure. table 309. auto stop card type transfer type byte count send_auto_stop bit set comments mmc stream read 0 no open-ended stream mmc stream read >0 yes auto-stop after all bytes transfer mmc stream write 0 no open-ended stream mmc stream write >0 yes auto-stop after all bytes transfer mmc single-block read >0 no byte count = 0 is illegal mmc single-block write >0 no byte count = 0 is illegal mmc multiple-block read 0 no open-ended multiple block mmc multiple-block read >0 yes [1] pre-defined multiple block mmc multiple-block write 0 no o pen-ended multiple block mmc multiple-block write >0 yes [1] pre-defined multiple block sdmem single-block read >0 no byte count = 0 is illegal sdmem single-block write >0 no byte count = 0 is illegal sdmem multiple-block read 0 no open ended multiple block smem multiple-block read >0 yes [1] auto stop after all bytes transfer sdmem multiple-block write 0 no open ended multiple block sdmem multiple-block write >0 yes [1] auto stop after all bytes transfer sdio single-block read >0 no byte count = 0 is illegal free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 196 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc figure 50 illustrates the idmac chain descriptor structure. each descriptor contains 16 bytes of control and status information. des_0 is a notation used to denote the [31:0] bits, des_1 to de note [63:32] bits, des_2 to denote [95:64] bits, and des_3 to denote [127:96] bits in a descriptor. fig 49. dual-buffer descriptor structure fig 50. chain descriptor structure 001aam975 des0_0 des0_1 des0_2 des0_3 data buffer 1 data buffer 2 des1_0 des1_1 des1_2 des1_3 data buffer 1 data buffer 2 des2_0 des2_1 des2_2 des2_3 data buffer 1 data buffer 2 001aam976 des0_0 des0_1 des0_2 des0_3 data buffer des1_0 des1_1 des1_2 des1_3 data buffer des2_0 des2_1 des2_2 des2_3 data buffer free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 197 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc the des0 descriptor in the idmac contai ns control and status information; table 310 lists the bits in this descriptor. [1] when set, this bit indicates that the descriptor is owned by the idmac. when this bit is reset, it indicates that the descriptor is owned by the host. the idma c clears this bit when it completes the data transfer. [2] these error bits indicate the status of the transacti on to or from the card. these bits are also present in rintsts. [3] when set, this bit indicates that the descriptor list reached its final descriptor. the idmac returns to the base address of the list, creating a descriptor ring. this is meaningful for only a dual-buffer descriptor structure. [4] when set, this bit indicates that the second addr ess in the descriptor is the next descriptor address rather than the second buffer address. when this bit is set, bs2 (des1[25:13]) should be all zeros. [5] when set, this bit indicates that this descriptor cont ains the first buffer of the data. if the size of the first buffer is 0, next descriptor contains the beginning of the data. [6] when set, this bit indicates that the buffers pointe d to by this descriptor are the last buffers of the data. [7] when set, this bit will prevent the setting of the ti/ri bit of the idmac status register (idsts) for the data that ends in the buffer pointed to by this descriptor. table 310. bits in idmac des0 descriptor bits name description 31 [1] own owned 30 [2] (ces) card error summary - indicates th e logical or of the following bits: ? ebe: end bit error ? rto: response time out ? rcrc: response crc ? sbe: start bit error ? drto: data read timeout ? dcrc: data crc for receive ? re: response error 29 - 06 - reserved 05 [3] er end of ring 04 [4] ch second address chained 03 [5] fs first descriptor 02 [6] ld last descriptor 01 [7] dic disable interrupt on completion 00 - reserved free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 198 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc the des1 descriptor contains the buffer size; table 311 lists the bits in this descriptor. [1] these bits indicate the second data buffer byte size. th e buffer size must be a multiple of 4 respectively. in the case where the buffer size is not a multiple of 4, the resulting behavior is undefined. this field is not valid if des0[4] is set. [2] indicates the data buffer byte size, which must be a multiple of 4 bytes. in the case where the buffer size is not a multiple of 4, the resulting behavior is undefined. if this field is 0, the dma ignores this buffer and proceeds to the next descriptor in case of a chain stru cture, or to the next buffer in case of a dual-buffer structure. the des2 descriptor contains the address pointer to the data buffer; table 312 lists the bits in this descriptor. idmac des2 descriptor. [1] these bits indicate the physical address of the firs t data buffer. the idmac ignores des2 [1:0] internally the des3 descriptor contains the address pointer to the next descriptor if the present descriptor is not the last descriptor in a chained descriptor structure or the second buffer address for a dual-buffer structure. [1] these bits indicate the physical address of the se cond buffer when the dual-buffer structure is used. if the second address chained (des0[4]) bit is set, then th is address contains the pointer to the physical memory where the next descriptor is present. if this is not the last descriptor, then the next descriptor address pointer must be bus-width aligned (des3[1 :0] = 0. internally the lsbs are ignored). table 311. bits in idmac des1 descriptor bits name descriptor 31 - 26 - reserved 25 - 13 [1] bs2 buffer 2 size 12 - 00 [2] bs1 buffer 1 size table 312. bits in idmac des2 descriptor bits name descriptor 31 - 00 [1] bap1 buffer address pointer 1 table 313. bits in idmac des3 descriptor address (bap2) bits name description 31 - 00 [1] bap2 buffer address pointer 2 / next descriptor address free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 199 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23. nand flash controller 23.1 general description there is a nand flash memory controller in asc8848/49/50/51 soc which supports two devices. it is designed to interface wit h nand flash devices that are compliant with onfi standard 1.0. some custom commands provided by samsung, micron and stm are also implemented. with built-in hardware ecc, mlc nand flash memories could be supported. 23.2 features the nand flash memory controller provides the following features. ? supports open nand flash interface (onfi) rev. 1.0 compatible devices ? programmable page size, 2kb and 4kb ? hardware bch ecc (correct up to 8 and detect up to 16 distorted bits every 512 bytes) ? embedded dma engine ? support 4 or 5 address cycles ? fully programmable timing parameters ? common ready/busy signal for each memory ? supports boot from nand flash by firmware 23.3 memory map register 23.3.1 flconf (0x00001300) timing parameter configuration register. tahb is the period of ahb clock. [1] edo mode is not supported which means t rp must be larger than t rea to ensure the correct operation. table 314. timing parameter configuration register name bit default r/w description - 31 - 30 - - reserved twb 29 -23 0x0 r/w we# high to r/b# low. t wb =(twb+1)* t ahb . twhr 22 - 17 0x0 r/w we# high to re# low. t whr =(twhr+1)* t ahb . twp 16 - 11 0x0 r/w we# pulse width. t wp =(twp+2)* t ahb . trp [1] 10 - 05 0x0 r/w re# pulse width. t rp =(trp+1)* t ahb . twh 04 - 00 0x0 r/w we# high hold time. t wh =(twh+1)* t ahb . free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 200 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.3.2 flctrl (0x00001304) control register. table 315. control register name bit default r/w description - 31 - 23 - - reserved wr_prot 23 0x1 r/w active- low write protect bit - 22 - 19 - - reserved flce 18 - 16 0x00 r/w chip enable (0~7). 15 - 13 r/w reserved block_size 12 0x0 r/w block size. 1?b0: 64 pages 1?b1: 128 pages page_size 11 0x0 r/w page size. 1?b0: 4kb 1?b1: 2kb spare_size 10 0x0 r/w spare area size. the first 64b will be used for error correction and could not be modified. 1?b0: 64b for 2kb page; 128b for 4kb page. 1?b1: 112b for 2kb page; 224b for 4kb page. ecc 09 0x0 r/w hardware ecc enable. 1?b0: disable 1?b1: enable intr_en 08 0x0 r/w global interrupt enable. 1?b0: disable 1?b1: enable acc_err_intr_en 07 0x0 r/w incorrect fldata regi ster access interrupt enable. fldata register could not be accessed during nand flash read or write transfer. 1?b0: disable 1?b1: enable - 06 0x0 r/w reserved rub_intr_en 05 0x0 r/w interrupt on the rising edge of read/busy port. 1?b0: disable 1?b1: enable dma_err_intr_en 04 0x0 r/w ahb error response interrupt enable during dma transfer. 1?b0: disable 1?b1: enable dma_trigger 03 0x0 r/w automatically complete the dma read data transfer before nand flash write transfer or complete the dma write data transfer after nand flash read transfer. 1?b0: disable 1?b1: enable free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 201 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.3.3 flcomm (0x00001308) command register. [1] refer to table 223 operations supported in the nand flash memory controller for the supported flash memory commands. 23.3.4 fladdr_0_lo (0x0000130c) lower bits for flash address 0 register. 23.3.5 fladdr_1_lo (0x00001310) lower bits for flash address 1 register. 23.3.6 fldata (0x00001314) data register to read/write the flash memory. [1] read/write the flash memory one by one through the host processor instead of using the internal buffer to transfer a whole page in a time. 23.3.7 reserved (0x00001318) this register is reserved. trans_cmpt_intr_en 02 0x0 r/w transfer complete interrupt enable. 1?b0: disable 1?b1: enable rnb_mode 01 0x0 r/w read/busy line mode. 1?b0: separate ready/busy line for each device 1?b1: common read/busy line for all devices addr_cycle 00 0x0 r/w number of addre ss bytes sent to nand flash device. 1?b0: 4 address cycles 1?b1: 5 address cycles table 315. control register ?continued name bit default r/w description table 316. command register name bit default r/w description - 31 - 16 - - reserved flcomm [1] 15 - 00 0x0 r/w flash memory commands. table 317. flash address 0 register name bit default r/w description fladdr_0_lo 23 0x1 r/w low 32 bits for the read flash memory address. table 318. flash address 1 register name bit default r/w description fladdr_1_lo 31 - 00 0x0 r/w low 32 bits for the write flash memory address. table 319. fldata name bit default r/w description fldata [1] 31 - 00 0x0 r/w flash memory data. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 202 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.3.8 flstate (0x0000131c) status register. [1] flag is cleared when a new command is written to the flcomm register. [2] this field gives the current state of the controller . when writing to flcomm register, fsm will be set to 2?b10 and back to 2?b00 when the command is done. [3] first code means that controller gives re try response, second one gives split response. [4] this bit is valid only when intr_en in flctrl r egister is enabled. those interrupts enabled in flctrl will trigger this bit. write 1?b0 to clear it. [5] this bit is set when an illegal access attempt has been detected. illegal access occurs when an executed command implies a transfer while the host tries to make an opposing attempt. write 1?b0 to clear it. [6] this bit is set when the rising edge of r/b# has been detected. write 1?b0 to clear it. [7] this bit reflects the current state of r/b# input pin 23.3.9 reserved (0x00001320~0x0000133c) 23.3.10 fleccstatus (0x00001340) ecc status register. [1] each bit corresponds to the 512 byte subpage of the memory page size. if errors occur during read process in buffered mode, bits corresponding to the subpage where errors were noticed are sets. [2] each bit corresponds to the 512 byte subpage of the memory page size. the only valid bits are those for which corresponding ecc error bits are set. if errors for a given subpage were successfully corrected, the appropriate bit is set. table 320. status register name bit default r/w description - 31 - 10 - - reserved trans_cmpt_flag [1] 09 0x0 r transfer complete flag. dma_err 08 0x0 r same as err_flag in fldma_ctrl dma_busy 07 0x0 r same dm a_busy in fldma_ctrl fsm [3] 06 - 05 0x0 r fsm busy. [3] 2?b00: controller is in an idle state 2?b01: controller executes command ending up to 16 clock cycles 2?b10/2?b11: controller executes normal command ? long delays. intr [4] 04 0x0 r interrupt request. - 03 - - reserved acc_err [5] 02 0x0 r access error. rnb_intr [6] 01 0x0 r ready/busy edge. rnb_state [7] 00 - r ready/busy state. table 321. ecc status register name bit default r/w description - 31 - 24 - - reserved error_flag [1] 23 - 16 0x0 r error flag. - 15 - 08 - - reserved correct_flag [2] 07 - 00 0x0 r error correct flag. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 203 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.3.11 fladdr_0_hi (0x00001344) higher bits for flash address 0 register. 23.3.12 fladdr_1_hi (0x00001348) higher bits for flash address 1 register. 23.3.13 reserved (0x0000134c~0x0000137c) this register is reserved. 23.3.14 fldma_addr(0x00001380) dma address register. 23.3.15 fldma_ctrl (0x00001384) dma control register. table 322. higher bits for flash address 0 register name bit default r/w description - 31 - 04 - - reserved fladdr_0_hi 03 - 00 0x1 r/w higher bits for the read flash memory address. table 323. higher bits for flash address 1 register name bit default r/w description - 31 - 04 - - reserved fladdr_1_h1 03 - 00 0x0 r/w higher bits for the write flash memory address. table 324. dma address register name bit default r/w description fldma_addr 31 - 00 0x0 r/w the base address of the dma buffer. table 325. dma control register name bit default r/w description - 31 - 25 - - reserved start_flag [1] 24 0x0 r/w dma start flag. - 23 - 17 - - reserved dma_dir [2] 16 0x0 r/w dma transfer direction. 1'b0: write data from ahb to internal buffer 1'b1: read from internal buffer and write to ahb dma_size [3] 15 - 14 0x0 r/w transfer size. 2'b00: 8-bits transfer size 2'b01: 16-bits transfer size 2'b10: reserved 2'b11: 32-bits transfer size free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 204 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] setting this bit forces the dma cont roller to start a block transfer. t he flag is cleared automatically by the dma controller when it gains control of the internal bus. [2] this flag defines transmission direction. [3] these bits define the request ed transfer size on the ahb bus. [4] these bits define the main transfer type used by the dma to precede the requested transfer. [5] the flag is set when the dma is transmitting data and a write attempt to sfr register is noticed. [6] flag is set when during dma transfer transmission errors occur. cleared when writing fldma_ctrl register. 23.3.16 fldma_cntr (0x00001388) dma counter and the internal buffer start address registers. [1] this register stores the size to be transferred. this register decrements its value during transfer. [2] only valid when writing nand flash memory. specify the address of the internal buffer from which the controller starts moving into nand flash memory. when reading nand flash memory, it always starts writing at address 0. dma_burst [4] 13 - 11 0x0 r/w burst type. 3'b000: single transfer address decrement 3'b001: burst of unspecified length address decrement 3'b010: single transfer address increment 3'b011: burst of unspecified length address increment 3'b100: 4 beat burst address increment 3'b101: 8 beat burst address increment 3'b110: 16 beat burst address increment 3'b111: stream burst (address const) - 10 - 03 - - reserved dma_busy [5] 02 0x0 r dma busy. err_flag [6] 01 0x0 r dma error flag. - 00 0x0 - reserved table 325. dma control register ?continued name bit default r/w description table 326. dma counter and internal buffer start address registers name bit default r/w description - 31 - 29 - - reserved dma_cntr [1] 28 - 16 0x0 r/w dma counter. - 15 - 13 - - reserved buff_addr [2] 12 - 00 0x0 r/w internal buffer address. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 205 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.4 timing timing parameters table 327 shows how to derive the timing parame ters defined in onfi rev. 1.0 from flconf register. 23.4.1 timing relationship the relationship of timing parameters stored in flconf is depicted below. table 327. timing parameter partnership parameter formula descriptions tadl twhr+1 ale to data start talh twh+1 ale hold time tals twp+1 ale setup time tch twh+1 ce# hold time tclh twh+1 cle hold time tcls twp+1 cle setup time tcs twp/trp+1 ce# setup time tdh twh+1 data hold time tds twp/trp+1 data setup time twc twh+twp+2 wr ite cycle time tar twhr+1 ale to re# delay tclr min 3 cle to re# delay toh twh+1 data output hold time trc trp+twh+2 read cycle time trea 0 re# access time treh twh+1 re# high hold time trr twp+1 ready to re# low fig 51. timing relationship 001aan236 ahb clk cle we# re# r/b# t wp t wh t whr t wb t rp free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 206 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.5 commands all commands supported in the nand flash memory controller is listed table 328 . to use page read operation, write 0x0030 to the flcomm register and the nand flash memory controller will write 0x00 command to the command register in the nand flash memory, then write 4 or 5 address cycles (fladdr_0_hi, fladdr_0_lo) depending on the addr_cycle in flctrl register and finish with 0x30 command. table 328. operations supported in nand flash memory controller operation command command valid while busy descriptions first second generic commands page read 0x0030 0x00 0x30 no reads full page automatically and transfers it into the buffer page read 1 0x0130 0x00 0x30 no sends instructions and address to the flash memory device read for internal data move 0x0035 0x00 0x35 no sends instructions and address (4 or 5 bytes) to flash memory random data read 0x0005 0x05 0xe0 no sends instructions and 2 address bytes to flash memory read status 0x0070 0x70 - yes sends instructions to flash memory program page 0x0080 0x80 0x10 no automatically writes contents of the buffer to the flash memory program page 1 0x0180 0x80 - no sends instruction and address to the flash memory program page cache 0x0580 0x80 0x15 no automatically writes contents of the buffer to the flash memory write page 0x0010 0x10 - no sends instruction to the flash memory write cache 0x0015 0x15 - no sends only instruction to flash memory program for internal data move 0x0085 0x85 0x10 no writes instruction 0x85h, next address (4 or 5 bytes) and instruction 0x10h random data input for program 0x0185 0x85 - no writes instruction and 2 address bytes block erase 0x0060 0x60 0xd0 no writes instructions address to flash memory reset 0x00ff 0xff - yes writes in struction to flash memory read id 0x0090 0x90 - no writes instruction and address micron memories page read cache mode start 0x1031 0x31 - no reads automatically full page and transfers it into the buffer page read cache mode start last 0x103f 0x3f - no reads automatically full page and puts it into the buffer page read cache mode start 1 0x1131 0x31 - no sends instruction to flash memory page read cache mode start last 1 0x113f 0x3f - no sends instruction to flash memory program page 2 0x1280 0x80 0x11 no automatically writes contents of buffer to flash memory. otp program 0x10a0 0xa0 0x10 no automatically write whole page to otp memory area otp program 1 0x11a0 0xa0 0x10 no sends instruction and address only free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 207 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc otp protect 0x10a5 0xa5 0x10 no protects otp memory area otp read 0x10af 0xaf 0x30 no reads automatically full page and puts it into buffer otp read 1 0x11af 0xaf 0x30 no sends instruction and address bytes only plane page read 0x1230 0x00 0x30 no writes read commands and addresses for first and second planes, next transfers first plane into the buffer plane page read 1 0x1330 0x00 0x30 no writes read commands and addresses for first and second planes plane random data read 0x1206 0x06 0xe0 no switches read to the second plane. after writing command the whole page is read into the buffer plane random data read 1 0x1306 0x06 0xe0 no switches read to the second plane. after writing command the controller goes to the idle read state plane page program 0x1081 0x81 0x10 no automatically writes contents of buffer to flash memory plane page program 1 0x1181 0x81 - no only writes command 0x81h and 4 or 5 address bytes. plane page read for internal data move 0x1235 0x00 0x35 no reads two pages on different planes to internal data buffer plane page program for internal data move 0x1285 0x85 0x11 no writes internal me mory data register contents to the new location plane page eraser 0x1160 0x60 0xd0 yes erases two pages on different planes plane page read status 0x1078 0x78 - yes writes read status command and goes to the idle read state write plane page 0x1011 0x11 - no stm memories cache read 0x2031 0x00 0x31 no reads automatically full page and puts it into buffer cache read 1 0x2131 0x00 0x31 no sends instruction and address bytes to flash memory cache read 2 0x2231 no only reads automatically full page and puts it into buffer, no instruction nor address bytes are sen exit cache read 0x2034 0x34 sends only an instruction to flash memory read block lock status 0x207a 0x7a - no writes only an instruction blocks unlock 0x2023 0x23 0x24 no writes an inst ruction followed by 2 or 3 address bytes, then again an instruction and 2 or 3 address bytes blocks lock 0x202a 0x2a no wr ites instruction only blocks lock-down 0x202c 0x2c - n o writes instruction only samsung memories program page 2 0x0280 0x80 0x11 no automatically writes contents of buffer to flash memory program page cache 0x0580 0x80 0x15 no automatically writes contents of buffer to flash memory table 328. operations supported in nand flash memory controller ?continued operation command command valid while busy descriptions first second free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 208 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.6 address mapping table 329 and ta b l e 3 3 0 show the address m apping from the flad dr0 and fladdr1 to the address bytes on the i/o lines. table 329 is for 2kb page size and table 330 is for 4kb page size. if addr_cycle in flctrl register is 0 (address cycle is 4), the 5th byte is ignored. 23.7 programming there are two kinds of transfers in the nand flash memory controller, dma transfer and nand flash memory transfer. dma transfer moves data from dram to the internal buffer or from the internal buffer to dram. nand flash memory transfer moves data from the internal buffer to the nand flash memory or from the nand flash memory to the internal buffer. the internal buffer is shared with the boot rom controller. block erase 1 0x0160 0x60 0xd0 no sends instru ction 0x60h, next address (2 or 3 byte), next command 0x60h, address (2 or 3 byte), and command (0xd0h) plane page program 0x0081 0x81 0x10 no automatically writes contents of buffer to flash memory plane page program 1 0x0181 0x81 - no only writes command 0x81h and 4 or 5 address bytes read edc status 0x007b 0x7b - yes writes instruction only read chip 1 status 0x00f1 0xf1 - yes writes instruction only read chip 2 status 0x00f2 0xf2 - yes writes instruction only write plane page 0x0011 0x11 - no writes command only table 328. operations supported in nand flash memory controller ?continued operation command command valid while busy descriptions first second table 329. address mapping and address bytes relation for 8-bit memory devices ? 2kb page address cycle i/o[0] i/o[1] i/o[2] i/o[3] i/o[4] i/o[5] i/o[6] i/o[7] 1 st cycle a0a1a2a3a4a5a6a7 2 nd cycle a8 a9 a10 a11 0 0 0 0 3 rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4 th cycle a20 a21 a22 a23 a24 a25 a26 a27 5 th cycle a28 a29 a30 a31 a32 a33 a34 a35 table 330. address mapping and address bytes relation for 8-bit memory devices ? 4kb page address cycle i/o[0] i/o[1] i/o[2] i/o[3] i/o[4] i/o[5] i/o[6] i/o[7] 1 st cycle a0a1a2a3a4a5a6a7 2 nd cycle a8 a9 a10 a11 a12 0 0 0 3 rd cycle a13 a14 a15 a16 a17 a18 a19 a20 4 th cycle a21 a22 a23 a24 a25 a26 a27 a28 5 th cycle a29 a30 a31 a32 a33 a34 a33 0 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 209 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.7.1 nand flash memory transfer there are two kinds of nand flash memory tr ansfers. one is to transfer whole page from/to internal buffer, like page read; the other is to transfer command first and then use the host processor to push or pop data through fldata register, like page read 1. use page read operation as an example. 1. switch the internal buffer for the nand flash memory controller. 2. set up flconf register according to the nand flash memory datasheet. 3. set up flctrl register a. write block_size, page_size, spare_ size, and addr_cycle according to the nand flash memory datasheet. b. dma_trigger = 1?b0, if only nand fl ash memory transfer is required. c. rnb_mode = 1?b0, according to the system configuration d. trans_cmpt_intr_en = 1?b1 e. rnb_intr_en = 1?b0 f. dma_err_intr_en = 1?b1 g. acc_err_intr_en = 1?b1 h. intr_en = 1?b1 i. ecc = 1?b1, enable error correction mechanism. this bit must be enabled or disabled for both read and write operations. j. flce = 3?b5, enable nand flash memory device 5. k. wr_prot = 1?b1, make na nd flash memory writable. 4. write fladdr_0_lo and fladdr_0_hi regi sters to specify the page to read from the nand flash memory. 5. write flcomm register with 0x0030 according to ta b l e 3 2 8 6. wait the interrupt or wait fsm in flstate register to be idle. fig 52. page read operation 001aam977 0x00 4 or 5 address cycles (from fladdr_0) 0x30 read whole page data correction and set ready flag fsm in idle state free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 210 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 23.7.2 dma transfer the programming procedure is as follows. 1. switch the internal buffer for the boot rom controller. 2. fill 2048 bytes in the internal buffer by the host processor. 3. switch the internal buffer for the nand flash memory controller. 4. write fldma_addr with 0x01000000, move 2048 bytes to address 0x01000000. 5. write fldma_cntr with 0x08000000. 6. set up fldma_ctrl a. dma_dir=1?b1, read data from the internal buffer and write to ahb. b. dma_size=2?b11, 32-bit transfer c. dma_burst=3?b101, 8-beat burst transfer d. start_flag=1?b1, start dma transfer. 7. wait dma_busy in flstate to become 1?b0, then check if the data in address 0x01000000 is correct by the host processor. 23.7.3 combined transfer to make the nand flash memory transfer and the dma transfer to start one by one automatically, set dma_trigger to 1?b1 with the above configurations and the page data will be first loaded from the nand flas h memory to the internal buffer, error corrected and then wri tten to the dma buffer. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 211 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 24. pci express dual mode controller 24.1 general description there is a one-lane pci express dual mode (d m) controller in asc88 48/49/50/51 soc. it is compliant with pcie 1.1 spec ification and could operate in either root complex (rc) mode or endpoint (ep) mode. pcie is ubiqui tous in all pcs and various applications are adopted quickly for this trend. built-in with pc ie, soc could connect with all pcie devices with less i/o than pci interface. with pcie dua l mode controller, it is easy to extend the system capability by cascading multiple chips with one acti ng as rc while the others acting as eps. 24.2 features the pcie dual mode controller provides the following features. ? supports 2.5gbps data transfer rate ? supports legacy pci and msi interrupts (only one intx interrupt and up to 8 msi interrupts) ? includes a dma controller to support tx and rx transfers ? supports memory space address translation ? supports pcie active state power management (aspm l0s) ? supports end-to-end crc (ecrc) generation and checking ? not support multi-function devices. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 212 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 25. uart interfaces 25.1 general description four uart interfaces are provided in asc8848/49/50/51 soc. uart provides a serial communication interface with a computer. on ly two interfaces su pport modem functions with cts, rts, dsr, dtr, ri and dcd. it is possible to use phone line communication through modem functions when the wired or wireless network is out of order. 25.2 features 25.2.1 fifo there is a 16-byte fifo for both tx and rx to reduce the number of interrupts sent to the host processor. 25.2.2 frame format adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data. 25.2.3 baud rate programmable baud rate generator divides uart clock by dl (divisor latch) and generate the 16x baud rate clock. the uart clock is 18.432mhz. 25.2.4 modem control supports modem control functions (c ts, rts, dsr, dtr, ri and dcd). 25.2.5 data format fully programmable serial interface characteristics. ? 5, 6, 7 or 8-bit characters. ? even, odd or no-parity bit generation and detection ? 1, 1.5, or 2 stop bits generation table 331. baud rate baud rate(bps) 16xbaud rate dl dll dlm 300 4,800 3840 0x00 0x0f 1,200 19,200 960 0xc0 0x03 2,400 38,400 480 0xe0 0x01 4,800 76,800 240 0xf0 0x00 9,600 153,600 120 0x78 0x00 19,200 307,200 60 0x3c 0x00 38,400 614,400 30 0x1e 0x00 57,600 921,600 20 0x14 0x00 115,200 1,843,200 10 0x0a 0x00 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 213 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 25.3 memory map register 25.3.1 uartc_version (0x00000000) version information register. 25.3.2 uartc_rbr (0x00000004) receive buffer register. 25.3.3 uartc_thr (0x00000004) transmitter holding register. 25.3.4 uartc_ier (0x00000008) interrupt enable register. table 332. version information register name bit default r/w description major_version 31 - 24 0x02 r major version number minor_version 23 - 16 0x00 r minor version number build_version 15 - 08 0x00 r build version number revision 07 - 00 0x17 r revision number table 333. receive buffer register name bit default r/w description - 31 - 08 0x0 - reserved rbr 07 - 00 0x0 r receive data port table 334. transmitter holding register name bit default r/w description - 31 - 08 0x0 - reserved thr 07 - 00 0x0 w transmit data port table 335. interrupt enable register name bit default r/w description - 31 - 04 0x0 - reserved modem status 03 0x0 r/w 1?b0: disable the modem status register interrupt. 1?b1: enable the modem status register interrupt receiver line status 02 0x0 r/w 1?b0: disable the receiver line status interrupt. 1?b1: enable the receiver line status interrupt. thr empty 01 0x0 r/w 1?b0: disable the transmitter empty interrupt. 1?b1: enable the transm itter empty interrupt. data ready 00 0x0 r/w 1?b0: disable the receiver ready interrupt. 1?b1: enable the receiver ready interrupt. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 214 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 25.3.5 uartc_iir (0x0000000c) interrupt identification register. [1] there is no interrupt pending [2] there is an overrun error, parity error, framing error or break interrupt indication corresponding to the received data on f ifo. [3] in non-fifo mode, there is receive available in the rbr register. in fifo mode, the number of characters in the rx fifo is equal to or greater than the trigger level programmed in fcr. [4] there is least one character in the rx fifo and during the ti me corresponding to four characters at the selected baud rate, no new characters has been received and no readi ng has been executed on the rx fifo. [5] in non-fifo mode, the 1-byte thr is empty. in fifo mode, the complete 16-byte tx fifo is empty, so 1to 16 characters can be written to thr. [6] a change has been detected in the clear to send (cts), data se t ready (dsr) or carrier detect (cd) input lines or a trailing edge in the ring indicator (ri) input line. table 336. interrupt identification register name bit default r/w description - 31 - 08 0x0 - reserved fifo enable mode 07 - 06 0x1 r 2?b00: no fifo. 2?b10: unusable fifo. 2?b11: fifo enable. - 05 - 04 0x0 - reserved fifi mode only 03 0x0 r in the fifo mode this bit is set along with bit 2 when a timeout is pending. interrupt identification 02 - 01 0x0 r these bits identify the highest priority interrupt that is pending. ta b l e 3 3 7 describes the different interrupt conditions and their identification code. interrupt status 00 0x1 r 1?b0: an interrupt is pending. 1?b1: no interrupt is pending. table 337. interrupt identification register fifo mode only interrupt iden tification register interrupt set a nd reset function bit3 bit2 bit1 bit 0 priority level interrupt type source description interrupt reset method 0 0 0 1 - none [1] none 0 1 1 0 first receiver line status [2] read line status register (lsr) 0 1 0 0 second receiver data ready [3] read receiver buffer register (rbr) 1 1 0 0 second character reception timeout [4] read receiver buffer register (rbr) 0 0 1 0 third transmitter holding register empty [5] write transmitter holding register (thr) 0 0 0 0 fourth modem status [6] read modem status register (msr) free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 215 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 25.3.6 uartc_fcr (0x0000000c) fifo control register. 25.3.7 uartc_lcr (0x00000010) line control register. table 338. fifo control register name bit default r/w description - 31 - 08 0x0 - reserved rx fifo trigger level 07 - 06 0x0 w 2?b00: 1 character. 2?b01: 4 characters. 2?b10: 8 characters. 2?b11: 14 characters. - 05 - 03 0x0 - reserved tx fifo reset 02 0x0 w 1?b0: no change. 1?b1: clears the content of the tx fifo and resets its counter logi c to zero. return to zero after clearing the fifos. do not assert this reset. tx fifo could possibly be regarded as non-empty temporarily. rx fifo reset 01 0x0 w 1?b0: no change. 1?b1: clears the content of the rx fifo and resets its counter logi c to zero. return to zero after clearing the fifos. do not assert this reset. rx fifo could possibly be regarded as non-empty temporarily. fifo enable 00 0x0 w 1?b0: disable tx and rx fifos. 1?b1: enable tx and rx fifos table 339. line control register name bit default r/w description - 31 - 08 0x0 - reserved dlab 07 0x0 r/w 1?b0: rbr, thr and ier accessible. 1?b1: dll and dlm accessible set break 06 0x0 r/w 1?b0: disable break condition 1?b1: enable break condition, fo rce the serial output to space (logic 0) state stick parity 05 0x0 r/w 1?b0: disable stick parity. 1?b1: if even parity is logic 1, the parity bit forced to logic 0. if even parity is logic 0, the parity bit forced to logic 1 even parity 04 0x0 r/w 1?b0: an odd number of logic 1s is transmitted or checked in the data word bits and parity bit. 1?b?1: an even number of logic 1s is transmitted or checked in the data word bits and parity bit. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 216 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 25.3.8 uartc_mcr (0x00000014) modem control register. 25.3.9 uartc_lsr (0x00000018) line status register. parity enable 03 0x0 r/w 1?b0: disable parity generation. 1?b1: enable parity generation. stop bits 02 0x0 r/w 1?b0: 1 stop bit. 1?b1: 1.5 stop bits (5-bit word) / 2 stop bits (6-,7- or 8-bit word). word length 01 - 00 0x0 r/w 2?b00: 5 bits. 2?b01: 6 bits. 2?b10: 7 bits. 2?b11: 8 bits table 339. line control register ?continued name bit default r/w description table 340. modem control register name bit default r/w description - 31 - 05 0x0 - reserved loop 04 0x0 r/w 1?b0: normal operating mode. 1?b1: enable local loop-back mode. out2 03 0x0 r/w 1?b0: force out2to high. 1?b1: force out2to low out1 02 0x0 r/w 1?b0: force out1 to high. 1?b1: force out1 to low. rts (request to send) 01 0x0 r/w 1?b0: force rts to high. 1?b1: force rts to low. this bit controls the ?request to send? active low output dtr (data terminal ready) 00 0x0 r/w 1?b0: force dtr to high. 1?b1: force dtr to low. this bit controls the ?data terminal ready?, active low output. table 341. line status register name bit default r/w description - 31 - 08 0x0 - reserved fifo data error 07 0x0 r 1?b0: none. 1?b1: at least one parity error, framing error and break indicator is in the fifo. cleared by read lsr. transmitter empty 06 0x1 r 1?b0: transmit holding or shift registers is full. 1?b1: transmitter hold and shift register are empty. thr empty 05 0x1 r 1?b0: transmit holding register is full. 1?b1: transmitter hold register is empty. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 217 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 25.3.10 uartc_msr (0x0000001c) modem status register. break interrupt 04 0x0 r 1?b0: no break condition. 1?b1: the receiver?s line input sin is held at zero for a complete character time. cleared by read lsr. framing error 03 0x0 r 1?b0: no framing error. 1?b1: the received character does not have a valid stop bit (a 0 is detected in the stop bit position instead of 1). cleared by read lsr. parity error 02 0x0 r 1?b0: no parity error. 1?b1: the parity of the received character is wrong according to the current setting in lcr. cleared by read lsr. overrun error 01 0x0 r 1?b0: no overrun error. 1?b1: a character has been completely assembled in the receiver shift register without free space to put it in the rx fifo or holding register. cleared by read lsr. receive data ready 00 0x0 r 1?b0: no data in receiver buffer. 1?b1: data has received in receiver buffer. table 341. line status register ?continued name bit default r/w description table 342. modem status register name bit default r/w description - 31 - 08 0x0 - reserved dcd 07 0x0 r data carrier detect, is complement of the dcd input. ri 06 0x0 r ring indicator, is complement of the ri input. dsr 05 0x0 r data set ready, is complement of the dsr input. cts 04 0x0 r clear to send, is complement of the cts input. delta dcd 03 0x0 r dcd state change detection. this bit is cleared after msr is read. 1'b0: no dcd changed state. 1'b1: dcd changed state. trailing edge ri 02 0x0 r ri trailing edge detection. this bit is cleared after msr is read. 1'b0: no ri changed state. 1'b1: ri changed state. delta dsr 01 0x0 r dsr state change detection. th is bit is cleared after msr is read. 1'b0: no dsr changed state. 1'b1: dsr changed state. delta cts 00 0x0 r cts state change detection. this bit is cleared after msr is read. 1'b0: no cts changed state. 1'b1: cts changed state. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 218 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 25.3.11 uartc_spr (0x00000020) scratch pad register. 25.3.12 uartc_dll (0x00000004) divisor latch lsb. 25.3.13 uartc_dlm (0x00000008) divisor latch msb. table 343. scratch pad register name bit default r/w description - 31 - 08 0x0 - reserved user data 07 - 00 0x0 r/w 8 bits of information can be stored in this register. table 344. divisor latch lsb name bit default r/w description - 31 - 08 0x0 - reserved dll 07 - 00 0x0 r/w baud rate divisor latch least significant byte. table 345. divisor latch msb name bit default r/w description - 31 - 08 0x0 - reserved dlm 07 - 00 0x0 r/w baud rate divisor latch most significant byte. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 219 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 26. watchdog 26.1 general description there is one watchdog timer in asc8848/49/ 50/51 soc and it is used to monitor the system. the watchdog counter decrements its value at ever y apb clock. if the system does not reload the c ounter, the interrupt will be asserted when the coun ter is equal to the match value. if there is st ill no response after the inte rrupt, the system reset will be asserted. 26.2 features 26.2.1 key value the key value to reload the watchdog counter is a specific 32-bit data, 0x28791166. the watchdog counter will not be reloaded if the written value in the wdtc_reload_ctrl register does not match the key value. 26.2.2 programmable reset length. once the watchdog counter reaches zero, the system re set will be asserted. the length of the system reset is programmable using wdtc_rst_len register. 26.3 memory map register 26.3.1 wdtc_version (0x00000000) version information register. table 346. wdtc version information register name bit default r/w description major_version 31 - 24 0x01 r major version number minor_version 23 - 16 0x00 r minor version number build_version 15 - 08 0x00 r build version number revision 07 - 00 0x03 r revision number free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 220 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 26.3.2 wdtc_ctrl (0x00000004) control register. 26.3.3 wdtc_stat (0x00000008) state register. 26.3.4 wdtc_count (0x0000000c) counter register. 26.3.5 wdtc_reload_value (0x00000010) reload value register. table 347. control register name bit default r/w description - 31 - 03 0x0 - reserved op_en 02 0x0 r/w operation enable control. 1?b0: disable wdtc. 1?b1: enable wdtc. ack_en 01 0x0 r/w match value match acknowledgement enable control. 1?b0: disable match acknowledgement (interrupt). 1?b1: enable match acknowledgement (interrupt). ack 00 0x0 r/w match value match acknowledgement. this bit is only valid when both op_en and ack_en bits are high. 1?b0: value of wdtc counter not equal to match value mmr. 1?b1: value of wdtc counter equals match value mmr. table 348. state register name bit default r/w description - 31 - 01 0x0 - reserved match 00 0x0 r match value match status. 1?b0: the value of wdtc counter doesn?t equal to match value mmr. 1?b1: the value of wdtc counter equals to match value mmr. table 349. counter register name bit default r/w description count 31 - 00 0xffffffff r wdtc counter value. table 350. reload value register name bit default r/w description reload_value 31 - 00 0xffffffff r/w wdtc reload value. when writing key value to reload_ctrl mmr, the count mmr will load the value in reload_value to it. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 221 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 26.3.6 wdtc_match_value (0x00000014) match value register. [1] when the count value equals to match_value and both op_en and ack_en are high, the wdtc will send a one-cycle pulse interrupt through its intc_o_intr_p output port. 26.3.7 wdtc_reload_ctrl (0x00000018) reload control register. [1] writing the key value to this register will make count mmr load reload_value to it. the key value is fixed to 0x28791166. 26.3.8 wdtc_rst_len (0x0000001c) reset length register. 26.4 operation figure 53 shows the operation of the watchdog ti mer. if the system keeps reloading the watchdog counter, the interr upt and the system reset will never be asserted. once the interrupt is asserted when the watchdog counter is equal to the match value, there is still a period of time for the system to reload the watchdog counter to prevent the system reset being asserted. the length of the system reset is program able depending on the application?s requirement. table 351. match value register name bit default r/w description match_value [1] 31 - 00 0x0 r/w wdtc match value. table 352. reload control register name bit default r/w description reload_ctrl [1] 31 - 00 0x0 w wdtc reload control. table 353. reset length register name bit default r/w description rst_len 31-00 0x0000ffff r/w wdtc output reset signal length control. fig 53. operation of the watchdog timer 001aam978 apb clock match value = 0x20 reload value = 0xe0 reset length = 0x08 watchdog counter reload interrupt reset counter system reset 0x35 0x34 0x33 0xe0 0xdf 0xde 0xdd 0xdc 0x22 0x21 0x20 0x1f 0x1e 0x01 0x00 0x08 0x07 0x06 0x02 0x01 0x00 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 222 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 27. video output controller 27.1 general description video output controller (voc) generates t he timing reference signals and transmits digital video content. it can connect to a video encoder, a lcd panel, or an hdmi transmitter. the pixel clock is up to 180mhz.. 27.2 features 27.2.1 input video data format supports ycbcr 4:2:0 and ycbcr 4:2:2 formats 27.2.2 output data format support 8-bit ycbcr 4:2:2 progressive or interlace format with separate sync signals and bt.656 interface . support 16-bit ycbcr 4:2:2 progressive format with separate sync signals and bt.1120 interface. support rgb24 raw data with separate sync signals. each vsync represents one field of the input frame and even (or top) field is output first 27.3 memory map register 27.3.1 voc_version (0x00000000) version information register. 27.3.2 voc_ctrl (0x00000004) control register. table 354. voc version information register name bit default r/w description major_version 31 - 24 0x01 r major version number minor_version 23 - 16 0x03 r minor version number build_version 15 - 08 0x00 r build version number revision 07 - 00 0x0e r revision number table 355. voc control register name bit default r/w description in_stride 31 - 16 0x0 r/w input video stride - 15 - 14 0x0 - reserved 13 -13 0x0 reserved for asc8848/49/50 m1 version and asc8848 m2 version. enable bt.1120 progressive output format for asc8849/50 m2 version and ASC8851 1?b0: output format is decided by out_format (voc_ctrl[6]). 1?b1: bt.1120 progressive output format free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 223 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc outpin_sel 12 - 11 0x0 r/w when out_format is bt .656, the 8-bit ycbcr 4:2:2 data could be output through different byte lanes. 2?b00: voc_o_data[7:0]. 2?b01: voc_o_data[15:8]. 2?b1x: voc_o_data[23:16]. when output format is bt.1120 the 16-bit ycbcr 4:2:2 data could be output through different byte lanes. 2?bx0: voc_o_data[0:7] for y; voc_o_data[8:15] for cbcr 2?bx1: voc_o_data[8:15] for y; voc_o_data[16:23] for cbcr freerun_en 10 0x0 r/w enable the free-run mode of buffer switching. 1?b0: disable. 1?b1: enable. cbcr_format 09 0x0 r/w the chroma components format in yuv420 input image format. 1?b0: one field ycbcr 4:2:2. 1?b1: two fields ycbcr 4:2:0. field_mode 08 0x0 r/w 1?b0: one interleaved field in sdram. 1?b1: two single fields in sdram. in_format 07 0x0 r/w input image format. 1?b0: ycbcr 4:2:0. 1?b1: ycbcr 4:2:2. out_format 06 0x0 r/w output format. 1?b0:output rgb data with hsync, vsync, and blank 1?b1: output bt.656 interlaced parallel data. blank_trg 05 0x0 r/w blank signal polarity. 1?b0: active high blank signal. 1?b1: active low blank signal. clk_pol 04 0x0 r/w output pixel clock polarity. 1?b0: positive edge aligned with data. 1?b 1: negative edge aligned with data. rst_en 03 0x0 r/w software reset signal. this signal will be cleared automatically once the reset procedure is complete. 1?b0: do nothing or voc reset is complete. 1?b1: start to reset voc module. op_en 02 0x0 r/w set to start voc operation. 1?b0: disable voc operation. 1?b1: enable voc operation. op_cmpt_ack_en 01 0x0 r/w mask for voc operation complete acknowledge. 1?b0: disable voc operation complete acknowledge. 1?b1: enable voc operation complete acknowledge. op_cmpt_ack 00 0x0 r/w set when voc operation is complete. 1?b0: voc is busy or idle. 1?b1: voc operation is complete. table 355. voc control register ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 224 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 27.3.3 voc_stat (0x00000008) status register. 27.3.4 voc_addr group (0x0000000c~0x00000020) these registers specify input video buffer addresses. 27.3.5 voc_in_size (0x00000024) this register specifies the input video/image size. 27.3.6 voc_out_size (0x0000028) this register specifies the output video full size (includes blanking). table 356. status register name bit default r/w description - 31 - 04 0x0 - reserved frame_num 03 0x0 r when this signal is set, the mmrs of address should be updated. 1?b0:. 1?b1: field 02 0x0 r current output field for interlace bt.656 output. 1?b0: top field. 1?b1: bottom field. amba_err 01 0x0 r set when amba error occurs. op_cmpt 00 0x0 r set when voc operation is complete. 1?b0: voc is busy or idle. 1?b1: voc operation is complete. table 357. input video size name bit default r/w description in_height 31 - 16 0x0 r/w input video height. in_width 15 - 00 0x0 r/w input video height. table 358. output video full size name bit default r/w description height 31 - 16 0x0 r/w output video height width 15 - 0 0x0 r/w output video width free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 225 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 27.3.7 voc_out_size_ctrl (0x0000002c) this register specifies the output video position configuration parameters for bt.656. 27.3.8 voc_hsync_ctrl (0x00000030) this register controls the hsync output signal behavior. 27.3.9 voc_vsync_ctrl (0x00000034) this register cont rols the vsync output signal behavior. table 359. video position configuration parameters name bit default r/w description - 31 - 24 0x0 - reserved f1_olap 23 - 20 0x0 r/w overlap of the sav a nd eav code from field 1 to field 0. (pal:2, ntsc:3) f0_olap 19 - 16 0x0 r/w overlap of the sav and eav codes from field 0 to field 1. (pal:2, ntsc:2) f0_height 15 - 00 0x0 r/w field 0 height (pal:312, ntsc:262) table 360. hsync output signal behavior name bit default r/w description polarity 31 0x0 r/w hsync polarity. 1?b0: active high. 1?b1: active low - 30 - 24 0x0 - reserved delay_end 23 - 12 0x0 r/w hsync end point delay cycle. delay_start 11 - 00 0x0 r/w hsync start point delay cycle. table 361. vsync output signal behavior name bit default r/w description polarity 31 0x0 r/w vsync polarity. 1?b0: active high. 1?b1: active low - 30 - 24 0x0 - reserved delay_end 23 - 12 0x0 r/w vsync end point delay cycle. delay_start 11 - 00 0x0 r/w vsync start point delay cycle. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 226 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 27.3.10 voc_sbc_ctrl (0x00000038) this register specifies saturation, brightness and contrast adjustments. 27.3.11 voc_ycbcr2rgb_ coeff_0 (0x000003c) ycbcr to rgb conversion matrix: this register configures the coefficien ts for rgb to ycbcr conversion matrix. 27.3.12 voc_ycbcr2rgb_ coeff_1 (0x00000040) this register configures the coefficien ts for rgb to ycbcr conversion matrix. table 362. saturation, brightness and contrast adjustments name bit default r/w description - 31 - 25 0x0 - reserved saturation 24-16 0x80 r/w the saturation control on the output chrominance. (0~511, 128: off) brightness 15-08 0x0 r/w the brightness control on the output luminance (-128~127, 0:off) contrast 07-00 0x0 r/w the contrast control on the output luminance. (-128~127, 0:off) table 363. ycbcr to rgb conversion matrix name bit default r/w description - 31 0x0 - reserved coeff2 29 - 20 0x12a r/w coefficient 2 coeff1 19 - 10 0x199 r/w coefficient 1 coeff0 09 - 00 0x12a r/w coefficient 0 00 1 _ 234_ 256 560 _ r coeff coeff y y offset g coeff coeff coeff cb cb offset b coeff coeff cr cr offset ? ?? ? ?? ? ?? ? ?? ? =?? ? ?? ? ?? ? ?? ? ?? ? ? ?? ? ?? ? table 364. rgb to ycbcr conversion name bit default r/w description - 31 - 30 0x0 - reserved coeff5 29 - 20 0x12a r/w coefficient 5 coeff4 19 - 10 0x0d0 r/w coefficient 4 coeff3 09 - 00 0x064 r/w coefficient 3 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 227 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 27.3.13 voc_ycbcr2rgb_ coeff_2 (0x00000044) this register configures the coefficien ts for rgb to ycbcr conversion matrix. 27.4 output format figure 54 shows the timing diagram of 8-bit ycbc r 4:2:2 with separate sync signals and the bt.656 interface. these two formats will be output at the same time. the 8-bit data port could be output from different byte lanes depending on the register outpin_sel. both progressive and interlaced formats are supported. each vsync contains one field when the output is interlaced. figure 55 shows the timing diagram of 16-bit ycbcr 4:2:2 with separate sync signals and bt.1120 interface. these two formats will be output at the same time. the 16-bit data port could be output from different byte lanes depending on the register outpin_sel. only progressive fo rmat is supported table 365. configure coefficient fo r rgb to ycbcr conversion matrix name bit default r/w description cr_offset 31 - 24 0x80 r/w offset for cr cb_offset 23 - 16 0x80 r/w offset for cb. y_offset 15 - 10 0x10 r/w offset for y coeff6 09 - 00 0x204 r/w coefficient 6 fig 54. timing diagram of 8-bit ycbcr 4. 2.2 with separate sync signals and bt.656 interface 001aam979 cb0 y0 cr0 y1 .... xy 00 00 ff vsync hsync data[7:0] or data[15:8] or data[23:16] pclk free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 228 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc figure 56 shows the timing diagram of 24-bit rgb interface. it could be used to connect with the lcd module, hdmi transmitters and dac for vga format fig 55. timing diagram of 16-bit ycbcr 4:2:2 with separate sync signals and bt.1120 interface data[1 5:00] or data[2 3:08] vsync hsyn c cb0y0 cr0y1 cb1y2 cr2y3 ??? ffff 0000 0000 xy x y pclk fig 56. timing diagram of 24-b it rgb parallel interface. r0 r1 r2 r3 ??? g0 g1 g2 g3 ??? b0 b1 b2 b3 ??? vsync hsync data[23:16] data[15:08] data[07:00] pclk free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 229 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 28. ahb-to-apb bridge and dma controller 28.1 features this controller provides an ahb-to-apb bridge and a dma engine to tran sfer between ahb and apb buses. the bridge is the only ma ster on the apb bus. the dma engine is mainly used to transfer data from main memory to a device or vice versa without the host processor?s intervention. there is a two-level priority in the dma arbitration. for dma operations in the same priority, round-rob in arbitration is used. the following list comprises the various features supported: ? up to 16-channel apb dma operations. each channel operat es independently. ? up to 15 peripheral dma request/grant ports. ? 4 directions: apb-to-apb, apb-to-ahb , ahb-to-apb, and ahb-to-ahb dma operations. ? 2d scatter dma with the linked list. inte rnal mmr will be upda ted automatically. ? 8-/16-/32-/64-bit transfers. ? single, burst 4, burst 8 and burst 16 transfers. ? increment and decrement dma addressing. 28.2 memory map register 28.2.1 apbc_slave_n_basesize (0x00000000+n*4) slave configuration register (n=0~31). 28.2.2 apbc_version (0x00000080) version information register. table 366. slave configuration register name bit default r/w description base_addr_n 31 - 20 - r/w slave n base address [31:20]. - 19 - 00 0x0 - reserved table 367. version information register name bit default r/w description major_version 31 - 24 0x06 r major version number minor_version 23 - 16 0x00 r minor version number build_version 15 - 08 0x00 r build version number revision 07 - 00 0x06 r revision number free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 230 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 28.2.3 apbc_dma_priority (0x00000084) dma priority level register. 28.2.4 reserved (0x00000088) 28.2.5 apbc_dma_chn_moniter(0x0000008c) dma channel monitor register. 28.2.6 apbc_dma_n_src_addr (0x00000090+n*16) source address for dma channel n (n = 0~15). 28.2.7 apbc_dma_n_des_addr (0x00000094+n*16) destination address for dma channel n (n = 0~15). table 368. dma priority level register name bit default r/w description - 31 - 16 0x0 - reserved priority_level 15 - 00 0x0 r/w bits 0 - 15 represent channel 0 - 15 priorities. round-robin arbitration is used for requests in the same priority. 1?b0: lower level. 1?b1: higher level table 369. dma channel mon iter register name bit default r/w description - 31 - 16 0x0 - reserved chn_moniter 15 - 00 0x0 r/w bits 0 - 15 represent channel 0 - 15 statuses. it shows the channel which activated the interrupt signal and won?t be set to 0 until th e software set it to 0. table 370. source address for dma channel n name bit default r/w description src_addr_n 31 - 00 0x0 r/w the source addr ess for the current dma cycle can be read from this register table 371. destination address for dma channel n name bit default r/w description des_addr_n 31 - 00 0x00 r/w the destination address of the current dma cycle can be read from this register. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 231 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 28.2.8 apbc_dma_n_llp (0x00000098+n*16) linked list description pointer address (n = 0~15). 28.2.9 apbc_dma_n_ctrl (0x0000009c+n*16) basic control register (n = 0~15). table 372. linked list description point address name bit default r/w description addr_llp_n 31 - 00 0x0 r/w linked list description pointer address. scatter dma require this pointer to locate the command of the subsequent dma transfer and trigger ahb master to acquire the info. zero pointer address means no further dma is requested. following diagrams illustrates the data structure of linked list description fig 57. data structure of linked list description link list description pointer address (32-bit) src_addr (32-bit) des_addr (32-bit) llp (32-bit) sdram ctrl (32-bit) 001aan674 table 373. basic control register n name bit default r/w description cyc_n 31 - 20 0x0 r/w a dma cycle consist of 1/4/8/16-beat bus data transfer cycles, depending on burst_mode_n in the dma channel command register. data_sz_n 19 - 18 0x0 r/w data width of transfer. 00: 8-bit, byte. 01: 16-bit, half-word. 10: 32-bit, word. if you use the data size, the burst length could not be set to exceed 8 in one cycle. 11: 64-bit, double-word. if you use the data size, the burst length could not be set to e xceed 4 in one cycle. byte_swap_option_n 17 0x0 r/w byte swap option for 16-bit and 32-bit data widths. 0: no swap. do not change the byte order of the transferred data. 1: use swap. swap the byte order of the transferred data free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 232 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc req_type_n 16 0x0 r/w dma transfer type co rresponding to one dma request. when req_sel_n is zero, this parameter would be ignored and proceed dma as req_type_n is assigned zero. 0: cease dma transfer and assert dma grant signal after the cyc_n is reduced as zero. 1: cease dma transfer and assert dma grant signal after the cyc_n is reduced by one req_sel_n 15 - 12 0x0 r/w request signal select for dma mode. 0000: no request / grant signal. 0001~1111 (1~15): request / grant signal multiplexer select. des_addr_inc_n 11 - 10 0x0 r/w destin ation address incremental style. 00: no increment. 01: positive increment. 10: negative increment. 11: reserved. refer src_addr_inc to understand the actual number of address increment. src_addr_inc_n 09 - 08 0x0 r/w source address incremental style. 00: no increment. 01: positive increment. burst_mo de byte half-word word double-wor d 0+1+2+4+8 1+4+8+16+32 2+8+16+32+64 3 +16 +32 +64 +128 10: negative increment 11: reserved trans_type_n 07 - 06 0x0 r/w transfer type. 00: ahb2ahb. 01: ahb2apb. 10: apb2ahb. 11: apb2apb. burst_mode_n 05 - 04 0x0 r/w burst mode. 00: single 01: incr burst type with length 4 10: incr burst type with length 8 11: incr burst type with length 16 intr_ll_en_n 03 0x0 r/w enable (1) / disable (0) link- list update interrupt flag. when link-list is updated from ahb sdram, 4-clk edge- style interrupt will be asserted. this interrupt can be used to notify individual continuous memory dma is completed. table 373. basic control register n ?continued name bit default r/w description free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 233 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 28.3 apb dma operation 28.3.1 dma port the dma port is hard coded and req_ sel_n must be f illed according to table 374 . there are two type of devices could benefi t from the dma operation, ssic and i2ssc 0~4. req_type_n must be 1 fo r both devices.req_type_n must be 1 for both devices. intr_cmpt_en_n 02 0x0 r/w enable (1) / disab le (0) dma completion interrupt flag. intr_cmpt_n 01 0x0 r/w dma co mpletion interrupt flag. 0: no interrupt occurs. 1: interrupt occurs, write 0 to clear flag. op_en_n 00 0x0 r/w enable / disable apbc 0: disable or stop the dma channel. 1: enable or start the dma channel. if the transfer doesn?t require dma re quest to trigger, the assertion of this bit will start the transfer. table 373. basic control register n ?continued name bit default r/w description table 374. dma port dma port dma operation 0- 1- 2 ssic rx dma 3 ssic tx dma 4- 5- 6 i2ssc 0 rx dma 7 i2ssc 0 tx dma 8 i2ssc 1 rx dma 9- 10 i2ssc 2 rx dma 11 - 12 i2ssc 3 rx dma 13 - 14 i2ssc 4 rx dma 15 - free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 234 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 28.3.2 programming 1. prepare the linked list in the main memory . the format is the same as the dma mmr including src_addr, des_addr, llp, and ct rl. if llp is equal to 0x00000000, it means the end of the linked list. the first en try has to be filled in the mmr directly. 2. for a ssic tx transfer using dma channel 0 with 16384 bytes separated in 4 linked list pointers: specify the first llp in the mmr a. 0xc8000090 (src_addr) = 0x01000000 (physical memory base address for tx data) b. 0xc8000094 (des_addr) = 0x40800060 (dr register in ssic) c. 0xc8000098 (llp) = 0x00100000 (next llp in the main memory) d. 0xc800009c (ctrl) = 0x20073145 (16-bit data width, byte swap enable, dma port 3 from table 374 , ahb-to-apb, burst le ngth 4, only one interrupt after four llps are done) specify the second llp in the main memory address, 0x00100000 a. 0x00100000 (src_addr) = 0x01001000 b. 0x00100004 (des_addr) = 0x40800060 c. 0x00100008 (llp) = 0x00100004 d. 0x0010000c (ctrl) = 0x20073145 specify the third llp in the main memory address, 0x00100004 a. 0x00100000 (src_addr) = 0x01002000 b. 0x00100004 (des_addr) = 0x40800060 c. 0x00100008 (llp) = 0x00100008 d. 0x0010000c (ctrl) = 0x20073145 specify the fourth llp in the main memory address, 0x00100008 a. 0x00100000 (src_addr) = 0x01003000 b. 0x00100004 (des_addr) = 0x40800060 c. 0x00100008 (llp) = 0x00000000 (the last llp) d. 0x0010000c (ctrl) = 0x20073145 3. configure the peripheral device like ssic or i2ssc 0~4 to start dma operations. the dma operation starts when the hard coded dma tx or rx request of the peripheral device is asserted. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 235 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 29. limiting values table 375. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions [7] min max unit t case case temperature - [1] 085c v dd(c)(1v0) core power supply on pin vddc_1_0 [2] [3] 0.975 1.025 v v dd(c_ddr32sdmc_io_phy)(1v0 ) ddr-ii/iii phy core power supply on pin ddr32sdmc_io_phy_pwr_vddc _1_0 v dda(pciec_i_phy)(1v0) pci express phy low-voltage power supply on pin pciec_i_phy_pwr_vdda_1_0 v dd(c_usbc_io_phy)(1v0) usbphy digital power supply on pin usbc_io_phy_pwr_vddc_1_0 v dd(io)(3v3) input/output supply voltage (3.3 v) on pin vddio_3_3 3.135 3.465 v v dd(io)( 3v3) i/o power supply for gmii on pin vddio_2_5_3_3 v dda(usbc_io_phy)(3v3) usbphy analog power supply on pin usbc_io_phy_pwr_vdda_3_3 v dd(io)( 3v3) i/o power supply for rgmii on pin vddio_2_5_3_3 2.375 2.625 v v dda(ddr32sdmc_io_phy)(2v5) ddr-ii/iii phy pll power supply on pin ddr32sdmc_io_phy_pwr_vdda _2_5 v dda(pciec_i_phy)(2v5) pci express phy high-voltage power supply. on pin pciec_i_phy_pwr_vdda_2_5 v dda(pllc_i_pll0)(2v5) pll0 analog power supply on pin pllc_i_pll_0_pwr_vdda_2_5 v dda(pllc_i_pll1)(2v5) pll1 analog power supply on pin pllc_i_pll_1_pwr_vdda_2_5 v dda(pllc_i_pll2)(2v5) pll2 analog power supply on pin pllc_i_pll_2_pwr_vdda_2_5 v dda(pllc_i_pll3)(2v5) pll3 analog power supply on pin pllc_i_pll_3_pwr_vdda_2_5 v dda(usbc_io_phy)(2v5) usbphy analog power supply on pin usbc_io_phy_pwr_vdda_2_5 v dd(io_ddr32sdmc_io)( 1v8) ddr-ii sdram i/o power supply (vddq). on pin ddr32sdmc_io_pwr_vddio_1_8 1.71 1.89 v ddr-iii sdram i/o power supply (vddq) 1.425 1.575 v v ref(ddr32sdmc_io)( 0v9) ddr-ii/iii sdram reference power supply (vref). on pin ddr32sdmc_io_pwr_vref_0_9 0.49* vddq 0.51* vddq v vtt external termination voltage vref- 0.04 vref +0.04 v free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 236 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] operating temperature is the case surface temperature [2] for lot numbers smaller than 1037(e.g., 1036, 1030) these voltages should be 1.025(min), 1.050(typ), 1.075(max) [3] for asc8848/49/50 m2 version ASC8851 the min and max voltages are 0.95v and 1.05v respectively [4] applicable for asc8848/49/50 m2 version and ASC8851 only v ss(c)(1v0) core ground supply on pin vssc_1_0 0 0 v v ss(io)( 3v3) i/o ground supply on pin vssio_2_5_3_3 v ssa(ddr32sdmc_io_phy)(2v5) ddr-ii/iii phy pll ground supply on pin ddr32sdmc_io_phy_pwr_vssa_ 2_5 v ss(c_ddr32sdmc_io_phy)(1v0 ) ddr-ii/iii phy core ground supply on pin ddr32sdmc_io_phy_pwr_vssc _1_0 v ssa(pciec_i_phy)(1v0, 2v5) pci express phy ground supply on pin pciec_i_phy_pwr_vssa_1_0_2_5 v ss(c_usbc_io_phy)(1v0) usbphy digital ground supply on pin usbc_io_phy_pwr_vssc_1_0 v ssa(usbc_io_phy)(1v0, 2v5) usbphy analog ground supply on pin usbc_io_phy_pwr_vssa_2_5_3_ 3 v ssa(pllc_i_pll0)(2v5) pll0 analog ground supply. on pin pllc_i_pll_0_pwr_vssa_2_5 v ssa(pllc_i_pll1)(2v5) pll1 analog ground supply. on pin pllc_i_pll_1_pwr_vssa_2_5 v ssa(pllc_i_pll2)(2v5) pll2 analog ground supply. on pin pllc_i_pll_2_pwr_vssa_2_5 v ssa(pllc_i_pll3)(2v5) pll3 analog ground supply. on pin pllc_i_pll_3pwr_vssa_2_5 operating temperature [1] 085c v esd electrostatic discharge voltage human body model; all pins for asc8848/49/50 m1 version -1000 +1000 v human body model; all pins for asc8848/49/50 m2 version and ASC8851 -2000 +2000 vddio_sensor sensor i/o power supply if sensor is not operating at 3.3v and level shifters are skipped [4] 3.135 3.465 v 2.85 3.15 2.66 2.94 2.375 2.625 1.71 1.89 table 375. limiting values ?continued in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions [7] min max unit free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 237 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 30. recommended operating conditions table 376. operating conditions [1] [2] [3] [4] symbol parameter conditions [7] min typ max unit t case case temperature [5] [1] 085 0 c v dd(c)(1v0) core power supply on pin vddc_1_0 [6] [ 8] 0.975 1.000 1.025 v v dd(c_ddr32sdmc_io_phy )(1v0) ddr-ii/iii phy core power supply on pin ddr32sdmc_io_phy_pwr_vdd c_1_0 v dda(pciec_i_phy)(1v0) pci express phy low-voltage power supply on pin pciec_i_phy_pwr_vdda_1_0 v dd(c_usbc_io_phy)(1v0) usbphy digital power supply on pin usbc_io_phy_pwr_vddc_1_0 v dd(io)(3v3) input/output supply voltage (3.3 v) on pin vddio_3_3 3.135 3.3 3.465 v v dd(io)( 3v3) i/o power supply for gmii on pin vddio_2_5_3_3 v dda(usbc_io_phy)(3v3) usbphy analog power supply on pin usbc_io_phy_pwr_vdda_3_3 v dd(io)( 3v3) i/o power supply for rgmii on pin vddio_2_5_3_3 2.375 2.5 2.625 v v dda(ddr32sdmc_io_phy)( 2v5) ddr-ii/iii phy pll power supply on pin ddr32sdmc_io_phy_pwr_vdda _2_5 v dda(pciec_i_phy)(2v5) pci express phy high-voltage power supply. on pin pciec_i_phy_pwr_vdda_2_5 v dda(pllc_i_pll0)(2v5) pll0 analog power supply on pin pllc_i_pll_0_pwr_vdda_2_5 v dda(pllc_i_pll1)(2v5) pll1 analog power supply on pin pllc_i_pll_1_pwr_vdda_2_5 v dda(pllc_i_pll2)(2v5) pll2 analog power supply on pin pllc_i_pll_2_pwr_vdda_2_5 v dda(pllc_i_pll3)(2v5) pll3 analog power supply on pin pllc_i_pll_3_pwr_vdda_2_5 v dda(usbc_io_phy)(2v5) usbphy analog power supply on pin usbc_io_phy_pwr_vdda_2_5 2.375 2.5 2.625 v v dd(io_ddr32sdmc_io)( 1v8) ddr-ii sdram i/o power supply (vddq) on pin ddr32sdmc_io_pwr_vddio_1_8 1.71 1.8 1.89 v ddr-iii sdram i/o power supply (vddq) 1.427 1.5 1.575 v ref(ddr32sdmc_io)( 0v9) ddr-ii/iii sdram reference power supply (vref). on pin ddr32sdmc_io_pwr_vref_0_9 0.49* vddq 0.5* vddq 0.51* vddq v v tt external termination voltage vref -0.04 vref vref +0.04 v vddio_sensor sensor i/o power supply 3.135 3.3 3.465 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 238 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] the power supply values specified in table 378 are dc design criteria only. they represent the dc supply limits at the devices internal to the design, including the effects of internal ir drop. [2] vref of the receiving device(s) should tr ack the variations in the dc value of vd dq of the sending device for best noise mar gins. the value of vref is to be selected by the user to provide optimum noise margin in the use conditions specified by the user. [3] peak-to-peak noise on vref may not exceed 5 % vref (dc). [4] power-up sequence for asc8848/49/50/51 is v1.0 -> v1.8 -> v2.5 -> v3.3 and power-down sequence is vdd3.3 -> vdd2.5 -> vdd1.8 -> vdd1.0. please refer to hardw are application note for details. [5] operating temperature is the case surface temperature [6] for lot numbers smaller than 1037(e.g., 1036, 1030) these voltages should be 1.025(min), 1.050(typ), 1.075(max) [7] applicable for asc8848/49/50 m2 version and ASC8851 only [8] for asc8848/49/50 m2 version ASC8851 the min and max voltages are 0.95v and 1.05v respectively 2.85 3.0 3.15 2.66 2.8 2.94 2.375 2.5 2.625 1.71 1.8 1.89 v ss(c)(1v0) core ground supply on pin vssc_1_0 0 0 0 v v ss(io)( 3v3) i/o ground supply on pin vssio_2_5_3_3 v ssa(ddr32sdmc_io_phy)( 2v5) ddr-ii/iii phy pll ground supply on pin ddr32sdmc_io_phy_pwr_vssa _2_5 v ss(c_ddr32sdmc_io_phy )(1v0) ddr-ii/iii phy core ground supply on pin ddr32sdmc_io_phy_pwr_vssc _1_0 v ss(io_ddr32sdmc_io)(1v8 ) ddr-ii/iii sdram i/o ground supply on pin ddr32sdmc_io_p wr_vssio_1_8 v ssa(pciec_i_phy)(1v0, 2v5) pci express phy ground supply on pin pciec_i_phy_pwr_vssa_1_0_2_ 5 v ss(c_usbc_io_phy)(1v0) usbphy digital ground supply on pin usbc_io_phy_pwr_vssc_1_0 v ssa(usbc_io_phy)(1v0, 2v5) usbphy analog ground supply on pin usbc_io_phy_pwr_vssa_2_5_3 _3 v ssa(pllc_i_pll0)(2v5) pll0 analog ground supply. on pin pllc_i_pll_0_pwr_vssa_2_5 v ssa(pllc_i_pll1)(2v5) pll1 analog ground supply. on pin pllc_i_pll_1_pwr_vssa_2_5 0 00v v ssa(pllc_i_pll2)(2v5) pll2 analog ground supply. on pin pllc_i_pll_2_pwr_vssa_2_5 v ssa(pllc_i_pll3)(2v5) pll3 analog ground supply. on pin pllc_i_pll_3_pwr_vssa_2_5 operating temperature 0 85 c table 376. operating conditions ?continued [1] [2] [3] [4] symbol parameter conditions [7] min typ max unit free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 239 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 31. characteristics the simulation environment for the thermal informatio n is as follows. ? pcb layers: 6 layers ? ambient temperature: 90 c ? substrate: 4 layers (1/2/1) ? maximum junction temperature: 125 c ? the air flow of ja is 0 m/s. 31.1 dc/ac i/o characteristics 31.1.1 ddr-ii interface for asc8848/49/50 m1 version table 377. thermal resistance characteristics symbol parameter value unit ja junction-to-free air 20.9 c/w jb junction-to-board 15.0 c/w jc junction-to-case 4.2 c/w psi jt junction-to-package top 13.5 c/w table 378. ddr-ii i/o dc characteristics symbol parameter min type max units v iht dc input logic threshold high - - vref + 0.025 v v ilt dc input logic threshold low vref-0.025 - - v v ih dc input voltage high - - vd33 + 0.3 v v il dc input voltage low ? 0.3 - - v v oh dc output voltage high vddq-0.3 - - v v ol dc output voltage low - - 0.3 v r tt1 rtt effective impedance value ? 30 % ? 50 +41 % ohm r tt2 rtt effective impedance value ? 42 % 75 +41 % ohm r tt3 rtt effective impedance value ? 42 % 150 +41 % ohm r serdrv series output resistance ? 10 % 34 +10 % ohm table 379. ddr-ii i/o ac characteristics symbol parameter min type max units t pdrv output delay 0.41 - 0.86 ns t rise/fall output driver slew rate 30 % - 70 % 40 - 200 ps t pvz output tri-state delay - valid data to high z 0.43 - 0.82 ns t pvz output tri-state delay - high z to valid data 0.47 - 0.74 ns t rcv input delay 0.30 - 0.50 ns t ipwd input pulse width distortion - - 35 ps free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 240 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] the values given are for the asc8850/51 on ly, for further details please refer to table 2 the following tables show ddr-ii i/o ac and dc characteristics. 31.1.2 ddr-ii interface for m2 vers ion of asc8848/ 8849/8850 and ASC8851 t opwd output pulse width distortion - - 35 ps f max maximum operating frequency - - 400 mhz d max maximum operating data rate - - 800 mb/s table 379. ddr-ii i/o ac characteristics ?continued symbol parameter min type max units table 380. ddr-ii i/o dc characteristics parameter symbol min typ max units dc input voltage high v ih(dc) vref+0.125 -- vddq+0.3 v dc input voltage low v il(dc) vssq-0.3 -- vref-0.125 v dc output voltage high v oh vddq-0.28----v dc output voltage low v ol -- -- vssq+0.28 v input termination resistance (odt) to vddq/2 r tt1 120 150 180 ohm 60 75 90 ohm 40 50 60 ohm table 381. ddr-ii i/o ac characteristics parameter symbol min typ max units output delay t pdrv 0.54 0.72 1.1 ns output driver slew rate (at sdram pin) sr 3.07 3.5 4.02 v/ns output tri-state delay - valid data to highz t pvz 0.57 0.74 1.12 ns output tri-state delay - highz to valid data t pzv 0.53 0.72 1.12 ns input delay t prcv 0.25 0.34 0.5 ns maximum operating frequency (ASC8851/50/49/48 m2) f max -- -- 400/400/300/266 mhz maximum operating data rate (ASC8851/50/49/48 m2) d max -- -- 800/800/600/533 mb/s input mode ac power (vddq rail) p rcv 0.7 0.8 0.93 uw/mhz free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 241 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 31.1.3 ddr-iii for m2 version of asc8848/8849/8850 and ASC8851 the following tables show ddr-i ii i/o ac and dc characteristics input mode ac power (vdd rail) p rcv 0.12 0.14 0.17 uw/mhz output mode ac power (vddq rail) p drv 14.87 15.72 17.81 uw/mhz output mode ac power (vdd rail) p drv 0.36 0.44 0.54 uw/mhz table 381. ddr-ii i/o ac characteristics parameter symbol min typ max units table 382. ddr-iii i/o dc characteristics parameter symbol min typ max units dc input voltage high v ih(dc) vref+0.100 -- vddq v dc input voltage low v il(dc) vssq-0.3 -- vref-0.100 v dc output voltage high v oh 0.8 vddq -- -- v dc output voltage low v ol -- -- 0.2 vssq v input termination resistance (odt) to vddq/2 r tt1 100 120 140 ohm 54 60 66 ohm 36 40 44 ohm table 383. ddr-iii i/o ac characteristics parameter symbol min typ max units output delay tpdrv 0.62 0.82 1.3 ns output driver slew rate (at sdram pin) sr 2.74 3.14 3.44 v/ns output tri-state delay - valid data to highz tpvz 0.63 0.82 1.32 ns output tri-state delay - highz to valid data tpzv 0.6 0.82 1.3 ns input delay tprcv 0.3 0.4 0.61 ns maximum operating frequency (ASC8851/50/49 /48 m2) fmax -- -- 400/400/300/266 mhz maximum operating data rate (ASC8851/50/49/ 48 m2) dmax -- -- 800/800/600/533 mb/s input mode ac power (vddq rail) prcv 0.49 0.59 0.75 uw/mhz free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 242 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 31.1.4 usb dp, dm and vbus are 5v-tolerant i/os and table 384 shows the usb i/o operating condition. 31.1.5 general i/os all 3.3v i/os except for gmii/rgmii i/os use the ta b l e 3 8 5 for i/o characteristics, such as gpio, mshc, nfc, ssi, uart, vic, voc. input mode ac power (vdd rail) prcv 0.12 0.14 0.18 uw/mhz output mode ac power (vddq rail) pdrv 7.38 8.08 9.18 uw/mhz output mode ac power (vdd rail) pdrv 0.36 0.44 0.54 uw/mhz table 383. ddr-iii i/o ac characteristics parameter symbol min typ max units table 384. usb i/o operating condition pad name min type max units usbc_io_phy_vbus - - 5.25 v usbc_io_phy_dp - - 5.25 v usbc_io_phy_dm - - 5.25 v table 385. general i/o characteristics parameter symbol min type max units input high level voltage v ih 0.7 * dvdd [1] -dvdd + 0.3v input low level voltage v il dvss [2] -0.3 - 0.3 * dvss v input hysteresis voltage v hys 0.4 - - v dvdd supply leakage current with vdd core power down (dvdd=1.98v, vdd=0v) i ilpd --0.5 a dvdd supply leakage current with vdd core power down (dvdd=3.60v, vdd=0v) 1 a io high-z state leakage current (dvdd=1.98v, vi=0~dvdd) i ilz --0.5 a io high-z state leakage current (dvdd=3.60v, vi=0~dvdd) --1 a pull-down current (dvdd=1.8v) i po 26.24 53.53 99.91 a pull-down current (dvdd=3v) 52.4 105.9 184.3 a pull-up current (dvdd=1.8v) i pu ? 74.23 ? 42.30 ? 23.35 a pull-up current (dvdd=3v) ? 115.2 ? 71.61 ? 42.58 a io high-z state leakage current i ilz --1 a output high level v oh dvdd-0.4 - - v output low level v ol --0.4v high level output current (dvdd=1.8v) v oh =dvdd-0.4 2 ma i oh 3.42 5.63 8.77 ma 4 ma 6.84 11.25 17.54 ma 8 ma 9.12 15.00 23.39 ma 12 ma 12.6 20.4 32.3 ma free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 243 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc [1] 1. dvdd is a symbol for vddio_sensor (vic) or vddio_common_3_3 (others). [2] dvss is a symbol for vssio_common. [3] it is recommended to use 1k ohm resistor to pull the signal to the opposite supply low level output current (dvdd=1.8v) v ol =0.4v 2 ma i ol 4.93 8.53 13.18 ma 4 ma 7.39 12.79 19.77 ma 8 ma 12.32 21.32 32.95 ma 12 ma 14.79 25.58 39.54 ma high level output current (dvdd=3.3v) v oh =dvdd-0.4 2 ma i oh 4.30 6.35 8.94 ma 4 ma 6.44 9.52 13.41 ma 8 ma 10.74 15.87 22.35 ma 12 ma 12.89 19.05 26.82 ma low level output current (dvdd=3.3v) v ol =0.4v 2 ma i ol 9.16 13.86 18.47 ma 4 ma 13.73 20.78 27.70 ma 8 ma 22.84 34.62 46.15 ma 12 ma 27.41 41.54 55.38 ma table 385. general i/o characteristics parameter symbol min type max units free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 244 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 31.1.6 gmii/rgmii gmii/rgmii i/os have two operating voltages, 2.5 v and 3.3 v. table 386 shows the i/o characteristics. [1] dvdd is a symbol for vddio_2_5_3_3. 31.1.7 osc the osc i/o is designed to generate an asynchronous on-chip clock signal with an appropriate external oscillator crystal. most crystal manufacturers recommend a 10 pf capacitor to ground from both the input and out put pins of the osc i/o for crystal stability. the design has been characterized to allow a variation of 4 pf to 18 pf on each pin. [1] when using an external oscillator on sys_i_ osc_0_clk, sys_i_osc_1_clk, or sys_i_osc_2_clk, the voltage level must not exceed vddc_1_0. [2] vdd is a symbol for vddc_1_0 [3] vss is a symbol for vssc_1_0 table 386. gmii/rgmii i/o characteristics symbol parameter min type max units v ih input high level voltage (rgmii) 1.7 - - v v il input low level voltage (rgmii) - - 0.7 v v ih input high level voltage (gmii) 1.7 - - v v il input low level voltage (gmii) - - 0.9 v v oh output high level (rgmii) 2.0 - dvdd [1] + 0.3 v v ol output low level (rgmii) -0.3 - 0.4 v v oh output high level (gmii) 2.1 - 3.6 v v ol output low level (gmii) 0 - 0.5 v table 387. osc i/o characteristics [1] symbol parameter min type max units v ih input high level voltage 0.9* vdd [2] - vdd + 0.3 v v il input low level voltage vss [3] - 0.3 - 0.3*vss v vhys input hysteresis voltage 0.4 - - v iddq bypass (using the external oscillator) - - 1 a free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 245 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 31.1.8 pcie 31.1.8.1 reference clock the reference clock signal is differenti al and supports frequencies of 25 mhz or 50 mhz to 156.25 mhz (100 mhz and 125 mhz are common frequencies). the 100 mhz reference clock specifications are defined in pci expresstm card electromechanical specification. 31.1.8.2 tx/rx characteristics it meets or exceeds the electrical compliance requirements in the pcie base specification. table 388. pcie reference clock characteristics symbol parameter min typ max units v high high voltage 600 710 850 mv v low low voltage ? 150 0 - mv v cross voltage absolute crossing point 250 - 550 mv v cross total variation of v cross - - 140 mv t ccjitter cycle-to-cycle jitter - - 125 ps t duty duty cycle 45 - 55 % table 389. pcie tx characteristics symbol parameter min typ max units v tx_diff_pp output voltage peak-to-peak differential amplitude 0.937 - 1.24 v v ctm transmit common mode voltage 0.4 - 0.6 v z d differential output impedance 85 - 115 table 390. pcie rx characteristics symbol parameter min typ max units v rx_diff_pp input voltage peak-to-peak differential amplitude 175 - mv z in differential input impedance 85 - 115 ppm tolerance ? 350 - 350 ppm free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 246 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 31.2 solder reflow profile asc8848/49/50/51 soc is available in a pb-free package. the reflow profile is shown below which follows ipc/jede c j-std-020 d. the time between reflows shall be 8 minutes minimum and 60 minutes maximum. it shall be 8 minutes maximum from 25c to the peak temperature fig 58. reflow profile 001aam934 25 c 217 c slope: 1 ~ 2 c/s max. (217 c to peak) 255 c peak temp 260 + 5 ? 0 c ramp down rate: 3 c/s max. above 30 s 60 s ~ 150 s 60 s ~ 120 s preheat: 150 c ~ 200 c free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 247 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 32. package outline fig 59. asc8848/49/50/51 soc tfbga-484 package physical dimension references outline version european projection issue date iec jedec jeita tfbga484 tfbga484_po 10-10-18 11-02-01 unit (1) mm max nom min 1.2 0.26 0.21 0.16 0.35 0.30 0.25 15.1 15.0 14.9 15.1 15.0 14.9 0.65 13.65 x x a dimensions note 1. xxxxxxx package description line tfbga484 a 1 a 2 0.94 0.89 0.84 bdeee 1 13.65 e 2 vw x yy 1 x 0 5 10 mm scale ball a1 index area b a d e c y c y 1 x detail x a a 1 a 2 b a b c d e f h k g l j m n p r t u v w y aa ab 2 4 6 8 10 12 14 16 13579111315 18 20 22 17 19 21 e 2 e 1 e e 1/2 e 1/2 e a c b ? v c ? w ball a1 index area free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 248 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 33. abbreviations 34. references [1] hdmi_nand_flash_app_note.pdf [2] thermal management for asc8850.pdf [3] asc8850_m1_to_m2_migration_guide_v1.2.pdf table 391. abbreviations acronym description adc analog-to-digital converter aes advanced encryption standard ahb advanced high-performance bus apb advanced peripheral bus dac digital-to-analog converter ddr double data rate dma direct memory access gmii gigabit media independent interface gpio general purpose input/output irda infrared data association jpeg joint photographic experts group jtag joint test action group lcd liquid crystal display lsb least significant bit mac media access control mii media independent interface mpeg moving picture experts group mshc memory stick host controller n.c. not connected rgmii reduced gigabit me dia independent interface otg on-the-go phy physical layer pll phase-locked loop pwm pulse width modulator sdram synchronous dynami c random access memory soc system on chip spi serial peripheral interface uart universal asynchronous receiver/transmitter usart universal synchronous asynchronous receiver/transmitter usb universal serial bus free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 249 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 35. revision history table 392. revision history document id release date data sheet status change notice supersedes asc8848_49_50_m1 m2 24-09-2011 preliminary draft details on ASC8851 and asc8848/49/50 m2 such as register settings, interfaces, pin-outs, ball map are provided. fig. 3 updated for a13 and b13 pins ball map for pin v13 has been updated in fig 5 asc8848_49_50_51 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 250 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 36. legal information 36.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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applications that are described herein for any of th ese products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without furthe r testing or modification. customers are responsible for the design and operation of their applications and products usin g nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or cust omer product design. it is customer?s sole responsibility to determine whether t he nxp semiconductors product is suitable an d fit for the customer?s applications and products planned, as well as for the planned application and us e of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimi ze the risks associated with thei r applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s) . customer is responsible for doing all necessary testing for the customer?s applications and pr oducts using nxp semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer?s third part y customer(s). nxp does not accept any liability in this respect. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification. free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 251 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting va lues are stress ratings only and (proper) operation of the device at these or any other conditions above those given in t he recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently a nd irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concl uded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expr essly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semicond uctors products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copy rights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. quick reference data ? the quick reference data is an extract of t he product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semiconductors product is automotive qualified, the product is not suitable for automotiv e use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in au tomotive equipment or applications. in the event that customer uses the product for design-in and us e in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semi conductors? warranty of the product for such automotive applications, use and specifications, and (b) whenever custom er uses the product for autom otive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond nxp se miconductors? standard warranty and nxp semiconductors? product specifications. 36.4 trademarks notice: all referenced brands, product names, service names an d trademarks are the property of their respective owners. 37. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 252 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc 38. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 high quality media . . . . . . . . . . . . . . . . . . . . . . 2 2.1.1 h.264 encoder . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1.2 mpeg-4 encoder . . . . . . . . . . . . . . . . . . . . . . . 2 2.1.3 jpeg encoder . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 flexible platform . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2.1 video/sensor interface . . . . . . . . . . . . . . . . . . . 3 2.2.2 audio interface . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.3 image processing . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.4 data encryption . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.5 host controller . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.6 external memory interface . . . . . . . . . . . . . . . . 4 2.2.7 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 ordering information . . . . . . . . . . . . . . . . . . . . . 5 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 8 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 16 6 functional description . . . . . . . . . . . . . . . . . . 44 6.1 function selection. . . . . . . . . . . . . . . . . . . . . . 44 6.2 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3 boot flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3.1 sd card boot flow . . . . . . . . . . . . . . . . . . . . . . 47 6.3.2 serial flash boot flow . . . . . . . . . . . . . . . . . . . 48 6.3.3 nand flash boot flow . . . . . . . . . . . . . . . . . . . 49 6.4 boot image . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4.1 sd card boot image . . . . . . . . . . . . . . . . . . . . 50 6.4.2 serial flash boot image . . . . . . . . . . . . . . . . . . 50 6.4.3 nand flash boot image . . . . . . . . . . . . . . . . . 51 6.5 limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5.1 sd card boot code . . . . . . . . . . . . . . . . . . . . . 52 6.5.2 serial flash boot code . . . . . . . . . . . . . . . . . . . 54 6.5.3 nand flash boot code . . . . . . . . . . . . . . . . . . 54 7 system controller, resets and clocks. . . . . . . 56 7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.1.1 clock generation. . . . . . . . . . . . . . . . . . . . . . . 56 7.1.2 reset signal generation . . . . . . . . . . . . . . . . . 56 7.1.3 i/o pad control . . . . . . . . . . . . . . . . . . . . . . . . 56 7.2 memory map register . . . . . . . . . . . . . . . . . . . 56 7.2.2 reserved (0x00000004) . . . . . . . . . . . . . . . . 56 7.2.3 sysc_chip_id_0 (0x00000008) . . . . . . . . . 56 7.2.4 sysc_chip_id_1 (0x0000000c) . . . . . . . . . 56 7.2.5 sysc_chip_id_2 (0x00000010) . . . . . . . . . 57 7.2.6 sysc_chip_version (0x00000014) . . . . . 57 7.2.7 sysc_cnt_ctrl (0x00000018) . . . . . . . . . 57 7.2.8 sysc_cnt_low (0 x0000001c) . . . . . . . . . 57 7.2.9 sysc_cnt_high (0x00000020) . . . . . . . . . 57 7.2.10 sysc_clk_en_ctrl_0 (0x00000024) . . . . 58 7.2.11 sysc_clk_en_ctrl_1 (0x00000028) . . . . 60 7.2.12 sysc_clk_gen_cfg (0x0000002c) . . . . . 62 7.2.13 sysc_mon_clk_sel (0x00000030) . . . . . 63 7.2.14 sysc_sys_info (0x00000034) . . . . . . . . . . 65 7.2.15 reserved (0x00000038~0x00000040) . . . . . . 65 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 253 of 263 continued >> nxp semiconductors asc8848_49_50_51 multimedia soc 7.2.16 sysc_pad_en_ctrl (0x00000044) . . . . . . 65 7.2.17 sysc_if_ctrl (0x00000048) . . . . . . . . . . . 66 7.2.18 sysc_slew_ctrl (0x0000004c). . . . . . . . 66 7.2.19 sysc_pull_ctrl (0x00000050) . . . . . . . . 67 7.2.20 sysc_drv_s trength_ctrl_0 (0x00000054) . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.2.21 sysc_drv_s trength_ctrl_1 (0x00000058) . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.2.22 sysc_drv_s trength_ctrl_2 (0x0000005c) . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3 clock signal distributions . . . . . . . . . . . . . . . . 70 7.3.1 system clocks . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.2 giga-bit ethernet mac . . . . . . . . . . . . . . . . . . 70 7.3.3 mobile storage controller . . . . . . . . . . . . . . . . 71 7.3.4 i 2 s and uart . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3.5 video output controller . . . . . . . . . . . . . . . . . 72 7.3.6 usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3.7 video input controller . . . . . . . . . . . . . . . . . . . 73 7.3.8 pci express . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4 reset signal generation . . . . . . . . . . . . . . . . . 73 8 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.1 general description . . . . . . . . . . . . . . . . . . . . 74 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.2.1 read only memory (rom) . . . . . . . . . . . . . . . 74 8.2.2 static random access memory (sram) . . . . 74 8.3 memory map register . . . . . . . . . . . . . . . . . . . 74 8.3.1 rom block (0x00000000~0x000007ff) . . . . 74 8.3.2 ram block (0x00001000~0x000021ff). . . . . 74 8.3.3 brc_version (0x00004000). . . . . . . . . . . . 74 8.3.4 brc_ctrl (0x00004004) . . . . . . . . . . . . . . . 75 9 ddr-ii sdram controller (for asc8848/49/50 m1 version only) . . . . . . . . . . . . . . . . . . . . . . . 75 9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.1 data width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.2 external bank . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.3 memory size . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.4 data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.5 page number . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.6 bank number . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.7 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.2 memory map register . . . . . . . . . . . . . . . . . . . 76 9.2.1 ddr2sdmc_version (0x00000000) . . . . . 76 9.2.2 ddr2sdmc_ctrl (0x00000004). . . . . . . . . 76 9.2.3 reserved (0x00000008) . . . . . . . . . . . . . . . . . 77 9.2.4 ddr2sdmc_size_cfg (0x0000000c) . . . . 77 9.2.5 ddr2sdmc_load_mode_0_1_cfg (0x00000010) . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.2.6 ddr2sdmc_load_mode_2_3_cfg (0x00000014) . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.2.7 ddr2sdmc_timing_c fg_0 (0x00000018) 78 9.2.8 ddr2sdmc_timing_cfg_1 (0x0000001c) 78 9.2.9 ddr2sdmc_timing_cfg_2 (0x00000020) 78 9.2.10 ddr2sdmc_timing_cfg_3 (0x00000024) 78 10 ddr-ii/iii sdram controller (for asc8848/49/50 m2 version and ASC8851) . . . . . . . . . . . . . . . 80 10.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.1.1 data width . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.1.2 . . . . . . . . . . . . . . . . . . . . . . . . . external bank 80 10.1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . memory size 80 10.1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . data type 80 10.1.5 . . . . . . . . . . . . . . . . . . . . . . . . . page number 80 10.1.6 . . . . . . . . . . . . . . . . . . . . . . . . . bank number 80 10.1.7 . . . . . . . . . . . . . . . . . . . . . . . column latency 80 10.1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . burst type 80 10.2 . . . . . . . . . . . . . . . . . . . memory map register 80 10.2.1 . . . . .ddr32sdmc_version (0x00000000) 81 10.2.1.1 . . . . . . . . ddr32sdmc_ctrl (0x00000004) 81 10.2.2 reserved (0x00000008) . . . . . . . . . . . . . . . . 82 10.2.3 . . . .ddr32sdmc_size_cfg (0x0000000c) 82 10.2.4 . . . . . . . ddr32sdmc_load_mode_0_1_cfg (0x00000010). . . . . . . . . . . . . . . . . . . . . . . . . 82 10.2.5 . . . . . . . ddr32sdmc_load_mode_2_3_cfg (0x00000014). . . . . . . . . . . . . . . . . . . . . . . . . 83 10.2.6 ddr32sdmc_timing_cfg_0 (0x00000018) 83 10.2.7 . . ddr32sdmc_timing_cfg_1 (0x0000001c) 83 10.2.8 ddr32sdmc_timing_cfg_2 (0x00000020) 84 10.2.9 ddr32sdmc_timing_cfg_3 (0x00000024) 84 10.2.10 . . . . ddr32sdmc_zq_ctrl (0x00000028) 84 10.2.11 . . ddr32sdmc_powr_down_mode_ctrl (0x0000002c) . . . . . . . . . . . . . . . . . . . . . . . . 85 10.2.12 .ddr32sdmc_self_refresh_mode_ctrl (0x00000030). . . . . . . . . . . . . . . . . . . . . . . . . 86 10.2.13 7.2.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ddr32sdmc_powr_down_and_self_re fresh_mode_timing (0x00000034) . . . . 86 10.2.14 . . . . . . . . . . ddr32sdmc_io_dynamic_ctrl (0x00000038). . . . . . . . . . . . . . . . . . . . . . . . . 86 10.2.15 . ddr32sdmc_io_bit_enable (0x0000003c) 87 10.2.16 . . . . ddr32sdmc_dfi_ctrl (0x00000040) 88 10.2.17 . . . . . . . . . . ddr32sdmc_load_mode_ctrl (0x00000044). . . . . . . . . . . . . . . . . . . . . . . . . 88 11 interrupt controller . . . . . . . . . . . . . . . . . . . . . 89 11.1 general description . . . . . . . . . . . . . . . . . . . . 89 11.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.1 interrupt number . . . . . . . . . . . . . . . . . . . . . . 89 11.2.2 interrupt source . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.3 interrupt map . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.3 memory map register . . . . . . . . . . . . . . . . . . . 90 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 254 of 263 continued >> nxp semiconductors asc8848_49_50_51 multimedia soc 11.3.1 intc_version (0x00000000) . . . . . . . . . . . 90 11.3.2 intc_src_lo (0x00000004) . . . . . . . . . . . . 91 11.3.3 intc_src_hi (0x00000008) . . . . . . . . . . . . . 91 11.3.4 intc_stat_lo (0x0000000c) . . . . . . . . . . . 91 11.3.5 intc_stat_hi (0x00000010) . . . . . . . . . . . . 91 11.3.6 intc_mask_lo (0x00000014) . . . . . . . . . . . 91 11.3.7 intc_mask_hi (0x00000018) . . . . . . . . . . . 91 11.3.8 intc_clear_lo (0x00000 01c). . . . . . . . . . 92 11.3.9 intc_clear_hi (0x00000020). . . . . . . . . . . 92 11.3.10 intc_trigger_mode_lo (0x00000024) . 92 11.3.11 intc_trigger_mode_hi (0x00000028) . . 92 11.3.12 intc_set_lo (0x0000002c ) . . . . . . . . . . . . 92 11.3.13 intc_set_hi (0x00000030) . . . . . . . . . . . . . 93 12 timer controller . . . . . . . . . . . . . . . . . . . . . . . . 93 12.1 general description . . . . . . . . . . . . . . . . . . . . 93 12.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.2.1 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . 93 12.2.2 counting direction. . . . . . . . . . . . . . . . . . . . . . 93 12.2.3 auto-reload value . . . . . . . . . . . . . . . . . . . . . . 93 12.2.4 memory map register . . . . . . . . . . . . . . . . . . . 94 12.2.4.1 tmrc_version (0x00000000) . . . . . . . . . . 94 12.2.4.2 tmrc_ctrl (0x00000004). . . . . . . . . . . . . . 94 12.2.4.3 reserved (0x00000008) . . . . . . . . . . . . . . . . . 95 12.2.4.4 tmrc_timer0_counter (0x0000000c). . 95 12.2.4.5 tmrc_timer0_auto_reload_value (0x00000010) . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.2.4.6 tmrc_timer0_match_value (0x00000014). 95 12.2.4.7 tmrc_timer1_counter (0x00000018) . . 96 12.2.4.8 tmrc_timer1_auto_reload_value (0x0000001c) . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.2.4.9 tmrc_timer1_match_value (0x00000020). 96 12.2.4.10 tmrc_timer2_counter (0x00000024) . . 96 12.2.4.11 tmrc_timer2_auto_reload_value (0x00000028) . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.2.4.12 tmrc_timer2_match_value (0x0000002c) 96 12.2.4.13 tmrc_timer3_counter (0x00000030) . . 97 12.2.4.14 tmrc_timer3_auto_reload_value (0x00000034) . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.2.4.15 tmrc_timer3_match_value (0x00000038). 97 13 phase lock loop controller . . . . . . . . . . . . . . 98 13.1 general description . . . . . . . . . . . . . . . . . . . . 98 13.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.3 memory map register . . . . . . . . . . . . . . . . . . 98 13.3.1 pllc_version (0x00000000). . . . . . . . . . . 98 13.3.2 pllc_ctrl_0 (0x00000004) . . . . . . . . . . . . 98 13.3.3 pllc_ratio_0 (0x00000008). . . . . . . . . . . . 99 13.3.4 pllc_ctrl_1(0x0000000c) . . . . . . . . . . . . 99 13.3.5 pllc_ratio_1 (0x00000010) . . . . . . . . . . 100 13.3.6 pllc_ctrl_2 (0x00000014) . . . . . . . . . . . 100 13.3.7 pllc_ratio_2 (0x00000018) . . . . . . . . . . 101 13.3.8 pllc_ctrl_3 (0x0000001c). . . . . . . . . . . 101 13.3.9 pllc_ratio_3 (0x00000020) . . . . . . . . . . 102 13.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . 102 13.5 programming . . . . . . . . . . . . . . . . . . . . . . . . 103 14 video input controller. . . . . . . . . . . . . . . . . . 104 14.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.1.1 input formats . . . . . . . . . . . . . . . . . . . . . . . . 104 14.1.2 image cropping . . . . . . . . . . . . . . . . . . . . . . 104 14.1.3 image adjustment . . . . . . . . . . . . . . . . . . . . 104 14.1.4 photometric lens distortion correction . . . . . 104 14.1.5 image front-end processing . . . . . . . . . . . . . 104 14.1.6 wide dynamic range (wdr) . . . . . . . . . . . 104 14.1.7 output modes . . . . . . . . . . . . . . . . . . . . . . . 104 14.1.8 output formats . . . . . . . . . . . . . . . . . . . . . . 104 14.1.9 horizontal blanking interv al . . . . . . . . . . . . . 105 14.2 memory map register . . . . . . . . . . . . . . . . . 105 14.2.1 vic_version (0x00000000) . . . . . . . . . . . 106 14.2.2 vic_ctrl (0x00000004) . . . . . . . . . . . . . . 106 14.2.3 vic_ctrl_device_n (0x00000008+n*4) . 107 14.2.4 vic_ctrl_ channel_n_m (0x00000010+(n*4+m)*4) . . . . . . . . . . . . . . 107 14.2.5 vic_stat_0 (0x00000030) . . . . . . . . . . . . . 109 14.2.6 vic_stat_1 (0x00000034) . . . . . . . . . . . . . . 111 14.2.7 vic_sync_delay_n (0x00000038+n*4). . . 114 14.2.8 vic_milli_second_n_m (0x00000040+n*0xe0+m*0x38). . . . . . . . . . . 114 14.2.9 vic_addr group1 (0x00000044+n*0xe0+m80x38~0x0000004c+n* 0xe0+m*0x38) . . . . . . . . . . . . . . . . . . . . . . . . 114 14.2.10 vic_addr group2 (0x00000050+n*0xe0+m*038~0x00000058 +n*0xe0+m*0x38) . . . . . . . . . . . . . . . . . . . . . 115 14.2.11 vic_in_size_n_m (0x0000005c+ n*0xe0+m*0x38) . . . . . . . . . . . . . . . . . . . . . . 115 14.2.12 vic_cap_h_n_m (0x00000060+n*0xe0+m*0x38). . . . . . . . . . . 115 14.2.13 vic_cap_v_n_m (0x00000064+ n*0xe0+m*0x38) . . . . . . . . . . . . . . . . . . . . . . 115 14.2.14 vic_stride_n_m (0x00000068+ n*0xe0+m*0x38) . . . . . . . . . . . . . . . . . . . . . . 116 14.2.15 vic_sbc_n_m (0x0000006c+ n*0xe0+m*0x38) 116 14.2.16 vic_ce_ctrl_n_m (0x0000070+n*0xe0+m*0x38). . . . . . . . . . . . 116 14.2.17 vic_ce_tbl_addr_n_m (0x00000074+n*0xe0+m*0x38) . . . . . . . . . . 116 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 255 of 263 continued >> nxp semiconductors asc8848_49_50_51 multimedia soc 14.2.18 vic_no_signal (0x00000200) . . . . . . . . . 117 14.2.19 vic_cmos_ctrl (0x00000204) . . . . . . . . 117 14.2.20 vic_rgb2ycbcr_coeff_0 (0x00000208) 118 14.2.21 vic_rgb2ycbcr_coeff_1 (0x0000020c) . . . 118 14.2.22 vic_rgb2ycbcr_coeff_2 (0x00000210) 118 14.2.23 vic_denoise_threshold (0x00000214) 118 14.2.24 vic_awb_ctrl (0x00000218) . . . . . . . . . . 119 14.2.25 vic_awb_ threshold (0x0000021c). . . 119 14.2.26 vic_ae_src_sel (0x00000220) . . . . . . . . 120 14.2.27 reserved (0x00000224~0x0000022c). . . . . 120 14.2.28 vic_awb_manual_gain (0x00000230). . 121 14.2.29 vic_colorcrt_coeff_r (0x00000234) 121 14.2.30 vic_colorcrt_coeff_g (0x00000238) 121 14.2.31 vic_colorcrt_coeff_b (0x0000023c) 121 14.2.32 vic_gamma_tbl_addr (0x00000240) . . 122 14.2.33 vic_af_ctrl0 (0x00000244) . . . . . . . . . . 122 14.2.34 vic_af_windo w_start_position (0x00000248) . . . . . . . . . . . . . . . . . . . . . . . . 122 14.2.35 vic_af_window_size (0x0000024c) . . . 122 14.2.36 vic_af_focus_value_high (0x00000250). . 123 14.2.37 vic_af_focus_value_low (0x00000254) . . 124 14.2.38 vic_ae_window0_start (0x0000025c) 124 14.2.39 vic_ae_window0_range (0x00000260) 124 14.2.40 vic_ae_window1_start (0x00000264) 124 14.2.41 vic_ae_window1_range (0x00000268) 124 14.2.42 vic_ae_window2_start (0x0000026c) 125 14.2.43 vic_ae_window2_range (0x00000270) 125 14.2.44 vic_ae_window3_start (0x00000274) 125 14.2.45 vic_ae_window3_range (0x00000278) 125 14.2.46 vic_ae_window4_start (0x0000027c) 126 14.2.47 vic_ae_window4_range (0x00000280) 126 14.2.48 vic_ae_window5_start (0x00000284) 126 14.2.49 vic_ae_window5_range (0x00000288) 126 14.2.50 vic_ae_window6_start (0x0000028c) 127 14.2.51 vic_ae_window6_range (0x00000290) 127 14.2.52 vic_ae_window7_start (0x00000294) 127 14.2.53 vic_ae_window7_range (0x00000298) 127 14.2.54 vic_ae_window8_start (0x0000029c) 128 14.2.55 vic_ae_window8_range (0x000002a0) 128 14.2.56 vic_ae_window0_luminance (0x000002a4) . . . . . . . . . . . . . . . . . . . . . . . . 128 14.2.57 vic_ae_window1_luminance (0x000002a8) . . . . . . . . . . . . . . . . . . . . . . . . 128 14.2.58 vic_ae_window2_luminance (0x000002ac) . . . . . . . . . . . . . . . . . . . . . . . 128 14.2.59 vic_ae_window3_luminance (0x000002b0) . . . . . . . . . . . . . . . . . . . . . . . . 128 14.2.60 vic_ycbcr_clip (0x0000 02b4) . . . . . . . . 129 14.2.61 vic_cmyg_ctrl0 (0x000002b8) . . . . . . . 129 14.2.62 vic_cmyg_ctrl1 (0x000002bc). . . . . . . 129 14.2.63 vic_ae_window4_luminance (0x000002c0) . . . . . . . . . . . . . . . . . . . . . . . 130 14.2.64 vic_ae_window5_luminance (0x000002c4) . . . . . . . . . . . . . . . . . . . . . . . 130 14.2.65 vic_ae_window6_luminance (0x000002c8) . . . . . . . . . . . . . . . . . . . . . . . 130 14.2.66 vic_ae_window7_luminance (0x000002cc) . . . . . . . . . . . . . . . . . . . . . . . 130 14.2.67 vic_tm_ctrl (0x000002d0). . . . . . . . . . . 130 14.2.68 vic_awb_exclude_hori_window (0x000002d4) . . . . . . . . . . . . . . . . . . . . . . . 131 14.2.69 vic_awb_exc lude_vert_window (0x000002d8) . . . . . . . . . . . . . . . . . . . . . . . 131 14.2.70 vic_awb_cb_sum (0x000002dc) . . . . . . 131 14.2.71 vic_awb_cr_sum (0x000002e0) . . . . . . 131 14.2.72 vic_ae_window8_luminance (0x000002e4) . . . . . . . . . . . . . . . . . . . . . . . 131 14.2.73 vic_ae_windows_msb_luminance (0x000002e8) . . . . . . . . . . . . . . . . . . . . . . . 132 14.2.74 vic_af_ctrl1 (0x000002e c). . . . . . . . . . 132 14.2.75 vic_photo_ldc_ctrl (0x000002f0) . . 132 14.2.76 vic_photo_ldc_tbl_addr (0x000002f4) . . 133 14.2.77 vic_awb_red_sum (0x000002f8) . . . . . 133 14.2.78 vic_awb_green_sum (0x000002fc) . . 133 14.2.79 vic_awb_blue_sum (0x00000300) . . . . 133 14.2.80 vic_cmos_hor_penalty_thr (0x00000304). . . . . . . . . . . . . . . . . . . . . . . . 133 14.2.81 vic_cmos_ver_penalty_thr (0x00000308) 133 14.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . 134 14.3.1 16-bit device . . . . . . . . . . . . . . . . . . . . . . . . 134 14.3.2 8-bit device . . . . . . . . . . . . . . . . . . . . . . . . . 134 14.4 input formats. . . . . . . . . . . . . . . . . . . . . . . . 134 14.4.1 16-bit device . . . . . . . . . . . . . . . . . . . . . . . . 134 14.4.1.1 bayer rgb and cmyg . . . . . . . . . . . . . . . . 134 14.4.1.2 ycbcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.4.2 8-bit device . . . . . . . . . . . . . . . . . . . . . . . . . 136 14.4.2.1 single-channel video stream . . . . . . . . . . . 136 14.4.2.2 2-channel video stream with single-edge clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 14.4.2.3 2-channel video stream with double-edge clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.4.2.4 4-channel video stream with single-edge clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.4.2.5 channel id format. . . . . . . . . . . . . . . . . . . . 138 14.4.3 interrupt generation. . . . . . . . . . . . . . . . . . . 139 15 general purpose i/o . . . . . . . . . . . . . . . . . . . 140 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 256 of 263 continued >> nxp semiconductors asc8848_49_50_51 multimedia soc 15.1 general description . . . . . . . . . . . . . . . . . . . 140 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 15.2.1 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 15.2.2 pull mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 15.2.3 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . 140 15.2.4 de-bounce mode . . . . . . . . . . . . . . . . . . . . . 140 15.3 memory map registers. . . . . . . . . . . . . . . . . 141 15.3.1 gpioc_version (0x00000000). . . . . . . . . 141 15.3.2 gpioc_data_out (0x00000004) . . . . . . . 141 15.3.3 gpioc_data_in (0x00000008) . . . . . . . . . 141 15.3.4 gpioc_pin_dir (0x0000000c) . . . . . . . . . 141 15.3.5 reserved (0x00000010) . . . . . . . . . . . . . . . . 141 15.3.6 gpioc_data_set (0x00000014). . . . . . . . 141 15.3.7 gpioc_data_clear (0x00000018) . . . . . 142 15.3.8 gpioc_pin_pull_enable (0x0000001c) 142 15.3.9 gpioc_pin_pull_type (0x00000020). . . 142 15.3.10 gpioc_intr_enable (0x00000024) . . . . 142 15.3.11 gpioc_intr_raw_state (0x00000028) . 142 15.3.12 gpoic_intr_mask_ state (0x0000002c) 142 15.3.13 gpioc_intr_mask (0x00000030) . . . . . . 143 15.3.14 gpioc_intr_clear (0x00000034). . . . . . 143 15.3.15 gpioc_intr_trigger_type (0x00000038). . 143 15.3.16 gpioc_intr_both (0x0000003c) . . . . . . 143 15.3.17 gpioc_intr_dir (0x00000040) . . . . . . . . 143 15.3.18 gpioc_debounce_enable (0x00000044) . . 143 15.3.19 gpioc_debounce_period (0x00000048). . . 144 16 usb 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 16.1 general description . . . . . . . . . . . . . . . . . . . 145 16.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 17 inter-ic sound slave controller . . . . . . . . . . 146 17.1 general description . . . . . . . . . . . . . . . . . . . 146 17.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 17.3 memory map register . . . . . . . . . . . . . . . . . 146 17.3.1 ier (0x00000000) . . . . . . . . . . . . . . . . . . . . 146 17.3.2 irer (0x00000004) . . . . . . . . . . . . . . . . . . . 146 17.3.3 iter (0x00000008) . . . . . . . . . . . . . . . . . . . 147 17.3.4 cer (0x0000000c) . . . . . . . . . . . . . . . . . . . 147 17.3.5 reserved (0x00000010) . . . . . . . . . . . . . . . . 147 17.3.6 rxffr (0x00000014) . . . . . . . . . . . . . . . . . 147 17.3.7 txffr (0x00000018) . . . . . . . . . . . . . . . . . . 147 17.3.8 lrbr (0x00000020) . . . . . . . . . . . . . . . . . . . 148 17.3.9 lthr (0x00000020) . . . . . . . . . . . . . . . . . . . 148 17.3.10 rrbr (0x00000024) . . . . . . . . . . . . . . . . . . 148 17.3.11 rthr (0x00000024). . . . . . . . . . . . . . . . . . . 149 17.3.12 rer (0x00000028) . . . . . . . . . . . . . . . . . . . . 149 17.3.13 ter (0x0000002c). . . . . . . . . . . . . . . . . . . . 149 17.3.14 rcr (0x00000030). . . . . . . . . . . . . . . . . . . . 150 17.3.15 tcr (0x00000034) . . . . . . . . . . . . . . . . . . . 150 17.3.16 isr (0x00000038) . . . . . . . . . . . . . . . . . . . . 151 17.3.17 imr (0x0000003c). . . . . . . . . . . . . . . . . . . . 151 17.3.18 ror (0x00000040) . . . . . . . . . . . . . . . . . . . 152 17.3.19 tor (0x00000044) . . . . . . . . . . . . . . . . . . . 152 17.3.20 rfcr (0x00000048) . . . . . . . . . . . . . . . . . . 152 17.3.21 tfcr (0x0000004c) . . . . . . . . . . . . . . . . . . 152 17.3.22 rff (0x00000050). . . . . . . . . . . . . . . . . . . . 153 17.3.23 tff (0x00000054) . . . . . . . . . . . . . . . . . . . . 153 17.3.24 rxdma (0x000001c0) . . . . . . . . . . . . . . . . 153 17.3.25 rrxdma (0x000001c4) . . . . . . . . . . . . . . . 153 17.3.26 txdma (0x000001c8). . . . . . . . . . . . . . . . . 154 17.3.27 rtxdma (0x000001cc) . . . . . . . . . . . . . . . 154 18 ethernet mac controller . . . . . . . . . . . . . . . 155 18.1 general description . . . . . . . . . . . . . . . . . . . 155 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 19 synchronous serial interface controller . . 156 19.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 19.2 memory map register . . . . . . . . . . . . . . . . . 156 19.2.1 ctrlr0 (0x00000000) . . . . . . . . . . . . . . . . 156 19.2.2 ctrlr1 (0x00000004) . . . . . . . . . . . . . . . . 157 19.2.3 ssienr (0x00000008) . . . . . . . . . . . . . . . . 158 19.2.4 mwcr (0x0000000c) . . . . . . . . . . . . . . . . . 158 19.2.5 ser (0x00000010) . . . . . . . . . . . . . . . . . . . 159 19.2.6 baudr (0x00000014) . . . . . . . . . . . . . . . . . 159 19.2.7 txftlr (0x00000018) . . . . . . . . . . . . . . . . 160 19.2.8 rxftlr (0x0000001c) . . . . . . . . . . . . . . . . 161 19.2.9 txflr (0x00000020) . . . . . . . . . . . . . . . . . 161 19.2.10 rxflr (0x00000024) . . . . . . . . . . . . . . . . . 161 19.2.11 sr(0x00000028) . . . . . . . . . . . . . . . . . . . . . 162 19.2.12 imr (0x0000002c). . . . . . . . . . . . . . . . . . . . 162 19.2.13 isr (0x00000030) . . . . . . . . . . . . . . . . . . . . 162 19.2.14 risr (0x00000034) . . . . . . . . . . . . . . . . . . . 162 19.2.15 txoicr (0x00000038) . . . . . . . . . . . . . . . . 163 19.2.16 rxoicr (0x0000003c) . . . . . . . . . . . . . . . . 163 19.2.17 rxuicr (0x00000040) . . . . . . . . . . . . . . . . 163 19.2.18 msticr (0x00000044) . . . . . . . . . . . . . . . . 163 19.2.19 icr (0x00000048) . . . . . . . . . . . . . . . . . . . . 164 19.2.20 dmacr (0x0000004c) . . . . . . . . . . . . . . . . 164 19.2.21 dmatdlr (0x00000050). . . . . . . . . . . . . . . 164 19.2.22 dmardlr (0x00000054) . . . . . . . . . . . . . . 165 19.2.23 reserved (0x00000058~0x0000005c) . . . . 165 19.2.24 dr (0x00000060 to 0x0000009c) . . . . . . . . 165 19.3 i/o timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 166 20 advanced general purpose output . . . . . . 167 20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 20.1.1 port control type . . . . . . . . . . . . . . . . . . . . . 167 20.1.2 pattern repeat. . . . . . . . . . . . . . . . . . . . . . . 167 20.1.3 non-stop pattern . . . . . . . . . . . . . . . . . . . . . 167 20.2 memory map register . . . . . . . . . . . . . . . . . 167 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 257 of 263 continued >> nxp semiconductors asc8848_49_50_51 multimedia soc 20.2.1 agpoc_version (0x00000000) . . . . . . . . 167 20.2.2 agpoc_ctrl(0x00000004) . . . . . . . . . . . . 167 20.2.3 agpoc_status(0x00000008). . . . . . . . . . 168 20.2.4 agpoc_intr_mask (0x0000000c) . . . . . 168 20.2.5 agpoc_dft_data_oe_n (0x00000010) . 168 20.2.6 agpoc_dft_data (0x00000014) . . . . . . . 168 20.2.7 agpoc_ctrl_port_sel (0x00000018) . 168 20.2.8 agpoc_bit_n_pattern _0 (0x0000001c + n*28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.2.9 agpoc_bit_n_pattern _1 (0x00000020 + n*28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.2.10 agpoc_bit_n_pattern_2 (0x00000024 + n*28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.2.11 agpoc_bit_n_ pattern _3 (0x00000028 + n*28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.2.12 agpoc_bit_n_period (0x0000002c +n*28) . . 169 20.2.13 agpoc_bit_n_length (0x00000030) . . . 169 20.2.14 agpoc_bit_n_intvrepeat (0x00000034 + n*28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 20.2.15 port control type . . . . . . . . . . . . . . . . . . . . . 170 20.3 programming . . . . . . . . . . . . . . . . . . . . . . . . 170 21 irda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 21.1 general description . . . . . . . . . . . . . . . . . . . 172 21.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 21.2.1 modulation type . . . . . . . . . . . . . . . . . . . . . . 172 21.2.2 de-bounce . . . . . . . . . . . . . . . . . . . . . . . . . . 172 21.3 memory map register . . . . . . . . . . . . . . . . . 172 21.3.1 irdac version (0x00000000) . . . . . . . . . 172 21.3.2 irdac_ctrl (0x00000004) . . . . . . . . . . . . 172 21.3.3 irdac_stat (0x00000008). . . . . . . . . . . . . 173 21.3.4 irdac_rbr_lo (0x0000000c) . . . . . . . . . 173 21.3.5 irdac_rbr_hi (0x00000010) . . . . . . . . . . 173 21.3.6 irdac_timing (0x00000014). . . . . . . . . . . 174 21.3.7 irdac_timing_ext(0x00000018). . . . . . . 174 21.3.8 irdac_interval_freq_div (0x0000001c) . . 174 21.4 programming . . . . . . . . . . . . . . . . . . . . . . . . 175 22 mobile storage host controller . . . . . . . . . . 177 22.1 general description . . . . . . . . . . . . . . . . . . . 177 22.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 22.3 memory map register . . . . . . . . . . . . . . . . . 177 22.3.1 ctrl (0x00000000) . . . . . . . . . . . . . . . . . . . 177 22.3.2 reserved (0x00000004) . . . . . . . . . . . . . . . . 178 22.3.3 clkdiv (0x00000008) . . . . . . . . . . . . . . . . . 179 22.3.4 reserved (0x0000000c) . . . . . . . . . . . . . . . 179 22.3.5 clkena (0x00000010) . . . . . . . . . . . . . . . . 179 22.3.6 tmout (0x00000014) . . . . . . . . . . . . . . . . . 179 22.3.7 ctype (0x00000018) . . . . . . . . . . . . . . . . . 180 22.3.8 blksiz (0x0000001c) . . . . . . . . . . . . . . . . . 180 22.3.9 bytcnt (0x00000020) . . . . . . . . . . . . . . . . 180 22.3.10 intmask (0x00000024) . . . . . . . . . . . . . . . 181 22.3.11 cmdarg (0x00000028) . . . . . . . . . . . . . . . 181 22.3.12 cmd (0x0000002c) . . . . . . . . . . . . . . . . . . . 182 22.3.13 resp0 (0x00000030) . . . . . . . . . . . . . . . . . 183 22.3.14 resp0 (0x00000030) . . . . . . . . . . . . . . . . . 184 22.3.15 resp1 (0x00000034) . . . . . . . . . . . . . . . . . 184 22.3.16 resp2 (0x00000038) . . . . . . . . . . . . . . . . . 184 22.3.17 resp3 (0x0000003c) . . . . . . . . . . . . . . . . . 184 22.3.18 mintsts (0x00000040) . . . . . . . . . . . . . . . 185 22.3.19 rintsts (0x00000044) . . . . . . . . . . . . . . . 186 22.3.20 status (0x00000048) . . . . . . . . . . . . . . . . 187 22.3.21 fifoth (0x0000004c) . . . . . . . . . . . . . . . . 188 22.3.22 cdetect (0x00000050). . . . . . . . . . . . . . . 188 22.3.23 wrtprt (0x00000054). . . . . . . . . . . . . . . . 188 22.3.24 reserved (0x00000058) . . . . . . . . . . . . . . . 189 22.3.25 tcbcnt (0x0000005c). . . . . . . . . . . . . . . . 189 22.3.26 tbbcnt (0x00000060) . . . . . . . . . . . . . . . . 189 22.3.27 debnce (0x00000064). . . . . . . . . . . . . . . . 189 22.3.28 usrid (0x00000068). . . . . . . . . . . . . . . . . . 189 22.3.29 verid (0x0000006c) . . . . . . . . . . . . . . . . . 189 22.3.30 reserved (0x00000070~0x0000007c) . . . . 189 22.3.31 bmod (0x00000080) . . . . . . . . . . . . . . . . . . 190 22.3.32 pldmnd (0x00000084). . . . . . . . . . . . . . . . 190 22.3.33 dbaddr (0x00000088). . . . . . . . . . . . . . . . 190 22.3.34 idsts (0x0000008c). . . . . . . . . . . . . . . . . . 191 22.3.35 idinten (0x00000090) . . . . . . . . . . . . . . . . 192 22.3.36 dscaddr (0x00000094) . . . . . . . . . . . . . . 193 22.3.37 bufaddr (0x00000098). . . . . . . . . . . . . . . 193 22.3.38 reserved (0x0000009c~0x000000fc) . . . . 193 22.4 auto stop . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 22.5 descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . 194 23 nand flash controller. . . . . . . . . . . . . . . . 198 23.1 general description . . . . . . . . . . . . . . . . . . . 198 23.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 23.3 memory map register . . . . . . . . . . . . . . . . . 198 23.3.1 flconf (0x00001300) . . . . . . . . . . . . . . . . 198 23.3.2 flctrl (0x00001304) . . . . . . . . . . . . . . . . 199 23.3.3 flcomm (0x00001308) . . . . . . . . . . . . . . . 200 23.3.4 fladdr_0_lo (0x0000130c) . . . . . . . . . . 200 23.3.5 fladdr_1_lo (0x00001310). . . . . . . . . . . 200 23.3.6 fldata (0x00001314). . . . . . . . . . . . . . . . . 200 23.3.7 reserved (0x00001318) . . . . . . . . . . . . . . . 200 23.3.8 flstate (0x0000131c) . . . . . . . . . . . . . . . 201 23.3.9 reserved (0x00001320~0x0000133c) . . . . 201 23.3.10 fleccstatus (0x00001340) . . . . . . . . . . 201 23.3.11 fladdr_0_hi (0x00001344) . . . . . . . . . . . 202 23.3.12 fladdr_1_hi (0x00001348) . . . . . . . . . . . 202 23.3.13 reserved (0x0000134c~0x0000137c) . . . . 202 23.3.14 fldma_addr(0x00001380) . . . . . . . . . . . 202 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 258 of 263 continued >> nxp semiconductors asc8848_49_50_51 multimedia soc 23.3.15 fldma_ctrl (0x00001384) . . . . . . . . . . . . 202 23.3.16 fldma_cntr (0x00001388) . . . . . . . . . . . 203 23.4 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 23.4.1 timing relationship . . . . . . . . . . . . . . . . . . . 204 23.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . 205 23.6 address mapping . . . . . . . . . . . . . . . . . . . . . 207 23.7 programming . . . . . . . . . . . . . . . . . . . . . . . . 207 23.7.1 nand flash memory transfer . . . . . . . . . . . 208 23.7.2 dma transfer . . . . . . . . . . . . . . . . . . . . . . . . 209 23.7.3 combined transfer . . . . . . . . . . . . . . . . . . . . 209 24 pci express dual mode controller. . . . . . . . 210 24.1 general description . . . . . . . . . . . . . . . . . . . 210 24.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 25 uart interfaces . . . . . . . . . . . . . . . . . . . . . . . 211 25.1 general description . . . . . . . . . . . . . . . . . . . 211 25.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 25.2.1 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 25.2.2 frame format . . . . . . . . . . . . . . . . . . . . . . . . 211 25.2.3 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . 211 25.2.4 modem control . . . . . . . . . . . . . . . . . . . . . . 211 25.2.5 data format . . . . . . . . . . . . . . . . . . . . . . . . . 211 25.3 memory map register . . . . . . . . . . . . . . . . . 212 25.3.1 uartc_version (0x00000000) . . . . . . . . 212 25.3.2 uartc_rbr (0x00000004). . . . . . . . . . . . . 212 25.3.3 uartc_thr (0x00000004). . . . . . . . . . . . . 212 25.3.4 uartc_ier (0x00000008) . . . . . . . . . . . . . 212 25.3.5 uartc_iir (0x0000000c) . . . . . . . . . . . . . . 213 25.3.6 uartc_fcr (0x0000000c) . . . . . . . . . . . . 214 25.3.7 uartc_lcr (0x00000010) . . . . . . . . . . . . . 214 25.3.8 uartc_mcr (0x00000014) . . . . . . . . . . . . 215 25.3.9 uartc_lsr (0x00000018) . . . . . . . . . . . . . 215 25.3.10 uartc_msr (0x0000001c) . . . . . . . . . . . . 216 25.3.11 uartc_spr (0x00000020). . . . . . . . . . . . . 217 25.3.12 uartc_dll (0x00000004) . . . . . . . . . . . . . 217 25.3.13 uartc_dlm (0x00000008). . . . . . . . . . . . . 217 26 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 26.1 general description . . . . . . . . . . . . . . . . . . . 218 26.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 26.2.1 key value . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 26.2.2 programmable reset length.. . . . . . . . . . . . 218 26.3 memory map register . . . . . . . . . . . . . . . . . 218 26.3.1 wdtc_version (0x00000000) . . . . . . . . . 218 26.3.2 wdtc_ctrl (0x00000004) . . . . . . . . . . . . 219 26.3.3 wdtc_stat (0x00000008) . . . . . . . . . . . . . 219 26.3.4 wdtc_count (0x0000000c) . . . . . . . . . . 219 26.3.5 wdtc_reload_value (0x00000010) . . . 219 26.3.6 wdtc_match_value (0x00000014) . . . . 220 26.3.7 wdtc_reload_ctrl (0x00000018) . . . . 220 26.3.8 wdtc_rst_len (0x0000001c) . . . . . . . . . 220 26.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 27 video output controller . . . . . . . . . . . . . . . . 222 27.1 general description . . . . . . . . . . . . . . . . . . . 222 27.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 27.2.1 input video data format . . . . . . . . . . . . . . . 222 27.2.2 output data format . . . . . . . . . . . . . . . . . . . 222 27.3 memory map register . . . . . . . . . . . . . . . . . 222 27.3.1 voc_version (0x00000000) . . . . . . . . . . 222 27.3.2 voc_ctrl (0x00000004). . . . . . . . . . . . . . 222 27.3.3 voc_stat (0x00000008) . . . . . . . . . . . . . . 224 27.3.4 voc_addr group (0x0000000c~0x00000020) 224 27.3.5 voc_in_size (0x00000024) . . . . . . . . . . . 224 27.3.6 voc_out_size (0x0000028) . . . . . . . . . . 224 27.3.7 voc_out_size_ctrl (0x0000002c) . . . 225 27.3.8 voc_hsync_ctrl (0x00000030) . . . . . . 225 27.3.9 voc_vsync_ctrl (0x00000034) . . . . . . 225 27.3.10 voc_sbc_ctrl (0x00000038) . . . . . . . . . 226 27.3.11 voc_ycbcr2rgb_coeff_0 (0x000003c). . . 226 27.3.12 voc_ycbcr2rgb_coeff_1 (0x00000040) . . 226 27.3.13 voc_ycbcr2rgb_coeff_2 (0x00000044) . . 227 27.4 output format . . . . . . . . . . . . . . . . . . . . . . . 227 28 ahb-to-apb bridge and dma controller . . 229 28.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 28.2 memory map register . . . . . . . . . . . . . . . . . 229 28.2.1 apbc_slave_n_basesize (0x00000000+n*4) 229 28.2.2 apbc_version (0x00000080) . . . . . . . . . 229 28.2.3 apbc_dma_priority (0x00000084) . . . . 230 28.2.4 reserved (0x00000088) . . . . . . . . . . . . . . . 230 28.2.5 apbc_dma_chn_moniter(0x0000008c) 230 28.2.6 apbc_dma_n_src_addr (0x00000090+n*16) 230 28.2.7 apbc_dma_n_des_addr (0x00000094+n*16) 230 28.2.8 apbc_dma_n_llp (0x00000098+n*16) . . 231 28.2.9 apbc_dma_n_ctrl (0x0000009c+n*16) . 231 28.3 apb dma operation . . . . . . . . . . . . . . . . . . 233 28.3.1 dma port . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 28.3.2 programming . . . . . . . . . . . . . . . . . . . . . . . . 234 29 limiting values . . . . . . . . . . . . . . . . . . . . . . . 235 30 recommended operating conditions . . . . . 237 31 characteristics . . . . . . . . . . . . . . . . . . . . . . . 239 31.1 dc/ac i/o characteristics . . . . . . . . . . . . . . 239 31.1.1 ddr-ii interface for asc8848/49/50 m1 version 239 31.1.2 ddr-ii interfac e for m2 version of asc8848/8849/8850 and ASC8851 . . . . . . 240 free datasheet http://
nxp semiconductors asc8848_49_50_51 multimedia soc ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 24 september 2011 document identifier: asc8848_49_50_51 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 31.1.2 ddr-ii interface for m2 version of asc8848/8849/8850 and ASC8851 . . . . . . . 240 31.1.3 ddr-iii for m2 version of asc8848/8849/8850 and ASC8851 . . . . . . . . . . . . . . . . . . . . . . . . 241 31.1.4 usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 31.1.5 general i/os . . . . . . . . . . . . . . . . . . . . . . . . . 242 31.1.6 gmii/rgmii . . . . . . . . . . . . . . . . . . . . . . . . . 244 31.1.7 osc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 31.1.8 pcie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 31.1.8.1 reference clock . . . . . . . . . . . . . . . . . . . . . . 245 31.1.8.2 tx/rx characteristics . . . . . . . . . . . . . . . . . . 245 31.2 solder reflow profile . . . . . . . . . . . . . . . . . . 246 32 package outline . . . . . . . . . . . . . . . . . . . . . . . 247 33 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 248 34 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 35 revision history . . . . . . . . . . . . . . . . . . . . . . . 249 36 legal information. . . . . . . . . . . . . . . . . . . . . . 250 36.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 250 36.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 36.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 250 36.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 251 37 contact information. . . . . . . . . . . . . . . . . . . . 251 38 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 260 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 261 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 262 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc free datasheet http://
asc8848_49_50_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. data sheet rev. 2.06 ? 24 september 2011 263 of 263 nxp semiconductors asc8848_49_50_51 multimedia soc free datasheet http://

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