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motorola semiconductor technical data order number: MPC93H51/d rev 2, 2/2004 ? motorola, inc. 2004 low voltage pll clock driver the MPC93H51 is a 3.3v compatible, pll based clock generator targeted for high performance clock di stribution systems. with output frequencies of up to 240 mhz and a maximum output skew of 150 ps the MPC93H51 is an ideal solution for the most demanding clock tree designs. the device offers 9 low ske w clock outputs, each is config- urable to support the clocking need s of the various high-performance microprocessors including the powerquicc ii integrated communica- tion microprocessor. the devices employs a fully differential pll de- sign to minimize cycle-to -cycle and long-term jitter. features ? 9 outputs lvcmos pll clock generator ? 25 - 240 mhz output frequency range ? fully integrated pll ? compatible to various microprocessors such as powerquicc ii ? supports networking, telecommunications and computer applications ? configurable outputs: divide-by- 2, 4 and 8 of vco frequency ? lvpecl and lvcmos compatible inputs ? external feedback enables zero-delay configurations ? output enable/disable and static test mode (pll enable/disable) ? low skew characteristics: ma ximum 150 ps output-to-output ? 32 lead lqfp package ? ambient temperature range 0c to +70c ? pin & function comp atible with the mpc951 functional description the MPC93H51 utilizes pll technology to frequency and phase lock its outputs ont o an input reference clock. normal operation of the MPC93H51 requires a connection of one of the device outputs to the ext_fb input to close the pll feedback path. the reference clock frequency and the output divider for the feedback path determine the vco frequency. both must be sele cted to match the vco frequency range. with available output dividers of divide-by-4 and divide-by-8 the internal vco of the MPC93H51 is running at either 4x or 8x of the re ference clock frequency. the frequency of the qa, qb, qc and qd outputs is either the one half, one fourth or one eighth of the selected vco frequency and can be configured for each output bank usin g the fsela, fselb, fselc an d fseld pins, respectively. the available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. the ref_sel pin selects the differential lvpecl (pclk and pclk ) or the lvcmos compatible reference input (t clk). the MPC93H51 also provides a static test mode when the pll enable pin (pll_en) is pulled to logic low state. in test mode, the selected input reference clock is routed directly to the out put dividers bypassing the pll. the test mode is intended for system diagnostics, test and debug purpose. this test mode is fully static and the mini mum clock frequency specificati on does not apply. the outputs can be disabled by deasserting the oe pin (logic high state). in pll mode, deasserting oe causes the pll to loose lock due to no feedback signal presence at ext_fb. asserting oe will enable the outputs and close the phase locked loop, also enabling the pll to recover to normal operation. the mp c93h51 is 3.3v compatible a nd requires no external loop filter components. all inputs except pclk and pclk accept lvcmos signals while the outputs provide lvcmos compatible levels wi th the capability to drive terminated 50 ? transmission lines. for series terminated transmission lines, each of the MPC93H51 outputs can drive one or two tr aces giving the devices an ef fective fanout of 1:18. the device is packaged in a 7x7 mm 2 32-lead lqfp package. application information the fully integrated pll of the MPC93H51 allows the low ske w outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. in zero-delay buffer mode, the pll minimizes phase offset between the outpu ts and the reference signal. MPC93H51 fa suffix lqfp package case 873a-03 low voltage 3.3 v pll clock generator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 2 low voltage pll clock driver motorola figure 1. MPC93H51 logic diagram figure 2. pinout: 32-lead lqfp package pinout (top view) d q pll (pulldown) ext_fb fsela qa ref_sel 0 1 (pullup) ref fb 200?480 mhz qb 0 1 0 1 0 1 fselb fselc (pulldown) (pulldown) (pullup) (pulldown) pll_en fseld d q qc1 0 1 d q qc0 qd2 0 1 d q qd1 qd0 qd4 qd3 (pulldown) (pulldown) (pulldown) (pulldown) tclk the MPC93H51 requires an external rc filter for the analog power supply pin vcca. pl ease see application section for details. pclk pclk oe 2 4 8 gnd qb vcco qa gnd tclk pll_en qd2 vcco qd3 gnd qd4 vcco qc0 vcco qc1 gnd qd0 vcco qd1 gnd vcca ext_fb fsela fselb fselc fseld gnd pclk 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 MPC93H51 ref_sel oe pclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 motorola low voltage pll clock driver 3 table 1. pin description pin i/o type function pclk, pclk input lvpecl differentia l clock reference low voltage positive ecl input tclk input lvcmos single ended reference clock signal or test clock ext_fb input lvcmos feedback signal input, connect to a qa, qb, qc, qd output ref_sel input lvcmos selects input reference clock fsela input lvcmos output a divider selection fselb input lvcmos output b divider selection fselc input lvcmos outputs c divider selection fseld input lvcmos outputs d divider selection oe input lvcmos output enable/disable qa output lvcmos bank a clock output qb output lvcmos bank b clock output qc0, qc1 output lvcmos bank c clock outputs qd0 - qd4 output lvcmos bank d clock outputs1.5 vcca supply vcc positive pow er supply for the pll vcc supply vcc positive power supply for i/o and core gnd supply ground negative power supply table 2. function table control default 0 1 ref_sel 0 selects pclk as reference clock selects tclk as reference clock pll_en 1 test mode with pll disabled. the input clock is directly routed to the output dividers pll enabled. the vco output is routed to the output dividers oe 0 outputs enabled outputs disabled, pll loop is open vco is forced to its minimum frequency fsela 0 qa = vco 2 qa = vco 4 fselb 0 qb = vco 4 qb = vco 8 fselc 0 qc = vco 4 qc = vco 8 fseld 0 qd = vco 4 qd = vco 8 table 3. absolute maximum ratings a a. absolute maximum continuos ratings are th ose maximum values beyond which damage to t he device may occur. exposure to these co nditions or conditions beyond those indicated may adver sely affect device reliabili ty. functional operation at absolute-maximum-rated condi tions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.9 v v in dc input voltage ?0.3 v cc +0.3 v v out dc output voltage ?0.3 v cc +0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature ?65 150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 4 low voltage pll clock driver motorola table 4. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc 2v mm esd (machine model) 200 v hbm esd (human body model) 2000 v lu latch-up 200 ma c pd power dissipation capacitance 10 pf per output c in input capacitance 4.0 pf inputs table 5. dc characteristics (v cc = 3.3 v 5%, t a = 0 to 70c) symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos v pp peak-to-peak input voltage pclk, pclk 250 mv lvpecl v cmr a common mode range pclk, pclk 1.0 v cc -0.6 v lvpecl v oh output high voltage 2.4 v i oh =-24 ma b v ol output low voltage 0.55 0.30 v v i ol = 24 ma i ol = 12 ma z out output impedance 7 ? 10 w i in input leakage current 150 av in = v cc or gnd i cca maximum pll supply current 6.0 12.0 ma v cca pin i ccq maximum quiescent supply current 10.0 14.0 ma all v cc pins a. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp (dc) specification. b. the MPC93H51 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the dev ice drives up to two 50 ? series terminated transmission lines. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 motorola low voltage pll clock driver 5 table 6. ac characteristics (v cc = 3.3 v 5%, t a = 0 to 70c) a a. ac characteristics apply for par allel output termination of 50 ? to v tt symbol characteristics min typ max unit condition f ref input frequency b 4 feedback 8 feedback static test mode b. the pll will be unstable with a divide by 2 feedback ratio. 50 25 0 120 60 300 mhz mhz mhz pll_en = 1 pll_en = 1 pll_en = 0 f vco vco frequency 200 480 mhz f max maximum output frequency b 2 output 4 output 8 output 100 50 25 240 120 60 mhz mhz mhz f refdc reference input duty cycle 25 75 % v pp peak-to-peak input voltage pclk, pclk 500 1000 mv lvpecl v cmr c c. v cmr (ac) is the crosspoint of the different ial input signal. normal ac operation is obtained when the cr osspoint is within the v cmr range and the input swing lies within the v pp (ac) specification. violation of v cmr or v pp impacts static phase offset t ( ? ) . common mode range pclk, pclk 1.2 v cc -0.9 v lvpecl tr, tf d d. the MPC93H51 will operate with input rise/fall times up to 3.0 ns, but the ac characteristics, specifically t ( ? ) , can only be guaranteed if tr/tf are within the specified range. tclk input rise/fall time 1.0 ns 0.8 to 2.0v t ( ? ) propagation delay (static phase offset) tclk to ext_fb pclk to ext_fb ?150 0 +150 +250 ps ps pll locked pll locked t sk(o) output-to-output skew 300 ps dc output duty cycle 100 ? 240 mhz 50 ? 120 mhz 25 ? 60 mhz 45 47.5 48.75 50 50 50 55 52.5 51.75 % % % t r , t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4v t plz, hz output disable time 7.0 ns t pzl, zh output enable time 6.0 ns bw pll closed loop bandwidth 2 feedback 4 feedback 8 feedback 9.0 ? 20.0 3.0 ? 9.5 1.2 ? 2.1 mhz mhz -3 db point of pll transfer characteristic t jit(cc) cycle-to-cycle jitter 4 feedback single output frequency configuration 40 ps rms value t jit(per) period jitter 4 feedback single output frequency configuration 25 ps rms value t jit( ? ) i/o phase jitter 30 ps rms value t lock maximum pll lock time 5 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 6 low voltage pll clock driver motorola applications information programming the MPC93H51 the MPC93H51 clock driver outputs can be configured into several divider modes, in addition the external feed- back of the device allows for flexibility in establishing var- ious input to output frequency relationships. the output divider of the four output groups allows the user to con- figure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. the use of even dividers ensure that the output duty cycle is always 50%. ?output frequency relation- ship for an example configurat ion? illustrate s the various output configurations, the ta ble describes the outputs us- ing the input clock frequency clk as a reference. the output division settings establish the output rela- tionship, in addition, it must be ensured that the vco will be stable given the frequency of the outputs desired. the feedback frequency should be used to situate the vco into a frequency range in which the pll will be stable. the design of the pll supports output frequencies from 25 mhz to 240 mhz while the vco frequency range is specified from 200 mhz to 480 mhz and should not be exceeded for stable operation. using the MPC93H51 in zero-delay applications nested clock trees are typical applications for the MPC93H51. for these applic ations the MPC93H51 of- fers a differential lvpecl clock input pair as a pll refer- ence. this allows for the use of differential lvpecl primary clock distribution devi ces such as the motorola mc100ep111 or mc10ep222, taking advantage of its superior low-skew performance. clock trees using lvpecl for clock distribution and the MPC93H51 as lvcmos pll fanout buffer wi th zero insertion delay will show significantly lower cloc k skew than clock distribu- tions developed from cmos fanout buffers. figure 1. the external feedback option of the MPC93H51 pll allows for its use as a zero delay buffer. the pll aligns the feedback clock output edge with the clock input refer- ence edge and virtually eliminates the propagation delay through the device. the remaining insertion de lay (skew error) of the MPC93H51 in zero-delay applications is measured be- tween the reference clock input and any output. this ef- fective delay consists of the static phase offset (spo or t ( ? ) ), i/o jitter (t jit( ? ) , phase or long-term jitter), feedback path delay and the output-to-output skew (t sk(o) relative to the feedback output. figure 2. table 7. output frequency relationship a for an example configuration a. output frequency relationship with respect to input reference frequency clk. qc1 is connected to ext_fb. inputs outputs fsela fselb fselc fseld qa qb qc qd 0 0 0 0 2 * clk clk clk clk 0 0 0 1 2 * clk clk clk clk 2 0 0 1 0 4 * clk 2 * clk clk 2* clk 0 0 1 1 4 * clk 2 * clk clk clk 0 1 0 0 2 * clk clk 2 clk clk 0 1 0 1 2 * clk clk 2 clk clk 2 0 1 1 0 4 * clk clk clk 2 * clk 0 1 1 1 4 * clk clk clk clk 1 0 0 0 clk clk clk clk 1 0 0 1 clk clk clk clk 2 1 0 1 0 2 * clk 2 * clk clk 2 * clk 1 0 1 1 2 * clk 2 * clk clk clk 1 1 0 0 clk clk 2 clk clk 1 1 0 1 clk clk 2 clk clk 2 1 1 1 0 2 * clk clk clk 2 * clk 1 1 1 1 2 * clk clk clk clk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 motorola low voltage pll clock driver 7 calculation of part-to-part skew the MPC93H51 zero delay buffer supports applica- tions where critical clock signal timing can be maintained across several devices. if the reference clock inputs (tclk or pclk) of two or more MPC93H51 are connect- ed together, the maximum overall timing uncertainty from the common tclk input to any output is: t sk(pp) = t ( ? ) + t sk(o) + t pd, line(fb) + t jit( ? ) ? cf this maximum timing uncerta inty consist of 4 compo- nents: static phase offset, output skew, feedback board trace delay and i/o (phase) jitter: due to the statistical nature of i/o jitter a rms value (1 ) is specified. i/o jitter numbers for other confidence factors (cf) can be derived from table 8. the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation a i/o jitter confidence factor of 99.7% ( 3 ) is assumed, resulting in a worst case timi ng uncertainty from input to any output of -251 ps to 351 ps relative to tclk (v cc =3.3v and f vco = 400 mhz): t sk(pp) = [?50ps...150ps] + [?150ps...150ps] + [(17ps @ ?3)...(17ps @ 3)] + t pd, line(fb) t sk(pp) = [?251ps...351ps] + t pd, line(fb) above equation uses the maximum i/o jitter number shown in the ac characteristic table for v cc =3.3v (17 ps rms). i/o jitter is frequency dependant with a maximum at the lowest vco freq uency (200 mhz for the MPC93H51). applications using a higher vco frequency exhibit less i/o jitter than th e ac characteristic limit. the i/o jitter characteristics in figure 4 can be used to derive a smaller i/o jitter number at the specific vco frequency, resulting in tighter timing li mits in zero-delay mode and for part-to-part skew t sk(pp) . qa qb qc0 qc1 qd0 qd1 qd2 qd3 qd4 MPC93H51 zero-delay configuration (feedback of qd4) MPC93H51 tclk fref = 100 mhz ref_sel pll_en fsela fselb fselc fseld ext_fb 2 x 100 mhz 2 x 100 mhz 4 x 100 mhz 100 mhz (feedback) 1 1 1 0 0 0 figure 3. MPC93H51 maximum device-to-device skew t pd,line(fb) t jit( ? ) + t sk(o) ?t ( ? ) +t ( ? ) t jit( ? ) + t sk(o) t sk(pp) max. skew tclk common qfb device 1 any q device 1 qfb device2 any q device 2 table 8. confidence facter cf cf probability of clock edge within the distribution 1 0.68268948 2 0.95449988 3 0.99730007 4 0.99993663 5 0.99999943 6 0.99999999 figure 4. maximu m i/o jitter (rms) versus frequency for v cc =3.3v max. i/o jitter ve rsus frequency 30 25 20 15 10 5 0 200 225 250 275 300 325 350 375 400 vco frequency [mhz] tjit( ) [ps] rms ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 8 low voltage pll clock driver motorola power supply filtering the MPC93H51 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is se en on the power supply pins. noise on the v cca (pll) power suppl y impacts the de- vice characteristics, for instance i/o jitter. the MPC93H51 provides separate power supplies for the output buffers (v cc ) and the phase-locked loop (v cca ) of the device.the purpose of this design technique is to iso- late the high switching noise digital outputs from the rela- tively sensitive internal analog phase-locked loop. in a digital system environment wher e it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simple but effective form of isolation is a power supply filter on the v cca pin for the MPC93H51. figure 5 illustrates a ty pical power supply filter scheme. the MPC93H51 freq uency and phase stability is most susceptible to noise with spectral content in the 100khz to 20mhz range. ther efore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop across the series filter resistor r f . from the data sheet the i cca current (the current sourced through the v cca pin) is typically 6 ma (12 ma maximum), assuming that a minimum of 3.0v must be maintained on the v cca pin. the resistor r f shown in figure 5 ?v cca power sup- ply filter? must have a resistance of 5?15 ? to meet the voltage drop criteria. as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance be- gins to look inductive and t hus increases with increasing frequency. the parallel capacitor combination shown en- sures that a low impedance path to ground exists for fre- quencies well above the bandwidth of the pll. although the MPC93H51 has several design features to minimize the susceptibilit y to power supply noise (isolated power and grounds and fully differen tial pll) there still may be applications in which overa ll performance is being de- graded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related prob- lems in most designs. driving transmission lines the MPC93H51 clock driver was designed to drive high speed signals in a terminated transmission line en- vironment. to provide the opt imum flexibility to the user the output drivers were designed to exhibit the lowest im- pedance possible. with an output impedance of less than 20 ? the drivers can drive either parallel or series termi- nated transmission lines. for more information on trans- mission lines the reader is referred to motorola application note an1091. in most high performance clock networks point-to-point distribution of signals is the meth- od of choice. in a point-to-point scheme either series ter- minated or parallel terminated transmission lines can be used. the parallel technique te rminates the si gnal at the end of the line with a 50 ? resistance to v cc 2. this technique draws a fairly high level of dc current and thus only a single termina ted line can be driven by each output of the MPC93H51 clock driver. for the series terminated case however there is no dc current draw, thus the outputs can drive mu ltiple series terminated lines. figure 6 ?single versus dual transmission lines? illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when tak- en to its extreme the fanout of the MPC93H51 clock driv- er is effectively doubled du e to its capability to drive multiple lines. the waveform plots in figure 7 ?single versus dual line termination waveforms? show the simulation results of an output driving a single line versus two lines. in both cases the drive capability of the MPC93H51 output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. note from the delay measurements in the simulations a delta of only 43ps exists between the figure 5. v cca power supply filter v cca v cc MPC93H51 0.01 f 22 f r f v cc 0.01 f figure 6. single versus dual transmission lines 10 ? in MPC93H51 output buffer r s = 36 ? z o = 50 ? outa 10 ? in MPC93H51 output buffer r s = 36 ? z o = 50 ? outb0 r s = 36 ? z o = 50 ? outb1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 motorola low voltage pll clock driver 9 two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC93H51. the output waveform in figure 7 ?single versus dual line termination waveforms? show s a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 ? series resistor plus the output impedance does not match the parallel combinatio n of the line impedances. the voltage wave launched do wn the two lines will equal: v l = v s ( z 0 (r s +r 0 +z 0 )) z 0 = 50w || 50 ? r s = 36w || 36 ? r 0 = 14 ? v l = 3.0 ( 25 3 (18+17+25) = 1.31v at the load end the voltag e will double, due to the near unity reflection coefficient, to 2.6v. it will then increment towards the quiescent 3.0v in steps separated by one round trip delay (in this case 4.0ns). since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multi- ple lines the situation in fi gure 8 ?optimized dual line termination? should be used. in this case the series ter- minating resistors are reduced such that when the paral- lel combination is added to the output buffer impedance the line impedance is perfectly matched. figure 9. tclk MPC93H51 ac test reference for v cc = 3.3v figure 10. pclk MPC93H51 ac test reference figure 7. single versus dual waveforms voltage (v) outb t d = 3.9386 outa t d = 3.8956 in 2 4 6 8 10 12 14 time (ns) 3.0 2.5 2.0 1.5 1.0 0.5 0 z o = 50 ? z o = 50 ? figure 8. optimized dual line termination 10 ? MPC93H51 output buffer r s = 22 ? r s = 22 ? 14 ? + 22 ? || 22 ? = 50 ? || 50 ? 25 ? = 25 ? pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? MPC93H51 dut v tt v tt differential pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? MPC93H51 dut v tt v tt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 10 low voltage pll clock driver motorola figure 11. propagation delay (t pd , static phase offset) test reference figure 12. propagation delay (t pd ) test reference figure 13. output duty cycle (dc) figure 14. output-to-output skew t sk(o) figure 15. cycle-to-cycle jitter figure 16. period jitter figure 17. i/o jitter figure 18. transition time test reference v cc v cc 2 gnd t ( ? ) pclk ext_fb pclk v cmr v cmr t ( ? ) v cc v cc 2 gnd v cc v cc 2 gnd tclk ext_fb the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc v cc 2 gnd t p t 0 dc = t p /t 0 x 100% the pin-to-pin skew is defined as the wo rst case difference in propagation delay between any similar delay pa th within a single device v cc v cc 2 gnd v cc v cc 2 gnd t sk(o) the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t jit(cc) = | t n -t n+1 | t n+1 the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles t jit(p) = | t n -1 / f 0 | t 0 t jit( ? ) = | t 0 -t 1 mean | tclk ext_fb the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles (pclk) t f t r v cc =3.3v 2.4 0.55 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC93H51 motorola low voltage pll clock driver 11 outline dimensions case 873a-03 issue b date 03/10/00 12 ref dim min max millimeters a a1 7.00 bsc a2 0.80 bsc b 9.00 bsc b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 e e e1 l l1 1.00 ref r1 0.08 0.20 r2 s 1 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.08 --- 0? 7? 9.00 bsc 7.00 bsc 0.50 0.70 q q 0.20 ref d1 d/2 e e1 1 8 9 17 25 32 d1/2 e1/2 e/2 4x d 7 a d b a-b 0.20 h d 4x a-b 0.20 c d 6 6 4 4 detail g pin 1 index detail ad r r2 ? (s) l (l1) 0.25 gauge plane a2 a a1 ( 1?) 8x r r1 e seating plane detail ad 0.1 c c 32x 28x h detail g f f e/2 a, b, d 3 section f-f base c1 c b b1 metal a-b m 0.20 d c 5 8 plating notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08-mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion: 0.07-mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25-mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1-mm and 0.25-mm from the lead tip. fa suffix lqfp package case 873a-02 issue b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to desi gn or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further notic e to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purp ose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or spec ifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, s ubsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 how to reach us: usa/europe/locations not listed: japan: motorola japan ltd.; sps, technical information center motorola literature distribution 3-20-1 mi nami-azabu. minato-ku, tokyo 106-8573, japan p.o. box 5405, denver, colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors MPC93H51/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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