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r19ds0069ej010 3 rev. 1 .0 3 page 1 of 3 7 j ul 17 , 2014 datasheet tps - 1 single chip interface solution for profinet io devices description the tps - 1 is a single - chip profinet interface component integrating a cpu, a 2 - port switch supporting latest profinet specifications, the ethernet phys and peripheral modules to interface to the application layer of any application building a profinet io d evice . t he internal structure is designed to fulfill the requirements of the irt protocol. the integrated components realize the complete interface functionality. tps - 1 rounds off the basic technology range of profinet s pecifically for compact devices, and complie s with profin et specification 2.3. detailed functions are described in the following user s manual. be sure to read this manual when you design your systems. tps - 1 user s manual : hardware ( r19uh0081ed ) features ? applications ? industrial drives ? compact and mo dular remote i/os ? product features ? integrated profinet io cpu ? compliant with conformance class c ? 2 ethernet ports, 100 mb ps, full duplex ? 2 integrated phys with an auto negotiation, auto crossover ? integrated irt switch, 8 priority levels ? support rj45 or fib er optic interfaces ? fiber optic diagnosis via i 2 c interface per port ? irt b ridge - d elay < 3 s ? hardware support for profinet protocols including ptcp and lldp ? versatile host interface for serial or parallel connection of external cpus or local inputs/outputs ? small package(15 x 15 mm),1mm ball pitch ? application interface the tps - 1 provides 48 gene ral purpose i/o(gpio) pins that you can individually configure according to your specific application requirements. ? 48 gpio for digital i/os ? 8 - or 16 - bit parallel host interface ? serial host interface (spi slave ) ? 5gpio for internal signals (e.g. leds) ? seri al flash interface the tps - 1 interfaces to an application cpu via the internal shared memory either through the fast spi slave interface or through the 8 - or 16 - bit parallel port. ordering information part no. application package mc - 10105f1 - 821 - fna - m1 - a tps - 1 profinet io device fpbga 196 pins 15 x 15 mm the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every count ry. please check with our sales representative for availability and additional information. r19ds0069ej010 3 rev. 1 .0 3 j ul 17 , 2014
tps - 1 internal block diagram r19ds0069ej010 3 rev. 1 . 0 3 page 2 of 3 7 j ul 17 , 2014 internal block diagram the block diagram shows the internal structure and main components of the tps - 1. the additional serial boot flash component , the oscillator and the physical adaptation for the e thernet interfaces are not listed. s h a r e d m e m o r y i / o i n t e r f a c e p h y 2 p h y 1 s p i s l a v e p a r a l l e l i n t e r f a c e 8 / 1 6 b i t h o s t i n t e r f a c e m u x p r o f i n e t i o c p u b o o t - r o m a r m c o r e r a m p r o f i n e t i o c o r e t i m e s y n c i r t s w i t c h p r o t o c o l h a n d l i n g l a n s i g n a l s ( i 2 c - b u s , l i n k a n d a c t i v i t y ) , t e s t s y n c c l o c k s i g n a l s t 1 t o t 6 c l o c k u n i t 2 5 m h z m d i m d i l i n k 1 , a c t 1 , l i n k 2 , a c t 2 t e s t s y n c j t a g / d e b u g s e r i a l f l a s h ( s p i s l a v e ) h o s t i n t e r f a c e / p a r a l l e l - s e r i a l 4 8 g p i o s t a t u s i n f o l e d s c o n t r o l s i g n a l s p o w e r s u p p l y s w i t c h i n g r e g u l a t o r 1 . 0 v 3 . 3 v 1 . 5 v
tps - 1 pin identification r19ds0069ej010 3 rev. 1 . 0 3 page 3 of 3 7 j ul 17 , 2014 pin identification spi master for boot flash rom cs_flash_out : f w flash: chip select spi3_sclk_out : f w flash: clock spi3_srxd_in : f w flash: receive data C miso spi 3 _stxd_out : f w flash: send data C mosi synchronisation signals test_s ync : clock signal for certification t (6: 1 ) : clock signals (6:1) (isochronous mode, irt) led signals device status profinet io led_bf_out : control led ?bus failure led_sf_out : control led ?system fail led_ready_out : control led ?device ready led_mt_ out : control led ?maintenance phy port 1 and 2 i2c_ (2: 1 ) _d_inout : fo i 2 c - bus data sclk_ (2: 1 ) _inout : fo i 2 c - bus clock link_phy (2: 1 ) : e thernet link indication (up o r down) act_phy (2: 1 ) : activity ethernet p (2: 1 ) _tx_p : ethernet t ransmit d ata (pos itive) p (2: 1 ) _tx_n : ethernet t ransmit d ata (negative) p (2: 1 ) _rx_p : ethernet receive data (positive) p (2: 1 ) _rx_n : ethernet receive data (negative) p (2 : 1 ) _sd_p : fo signal detect (positive) p (2 : 1 ) _sd_n : fo signal detect (negative) p (2 : 1 ) _rd_p : fo rece ive data (positive) p (2 : 1 ) _rd_n : fo receive data (negative) p (2 : 1 ) _td_out_p : fo transmit data (negative) p (2 : 1 ) _td_out_n : fo transmit data (positive) p (2 : 1 ) _fx_en_out : fo transmitter enable (active high) oscillato r xclk1 : connection external oscil lator (1) in , 25 mhz xclk2 : c onnection external oscillator ( 2 ) out , 25 mhz jtag C interface tm (1: 0 ) : test input (1: 0 ) trst n : test reset tms : test mode select tdo : test data output tck : test clock tdi : test data input reset / test resetn : tps - 1 reset (global reset) atp : test pin f or production test (n.c.) extres : external reference resistor tmc (2: 1 ) : test mode control (2: 1 ) ( production test ) test_ (2: 1 ) _in : test pin (2: 1 ) for hw test of tps - 1 testdout (7: 5 ) : test data output (7:5) (high spee d signals for phy) host interface wd_in : watchdog input (from the host ) wd_out : watchdog output (to the host ) int_out : interrupt output (to the host ) boot interface (serial) uart 6 _ t x : boot uart transmit data uart 6 _ r x : boot uart receive data boot _ 1 : forced boot
tps - 1 pin identification r19ds0069ej010 3 rev. 1 . 0 3 page 4 of 3 7 j ul 17 , 2014 test signals for switching regulator test (3: 1 ) : test pin switching regulator ( in combination with ano ther test pins) phy supply voltages vdd33esd : analog test supply, 3.3 v vddq_pecl_b (2: 1 ) : pecl bu ffer power supply 3.3 v (port (2: 1 ) ) p (2: 1 ) vddarxtx : analog rx/tx power supply 1.5 v C port (2: 1 ) vddacb : analog central power supply 3.3 v vssapllcb : analog central gnd vddapll : analog central power supply 1.5 v pins for core pll power supply pll_agnd : pll analog gnd (core pll) pll_avdd : pll analog 1. 0 v (core pll) pins for switching regulator bvdd : supply voltage for the switching regulator (3.3 v supply for the switching transistor) bgnd : gnd for switching regulator (please place bypass capacitor between analog power supply and gnd). avdd _ reg : analog vdd for regulator ( 3.3 v supply),s moothed voltage to feed the internal por. agnd_reg : analog gnd switching regulator lx : 1.5 v output of the internal switching regulator fb : feedback (regulator) configurable gpios gp io_ (47: 0 ) : gpio pins alternate use of the gpios lbu_wr_en_in : write enable lbu_read_en_in : read enable lbu_cs_in : chip select lbu_be_ (2: 1 ) _in : byte selection ( 1: low ,2:high ) lbu_ready_out : ready signal tps - 1 lbu_data (15: 0 ) : data bit s lbu_a (13: 0 ) _in : address bit s lbu_seg (1: 0 ) _in : segment select (2: 1 ) host_reset_in : reset host spi interface host_sfrn_in : start new spi transfer host_srxd_in : spi receive data host_sclk_in : spi clock host_stxd_out : spi transmit data host_shdr_out : header recogn ized local_sclk_out : spi clock local_sfrm_out : s pi chip select local_srxd_in : spi receive data local_stxd_out : spi transmit data
tps - 1 pin configuration r19ds0069ej010 3 rev. 1 . 0 3 page 5 of 3 7 j ul 17 , 2014 pin configuration 196 - pin plastic bga(15x15)
tps - 1 pin configuration r19ds0069ej010 3 rev. 1 . 0 3 page 6 of 3 7 j ul 17 , 2014 pin designation pin designation pin designation pin designation a1 g nd d8 testdout5 h1 lx l8 testdout7 a2 vdd15 d9 testdout6 h2 vdd33 l9 pll_agnd a3 gpio_7 d10 act_phy1 h3 test1 l10 pll_avdd a4 gpio_4 d11 t6 h4 gpio_26 l11 sclk_2_inout a5 p1_fx_en_out d12 agnd h5 gpio_25 l12 agnd a6 p1_td_out_n d13 agnd h6 gnd l13 agn d a7 vdd15 d14 p1vddarxtx h7 gnd l14 p2vddarxtx a8 p1_sd_n e1 test3 h8 gnd m1 gpio_36 a9 p1_rd_n e2 gpio_16 h9 gnd m2 gpio_35 a10 act_phy2 e3 gpio_17 h10 gnd m3 gpio_37 a11 wd_in e4 gpio_18 h11 t2 m4 gpio_42 a12 resetn e5 gpio_19 h12 atp m5 gpio_45 a13 vdd15 e6 vdd10 h13 extres m6 gpio_46 a14 gnd e7 vdd10 h14 vddacb m7 gpio_47 b1 vdd33 e8 vdd10 j1 bvdd m8 vddq_pecl_b2 b2 gpio_9 e9 vdd10 j2 gnd m9 vdd15 b3 gpio_8 e10 tmc1 j3 gpio_28 m10 gnd b4 gpio_5 e11 t5 j4 gpio_27 m11 i2c_2_d_inout b5 gpio_1 e12 vdd33esd j5 tck m12 cs_flash_out b6 p1_td_out_p e13 p1_rx_p j6 gnd m13 spi3_srxd_in b7 gnd e14 p1_rx_n j7 gnd m14 spi3_stxd_out b8 p1_sd_p f1 fb j8 gnd n1 vdd33 b9 p1_rd_p f2 avdd_reg j9 gnd n2 gpio_40 b10 led_mt_out f3 gpio_22 j10 tm1 n3 gpio_39 b11 led_sf_out f4 gpio_21 j11 t1 n4 gpio_41 b12 wd_out f5 gpio_2 0 j12 gnd n5 gpio_44 b13 led_bf_out f6 vdd33 j13 p2_tx_p n6 p2_td_out_p b14 vdd33 f7 gnd j14 p2_tx_n n7 gnd c1 gpio_12 f8 gnd k1 vdd15 n8 p2_sd_p c2 gpio_13 f9 gnd k2 gpio_31 n9 p2_rd_p c3 gpio_6 f10 vdd33 k3 gpio_29 n10 gnd c4 gpio_3 f11 t4 k4 gpio_30 n11 xclk1 c5 gpio_2 f12 vdd15 k5 trstn n12 test_sync c6 sclk_1_inout f13 p1_tx_p k6 vdd10 n13 spi3_sclk_out c7 vdd33 f14 p1_tx_n k7 vdd10 n14 vdd33 c8 vddq_pecl_b1 g1 bgnd k8 vdd10 p 1 gnd c9 i2c_1_d_inout g2 agnd_reg k9 vdd10 p2 vdd15 c10 led_ready_out g3 test2 k10 tmc2 p3 gpio_38 c11 link_phy2 g4 gpio_24 k11 int_out p4 gpio_43 c12 link_phy1 g5 gpio_23 k12 vdd15 p5 p2_fx_en_out c13 uart6_rx g6 gnd k13 p2_rx_p p6 p2_td_out_n c14 uart6_tx g7 gnd k14 p2_rx_n p7 vdd33 d1 gpio_15 g8 gnd l1 gpio_34 p8 p2_sd_n d2 gpio_14 g9 gnd l2 gpio_32 p9 p2_rd_n d3 gpio_10 g10 gnd l3 gpio_33 p10 vdd33 d4 gpio_11 g11 t3 l4 tm0 p11 xclk2 d5 gpio_0 g12 gnd l5 tdi p12 boot_1 d6 test_1_in g13 vssap llcb l6 tms p13 vdd15 d7 test_2_in g14 vddapll l7 tdo p14 gnd
tps - 1 table of content s r19ds0069ej010 3 rev. 1 .0 3 page 7 of 3 7 j ul 17 , 2014 table of contents 1. pin functions ................................ ................................ ................................ .................... 10 1.1. list of pin functions ................................ ................................ ................................ ......... 10 1.1.1. host interface C parallel interface ................................ ................................ ........ 10 1.1.2. host interface C spi slave interface ................................ ................................ ...... 10 1.1.3. profinet io switch ................................ ................................ ......................... 11 1.1.4. integrated peripherals ................................ ................................ ........................... 12 1.2. pin characteristics ................................ ................................ ................................ ............ 16 2. electrical specifications ................................ ................................ ................................ .... 20 2.1. absolute maximum ratings ................................ ................................ ............................. 20 2.2. oper ating conditions ................................ ................................ ................................ ........ 21 2.3. thermal characteristics ................................ ................................ ................................ .... 22 2.4. ac characteristics ................................ ................................ ................................ ............ 23 2.4.1. clock timing ................................ ................................ ................................ ....... 23 2.4.2. i/o timing specification ................................ ................................ ....................... 24 2.4.2.1. jtag interface timing ................................ ................................ ......................... 25 2.4.2.2. parallel host interface timing diagrams ................................ ............................... 26 2.4.2.2.1.host read from tps - 1 with separate read/write line ................................ .......... 26 2.4.2.2.2.host write to tps - 1 with separate read/write line ................................ .............. 27 2.4.2.2.3. host read from tps - 1 with common read/write line ................................ ......... 28 2.4.2.2.4.host write to tps - 1 with common read/write line ................................ ............. 29 2.4.2.3. spi timing diagrams ................................ ................................ ............................ 30 2.4.3. i2c - bus timing definition ................................ ................................ ................... 31 2.4.3.1 . phy dc specifications(100 base - tx) ................................ ............................. 32 2.4.3.2 . phy ac specifications (100base - tx) ................................ ............................. 33 2.4.4. power - up sequence ................................ ................................ .............................. 34 2.4.5. reset timing ................................ ................................ ................................ ......... 35 3. package drawing ................................ ................................ ................................ .............. 36 4. recommended soldering conditions ................................ ................................ ................ 37
tps - 1 list of figures r19ds0069ej010 3 rev. 1 .0 3 page 8 of 3 7 j ul 17 , 2014 list of figures figure 2 - 1: clock waveforms ................................ ................................ ................................ ... 23 figure 2 - 2: input setup and hold waveforms ................................ ................................ ............ 24 figure 2 - 3: output delay waveforms ................................ ................................ ........................ 24 figure 2 - 4: host read with separate read/write line ................................ ................................ .. 26 figure 2 - 5: ho st write with separate read/write line ................................ ................................ . 27 figure 2 - 6: host read with common read/write line ................................ ................................ . 28 figure 2 - 7: host write with commo n read/write line ................................ ................................ 29 figure 2 - 8: spi slave timing ................................ ................................ ................................ .... 30 figure 2 - 9 : i2c - bus timing definition ................................ ................................ ...................... 31 figure 2 - 10 : phy dc specification ................................ ................................ ........................... 32 figure 2 - 1 1 : phy ac specification ................................ ................................ ........................... 33 figure 2 - 1 2 : power - up sequence timing diagram ................................ ................................ .... 34 figure 2 - 1 3 : reset timing diagram ................................ ................................ ........................... 35 figure 3 - 1: 196 - ball fpb ga package drawing ................................ ................................ ........ 36
tps - 1 list of tables r19ds0069ej010 3 rev. 1 .0 3 page 9 of 3 7 j ul 17 , 2014 list of tables table 1 - 1: parallel host interface ................................ ................................ ............................. 10 table 1 - 2: spi host interface ................................ ................................ ................................ ... 10 table1 - 3: status signals of the ethernet interface (port 1/port2) ................................ .... 11 table 1 - 4: signal lines 100base - tx interface (port 1/port2) ................................ .................. 11 table 1 - 5: signal lines 100base - fx interface (port 1/port2) ................................ .................. 11 table1 - 6: additional tps - 1 pins ................................ ................................ ............................ 11 table 1 - 7: boot flash spi master interface ................................ ................................ ............ 12 table 1 - 8: general purpose i/o pin functions ................................ ................................ ......... 13 table 1 - 9: status leds profinet io ................................ ................................ ................... 14 table 1 - 10: i2c interface lines ................................ ................................ ................................ .. 14 table 1 - 11: boot uart li nes ................................ ................................ ................................ .... 14 table 1 - 12: watchdog signals ................................ ................................ ................................ ... 15 table 1 - 13: jtag interface pin definition ................................ ................................ ................. 15 table 1 - 14: supply voltage circuitry ................................ ................................ ....................... 15 table 1 - 15: signal characteristics ................................ ................................ .............................. 16 table 2 - 1: absolute maximum ra tings ................................ ................................ ................... 20 table 2 - 2: recommended operating conditions (supply voltages) ................................ ........ 21 table 2 - 3: recommended operating conditions (input / o utput level) ................................ ... 21 table 2 - 4: tps - 1 power consumption overview ................................ ................................ ..... 21 table 2 - 5: thermal characteristics of the package ................................ ................................ . 22 table 2 - 6: clock ac characteristics ................................ ................................ ....................... 23 table 2 - 7: timing jtag interface ................................ ................................ .......................... 25 t able 2 - 8: host read with separate read/write line ................................ ................................ .. 26 table 2 - 9: host write with separate read/write line ................................ ................................ . 27 table 2 - 10: host rea d with common read/write line ................................ ................................ . 28 table 2 - 11: host write with common read/write line ................................ ................................ 29 table 2 - 12: spi slave timing ................................ ................................ ................................ ... 30 table 2 - 1 3 : characteristics of the scl and sda lines ................................ ............................. 31 table 2 - 1 4 : phy dc specification ................................ ................................ ........................... 32 table 2 - 1 5 : phy ac timing ................................ ................................ ................................ .... 33 table 2 - 1 6 : signals for power - up ................................ ................................ ............................. 34 table 2 - 1 7 : signals for reset timing ................................ ................................ ........................ 35 table 4 - 1: recommended soldering conditions ................................ ................................ ....... 37
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 10 of 3 7 j ul 17 , 2014 1. pin functions 1.1 . list of pin functions 1.1.1 . host interface C parallel interface table 1 - 1 : pa rallel h ost i nterface pin name i/o function remarks alternate function lbu_wr_en_in i write control active low (intel mode) gpio_0 0:write; 1:read (motorola mode) lbu_read_en_in i read control active low (intel mode) gpio_1 no function (motorol a mode) lbu_cs_in i chip select gpio_2 lbu_be_1_in i byte select 1 gpio_3 lbu_be_2_in i byte select 2 gpio_4 lbu_ready_out o ready signal p olarity configur able gpio_5 lbu_data (15: 0 ) i/o data line 0 C 1 5 gpio_(21:6) lbu_a (13: 0 ) _in i address lines 0 - 1 3 gpio_(35:22) lbu_seg 0 _in i low bit of the segment select p age selection gpio_36 lbu_seg 1 _in i high bit of the segment select p age selection gpio_37 1.1.2. host interface C spi slave interface table 1 - 2 : spi host interface pin name i/o functio n remarks alternate function host_reset_in i serial reset the spi slave interface can be reset by using this signal. (signal is active high) gpio_38 host_sfrn_in i serial frame the start of a new spi transfer is signaled. gpio_39 host_srxd_in i serial data input mosi (master out slave in) gpio_40 host_sclk_in i serial clock input serial clock driven by the spi master gpio_41 host_s t xd_out o serial data output miso (master in slave out) gpio_42 host_shdr_out o serial header information header inf or mation avai lable gpio_43
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 11 of 3 7 j ul 17 , 2014 1.1.3. profinet io switch table 1 - 3 : status signals of the ethernet interface (port 1 /port2 ) pin name i/o function remarks l ink _phy (2: 1 ) o link ethernet a ctive high act_phy (2: 1 ) o activity ethernet a ctive high table 1 - 4 : signal lines 100base - tx interface (port 1 /port2 ) pin name i/o function remarks p ( 2:1 ) _tx_p o transmit data+ e.g. rj45 p (2: 1 ) _tx_n o transmit data - e.g. rj45 p (2: 1 ) _rx_p i receive data+ e.g. rj45 p (2: 1 ) _rx_n i receive data - e.g. rj45 table 1 - 5 : signal lines 100bas e - fx interface (port 1 /port2 ) pin name i/o function remarks i 2 c_ (2: 1 ) _d_inout i/o i 2 c data line e.g. sc - rj sclk_ (2: 1 ) _inout o i 2 c clock line e.g. sc - rj p (2: 1 ) _sd_p i signal detect ( d ifferen tial, + ) e.g. sc - rj p (2: 1 ) _sd_n i signal detect ( d ifferen tial, - ) e.g. sc - rj p (2: 1 ) _rd_n i receive signal ( d ifferen tial, - ) e.g. sc - rj p (2: 1 ) _rd_p i receive signal ( d ifferen tial, +) e.g. sc - rj p (2: 1 ) _fx_en_out o transmitter enable (transceiver output) e.g. sc - rj p (2: 1 ) _td_out_p o transmit signal ( d iff eren tial, +) e.g. sc - rj p (2: 1 ) _td_out_n o transmit signal ( d ifferen tial, - ) e.g. sc - rj table 1 - 6 : additional tps - 1 pins pin name i/o function remarks atp ai/o (analog i/o) analog test: this signal is used for the manufacturing process. pin is left ope n . extres ai/o (analog i/o) reference resistor: connect via a resistor 12.4 k? / 1% to gnd. this external resistor should be place d as close as possible to the chip. it must be terminated to analog gnd.
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 12 of 3 7 j ul 17 , 2014 1.1.4. integrated peripherals table 1 - 7 : boot flash spi master interface pin name i/o function cs_flash_out o spi - master - interface firmware flash: chip select ( tps - 1) C active low spi3_sclk_out o spi - master - interface firmware flash: clock (tps - 1) spi3_srxd_in i spi - master - interface firmware flash: receive data (tps - 1) C miso spi 3 _stxd_out o spi - master - interface firmware flash: send data (tps - 1) C mosi
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 13 of 3 7 j ul 17 , 2014 table 1 - 8 : general purpose i/o pin functions pin name i/o function alternate function gpio_0 i/o general purpose digital i/o signal / write ena ble lbu_wr_en_in gpio_1 i/o general purpose digital i/o signal / read enable lbu_read_en_in gpio_2 i/o general purpose digital i/o signal / chip select lbu_cs_in gpio_3 i/o general purpose digital i/o signal / byte selection (low) lbu_be_1_in gpio_4 i/ o general purpose digital i/o signal / byte selection (high) lbu_be_2_in gpio_5 i/o general purpose digital i/o signal / ready signal tps - 1 note3 lbu_ready_out gpio_6 i/o general purpose digital i/o signal / data bit lbu_data 0 gpio_7 i/o general purpose digital i/o signal / data bit lbu_data 1 gpio_8 i/o general purpose digital i/o signal / data bit lbu_data 2 gpio_9 i/o general purpose digital i/o signal / data bit lbu_data 3 gpio_10 i/o general purpose digital i/o signal / data bit lbu_data 4 gpio_11 i/ o general purpose digital i/o signal / data bit lbu_data 5 gpio_12 i/o general purpose digital i/o signal / data bit lbu_data 6 gpio_13 i/o general purpose digital i/o signal / data bit lbu_data 7 gpio_14 i/o general purpose digital i/o signal / data bit l bu_data 8 gpio_15 i/o general purpose digital i/o signal / data bit lbu_data 9 gpio_16 i/o general purpose digital i/o signal / data bit lbu_data1 0 gpio_17 i/o general purpose digital i/o signal / data bit lbu_data1 1 gpio_18 i/o general purpose digital i /o signal / data bit lbu_data1 2 gpio_19 i/o general purpose digital i/o signal / data bit lbu_data1 3 gpio_20 i/o general purpose digital i/o signal / data bit lbu_data1 4 gpio_21 i/o general purpose digital i/o signal / data bit lbu_data1 5 gpio_22 i/o g eneral purpose digital i/o signal / address bit lbu_a 0 _in gpio_23 i/o general purpose digital i/o signal / address bit lbu_a 1 _in gpio_24 i/o general purpose digital i/o signal / address bit lbu_a 2 _in gpio_25 i/o general purpose digital i/o signal / addr ess bit lbu_a 3 _in gpio_26 i/o general purpose digital i/o signal / address bit lbu_a 4 _in gpio_27 i/o general purpose digital i/o signal / address bit lbu_a 5 _in gpio_28 i/o general purpose digital i/o signal / address bit lbu_a 6 _in gpio_29 i/o general p urpose digital i/o signal / address bit lbu_a 7 _in gpio_30 i/o general purpose digital i/o signal / address bit lbu_a 8 _in gpio_31 i/o general purpose digital i/o signal / address bit lbu_a 9 _in gpio_32 i/o general purpose digital i/o signal / address bit lbu_a1 0 _in gpio_33 i/o general purpose digital i/o signal / address bit lbu_a1 1 _in gpio_34 i/o general purpose digital i/o signal / address bit lbu_a1 2 _in gpio_35 i/o general purpose digital i/o signal / address bit lbu_a1 3 _in gpio_36 i/o general purpo se digital i/o signal / segment select 1 lbu_seg 0 _in gpio_37 i/o general purpose digital i/o signal / segment select 2 lbu_seg 1 _in gpio_38 i/o general purpose digital i/o signal / reset host spi interface host_reset_in gpio_39 i/o general purpose digita l i/o signal / start new spi transfer host_sfrn_in gpio_40 i/o general purpose digital i/o signal / spi receive data host_srxd_in gpio_41 i/o general purpose digital i/o signal / spi clock host_sclk_in gpio_42 i/o general purpose digital i/o signal / sp i transmit data host_stxd_out gpio_43 i/o general purpose digital i/o signal / header recognized host_shdr_out gpio_44 i/o general purpose digital i/o signal / spi clock local_sclk_out gpio_45 i/o general purpose digital i/o signal / start new spi trans fer local_sfrm_out gpio_46 i/o general purpose digital i/o signal / spi receive data local_srxd_in gpio_47 i/o general purpose digital i/o signal / spi transmit data local_stxd_out note s : 1. you can only use one interface exclusive. it is not allowed t o use e.g. the parallel and serial host interface at the same time. 2. unused gpio pins should be pulled up (10 k? to vcc33).
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 14 of 3 7 j ul 17 , 2014 3. the lbu_ready_out is designed to connect only to a single microcontroller. if you want to connect additional devices, you m ust add circuitry to realize the high - impedance state. 4. if the cpu does not have a ready input for connection to lbu_ready_out, customers can choose a wait time of 80 ns (8 cpu cycles) during each transfer cycle. table 1 - 9 : status leds profinet io pin name( led ) color i/o state function led_bf_out red o bus communication (active low) : on no link status available. flashing link status ok; no communication link to a profinet io - controller. off the profinet io - controller has an active communi cation link to this profinet io - device. led_sf_out red o system fail (active low) : on profinet diagnostic exists. off no profinet diagnostic. led_mt_out yellow o maintenance required (active low) : manufacturer specific C depends on the ability of the device. led_ready_out green o device ready (active low) : off tps - 1 has not started correctly. flashing tps - 1 is waiting for the synchronization of the host cpu (firmware start is complete). on tps - 1 has started correctly. table 1 - 10 : i 2 c interface lines pin name i/o function i2c_ (2: 1 ) _d_inout i/o fiber optic port (2: 1 ) i 2 c - bus data sclk_ (2:1) _inout o fiber optic port (2: 1 ) i 2 c - bus clock table 1 - 11 : boot uart lines pin name i/o function uart 6 _tx o boot uart transmit data ua rt 6 _rx i boot uart receive data boot_1 i forced boot value function 0x0 brom: boot from boot flash is enabled (normal operating mode). 0x1 uart: boot via uart is enabled.
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 15 of 3 7 j ul 17 , 2014 table 1 - 12 : watchdog signals pin name i/o function remark wd_in i wat chdog input (from the host ) this signal triggers the tps - 1 watchdog that monitors the host cpu. a rising edge of this signal restarts the watchdog counter (active high) . wd_out o watchdog output (to the host ) this signal is set when a watchdog trigger o f the tps - 1 occurs (active low). table 1 - 13 : jtag interface pin definition pin name i/o function remark trstn i test reset jtag reset. input: reset signal of the target port. external p ull - down (4 . 7 k ? to gnd ) tms i test mode select jtag interface is activated from the debug unit. p ull - u p ( 4 . 7k ? to v dd ) tdo o test data output can be left open tck i test clock jtag clock signal to the tps - 1. it is recommended that this pin is set to a defined stat e on the target board. external p ull - up ( 4 . 7k ? to v dd ) tdi i test data input external p ull - u p( 4 . 7k ? to v dd ) table 1 - 14 : supply voltage circuitry pin name function supply voltage generation p (2: 1 ) vddarxtx analog port rx/tx power supply, 1.5 v (phy por t 2: 1) mus t be generated from vdd15 via a filter. vddapll analog central power supply, 1.5 v (phy) vddacb analog central power supply, 3.3 v (phy) must be generated from vdd33 via a filter. vdd33esd analog test power supply, 3.3 v (phy) vssapllcb ana log central g n d (phy) must be generated from gnd core/io via a filter or connected to gnd core/io at the far end from tps - 1. vddq_pecl_b (2: 1 ) pecl buffer power supply 3.3 v ( port 1 and p ort 2) pll_agnd analog ground for the internal cpu clock generation pll_avdd power supply for the internal cpu clock generation (1.0v) gnd digital gnd agnd analog ground for phys vdd33 voltage supply 3.3 v (external) vdd15 voltage supply 1.5 v f ro m switching regulator or external vdd10 voltage supply 1.0 v (ex ternal) agnd _reg analog ground for s witching r egulator . avdd_reg supply voltage for regulator(3.3v supply), smoothed voltage to feed the internal por. bgnd gnd for switching regulator p lease place bypass capacitor between analog power supply and gnd bvdd supply voltage for the switching regulator (3.3v) f or the switching transistor
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 16 of 3 7 j ul 17 , 2014 1.2 . pin characteristics table 1 - 15 : signal characteristics pin name i/o input type output type p ull u p / down p ull u p / down capacity load (pf) drive capability i nternal external i oh i ol spi - master for flash rom cs_flash_out o - 3.3v cmos - 30 6 ma 6 ma spi3_sclk_out o - 3.3v cmos - 30 6 ma 6 ma spi3_srxd_in i schmitt 3.3v cmos - - - - spi 3 _stxd_out o - 3.3v cmos - 30 6 ma 6 ma synchronisation signals t est_sync o - 3.3v cmos - 30 6 ma 6 ma t1 o - 3.3v cmos - 30 6 ma 6 ma t2 o - 3.3v cmos - 30 6 ma 6 ma t3 o - 3.3v cmos - 30 6 ma 6 ma t4 o - 3.3v cmos - 30 6 ma 6 ma t5 o - 3.3v cmos - 30 6 ma 6 ma t6 o - 3.3v cmos - 30 6 ma 6 ma led signals for profinet io status led_bf_out o - 3.3v cmos - 30 6 ma 6 ma led_sf_out o - 3.3v cmos - 30 6 ma 6 ma led_ready_out o - 3.3v cmos - 30 6 ma 6 ma led_mt_out o - 3.3v cmos 30 6 ma 6 ma phy port 1 i2c_1_d_inout i/o schmitt 3.3v cmos - 30 6 ma 6 m a sclk_1_inout i/ o schmitt 3.3v cmos - 30 6 ma 6 ma link_phy1 o - 3.3v cmos - 30 6 ma 6 ma act_phy1 o - 3.3v cmos - 30 6 ma 6 ma p1_tx_p o - analog - - - - p1_tx_n o - analog - - - - p1_rx_p i - analog - - - - p1_rx_n i - analog - - - - p1_s d_p i pecl - - - - - p1_sd_n i pecl - - - - - p1_rd_p i pecl - - - - - p1_rd_n i pecl - - - - - p1_td_out_p o - 3.3v cmos - - 12 ma 12 ma p1_td_out_n o - 3.3v cmos - - 12 ma 12 ma p1_fx_en_out o - 3.3v cmos - 30 12 ma 12 ma phy port 2 i2c_2_ d_inout i/o schmitt 3.3v cmos - 30 6 ma 6 ma sclk_2_inout i/ o schmitt 3.3v cmos - 30 6 ma 6 ma link_phy2 o - 3.3v cmos - 30 6 ma 6 ma act_phy2 o - 3.3v cmos - 30 6 ma 6 ma p2_tx_p o - analog - - - - p2_tx_n o - analog - - - - p2_rx_p i - analog - - - - p2_rx_n i - analog - - - - p2_sd_p i pecl - - - - - p2_sd_n i pecl - - - - - p2_rd_p i pecl - - - - - p2_rd_n i pecl - - - - - p2_td_out_p o - 3.3v cmos - - 12 ma 12 ma
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 17 of 3 7 j ul 17 , 2014 pin name i/o input type output type p ull u p / down p ull u p / down capacity load (pf) drive capability i nternal external i oh i ol p2_td_out_n o - 3.3v cmos - - 12 ma 12 ma p2_fx_en_out o - 3.3 v cmos - 30 12 ma 12 ma oscillator xclk1 i osc. in - - - - - xclk2 o osc. out - - 25 6 ma 6 ma jtag C interface tm0 i schmitt pull - up 50 k ? ? pull - down 1 k ? ? ? ? ? reset / test resetn i schmitt 3.3v cmos - - - - atp io - - - - - extres i o analog - - - - - tmc1 i 3.3v cmos pull - down (50 k?) - - - tmc2 i 3.3v cmos pull - down (l 50 k?) (50 k?) ( 50 k?) host interface wd_in i schmitt 3.3v cmos - - - - wd_out o - 3.3v cmos - 30 6 ma 6 ma int_out o - 3.3v cmos - 30 6 ma 6 ma boot interface (serial) uar t6_ t x o - 3.3v cmos - 30 6 ma 6 ma uart6_ r x i schmitt 3.3v cmos - - 6 ma 6 ma boot_1 i schmitt - p ull - down ( 50 k?) test signals C switching regulator test1 i - - - see note - - - test2 i - - - see note - - - test3 i - - - see note - - - power supplies gnd - - - - - - - vdd33 - - - - - - - vdd15 - - - - - - -
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 18 of 3 7 j ul 17 , 2014 pin name i/o input type output type p ull u p / down p ull u p / down capacity load (pf) drive capability i nternal external i oh i ol vdd10 - - - - - - - v dd 33esd - - - - - - - vddapll - - - - - - - vdda cb - - - - - - - vddq_pecl_b1 i - - - - - - vddq_pecl_b2 i - - - - - - p1vddarxtx i - - - - - - p2vddarxtx i - - - - - - vssapllcb - - - - - - - lx o - - - - - - fb (1.5v analog) i - - - - - - avdd_re g i - - - - - - bgnd - - - - - - - agnd_reg - - - - - - - bvdd - - - - - - - pll_agnd i - - - - - - pll_avdd i - - - - - - gpios gpio_00 i/o schmitt 3.3v cmos - 30 6 ma 6ma gpio_01 i/o schmitt 3.3v cmos - 30 6 ma 6ma gpio_02 i/o schmitt 3. 3v cmos - 30 6 ma 6ma gpio_03 i/o schmitt 3.3v cmos - 30 6 ma 6ma gpio_04 i/o schmitt 3.3v cmos - 30 6 ma 6ma gpio_05 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_06 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_07 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_08 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_09 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_10 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_11 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_12 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_13 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_14 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_15 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_16 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_17 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_18 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_19 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_20 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_21 i/o schmitt 3.3v cmos - 50 9 ma 9 ma gpio_22 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_23 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_24 i/o sch mitt 3.3v cmos - 30 6 ma 6 ma gpio_25 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_26 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_27 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_28 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_29 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_30 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_31 i/o schmitt 3.3v cmos - 30 6 ma 6 ma
tps - 1 1. pin functions r19ds0069ej010 3 rev. 1 . 0 3 page 19 of 3 7 j ul 17 , 2014 pin name i/o input type output type p ull u p / down p ull u p / down capacity load (pf) drive capability i nternal external i oh i ol gpio_32 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_33 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_34 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_35 i/ o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_36 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_37 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_38 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_39 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_40 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_41 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_42 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_43 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_44 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_45 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_ 46 i/o schmitt 3.3v cmos - 30 6 ma 6 ma gpio_47 i/o schmitt 3.3v cmos - 30 6 ma 6 ma note: these pins (test(3:1) ) must not be left open. for the required connection please consult the tps - 1 user manual. abbreviations: i input o output i/o input/out put
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 .0 3 page 20 of 3 7 j ul 17 , 2014 2. electrical specifications 2.1 . absolute maximum ratings table 2 - 1 : absolute maximum ratings parameter symbol rating unit power supply for core vdd10 - 0.5 to + 1.4 v power supply for io vdd33 - 0.5 to +4.6 v power supply for phys vdd15 - 0.5 to +2.0 v analog power supply for pll pll _a vdd - 0.5 to + 1.4 v analog central 3.3v supply for phys vddacb - 0.5 to +4.6 v analog central 1.5v supply for phys vddapll - 0.5 to +2.0 v analog rx/tx port power supply p(2:1)vddarxtx - 0.5 to +2.0 v pecl buffer p ower supply phy 1 vddq_pecl_b1 - 0.5 to +4.6 v pecl buffer power supply phy 2 vddq_pecl_b2 - 0.5 to +4.6 v analog test supply vdd33esd - 0.5 to +4.6 v input voltage 3.3v cmos v i < vdd + 0.5v v i - 0.5 to +4.6 v operating temperature t j - 40 to + 12 5 0 c sto rage temperature t stg - 65 to + 150 0 c caution:product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffer ing physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation.
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 21 of 3 7 j ul 17 , 2014 2.2 . operating conditions table 2 - 2 : recommended operati ng conditions (supply voltages) parameter symbol min. typ. max. unit power supply for core (digital) vdd10 0.9 1.0 1.1 v power supply for io (digital) vdd33 3.0 3 .3 3.6 v power supply for phys (digital) vdd15 1.35 1.5 1.65 v analog power supply for phys avdd_reg 3.0 3.3 3.6 v analog central 3.3v supply for phys vddacb 3.0 3.3 3.6 v analog central 1.5v supply for phys vddapll 1.35 1.5 1.65 v pecl buffer power s upply phy 1 vddq_pecl_b1 3.0 3.3 3.6 v pecl buffer power supply phy 2 vddq_pecl_b2 3.0 3.3 3.6 v analog test supply vdd33esd 3.0 3.3 3.6 v analog power supply for pll pll_avdd 0.9 1.0 1.1 v ambient temperature t a - 40 +85 0 c table 2 - 3 : recommended o perating conditions (input / output level) parameter symbol test conditions min . typ. max. unit output voltage high 3.3v cmos v oh i oh = 0 ma vdd33 C 0.1v v n ominal output current 2.4 v output voltage low 3.3v cmos v ol i ol = 0 ma 0.1 v n ominal output current 0.4 v input voltage high 3.3v cmos v ih 2 vdd33 v 3.3v pecl difference to vddq_pecl_b(2:1) - 0.880 1.165 v input voltage low 3.3v cmos v il 0 0.8 v 3.3v pecl difference to vddq_pecl_b(2:1) - 1.474 - 1.880 v positive trigger volt age 3.3v buffer v p 1.2 2.4 v negative trigger voltage 3.3v buffer v n 0.6 1.8 v hysteresis voltage 3.3v buffer v h 0.3 1.5 v table 2 - 4 : tps - 1 power consumption overview parameter min . typ. max. unit p ower consumption 1.0 v 300 mw 1.5v 240 m w 3.3v 363 mw t otal: 800 note 903 mw note: the power consumption of the tps - 1 is approx. 800mw (ave rage).
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 22 of 3 7 j ul 17 , 2014 2.3 . thermal characteristics table 2 - 5 : thermal characteristics of the package parameter symbol airflow (m/s) unit 0 0.2 1 2 thermal r esistance junction to ambient n ote1 ja 21.99 20.91 18.86 17.80 k/w thermal resistance junction to top centre of the package surface n ote1 jt 0.12 0.17 0.31 0.37 k/w thermal resistance junction to case n ote2 jc 7.38 k/w note 1. the parameters are valid, if no heat sink is used and pcb w ith 4 layers and massive ground and power planes. 2. the parameter is valid, if a heat sink is used.
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 23 of 3 7 j ul 17 , 2014 2.4 . ac characteristics 2.4.1 . clock timing table 2 - 6 : clock ac characteristics parameter symbol min. typ. max. unit oscillator clock frequency t c 25 - 50 ppm 25 25 + 50 ppm mhz jtag clock frequency - 20 mhz figure 2 - 1: cl ock waveforms t c 2 . 0 v 1 . 5 v 0 . 8 v
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 24 of 3 7 j ul 17 , 2014 2.4.2 . i/o timing specification figure 2 - 2 : input setup and hold waveforms figure 2 - 3 : output delay waveforms
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 25 of 3 7 j ul 17 , 2014 2.4.2.1 . jtag interface timing table 2 - 7 : timing jtag interface signal input output unit clock notes setup time (t is min.) hold time (t ih min.) valid delay (t ov max.) hold time (t oh min.) trst n 8 0 ns tck tms 8 0 ns tck tdi 8 0 ns tck tck - - - - - - note 2 tdo 10 2 ns tck note 1 note 1 : minimum hold time is measured with 10 pf load an d maximum valid delay is measured with 30 pf load. 2: for tck a maximum speed of 20 mhz is allowed.
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 26 of 3 7 j ul 17 , 2014 2.4.2.2 . parallel host interface timing diagrams 2.4.2. 2 .1 . host read from tps - 1 with separate read/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2 - 8 : host read with separate read/write line parameter symbol condition min. max. unit chip sele ct asserted to read pulse asserted delay t csrs - 0 - ns address valid to read pulse asserted setup time t ars - 0 - ns read pulse asserted to ready enabled delay t rre - 5 12 ns read pulse asserted to data enable delay t rde - 5 12 ns ready asserted to da ta valid delay t rtd - - 5 ns read pulse deasserted to chip select deasserted delay t rcsh - 0 - ns address valid to read pulse deasserted hold time t rha - 0 - ns data valid/enable to read pulse deasserted hold time t rdh - 0 12 ns read recovery time t rr - 25 - ns figure 2 - 4 : host read with separate read/write line l b u _ a ( 1 3 : 0 ) _ i n l b u _ s e g ( 1 : 0 ) _ i n l b u _ b e _ ( 2 : 1 ) _ i n l b u _ r e a d y _ o u t l b u _ d a t a ( 1 5 : 0 ) l b u _ c s _ n l b u _ r d _ e n _ n t c s r s t a r s t r r e t r d e t r t d t r d h t r a h t r r t r c s h
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 27 of 3 7 j ul 17 , 2014 2.4.2.2 .2 . host write to tps - 1 with separate read/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2 - 9 : host write with separate read/write line parameter symbol condition min. max. unit chip select asserted to write pulse asserted delay t csws - 0 - ns address valid to write pulse asserted setup time t aws - 0 - ns write pulse asserted to ready enabled delay t wre - 5 12 ns write pulse asserted to data valid delay t wd v - - 40 ns write pulse deasserted to chip select deasserted delay t wcsh - 0 - ns address hold time after write strobe deasserted t wah - 0 - ns ready asserted to write pulse deass erted delay t rtw - 0 - ns data hold time after write pulse deasserted t wdh - 0 - ns write recovery time t wr - 25 - ns figure 2 - 5 : host write with separate read/write line l b u _ a ( 1 3 : 0 ) _ i n l b u _ s e g ( 1 : 0 ) _ i n l b u _ b e _ ( 2 : 1 ) _ i n l b u _ r e a d y _ o u t l b u _ d a t a ( 1 5 : 0 ) l b u _ c s _ n l b u _ w d _ e n _ n t c s w s t a w s t w r e t w d v t w d h t w a h t w r t w c s h t r t w
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 28 of 3 7 j ul 17 , 2014 2.4.2.2 .3 . host read from tps - 1 with common re ad/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2 - 1 0 : host read with common read/write line parameter symbol condition min. max. unit write signal deasserted to chip select asserted setu p time t wcs - 2 - ns address valid to chip select asserted setup time t acs - 0 - ns chip select asserted to ready enabled delay t cre - 5 12 ns chip select asserted to data enable delay t cde - 5 12 ns ready asserted to data valid delay t rtd - - 5 ns wr ite signal inactive to chip select deasserted hold time t cwh - 0 - ns c hip select deasserted to address invalid hold time t cah - 0 - ns c hip select deasserted to data invalid hold time t cdh - 0 12 ns read recovery time t rr - 25 - ns figure 2 - 6 : h ost read with common read/write line l b u _ a ( 1 3 : 0 ) _ i n l b u _ s e g ( 1 : 0 ) _ i n l b u _ b e _ ( 2 : 1 ) _ i n l b u _ r e a d y _ o u t l b u _ d a t a ( 1 5 : 0 ) l b u _ c s _ n l b u _ w r _ e n _ n t w c s t a c s t c r e t c d e t r t d t c d h t c a h t r r t c w h
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 29 of 3 7 j ul 17 , 2014 2.4.2.2 .4 . host write to tps - 1 with common read/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2 - 11 : host write with common read/write line parameter s ymbol condition min. max. unit write signal deasserted to chip select asserted setup time t wcs - 2 - ns address valid to chip select asserted setup time t acs - 0 - ns chip select asserted to ready enabled delay t cre - 5 12 ns chip select asserted to da ta valid delay t cdv - - 40 ns write signal deasserted to chip select deasserted hold time t cwh - 0 - ns address hold time after chip select deasserted t cah - 0 - ns ready asserted to chip select deasserted delay t rtc - 0 - ns c hip select deasserted to data invalid hold time t cdh - 0 - ns read recovery time t wr - 25 - ns figure 2 - 7 : host write with common read/write line l b u _ a ( 1 3 : 0 ) _ i n l b u _ s e g ( 1 : 0 ) _ i n l b u _ b e _ ( 2 : 1 ) _ i n l b u _ r e a d y _ o u t l b u _ d a t a ( 1 5 : 0 ) l b u _ c s _ n l b u _ w r _ e n _ n t w c s t a c s t c r e t c d v t r t c t c d h t c a h t w r t c w h
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 30 of 3 7 j ul 17 , 2014 2.4.2.3 spi slave timing t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v t able 2 - 12 : spi slave timing pa rameter symbol condition min. max. unit spi clock t cl - 40 - ns setup time t su - 13 - ns hold time t h - 13 - ns figure 2 - 8: spi slave timing h o s t _ s c l k _ i n h o s t _ r e s e t _ i n h o s t _ s f r m _ i n h o s t _ s r x d _ i n h o s t _ s t x d _ o u t h o s t _ s h d r _ o u t t c l t s u t h t s u t h
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 31 of 3 7 j ul 17 , 2014 2.4.3 . i2c - bus timing definition t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2 - 1 3 : characteristics of the scl and sda lines parameter symbol standard - mode fast - mode unit min. max. min. max. scl clock frequency f scl 0 100 0 400 khz bus free time between a stop and start condition t buf 4.7 - 1.3 - s hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - s low period of the scl clock t low 4.7 - 1.3 - s high period of the scl clock t high 4.0 - 0.6 - s set - up time for repeated start condition t su;dat 4.7 - 0.6 - s data hold time t hd;dat 0 (1) - 0 (1) 0.9 s data set - up time t su;sta 250 - 100 (2) - n s rise time of both sda and scl signals t r - 1000 20+0.1c b 300 ns fall time of both sda and scl signals t f - 300 20+0.1c b 300 ns capacitive load for each bus line c b - 400 - 400 pf notes: 1. the devi c e must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 2. a fast - mode device can be used in a standard - bus system, but the requirement t su;sta must be met. figure 2 - 9 : i2c - bus timing definition t b u f t l o w t h d ; s t a t r t h d ; d a t t h i g h t f t s u ; d a t t s u ; s t a t h d ; s t a i 2 c _ x _ d _ i n o u t s c l k _ x _ i n o u t
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 32 of 3 7 j ul 17 , 2014 2.4.3.1 . phy dc specifications(100 base - tx) t a = - 40 to + 85 o c, avdd33 = 3.0 to 3.6v, avdd15 = 1.35 to 1.65v, dvdd = 1.35 to 1.65v table 2 - 1 4 : phy dc specification parameter symbol min. typ. max. unit tx output, high level differential signal, txp/txn v outh 0.95 1.05 v tx output, low level differential signal, txp/txn v outl - 0.95 - 1.05 v tx output, mid. level differential signal, txp/txn v outm - 0.05 +0.05 v tx output, overshoot differential signal, txp/txn v 0vs 0 5 % these specifications are complying with ansi/ieee 802.3 std. figure 2 - 10 : phy dc specification 0 v v o u t t h ( m a x ) v o u t t h ( m i n ) v o u t m ( m i n ) v o u t m ( m a x ) v o u t l ( m i n ) v o u t l ( m a x )
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 33 of 3 7 j ul 17 , 2014 2.4.3.2 . phy ac specifications (100base - tx) t a = - 40 to + 85 o c, avdd33 = 3.0 to 3.6v, avdd15 = 1.35 to 1.65v, dvdd = 1.35 to 1.65v table 2 - 1 5 : phy ac timing parameter symbol min. typ. max. unit rise time an d fall time, txp/txn t r , t f 3 5 n s duty cycle distorti on, txp/txn 0.5 n s transmit jitter, txp/txn 1.4 n s these specifications are comply ing with ansi/ieee 802.3 std. figure 2 - 1 1 : phy ac specification 0 v t r t r t f t f
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 34 of 3 7 j ul 17 , 2014 2.4.4 . power - up sequence for operation the tps - 1 needs three sup ply voltages. these are 3.3v, 1.5v and 1.0v, whereby the 1.5v power supply can be generated internally by a switch regulator. it is also possible to feed this power supply f r om an external circuitry. table 2 - 1 6 : signals for p ower - u p signal tps - 1 descripti on remark vdd power supply (all voltages) reset_n external reset active low xclk_1 quartz connection (input) figure 2 - 1 2 : power - up sequence timing diagram v d d r e s e t _ n x c l k 1 m i n . 3 5 u s u n s t a b l e m i n . 2 u s
tps - 1 2. electrical specifications r19ds0069ej010 3 rev. 1 . 0 3 page 35 of 3 7 j ul 17 , 2014 2.4.5 . reset timing table 2 - 1 7 : signals for r eset timing signal tps - 1 description remark xclk1 quartz connection (input) external signal clk_arm clock for the arm cpu internal signal reset_n external reset external signal (active low) por_out power on reset internal signal (supply voltages stable) pll_lock clocks are synchronous to xclk1 internal signal the start - up time of the oscillator cannot be defined by the semiconductor vendor, because the timing heavily depends on the external components (external resonator crystal). figure 2 - 1 3 : reset timing diagram (internal) (internal) x c l k 1 ( 2 5 m h z ) r e s e t _ n c l k _ a r m ( 1 0 0 m h z ) p l l _ l o c k ( i n t e r n a l ) 3 . 3 v s u p p l y s t a b l e 1 . 5 v s u p p l y a c t i v e p o r _ o u t 3 0 u s 5 0 0 u s 1 . 0 v s u p p l y a c t i v e
tps - 1 3. package drawing r19ds0069ej010 3 rev. 1 .0 3 page 36 of 3 7 j ul 17 , 2014 3. package drawing figure 3 - 1 : 196 - ball fpbga package drawing package: package fpbga 196 pins ball pitch 1.0 mm pitch dimensions 15 mm * 15 mm
tps - 1 4. recommended soldering conditions r19ds0069ej010 3 rev. 1 .0 3 page 37 of 3 7 j ul 17 , 2014 4. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to the information document. renesas semiconductor package mount manual, (rev. 3 .0, mar 20 13 ) ( r50zz0003ej0300 ) the applied standard is ir60 - 107 - 3. table 4 - 1 : recommended soldering conditions condition symbol soldering conditions ir60 package peak temperature: 260 0 c, time: 60 seconds max. (at 220 0 c or higher). - 107 exposure limit: 7 days note (after that, prebake at 125 0 c for 20 to 72 hours). - 3 co unt: three times or less. note: after opening the dry pack, store it at 25 0 c or less and 65% rh or less for the allowable storage period.

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