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preliminary rev. 0.1 7/07 copyright ? 2007 by silicon laboratories SI85XX this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. silicon laboratories confidential. information contained herein is covered under non-disclosure agreement (nda). SI85XX si85 xx unidirectional ac current sensors features applications description the SI85XX products are unidirectional ac current sensors available in full- scale ranges of 5, 10, and 20 a. SI85XX products are ideal upgrades for older current-sensing technologies offering size, performance and cost advantages over current transformers, hall effect devices, dcr circuits and other approaches. the SI85XX ar e extremely low loss, adding less than 1.3 m of series resistance and less than 2 nh series inductance in the sensing path at 25 oc. current-sensing terminals are isolated from the other package pins to a maximum voltage of 1,000 vdc. functional block diagram ? single-chip ac current sensor/conditioner ? low loss: less than 1.3 m primary series resistance; less than 2 nh primary inductance at 25 oc ? leading-edge noise suppression eliminates need for leading-edge blanking ? "ping-pong" output version allows one SI85XX to replace two current transformers in full-bridge applications ? 5, 10, and 20 a full-scale versions ? fault output helps safeguard operation ? 1,000 vdc isolation ? accurate to 5% of measurement ? large 2 v pp output pins signal at full scale ? high-side or low-side current sensing ? ?40 to 125 oc operating range (si85x4/5/6) ? small 4x4x1mm package ? low cost ? power supplies ? motor controls ? lighting equipment ? industrial equipment typical application vdd vout iin iout l c q1 q2 ph1 ph2 r1 out vdd1 gnd2 vin si850x trst r2 si851x metal slug vdd trst/fault iout iin gnd integrator signal conditioning adc auto calibration logic temp sensor out1 out2 mode logic mode r1 r2 r3 r4 reset logic gnd1 patents pending pin assignments: see page 20 12-pin qfn si850x 1 r1 r2 gnd2 gnd3 out nc trst gnd1 vdd2 vdd1 iin iout si851x 1 r1 r2 r3 r4 out1 out2 trst/fault gnd mode vdd iin iout
SI85XX 2 preliminary rev. 0.1
SI85XX preliminary rev. 0.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. under voltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. device start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3. integrator reset and cu rrent measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.4. effect of operating frequency on output accuracy . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. effect of temperature on accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.6. leading edge noise suppressi on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.7. fault output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1. board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2. device configurati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.3. single-phase buck conver ter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4. full-bridge converter exam ple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5. push-pull converter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4. pin descriptions?SI85XX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. package outline?12-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SI85XX 4 preliminary rev. 0.1 1. electrical specifications table 1. electrical specifications ta = ?40 to +85 oc (typical spec ified at 25 oc), vdd = 2.7 to 5.5 v parameter conditions min typ max unit supply voltage (v dd ) 2.7 ? 5.5 v supply current fully enabled, input frequency = 1mhz ? 4 7 ma undervoltage lockout (v uvlo ) 2.1 2.3 2.5 v undervoltage lockout hysteresis (v hyst ) ? 100 ? mv logic input high level mode, r1, r2, r3, r4 inputs (ttl compatible) 2.0 ? ? v logic input low level ? ? 0.8 v reset time (t r ) 250 ? ? ns r1, r2, r3, r4 in put rise time (t rr ) ? ? 30 ns r1, r2, r3, r4 in put fall time (t fr ) ? ? 30 ns measurement watchdog timeout (t wd ) 30 50 80 s series input resistance measured from iin to iout ? 1.3 ? m series inductance measured from iin to iout ? 2 ? nh input/output delay out, out1, out2 delay relative to input ? 50 100 ns start-up self-cal delay (t cal ) time from vdd = v uvlo + v hyst to cal complete ? 150 200 s input common mode voltage range ? ? 1,000 v operating input frequency range (f) 50 ? 1,200 khz dc power supply rejection ratio ? 80 ? db sensitivity si85x1/4/7 ? 400 ? mv/a si85x2/5/8 ? 200 ? mv/a si85x3/6/9 ? 100 ? mv/a out, out1, out2 offset voltage (v outmin ) current flow from i in to i out = 0 ? 10 ? mv vout slew rate out, out1, out2 load = 5k || 50 pf ? 50 ? v/s out, out1, out2 output resistance 20 30 measurement error (%)?all devices (?40 to 85 oc temp range) 5 to 10% of full scale ?20 ? +20 % 10 to 20% of full scale ?10 ? +10 % 20 to 100% of full scale ?5 ? +5 %
SI85XX preliminary rev. 0.1 5 measurement error (%)?all devices (?40 to 125 oc temp range) 5 to 10% of full scale ?30 ? +30 % 10 to 20% of full scale ?25 ? +25 % 20 to 100% of full scale ?20 ? +20 % table 2. absolute maximum ratings parameter symbol min typ max units storage temperature t stg ?65 +150 oc ambient temperature under bias t a ?40 +125 oc supply voltage v dd 5.75 v voltage on any pin with respect to ground (not including iin, iout) v in ?0.5 vdd + 0.5 v lead solder temperature (10 sec.) - 260 oc dc isolation - 1000 vdc note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the oper ational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 1. electrical specifications (continued) ta = ?40 to +85 oc (typical spec ified at 25 oc), vdd = 2.7 to 5.5 v parameter conditions min typ max unit
SI85XX 6 preliminary rev. 0.1 2. functional overview the SI85XX ac current sensor family of products mimic the functionality of a traditional current transformer (ct) circuit with burden resistor, diode and output filter, but offers enhanced performanc e and added capabilities. these devices use inductive current sensing and on- board signal conditioning electronics to generate a 2 v full-scale output signal proportional to the ac current flowing from the iin to the iout terminals. as shown in figure 1 and figure 2, current flowing through the metal package slug induces a signal in the pickup coil on- board the SI85XX die. this signal is applied to the input of an integrator that re-constructs the ac current flowing from iin to iout. on-board circuitry provides cycle-by- cycle integrator reset, and temperature and offset voltage compensation to achieve measurement accuracy to within 5%. figure 1. si850x (single output) block diagram figure 2. si851x (ping pong output) block diagram the SI85XX is superior to other current sensing approaches and benefits the system in a number of ways: ? small size: with its 4x4 mm footprint and 1 mm height, the SI85XX is among the smallest current sensors available. ? large output signal: the 2.0 v full-scale output swing offers superior noise immunity versus other current sensing technologies. ? low loss: the SI85XX adds only 1.3 m (at 25 c) to the sensing path making it one of the lowest loss current sensors available. low 2 nh primary series inductance is 2,000 times lower compared to a ct, and results in significantly less ringing. ? high precision: the si8501/2/3 versions are available with a max error of 5% of reading; one of the highest accuracy current sensors available. ? ping-pong output mode (si851x): alternately routes the current measurements from each side of a full-bridge circuit to separate output pins for comparison, which is very useful for transformer flux balancing applications. eliminates a second ct in a full-bridge application. ? leading edge noise suppression: filters out reflected noise due to long reverse recovery time of output rectifier. eliminates the need for external leading edge blanking circuit. ? high common mode voltage: the SI85XX offers up to 1,000 vdc of isolation making it useful over a very wide voltage range. si850x metal slug vdd1 trst iout iin gnd1 integrator signal conditioning adc auto calibration logic temp sensor out vdd2 r1 r2 reset logic gnd2 nc gnd3 pickup coil si851x metal slug vdd trst/fault iout iin gnd integrator signal conditioning adc auto calibration logic temp sensor out1 out2 mode logic mode r1 r2 r3 r4 reset logic pickup coil
SI85XX preliminary rev. 0.1 7 ? fault output (si8517/8/9): goes low when external reset timing is in error. ? ease-of-use: other than conventional power and grounding techniques, no special board layout considerations are required. built-in timing interface circuits allow already available system switching signals to be used for reset?no external circuits required. 2.1. under voltage lockout (uvlo) uvlo is provided to prevent erroneous operation during device start-up and shutdown, or when vdd is significantly below specif ied operating range. the SI85XX is in uvlo state when vdd < v uvlo (figure 3). during uvlo, the output(s) are held at minimum value regardless of the amount of current flowing from iin to iout and signals on integrator reset inputs r1-r4 are ignored. the SI85XX exits uvlo when vdd > (v uvlo + v hyst ). 2.2. device start-up upon exit from uvlo, the SI85XX performs a voltage offset and temperature self-calibration cycle. during this time, output(s) are held at minimum value and reset inputs (r1-r4) are ignored. the reset inputs are enabled at the end of the self-calibration cycle, and an integrator reset cycle is init iated on the fi rst occurrence of active signals on r1-r4. a current measurement is initiated immediately after the completion of the integrator reset cycle, and the resulting current waveforms appear on the output pins. this "reset- measure-reset" pattern repeats throughout steady-state operation. 2.3. integrator reset and current measurement the SI85XX measures current flowing from the iin to iout terminals. current is allowed to flow in the opposite direction, but will not be measured (out1 and out 2 remain at their minimum values during reverse current flow. reverse curr ent flow will not damage the SI85XX). to achieve specified accuracy , the integrator capacitor must be discharged (reset) for time period t r prior to the start of every measurement cycle. this cycle-by-cycle reset is implemented by connecting existing system gate control signals to the r1?r4 inputs in a way that resets the integrator when no current is flowing from iin to iout. to achieve rate d accuracy, the reset cycle must be completed prior to the start of the measurement cycle. for maximum flexibility, integrator re set operation can be configured in one of two ways: option 1: the start and duration of reset is determined by the states of the timing signals applied to r1-r4. option 2: the timing signals applied to r1-r4 trigger the start of reset, and the duration of the reset is determined by an on-board programmable reset timer. figure 3. SI85XX startup and control timing under voltage lockout state measure current vdd supply integrator reset SI85XX status SI85XX output first positive edge following end of self-cal start-up self-cal cycle tcal reset reset don?t care tr vout min out1, out2 valid trp tr v uvlo + v hyst trp
SI85XX 8 preliminary rev. 0.1 integrator reset option 1 is selected by connecting t rst to vdd. in this mode, the SI85XX is held in reset as long as the signals on r1-r4 satisfy the logic equations of tables 3 and 4. it is typically used in applications where the gate drivers are external to the system controller i.c. (the gate driver delay ensures reset is completed prior to the start of measurement). reset option 2 is selected by connecting a timing resistor (r trst in figure 4) from the trst input to ground. it is typically used in applications where the gate drivers are on-board the controller. in this mode, the on-chip reset timer is triggered when the signals on r1-r4 satisfy the logic equations of tables 3 and 4. once triggered, the timer maintains integrator in reset for time duration t r as programmed by the value of resistor r trst . the user must select the value of resistor r trst to terminate the reset cycle prior to the start of measurement under worst-case timing conditions. note th at values of t r below the specified value in section ?1. electric al specifications? results in increased integrator output offset error and increased output noise on vout. moreover, t r ?s time is summarized by the following equation: t r = 10 ns/k where values of r trst that produce a reset time less than 200 ns (r trst < 20 k ) should not be used. figure 4. programming reset time (t r ) 2.4. effect of operating frequency on output accuracy the SI85XX includes a built-in watchdog timer that disables measurement and holds out or out1 and out2 at their minimum val ues when the timer?s preset limit is exceeded. this time r limits the operation of the SI85XX in dc measurement applications. as figure 5 illustrates, the si 85xx operates down to about 10 khz with the nominal measurement error doubling to about 10 percent. figure 5. full-scale error vs. frequency 2.5. effect of te mperature on accuracy offset voltage present at the SI85XX output terminals (output offset voltage) is calibrated out each time vdd is applied to the SI85XX; so, its error contribution is minimized when the temperature at which calibration occurred is at or near the steady-state operating temperature of the SI85XX. for example, applying vdd at 25 c (offset cal is performed) and operating at 85 c will result in a larger offset error than operating at 50 oc. the effect of this error is summarized in figure 6. the chart is referenced to 25 c . if the SI85XX is powered up at 25 c and then operated at 125 c with no auto- calibration performed (i.e ., the power is not cycled at 125 c, which causes an auto-calibration), a 3 percent measurement error can be expected. figure 6. differential temperature calibration error SI85XX trst r trst 0% 3% 6% 9% 12% 15% 10 20 30 40 50 frequency (khz) % typical error -3.5% -3.0% -2.5% -2.0% -1.5% -1.0% -0.5% 0.0% 0.5% 1.0% 0255075100125 temperature (celcius) % typical erro r
SI85XX preliminary rev. 0.1 9 figure 7 shows the SI85XX thermal characteristics over the temperature range of ?40 to +125 oc. series inductance is constant at 2 nh (max) across this same temperature range. figure 7. series resistance thermal characteristics 2.6. leading edge noise suppression high-amplitude spikes on the leading edge of the primary switching waveforms can cause the pwm latch to be erroneously reset at the start of the switching cycle when operating in current m ode control. to prevent this problem, leading edge blanking is commonly used to disable the current comparator during the early portion of the primary-side s witching cycle. the SI85XX eliminates leading-edge noise spikes by including them in the signal integration. as shown in the output waveform of figure 8, noise present in the input waveform is eliminated without the use of blanking. figure 8. leading-edge noise suppression waveforms (200 khz, 9.3a load) (si8502 waveform measured directly on out pin with no external filter) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -20 0 20 40 60 80 100 12 0 temperature (c) typical series resistance (mohm) current sense transformer si8502
SI85XX 10 preliminary rev. 0.1 2.7. fault output the fault output (si8517/8/9) guards against SI85XX output signal errors caused by missing reset cycles. fault is asserted when a measurement cycle exceeds the internal watchdog timer times limit of t wd . fault can be used to alert a local microcontroller or digital power controller of a current sense failure, or initiate a system shutdown. to detect faults, tie a 200 k resistor from trst/fault to vdd. 3. application information 3.1. board layout the SI85XX is connected in the series path of the current to be measured. the SI85XX must be located as far away from away from transformer and other magnetic field sources as possible. like other analog components, the SI85XX should be powered from a low- noise dc source, and preferably connected to a low noise analog ground plane. recommended bypass capacitors are 1 f in parallel with a 0.1 f, positioned as close to the SI85XX as possible. when using the si850x (single output versions), all 3 ground pins must be connected to the same ground point, and both vdd and vdd2 pins must be tied to vdd. 3.2. device configuration configuring the SI85XX involves the following steps: 1. selecting an output mode 2. configuring integrator reset timing 3. setting integrator reset time t r 3.2.1. device selection the SI85XX family offers three output modes: single output (si850x), and 2 and 4-wire ping pong (si851x). the si851x products can be c onfigured to operate in all three of these output modes. the si850x products operate only in single output mode. most half-wave and single-phase applications require only single output mode, and will typically use the si850x. in single output mode, output current always appears on the out pin (si850x) or the out1 pin (si851x). a single integrator reset signal is typically sufficient when operating in this mode. ping-pong mode routes the current waveform to two different output pins on alternate measurement cycles. it is useful in full-wave and push-pull topologies where external circuitry can be used to monitor and/or control transformer flux balance. (note: the applications section of this data shee t (section 3) shows design examples using both output modes in various power topologies.) 2-wire ping-pong mode is useful mainly in non- overlapping two-phase buck converters, but may also be used in full-bridge applications. in this output mode, reset inputs r1 and r2 are used, and input r3 is grounded. measured current appears on out1 when r2 is high, and appears on out2 when r1 is high as shown in the full-bridge timing example of figure 9. figure 9. full-bridge timing example a 4-wire ping-pong mode is recommended for full-bridge applications over 2-wire because it uses all four inputs making the reset function tolerant to single-point signal failures. in 4-wire ping-pong mode, current appears on out2 when r1 is high and r2 is low; and appears on out1 when r3 is high and r4 is low as shown in the full-bridge timing example of figure 10. table 3 shows the states of the mode and r4 inputs that select each output, and the resulting reset logic functions and truth tables. r1 r2 reset SI85XX state measure out1 out2 measure reset tr tr time
SI85XX preliminary rev. 0.1 11 figure 10. full-bridge timing example b 3.2.2. selecting reset timing signals reset timing signals should be chosen to meet the following conditions: ? satisfy reset time t r ? not overlap integrator reset into the desired measurement period ? not violate reset watchdog timeout period t wd 3.2.3. configuring integrator reset per section ?2. functional overview?, the integrator must be reset (zeroed) prior to the start of each measurement cycle to achieve specified measurement accuracy. this reset must be synchronized with the system switch timing signals to ensure current is measured during the appropriate time, so the SI85XX integrator reset circuitry uses system timing as its reference. timing signals connect to reset inputs r1 through r4 where built-in logic functions allow the user to choose the conditions that cause an integrator reset event. important note: reset inputs r1?r4 are rated to a maximum input voltage of vdd. extern al resistor dividers must be used w hen connecting driver output signals to r1?r4 that swing beyond vdd. r1 r3 r2 r4 measure out1 out2 measure reset tr reset tr
SI85XX 12 preliminary rev. 0.1 table 3. si850x reset mode summary output mode r2 r1 reset state* logic expression single-ended 0 0 0 reset = xor [r1, r2] 01 1 10 1 11 0 *note: device is in reset when reset state = 1. table 4. si851x output and reset mode summary part # output mode mode input r4 r3 r2 r1 reset state* logic expression si850x single-ended ? ? ?0 0 0 reset = xor [r1, r2] 1 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 0 *note: device is in reset when reset state = 1.
SI85XX preliminary rev. 0.1 13 as shown in table 3, the si850x integrator reset logic is a simple xor gate where rese t is maintained (or triggered, depending on use of the trst input) when states of reset inputs r1 and r2 are not equal. figure 11 shows the logic for the si851x products, wher e any one of three reset logic functions can cause integrator reset. the output mode (si851x) is determined by the states of the mode and r4 inputs, as shown in ta b l e 4 . as explained in section 2.3, the signals applied to r1-r4 can control integrator reset in real time (option 1), or can trigger a reset event of programmable duration (option 2) . referring to figure 11, reset timing is exclusively a function of the signals applied to r1-r4 when trst is tied to vdd. if not connected to vdd, the reset timer is enabled and trst must be connected through a resistor to ground to set the reset duration (t r ). note the reset timer is retriggerable, and generates a timed integrator discharge pulse whe never the reset logic output transitions from low to high. si851x single-ended 1 0 0 0 0 0 reset = xor [r1, r2] 1 1 1 0 1 1 0 10 0 1 reset = xnor [r1, r2] 1 0 1 0 1 1 0 2-wire ping pong 1 1 0 0 0 1 1 0 1 0 0 1 1 4-wire ping pong 0 0 0 0 0 0 reset = [r1 & r2] | [r3 & r4] 1 0 1 0 0 1 1 10 0 0 1 0 1 0 0 1 1 100 0 0 1 0 1 0 0 1 1 10 0 1 1 1 1 0 1 1 1 table 4. si851x output and reset mode summary (continued) part # output mode mode input r4 r3 r2 r1 reset state* logic expression *note: device is in reset when reset state = 1.
SI85XX 14 preliminary rev. 0.1 figure 11. si851x integrator reset logic r4 r2 r1 r3 integrator mode = 1 r4 = 0 mode = 1 r4 = 1 mode = 0 system controller logic level gate control signals (to rn inputs) logic level gate control signals (to rn inputs) external driver internal driver required if driver output voltage > vdd output 1 output 2 output 3 reset timer out clk trst pgm vref reset timing determined only by inputs r1?r4. reset triggered by inputs r1?r4. reset time (t r ) set by value of resistor r trst . trst = r1 to gnd trst = vdd 0 + 1
SI85XX preliminary rev. 0.1 15 3.2.4. setting reset time t r the programmable reset timer is triggered when the stat es of the signals applied to r1?r4 cause the associated logic expression (tables 3 and 4) to go high (transition to the true state). because this timer is re-triggerable, r1? r4 must remain true for the duration of the desired t r as shown in figure 12. should r1?r4 transition false during t r , integrator reset will be immediat ely halted resulting in lower meas urement accuracy due to higher integrator offset error. figure 12. correct t r programming using resistor from trst input to ground current true false r1?r4 state reset measure SI85XX status programmed value of t r SI85XX output r1?r4 true for programmed t r (minimum) 0 ns (min)
SI85XX 16 preliminary rev. 0.1 3.2.5. measurement wa tchdog timer and fault output a built-in watchdog timer disables measurement and holds out or out1 and out2 at their minimum values when the time between integrator resets exceeds t wd . the output signal from this watchdog is available on the fault output pin (si8517/8/9 only). figure 13. measurement watchdog timer operation as shown in figure 13, the time between integrator resets for system timing phase t 1 is greater than watchdog period t wd . as a result, measurement occurs until t wd is exceeded, at which time th e output is immediately forced to minimum value and fault transitions low. further measurements are inhibited until the application of another integrator reset, which also resets the watchdog driving fault high, and enables another measurement cycle. this process continues until t wd is no longer violated, as shown in period t 2 where normal operation is restored. the current measurements made in pe riod t1 will have reduced accuracy vers us those made within the specified operating frequency range. t wd t wd t 1 t 2 system timing phase output t r reset trigger measurement period measurement period t r t wd fault
SI85XX preliminary rev. 0.1 17 3.3. single-phase buck converter example in this example, the si850x is configured to operate in a single-phase synchronous buck converter (figure 14). this converter has a pwm frequency of 1 m hz, and a maximum duty cycle of 80%. figure 14. si850x single-phase buck converter this is an example of a half-wave application that can be addressed with single-ended output mode. the pwm period is calculated to be 1/10 ?6 = 1.0 s, and the worst-case value t r is 0.2 x 1.0 x 10 ?6 = 200 ns at 80% maximum duty cycle (r trst =20k ). in this example, the current meas urement is made when the buck switch is on, so ph2 is chosen as the reset si gnal by connecting ph2 to r1 and gr ounding the r2 and r3. the ph2 signal can be obtained at the input of the driver external to the pwm controller, or the output of the controller's internal driver (through a resistor divider if the driver output swings beyond the device vdd range). vdd vout 2 vpp iin iout l1 c3 q1 q2 ph1 ph2 r1 out vdd1 gnd1 vin si850x vdd2 r2 pwm reset ph2 si850x state i > 0 i = 0 current measure gnd2 trst r trst 100 ns gnd3 c1 0.1 f c2 1 f
SI85XX 18 preliminary rev. 0.1 3.4. full-bridge converter example the full-bridge circuit of figure 15 uses an si851x config ured in 4-wire ping-pong output mode. the switching frequency of this phase-shifted full-bridge is 150 khz, and the maximum control phase overlap is 70%. figure 15. full-bridge converter given the 150 khz switching frequency (duty cycle fi xed at 50%), the equivalent period is 1/150 x 10 3 = 6.6 s. at 70% maximum overlap, this equates to a worst-case t r value of is 0.3 x 6.6 x 10 ?6 = 1.98 s; the default value for t r can therefore be used, and is selected by connecting trst to vdd. as shown in the timing diagram of figure 15, integrator reset occurs when current circulates between q1 and q2, and between q3 and q4 (i.e. when current is not being sourced from vin). the external driver delay ensures reset is complete prior to the start of measurement. iin iout ti q1 q3 ph1 ph2 r1 out1 gnd vin si851x mode ph4 ph3 q2 q4 r2 vdd vdd out2 out1 out2 ph1 ph3 ph2 ph4 3?4 1?4 1?2 2?3 reset reset SI85XX state measure trst out1 out2 measure r3 r4 switches turned on vdd c1 0.1 f c2 1 f
SI85XX preliminary rev. 0.1 19 3.5. push-pull converter example the push-pull converter of figure 16 uses 2-wire ping po ng output mode. as shown in the timing diagram, the integrator reset occurs when the inputs of both the ph1 and ph2 drivers are low. as shown, trst is connected to vdd, selecting the default value of t r (250 ns). assuming an 80% maximum duty cycle, this value of t r would deliver specified accuracy over a pwm frequency ran ge of 50 to 400 khz. frequencies above 400 khz would require the selection of a lower t r value by connecting a resistor from trst to ground. figure 16. push-pull example using default t r value vdd iin iout q1 q2 ph2 r1 out1 vdd gnd vin si851x mode SI85XX status t1 ph1 ph2 measure reset ph1 r2 r3 r4 out2 measure reset measure out1 out2 trst c1 0.1 f c2 1 f
SI85XX 20 preliminary rev. 0.1 4. pin descriptions?SI85XX figure 17. example pin configurations table 5. SI85XX family pin descriptions pin# si850x pin name description si851x pin name description 1 r1 integrator reset input 1 r1 integrator reset input 1 2 r2 integrator reset input 2 r2 integrator reset input 2 3 gnd2 ground r3 integrator reset input 3 4 gnd3 r4 integrator reset input 4 5 out output out1 output in single-ended output mode, or one of two outputs in ping-pong mode. 6 nc no connect out2 second of two ping-pong mode outputs 7 trst reset time control t rst reset time control 8 gnd1 ground gnd ground 9 iout current output terminal iout current ou tput terminal 10 iin current input terminal iin current input terminal 11 vdd1 power supply input vdd power supply input 12 vdd2 mode mode control input 12-pin qfn si850x 1 r1 r2 gnd2 gnd3 out nc trst gnd1 vdd2 vdd1 iin iout si851x 1 r1 r2 r3 r4 out1 out2 trst/fault gnd mode vdd iin iout
SI85XX preliminary rev. 0.1 21 5. ordering guide p/n full scale current (a) full scale error (% of reading) temp range ( c) pin 7 function output mode package si8501-b-gm 5 5 ?40 to +85 integrator reset time programming input single 4x4 mm qfn si8502-b-gm 10 si8503-b-gm 20 si8504-b-im 5 20 ?40 to +125 integrator reset time programming input si8505-b-im 10 si8506-b-im 20 si8511-b-gm 5 5 ?40 to +85 integrator reset time programming input ping-pong si8512-b-gm 10 si8513-b-gm 20 si8514-b-im 5 20 ?40 to +125 integrator reset time programming input si8515-b-im 10 si8516-b-im 20 si8517-b-gm 5 5 ?40 to +85 fault output si8518-b-gm 10 si8519-b-gm 20 note: all packages are pb-free and rohs compliant. moisture sens itivity level is msl2 with pe ak reflow temperature of 260 oc according to the jedec industry classification, and peak solder temperature.
SI85XX 22 preliminary rev. 0.1 6. package outline?12-pin qfn figure 18 illustrates the package details for the SI85XX. table 6 lists the val ues for the dimensions shown in the illustration. figure 18. 12-pin qfn package diagram table 6. qfn-12 package diagram dimensions dimension min nom max a 0.80 0.85 0.90 b 0.25 0.30 0.35 c 0.85 0.90 0.95 d4.00 bsc. e0.50 bsc. e4.00 bsc. f2.45 bsc. g1.30 bsc. k0.75 bsc. l 0.35 0.40 0.45 l1 0.03 0.05 0.08 l2 0.45 0.50 0.55 aaa ? ? 0.05 bbb ? ? 0.05 ccc ? ? 0.08 ddd ? ? 0.05 eee ? ? 0.05
SI85XX preliminary rev. 0.1 23 n otes :
SI85XX 24 preliminary rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: powerproducts@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believ ed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. the sale of this product contains no licens es to power-one?s intellectual property. contact power-one, inc. for appropriate lic enses.

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