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all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. customer approval sheet customer model customer approved approval for specifications only (spec. ver. 0.7 ) approval for specifications and es sample (spec. ver. 0.7 ) approval for specifications and cs sample (spec. ver. 0.7 ) p/n : 97.03a11.900-s06 comment : www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 2/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. product specification 3.5" color tft-lcd module model name: a035qn02 v9 < >preliminary specification < > final specification note: the content of this specificat ion is sub ject to change . ? 2009 au optronics a ll rights reserved do not copy. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 3/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. record of revision version revise date page content 0.0 2008/04/29 first draft. 5 modify module dimension (thickness 4.32mm 4.07mm) 6 update drawing 19 modify the command register settings ( r12 : 0050 h ) 29 add packing form 0.1 2008/07/02 30 update recommend register settings ( r12 : 0050h ) 0.2 2008/10/06 30 update recommend register setting s ( r0c : 0004h ) 0.3 2008/11/03 30 update recommend register setting s (r0c : 0005h / r1e : 00a4h ) 7 update pin assignment 9 update led forward current 10 update backlight driving conditions 15~23 update command register settings 31 update recommended register settings 0.4 2008/12/05 32~33 update power on/off sequence 9 update led forward current ( max 25ma ) 0.5 2009/01/21 10 update led supply current ( max 22ma ) 22 update command register settings 33,34 add shut in power on sequence 0.6 2009/06/02 35 update suggested circuit 12 update thv and add design note 13~15 add max and min value in the timing format 19 add r0b description 0.7 2009/06/17 33 add r08 register (dc80h) in the recommended regis ter setting www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 4/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. contents: a. general description ...................................... ................................................... ................. 5 b. features .............................................. ................................................... ............................. 5 c. physical specifications .................................... ................................................... ............. 6 d. outline dimension ..................................... ................................................... ..................... 7 e. electrical specifications .................................. ................................................... .............. 8 1. pin assignment..................................... ................................................... ................................................. 8 2. absolute maximum ratings ........................... ................................................... .................................... 10 3. electrical characteristics ..................... ................................................... .............................................. 11 a. tft- lcd panel (gnd=0v) ............................ ................................................... ................................. 11 b. backlight driving conditions ...................... ................................................... ...................................... 11 4. ac timing ....................................... ................................................... ................................................... ..... 12 a. display general information ........................ ................................................... .................................... 12 b. 8-bit serial interface .............................. ................................................... ........................................... 13 c. spi timing diagram .................................. ................................................... ....................................... 16 d. spi timing specification ............................. ................................................... ..................................... 16 5. command register settings....................... ................................................... .......................................... 17 a. serial setting map ................................. ................................................... ........................................... 17 b. description of serial control data.................. ................................................... .................................... 18 f. optical specifications (note 1, 2) ........................... ................................................... .... 26 g. touch screen panel specifications ............................ .................................................. 28 1. electrical characteristics ...................... ................................................... ................................................ 28 2. mechanical characteristics...................... ................................................... ............................................. 28 3. life test condition ............................. ................................................... ................................................... . 28 4. attention....................................... ................................................... ................................................... ........ 29 h. reliability test items ................................... ................................................... ................. 31 i. packing form .......................................... ................................................... ...................... 32 j. application note ..................................... ................................................... ...................... 33 1. recommended register settings ...................... ................................................... ................................ 33 2. power on/off sequence.............................. ................................................... ......................................... 34 3. suggested circuit.................................. ................................................... .............................................. 36 www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 5/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. a. general description a035qn02 v9 is an amorphous transmissive type thin film transistor liquid crystal display (tft-lcd). this model is composed of a tft-lcd, a driver, an fpc (fl exible printed circuit), a backlight unit and a touch panel. b. features 3.5-inch display with integrated resistive type touch panel qvga resolution in rgb stripe dot arrangement single power, dc/dc integrated high brightness 3-wire register setting interfaces: serial rgb 8-bit wide viewing angle 3-in-1 fpc for lcd signals, backlight led power and touch panel green design www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 6/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. c. physical specifications no. item unit specification remark 1 display resolution dot 320 rgb (h)240(v) 2 active area mm 70.08(h)52.56(v) 3 screen size inch 3.5(diagonal) 4 dot pitch mm 0.073(h)0.219(v) 5 color configuration -- r. g. b. stripe note 1 6 color depth -- 16.7m colors 7 overall dimension mm 76.9(h) 63.9(v) 4.07(t) note 2 8 weight g 40 9 display mode -- normally white 10 gray level inversion direction 6 oclock note 1: below figure shows dot stripe arrangement. note 2: not including fpc. refer to the drawing next page for further information. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 7/36 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. d. outline dimension www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 8/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. e. electrical specifications 1. pin assignment no. pin name i/o description remarks 1 led_c p cathode foe led back-light 2 led_a p anode for led back-light 3 nc no connection. please leave it open 4 y1 o touch panel top electrode 5 x1 o touch panel right electrode 6 y2 o touch panel bottom electrode 7 x2 o touch panel left electrode 8 nc no connection. please leave it open 9 vgh c stabilizing capacitor 10 c2p c booster capacitor 11 c2n c booster capacitor 12 c1p c booster capacitor 13 c1n c booster capacitor 14 vgl c stabilizing capacitor 15 c3n c booster capacitor 16 c3p c booster capacitor 17 vcix2 c stabilizing capacitor 18 cyp c booster capacitor 19 cyn c booster capacitor 20 vci p booster input voltage pin 21 gnd c power grounding 22 vcim c booster capacitor 23 cxp c booster capacitor 24 cxn c booster capacitor 25 reset i system reset pin 26 vddio p voltage input pin for logic i/o 27 vcore c stabilizing capacitor 28 gnd g power grounding 29 csb i chip select pin of serial interface 30 sdi i data input pin in serial mode 31 sck i clock input pin in serial mode www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 9/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 32 den i data enable pin from controller fixed to vddio if not used. 33 db7 i serial data ( msb ) 34 db6 i serial data 35 db5 i serial data 36 db4 i serial data 37 db3 i serial data 38 db2 i serial data 39 db1 i serial data 40 db0 i serial data 41 hsync i line synchronization signal fixed to vddi o or vss if not used. 42 vsync i frame synchronization signal fixed to vddio or vss if not used 43 dotclk i dot-clock and oscillator source 44 nc no connection. please leave it open 45 vlcd63 c stabilizing capacitor 46 vcomh c stabilizing capacitor 47 vcoml c stabilizing capacitor 48 cdmuo c stabilizing capacitor 49 csvcmp c stabilizing capacitor 50 csvcmn c stabilizing capacitor i: input pin; p: power pin; g: ground pin; c: capacit or pin www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 10/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 2. absolute maximum ratings values items symbol min. max. unit condition power voltage vcc -0.3 4 v led reverse voltage vr 5 v one led led forward current if 25 ma one led, note 2 note 1.if the operating condition exceeds the absolute maximum ratings, the tft-lcd module may be damaged permanently. also, if the module operated w ith the absolute maximum ratings for a long time, its reliability may drop. note 2. if led current exceeds the limit curve, the l ifetime will drop dramatically. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 11/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3. electrical characteristics the following items are measured under stable condit ion and suggested application circuit. a. tft- lcd panel (gnd=0v) parameter symbol min typ max unit notes power supply vcc 2.8 3.3 3.6 v frame frequency f frame 60 hz 8 bits serial without dummy 15 24 dot data clock 8 bits serial with dummy dclk 20 32 mhz vi 0 0.2 x vddio v input signal voltage vi 0.8 x vddio vddio v vcom high voltage vcomh 3.3 6 v vcom low voltage vcoml -2.5 v current consumption ivcc 7 10 ma vcc= 3.3v b. backlight driving conditions parameter symbol min. typ. max. unit remark led supply current i l 20 22 ma single serial led supply voltage v l 18 21.6 v single serial led life time l l 10,000 --- --- hr note 2, 3 note 1: led backlight is six leds serial type. note 2: the led supply voltage is defined by the n umber of led at ta=25 ? c, i l =20ma. in the case of 6 pcs led, v l =3.2*6=19.2v note 3: the led life time is defined as the time for the module brightness to decrease to 50% of the initial value at ta=25 ? c, i l =20ma note 4: the led lifetime could be decreased if operat ing i l is larger than 20ma www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 12/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 4. ac timing a. display general information reset pulse width: characteristics symbol target min target typ target max units 8 bits serial without dummy - 15 24 dotclk frequency 8 bits serial with dummy f dotclk - 20 32 mhz 8 bits serial without dummy 42 67 - dotclk period 8 bits serial with dummy t dotclk 31 50 - nsec vertical sync. setup time t vsys 5 - - nsec vertical sync. hold time t vsyh 5 - - nsec horizontal sync. setup time t hsys 5 - - nsec horizontal sync. hold time t hsyh 5 - - nsec 8 bits serial without dummy t hv 0 - 960 t dotclk phase difference of sync. signal falling edge 8 bits serial with dummy t hv 0 1280 t dotclk dotclk low period t ckl 16 - - nsec dotclk high period t ckh 16 - - nsec data setup time t ds 10 - - nsec data hold time t dh 10 - - nsec reset pulse width t res 2.5 - - usec rise/fall time t r /t f 5 - 25 nsec note: hsyncs falling and clks rising cannot be con flicted. note: amplitude of input single is assumed to be eq ual to vddio (input digital voltage). www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 13/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. b. 8-bit serial interface table: 8-bit serial interface hv sync. mode without d ummy timing characteristics hv sync mode without dummy characteristics symbol min. typical max. units serial clock frequency 1/t dotclk 13 15 24 mhz one line period t h 975 1008 1023 t dotclk active data period t data 960 960 960 t dotclk horizontal back porch t hbp 10 24 24 t dotclk horizontal front porch t hfp 5 24 39 t dotclk horizontal hsyn. low polarity width 3 t dotclk one field period t v 244 244 391 t h active line period t al 240 240 240 t h vertical back porch t vbp 2 2 2 t h vertical front porch t vfp 2 2 149 t h vertical vsyn. low polarity width 3 t dotclk frame rate frequency 55 60 65 hz www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 14/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. table: 8-bit serial interface hv sync. mode with dumm y timing characteristics hv sync mode with dummy characteristics symbol min. typical max. units serial clock frequency 1/t dotclk 18 20 24 mhz one line period t h 1344 1344 1344 t dotclk active data period t data 1280 1280 1280 t dotclk horizontal back porch t hbp 32 32 32 t dotclk horizontal front porch t hfp 32 32 32 t dotclk horizontal hsyn. low polarity width 3 t dotclk one field period t v 244 244 275 t h active line period t al 240 240 240 t h vertical back porch t vbp 2 2 2 t h vertical front porch t vfp 2 2 33 t h vertical vsyn. low polarity width 3 t dotclk frame rate frequency 55 60 65 hz table: 8-bit serial interface den mode without dummy timing characteristics den mode without dummy characteristics symbol min. typical max. units serial clock frequency 1/t dotclk 13 15 24 mhz one line period t h 975 1008 1023 t dotclk active data period t data 960 960 960 t dotclk horizontal data enable period t den 960 960 960 t dotclk one field period t v 244 244 391 t h vertical active line period t al 240 240 240 t h frame rate frequency 55 60 65 hz table: 8-bit serial interface den mode with dummy ti ming characteristics den mode with dummy characteristics symbol min. typical max. units serial clock frequency 1/t dotclk 18 20 24 mhz one line period t h 1344 1344 1344 t dotclk horizontal active data period t data 1280 1280 1280 t dotclk auo confidential for eric internal use only / 2009/11/17 www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 15/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. data enable period t den 1280 1280 1280 t dotclk one field period t v 244 244 275 t h vertical active line period t al 240 240 240 t h frame rate frequency 55 60 65 hz www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 16/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. c. spi timing diagram write mode rw=0 tcss tcsh 0 tdh tds first transmission (register/dc=0) second transmission (data/dc=1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 1 1 0 0 dc rw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 0 1 1 1 rw dc 0 cs scl sdi sdi scl cs device id address device id data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d. spi timing specification item symbol conditions min typical max unit serial clock frequency tfclk 20 mhz serial clock cycle time tclk 50 nsec clock low width tsl 25 nsec clock high width tsh 25 nsec chip select set up time tcss 0 nsec chip select hold time tcsh 10 nsec chip select high delay time tcsd 20 nsec data set up time tds 5 nsec data hold time tdh 10 nsec www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 17/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 5. command register settings a. serial setting map reg# register * d/c ib15 ib14 ib13 ib12 ib11 ib10 ib09 ib08 ib07 ib06 ib05 ib04 ib03 ib02 ib01 ib00 r index 0 0 * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 driver output 0 1 0 0 * * * * tb rl 1 1 1 0 1 1 1 1 r01h (2aefh) 0 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 power control (1) 0 1 * * * * bt2 bt1 bt0 0 * * * * * * * 0 r03h (920eh) 1 0 0 1 0 0 1 0 0 0 0 0 1 1 1 0 power control (2) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vrc2 vrc1 vrc0 r0ch (0005h) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 power control (3) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 vrh3 vrh2 vrh1 vrh0 r0dh (000ch) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 power control (4) 0 1 0 0 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 0 0 0 0 0 r0eh (3100h) 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 uniformity 0 1 0 0 0 0 0 0 0 0 ensvin 1 0 1 1 1 0 0 r10h (00dch) 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 entry control 0 1 0 0 0 0 0 0 0 0 0 * * * ifs1 ifs0 0 0 r12h (0050h) 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 horizontal porch 0 1 xl8 xl7 xl6 xl5 xl4 xl3 xl2 xl1 xl0 0 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 r16h (9f86h) 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 vertical porch 0 1 0 0 0 0 0 0 0 0 vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 r17h (0002h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 power control (5) 0 1 0 0 0 0 0 0 0 0 notp 0 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 r1eh (00a4h) 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 control (1) 0 1 r30h (0304h) control (1) 0 1 r31h (0507h) control (1) 0 1 r32h (0405h) control (1) 0 1 r33h (0007h) control (1) 0 1 r34h (0507h) control (1) 0 1 r35h (0004h) the register setting of r30h ~ r3bh is adjusted after optical measurement under gamma 2.2 criteria. please refer to our recommended register settings for better performance. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 18/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. control (1) 0 1 r36h (0605h) control (1) 0 1 r37h (0103h) control (2) 0 1 r3ah (000fh) control (2) 0 1 r3bh (000fh) note: 1. * is for engineering reserved register setting , and please follow the suggested value. 2. the map shows the recommended values of the lcm, which should be written into the asic. however, r16h and r17h are showed default value. 3. please refer to our recommended register settings section for better performance. b. description of serial control data driver output 0 1 0 0 * * * * tb rl 1 1 1 0 1 1 1 1 r01h 2aef 0 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 tb: selects the vertical scanning direction of the display . when tb = 1, the scanning direction is from top to b ottom. when tb = 0, the scanning direction is from bottom t o top. rl: selects the horizontal scanning direction of the disp lay. when rl = 1, the scanning direction is from right to left. when rl = 0, the scanning direction is from left to right. note: 1. when the display surface is upward and the fpc gol den finger is toward the right, top, bottom, l eft and right are defined as in the picture below: 2. please refer to our recommended register setting s section for better performance. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 19/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. power control 0 1 * * * * bt2 bt1 bt0 0 * * * * * * * 0 r03h (920eh) 1 0 0 1 0 0 1 0 0 0 0 0 1 1 1 0 bt2-0: control the step-up factor of the step-up circuit. a djust the step-up factor according to the power-supply voltage to be used. bt2 bt1 bt0 v gh output v gl output v gh booster ratio v gl booster ratio 0 0 0 v cix2 x3 - v gh + vci 6 -5 0 0 1 v cix2 x3 - v gh + v cix2 6 -4 0 1 0 v cix2 x3 - v cix2 6 -2 0 1 1 v cix2 x2+vci - v gh 5 -5 1 0 0 v cix2 x2+vci - v gh + v cix2 5 -4 1 0 1 v cix2 x2+vci - v gh + v cix2 x2 5 -3 1 1 0 v cix2 x2 - v gh 4 -4 1 1 1 vcix2x2 - v gh +vci 4 -3 note: please refer to our recommended register sett ings section for better performance. frame control 0 1 0 0 0 0 eq1 eq0 0 0 eq2 0 0 0 0 0 0 0 r0bh (d800h) 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 eq[2:0]: sets the equalizing period on source eq2 eq1 eq0 eq period 0 0 0 no eq 0 0 1 24 pixel clock 0 1 0 42 pixel clock 0 1 1 after vcom charge sharing + 12 pixel clock cycle 1 0 0 64 pixel clock 1 0 1 80 pixel clock 1 1 0 96 pixel clock 1 1 1 106 pixel clock g(n) s(n) eq equalizing period www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 20/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. power control 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vrc2 vrc1 vrc0 r0ch (0005h) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 vrc[2:0]: adjust vcix2 output voltage. the adjusted level is in dicated in the chart below vrc2-0 setting. vrc2 vrc1 vrc0 v cix2 voltage 0 0 0 5.1v 0 0 1 5.3v 0 1 0 5.5v 0 1 1 5.7v 1 0 0 5.9v 1 0 1 6.1v 1 1 0 reserved 1 1 1 reserved note: please refer to our recommended register sett ings section for better performance. power control 0 1 0 0 0 0 0 0 0 0 0 0 0 0 vrh3 vrh2 vrh1 vrh0 r0dh (000ch) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 vrh3-0: set amplitude magnification of gamma reference volt age vlcd63. these bits amplify the vlcd63 voltage 1.78 to 3.00 times the vref voltage set by vrh3-0. vrh3 vrh2 vrh1 vrh0 v lcd63 voltage 0 0 0 0 vref x 2.815 0 0 0 1 vref x 2.905 0 0 1 0 vref x 3.000 0 0 1 1 vref x 1.780 0 1 0 0 vref x 1.850 0 1 0 1 vref x 1.930 0 1 1 0 vref x 2.020 0 1 1 1 vref x 2.090 1 0 0 0 vref x 2.165 1 0 0 1 vref x 2.245 1 0 1 0 vref x 2.335 1 0 1 1 vref x 2.400 1 1 0 0 vref x 2.500 1 1 0 1 vref x 2.570 1 1 1 0 vref x 2.645 1 1 1 1 vref x 2.725 note: please refer to our recommended register sett ings section for better performance. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 21/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. power control 0 1 0 0 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 0 0 0 0 0 r0eh (3100h) 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 vcomg: when vcomg = 1, it is possible to set output volta ge of vcoml to any level, and the instruction (vdv4-0) becomes available. when vcomg = 0, vcoml output is fixed to hi-z level, vci2 output for vcoml power supply stops, and the instruction (v dv4-0) becomes unavailable. set vcomg according to the sequence of power supply s etting flow as it relates with power supply operating sequence. vdv4-0: set the alternating amplitudes of vcom at the vcom alternating drive. these bits amplify vcom amplitude 0.6 to 1.23 times the vlcd63 voltage. when vcomg = 0, the settings become invalid. vdv4 vdv3 vdv2 vdv1 vdv0 vcoma 0 0 0 0 0 vlcd63 x 0.60 0 0 0 0 1 vlcd63 x 0.63 : : : step = 0.03 0 1 1 0 1 vlcd63 x 0.99 0 1 1 1 0 vlcd63 x 1.02 0 1 1 1 1 reserved 1 0 0 0 0 vlcd63 x 1.05 1 0 0 0 1 vlcd63 x 1.08 : : : step = 0.03 1 0 1 0 1 vlcd63 x 1.20 1 0 1 1 0 vlcd63 x 1.23 1 0 1 1 1 reserved 1 1 * * * reserved note: please refer to our recommended register sett ings section for better performance. uniformity 0 1 0 0 0 0 0 0 0 0 ensvin 1 0 1 1 1 0 0 r10h (00dch) 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 ensvin: when ensvin = 1, uniformity improvement scheme is e nabled. when ensvin = 0, uniformity improvement scheme is d isabled. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 22/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. entry mode 0 1 0 0 0 0 0 0 0 0 0 * * * ifs1 ifs0 0 0 r12h (0050h) 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 ifs1-0: selection for hv sync, den, with and withou t dummy modes. if1 if0 interface 0 0 8-bit serial rgb den mode (without dummy) 0 1 8-bit serial rgb den mode (with dummy) 1 0 8-bit serial rgb hv sync mode (without dummy) 1 1 8-bit serial rgb hv sync mode (with dummy) horizontal 0 1 xl8 xl7 xl6 xl5 xl4 xl3 xl2 xl1 xl0 0 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 r16h (9f86h) 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 xl7-0: set the number of valid pixel per line. xl8 xl7 xl6 xl5 xl4 xl3 xl2 xl1 xl0 # of pixels per line 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 1 0 3 : : : : step = 1 : 1 0 0 1 1 1 1 1 0 319 1 0 0 1 1 1 1 1 1 320 1 0 1 * * * * * * reserved 1 1 * * * * * * * reserved hbp5-0: set the delay period from falling edge of hsync sig nal to first valid data. the pixel data exceed the range set by xl8-0 and bef ore the first valid data will be treated as dummy data. # of clock cycle of dotclk hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 8-bit rgb (without dummy) 8-bit rgb (with dummy) 0 0 0 0 0 0 6 8 0 0 0 0 0 1 9 12 0 0 0 0 1 0 12 16 www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 23/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 0 0 0 0 1 1 15 20 0 0 0 1 0 0 18 24 0 0 0 1 0 1 21 28 0 0 0 1 1 0 24 32 : : : : step = 3 : : step = 4 : 1 1 1 1 1 0 192 256 1 1 1 1 1 1 195 260 example for 8-bit rgb interface (without dummy): example for 8-bit rgb interface (with dummy): www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 24/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. vertical porch 0 1 0 0 0 0 0 0 0 0 vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 r17h (0002h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 vbp7-0: set the delay period from falling edge of vsync to first valid line. the line data within this delay period will be trea ted as dummy line. vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 # of lines per frame 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 : : : : step = 1 : 1 1 1 0 1 1 1 1 239 1 1 1 1 0 0 0 0 240 1 1 1 1 * * * * reserved power 0 1 0 0 0 0 0 0 0 0 notp 0 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 r1eh (00a4h) 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 notp: notp equals to 0 after power on reset and vcomh v oltage equals to programmed otp value. when notp set to 1, setting of vcm5-0 becomes valid and voltage of vcomh can be adjusted. vcm5-0: set the vcomh voltage if notp = 1. these bits amp lify the vcomh voltage 0.36 to 0.99 times the vlcd63 voltage by step = 0.01. note: please refer to our recommended register sett ings section for better performance. control (1) r30h (0000h) r31h control (1) the register setting of r30h ~ r3bh is adjusted afte r optical measurement under gamma 2.2 criteria. please refer to our recommended registe r settings for better performance. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 25/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. (0200h) control (1) r32h (0001h) control (1) r33h (0700h) control (1) r34h (0405h) control (1) r35h (0202h) control (1) r36h (0707h) control (1) r37h (0006h) control (2) r3ah (0700h) control (2) r3bh (0003h) www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 26/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. f. optical specifications (note 1, 2) item symbol condition min. typ. max. unit remark response time rise fall tr tf =0 - - 10 15 20 25 ms ms note 3 contrast ratio cr at optimized viewing angle 150 300 - note 5, 6 viewing angle top bottom left right cr R 10 35 40 45 45 50 55 60 60 - - - - deg. note 7, 8 brightness y l =0 280 350 - cd/m 2 note 9 ntsc 50 60 % x =0 0.26 0.31 0.36 white chromaticity y =0 0.28 0.33 0.38 note 1: measurement should be performed in the dark room, optical ambient temperature =25 c, and backlight current i l =20 ma note 2: to be measured on the center area of panel with a field angle of 1by topcon luminance meter b m-7, after 10 minutes operation. note 3: definition of response time: the output signals of photo detector are measured w hen the input signals are changed from black to white(falling time) and from white to black (rising time), respectively. s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 10% 90% 100% note 4. from liquid crystal characteristics, response time will become slower and the color of panel will become darker when ambient temperature is below 25 ? c. note 5. contrast ratio is calculated with the follo wing formula. state black" " at is lcd n output whe detector photo state white" " at is lcd n output whe detector photo tio contrastra = www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 27/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. note 6. white vi=vi50 1.5v black vi=vi50 2.0v means that the analog input signal swings in phas e with com signal. means that the analog input signal swings out of p hase with com signal. vi50 :the analog input voltage when transmission is 50% the 100% transmission is defined as the transmissio n of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: refer to figur e as below. note 8. the viewing angles are measured at the cent er area of the panel when all the input terminals o f lcd panel are electrically opened. note 9. brightness is measured at the center point of the display area. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 28/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. g. touch screen panel specifications 1. electrical characteristics item min. max. unit remark rate dc voltage 7 v x (film) 350 950 resistance y (glass) 150 800 at connector linearity -1.5% 1.5% -- note 1, test by 250 gf chattering 10 ms at connector pin insulation resistance 10m dc 25v note 1: measurement condition of linearity: differe nce between actual voltage & theoretical voltage is an error at any points. linearity is the value max. error voltage divided by voltage difference on active area. 2. mechanical characteristics item min. max. unit remark hardness of surface 3 -- h jis k-5400 operation force (pen or finger) -- 100 gf note 1 note 1: within guaranteed active area, but not on the edge and dot-spacer. 3. life test condition item min. max. unit remark notes life 10 5 -- words note 1, 2 input life 10 6 -- times note 1, 3 note 1: measurement condition of operation force: w ithin guaranteed active area. resistance, www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 29/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. insulation resistance, and operation force should be under 5.2 & 5.3 condition. when user pushes down on the film, resistance between x & y axis must be equal or lower than 2k?. below is test figure. note 2: notes life test condition (by pen): notes ar ea for pen notes life test is 109 mm. size of word is 7.56.75mm. word is any a.b.c.. letter. writing spe ed is 60mm/s. center of each word is changed at random in notes area. note 3: input life test condition( by finger): by si licone rubber tapping at same point. tapping load is 200g, and tapping frequency is 5hz. 4. attention please pay attention for below matters at mounting design of touch panel of lcd module. 1. do not design enclosure pressing the view area t o prevent from miss input. 2. enclosure support must not touch with view area. 3. use elastic or non-conductive material to enclosure touch panel. 4. do not bond film of touch panel with enclosure. 5. the touch panel edge is conductive. do not touch it with any conductive part after mounting. 6. if user wants to cleaning touch panel by air gun, pressure 2kg/cm2 below is suggested. not to blow gla ss from fpc site to prevent fpc peeled off. 7. do not put a heavy shock or stress on touch panel and film surface. ex. dont lift the panel by film f ace with vacuum. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 30/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 8. do not lift lcd module by fpc. 9. please use dry cloth or soft cloth with neutral detergent (after wring dry) or one with ethanol at cleaning. do not use any organic solvent, acid or alkali liquor . 10. do not pile touch panel. do not put heavy goods on touch panel. recommendation of the cushion area: www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 31/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. h. reliability test items no. test items conditions remark 1 high temperature storage ta= 85 ? c 240hrs 2 low temperature storage ta= -30 ? c 240hrs 3 high temperature operation ta= 70 ? c 240hrs 4 low temperature operation ta= -20 ? c 240hrs 5 high temperature & high humidity ta= 60 ? c. 90% rh 240hrs operation 6 heat shock -25 ? c~70 ? c, 50 cycle, 2hrs/cycle non-operation 7 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz C6db/octave from 200~500hz iec 68-34 8 drop (with carton) height: 66cm 1 corner, 3 edges, 6 surfaces note 1: in the standard conditions, there is no dis play function ng issue occurred. all the cosmetic specification is judged before the reliability stres s. note 2: ta: ambient temperature. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 32/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. i. packing form model(a035qn02) a u o a u o a u o a u o a u o a u o a u o www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 33/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. j. application note 1. recommended register settings register setting r01 2aefh r03 920eh r0b dc80h r0c 0005h r0d 000ch r0e 3100h r10 00dch r12 0050h, which is set to be den mode and rgb without dummy data r16 r17 h/v blanking setting if necessary. r1e 00a4h r30 0304h r31 0507h r32 0405h r33 0007h r34 0507h r35 0004h r36 0605h r37 0103h r3a 000fh r3b 000fh note: 1. the different sequence of registers setting would not affect the normal behavior of lcm. 2. please refer to the power on/off sequence section f or register setting timing as power-on. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 34/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 2. power on/off sequence power on characteristics symbol min typ max unit vddio on to falling edge of shut tp-shut 1 - - usec dotclk tclk-shut 1 - - clk - - 10 frame falling edge of shut to display on -- 1 line: 336 clk -- 1frame: 244 line -- dotclk = 5.0 mhz tshut-on - 164 - msec note1: it is necessary to input dotclk before the fal ling edge of shut. note2: display starts at 10th falling edge of vstnc after the falling edge of shut www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 35/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. power off characteristics symbol min typ max unit 2 - 10 frame rising edge of shut to display off -- 1 line: 336 clk -- 1frame: 244 line -- dotclk = 5.0 mhz tshut-off 32.8 - - msec input-signal-off to v ddio off toff-vdd 1 - - usec note1: dotclk must be maintained at lease 2 frames after the rising edge of shut. note2: display become off at the 2nd falling edge of vstnc after the falling edge of shut. note3: if reset signal is necessary for power down, p rovide it after the 2-frames-cycle of the shut period. www.datasheet.co.kr datasheet pdf - http://www..net/
version 0.7 page: 36/36 all rights strictly reserved. any portion of this paper shall not b e reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3. suggested circuit the suggested circuit and recommended capacitor sepcif ication are both showed as follows. please refer to the design for better display quali ty. vgl cxn reset c2n vcc vcore csb vcc sdi scl den r7 vgh r6 c3p r5 r4 c3n r3 r2 r1 r0 hsy nc vcore cdmu0 csvcmp vcoml csvcmn vlcd63 vcomh vsy nc vcim cy n cy p cxn cxp c15 2.2uf /6.3v c14 2.2uf /6.3v c13 2.2uf /6.3v c12 2.2uf /10v c11 2.2uf /16v dclk c4 2.2uf /16v c7 0.22uf /16v c3 2.2uf /10v c2 2.2uf /10v c5 2.2uf /16v c1 2.2uf /6.3v c6 0.22uf /16v c16 2.2uf /6.3v c17 2.2uf /6.3v c8 0.22uf /16v c9 0.22uf /16v c10 0.22uf /16v led_c vlcd63 led_a led_c 1 led_a 2 nc 3 y 1 4 x1 5 y 2 6 x2 7 nc 8 vgh 9 c2p 10 c2n 11 c1p 12 c1n 13 vgl 14 c3n 15 c3p 16 vcix2 17 cy p 18 cy n 19 vci 20 gnd 21 vcim 22 cxp 23 cxn 24 reset 25 vddio 26 vcore 27 gnd 28 csb 29 sdi 30 sck 31 den 32 db7 33 db6 34 db5 35 db4 36 db3 37 db2 38 db1 39 db0 40 hsy nc 41 vsy nc 42 dotclk 43 nc 44 vlcd63 45 vcomh 46 vcoml 47 cdmu0 48 csvcmp 49 csvcmn 50 j1 50-pin connector(top contact) vcomh y 1 x1 vcoml y 2 c1p x2 c1n cdmu0 vgh c2p csvcmp c2n csvcmn c1p c1n vgl c3n vcix2 c3p vcix2 1 2 3 4 j2 con4 cy p cy n vcc c2p vcim cxp 1 2 r1 100kohm/1/4w www.datasheet.co.kr datasheet pdf - http://www..net/

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