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stmicroelectronics OS21 for arm user manual 8083358 rev c may 2008 www.st.com
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may 2008 8083358 rev c 1/14 user manual OS21 for arm introduction the api defined in the OS21 user manual (adcs 7358306) encapsulates the generic facilities offered by OS21 on all target pl atforms. however each processor implements certain features in different ways, and some processors offer facilities appropriate to their own specific api. arm specific apis can be accessed by a single #include : #include <OS21/arm.h> this include file is auto matically included from <OS21.h> when __arm__ is defined. the arm gcc compiler always defines __arm__; therefore #include is normally all that is necessary to include both the generic OS21 api and the arm specific api. www.st.com
contents OS21, arm 2/14 8083358 contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 document identification and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 conventions used in this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 memory access overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 timers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 input clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 OS21 tick duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 arm timer assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 board support packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 board support packages overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 bsp interrupt system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2.1 interrupt names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2.2 interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.3 interrupt controller base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2.4 interrupt controller slave priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2.5 interrupt controller initialization flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OS21, arm preface 8083358 3/14 preface document identification and control each book carries a unique adcs identifier of the form: adcs nnnnnnnx where nnnnnnn is the document number, and x is the revision. whenever making comments on a document, the complete identification adcs nnnnnnnx should be quoted. conventions used in this guide general notation the notation in this document uses the following conventions: sample code , keyboard input and file names , variables and code variables , code comments , screens , windows and dialog boxes, instructions . hardware notation the following conventions are used for hardware notation: register names and field names, pin names and signal names. software notation syntax definitions are presented in a modified backus-naur form (bnf). briefly: 1. terminal strings of the language, that is, strings not built up by rules of the language are printed in teletype font. for example, void . 2. nonterminal strings of the language, that is, strings built up by rules of the language are printed in italic teletype font. for example, name . 3. if a nonterminal string of the language starts with a nonitalicized part, it is equivalent to the same nonterminal string without that nonitalicized part. for example, vspace- name . 4. each phrase definition is built up using a double colon and an equals sign to separate the two sides (? ::= ?). 5. alternatives are separated by vertical bars (? | ?). 6. optional sequences are enclosed in square brackets (? [ ? and ? ] ?). 7. items which may be repeated appear in braces (? { ? and ? } ?). acknowledgements arm is a registered trademark of arm ltd.
memory access OS21, arm 4/14 8083358 1 memory access 1.1 memory access overview on all arm variants that are supported by OS21, memory regions can be given various characteristics such as cacheability and pr otection modes. these characteristics are controlled through an mmu. exact details of the mmu hardware can be found in the appropriate hardware manual. OS21 provides two areas of memory access support. cache support functions are available on all arm variants. details are given in the OS21 user manual (adcs 7358306). mmu support functions are available on all arm variants. these functions are provided using the virtual memory api. details are given in the OS21 user manual (adcs 7358306).
OS21, arm timers 8083358 5/14 2 timers 2.1 timers overview in order to run, OS21 requires at least three independent timers. each of these must be capable of running as a free running, auto-reload counter, with interrupt on underflow. each is programmed to count some fraction of the input clock. the greatest accuracy is obtained by counting based on a large fraction of the input clock, and running that clock at high frequency. 2.2 input clock frequency the precise speed of the input clock is determined by the end user; it is a function of the board design and boot software. OS21 is not responsible for setting the input speed, therefore it has to be made aware of what it is. this is done with the board support pa ckage (bsp) using a function called bsp_timer_input_clock_frequency_hz (). full details on how to use this function can be found in the OS21 user manual (adcs 7358306), chapter 16. 2.3 OS21 tick duration OS21 establishes the period of one tick when it boots. based on the input clock frequency it selects an appropriate divisor to yield a ti ck which is approximately 10 microseconds. 2.4 arm timer assignments how OS21 uses the arm timers depends upon the exact hardware available. ta bl e 1 shows an example of how the timers (four in this case) are assigned in a typical configuration. the system timer is left free running and is used by time_now() to return the system time. on arm platforms, the system time ( osclock_t ) is a 64-bit value. OS21 maintains the top 32 bits of the 64-bit time via an interrupt handler which is called each time the 32-bit timer reaches zero. the lower 32 bits of the system time are the value in the system timer. the timeslice timer is programmed to run for the timeslice period before generating an interrupt and reloading. this is used to drive timeslice events into the task scheduler. table 1. arm timer assignments timer name OS21 usage timer0 system timer timer1 timeslice timer timer2 timeout timer timer3 OS21 profiling timer
timers OS21, arm 6/14 8083358 the timeout timer is programmed on demand to interrupt when the required number of ticks have elapsed. when multiple timeouts are requested OS21 orders which timeout should occur next, and programs the timeout timer appropriately. when OS21 profiling is enabled, the profiling timer generates interrupts at regular intervals. the profiler samples the pc whenever this interrupt is fired.
OS21, arm register context 8083358 7/14 3 register context 3.1 registers overview the following registers are saved as part of each task's context. on all platforms: r0 to r12 r13 (stack pointer) r14 (link register) r15 (pc) cpsr (status register) on platforms with a vfp present: f0 to f31 fpinst2, fpinst, fpexc, fpscr (control and status registers) on platforms with interrupt levels: priority mask register
board support packages OS21, arm 8/14 8083358 4 board support packages 4.1 board support packages overview OS21 board support packages (bsps) are supplie d for all supported pl atforms as both pre- built libraries, and accompanying sources. the generic features of the bsps can be found in the OS21 user manual (adcs 7358306), chapter 16. this section describes the platform-specific feat ures of the bsp. for the arm, this consists of the interrupt system description. 4.2 bsp interrupt system description the bsp is responsible for describing the inte rrupt system to OS21. this coupled with the platform specific interrupt code implements OS21's generic interrupt api. on arm platforms, this comprises the following elements: interrupt names interrupt table interrupt controller base address interrupt controller slave priority interrupt system initialization flags and settings 4.2.1 interrupt names a type is provided by OS21 called interrupt_name_t . each interrupt is assigned a unique name ( interrupt_name_t ) which allows it to be identified both in the bsp interrupt tables that follow, and in the interrupt api. the bsp need only contain those interrupts that are used by other OS21 or the application code. if any interrupts are missing then a linker error occurs. if interrupts are declared in the bsp but are subsequently not used, then this d oes no harm other than use memory. for example: /* define a dma interrupt in the bsp */ interrupt_name_t OS21_interrupt_dma_0 = 21; header files are provided with OS21 which complement the interrupt description in the bsp. by including the appropriate header file, all the relevant external interrupt_name_t declarations are obtained. user code is also fr ee to declare only those interrupt names that it requires. for example: /* how to access the dma interrupt in user code */ extern interrupt_name_t OS21_interrupt_dma_0; the interrupt_handle() function takes an interrupt_name_t parameter and returns a handle to the given interrupt.
OS21, arm board support packages 8083358 9/14 4.2.2 interrupt table the interrupt table describes the interrupt system to the OS21 platform-specific interrupt api implementation code. on arm there is only one interrupt table. the format of the table depends upon whether or not interrupt priority levels are supported. interrupt table - no interrupt priority level support some arm platforms do not support interrupt levels (for example, stn8815). in this case each entry in the interrupt table has four fields, as follows: /* an entry in the interrupt table */ typedef struct interrupt_table_entry_s { interrupt_name_t * namep; unsigned int controller; unsigned int reg_set; unsigned int bit_set; } interrupt_table_entry_t; the table describes interrupts that are routed to specific interrupt controllers. namep is a pointer to the name of the interrupt. controller specifies the interrupt controller where the interrupt arrives (only OS21_ctrl_intc is supported on arm platforms). reg_set is the number of the register set to which the interrupt is routed. currently interrupts are routed to two registers on the interrupt controller; OS21 numbers these 0 or 1. bit_set is the bit number within this register. this table enables OS21 to locate an appropriate bit in the intc that maps to the named interrupt. for example: interrupt_name_t OS21_my_interrupt = 21; interrupt_table_entry_t my_interrupt = { &OS21_my_interrupt, OS21_ctrl_intc, 1, 15 }; this describes an interrupt called OS21_my_interrupt , which is routed into bit 15 of register set 1 on the interrupt controller OS21_ctrl_intc . interrupt_table_entry_t bsp_interrupt_table []; this describes the set of interrupts that arrive on the intc. it comprises a list of interrupt_table_entry_t types. for example: interrupt_table_entry_t bsp_interrupt_table [] = { { &OS21_interrupt_timer_0, OS21_ctrl_intc, 0, 0 }, { &OS21_interrupt_timer_1, OS21_ctrl_intc, 0, 1 }, { &OS21_interrupt_timer_2, OS21_ctrl_intc, 0, 2 }, { &OS21_interrupt_timer_3, OS21_ctrl_intc, 0, 3 } }; this describes a basic system with four timer interrupts. real systems are likely to be different to this.
board support packages OS21, arm 10/14 8083358 interrupt table - with interrupt priority level support for those arm platforms that do support interrupt levels (for example stn8820) each entry in the interrupt table has five entries: /* an entry in the interrupt table */ typedef struct interrupt_table_entry_s { interrupt_name_t * namep; unsigned int controller; unsigned int reg_set; unsigned int bit_set; unsigned int priority; } interrupt_table_entry_t; this table describes interrupts that are routed to the interrupt controllers. namep is a pointer to the name of the interrupt. controller specifies the interrupt controller where the interrupt is directed (only OS21_ctrl_intc is supported on arm platforms). reg_set is the number of the register set to which the interrupt is routed. currently interrupts are routed to two registers on the interrupt controller; OS21 numbers these 0 or 1. bit_set is the bit number within this register. priority is the priority or level of the given interrupt. OS21 implements 16 interrupt levels on arm platforms with level support. level 1 is assigned to the lowest priority level, level 16 to the highest. this is not necessarily the same as implemented in hardware. this table allows OS21 to locate an appropriate bit in the intc which maps to the named interrupt. for example: interrupt_name_t OS21_my_interrupt = 21; interrupt_table_entry_t my_interrupt = { &OS21_my_interrupt, OS21_ctrl_intc,1, 15, 4 }; this describes an interrupt called OS21_my_in terrupt which is routed into bit 15 of register set 1 on the interrupt controller OS21_ctrl_intc. the interrupt has a level of 4. interrupt_table_entry_t bsp_interrupt_table []; this describes the set of interrupts that arrive on the intc. it comprises a list of interrupt_table_entry_t types. for example: interrupt_table_entry_t bsp_interrupt_table [] = { { &OS21_interrupt_timer_0, OS21_ctrl_intc, 0, 0, 1 }, { &OS21_interrupt_timer_1, OS21_ctrl_intc, 0, 1, 2 }, { &OS21_interrupt_timer_2, OS21_ctrl_intc, 0, 2, 3 }, { &OS21_interrupt_timer_3, OS21_ctrl_intc, 0, 3, 4 } }; this describes a basic system with four timer interrupts. the four interrupts have different priorities, with timer 3 being the highest priority. real systems are likely to be different to this.
OS21, arm board support packages 8083358 11/14 4.2.3 interrupt controller base address this variable informs OS21 of the base address of the interrupt controller. for example: void * bsp_intc_base_address = (void *)(0x90410000); this tells OS21 the interrupt controller registers commence at address 0x90410000. 4.2.4 interrupt controller slave priority on platforms that support interrupt levels, and where slave controllers drive master controllers, this variable informs OS21 of the priority of the slave controller interrupts relative to the interrupts on the master. for example: unsigned int bsp_intc_slave_pri = 15; this says that all interrupts on the slave controller are given a priority of 15 into the master controller. note: this item is not required on platforms that do not support interrupt priority levels. 4.2.5 interrupt controller initialization flags interrupt_init_flags_t bsp_interrupt_init_flags; this is a set of flags that ar e used to control how OS21 init ializes the interrupt subsystem. these may be combined by logically oring the appropriate flags. the normal value on arm platforms is 0.
revision history OS21, arm 12/14 8083358 5 revision history table 2. document revision history date revision changes 9-may-2008 c moved mmu mappings description of the board support package to the OS21 user manual (adcs 7358306r) 13-nov-2007 b moved the generic description of the board support package to the OS21 user manual (adcs 7358306q) . 14-sep- 2007 a initial release.
OS21, arm index 8083358 13/14 index a access memory . . . . . . . . . . . . . . . . . . . . . . . . .4 arm specific api . . . . . . . . . . . . . . . . . . . . . . . .1 b backus-naur form . . . . . . . . . . . . . . . . . . . . . . .3 bsp interrupt system . . . . . . . . . . . . . . . . . . . . . . . .8 interrupt tables . . . . . . . . . . . . . . . . . . . . . . . .8 g gcc compiler . . . . . . . . . . . . . . . . . . . . . . . . . .1 i input clock determining speed . . . . . . . . . . . . . . . . . . . . . .5 interrupt controller base address . . . . . . . . . . .11 interrupt controller initialization flags . . . . . . . .11 interrupt controller slave priority . . . . . . . . . . . .11 interrupt names . . . . . . . . . . . . . . . . . . . . . . . . .8 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . .8 interrupt tables . . . . . . . . . . . . . . . . . . . . . . . . . .9 l linker error . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 m memory access . . . . . . . . . . . . . . . . . . . . . . . . .4 o OS21 profiler . . . . . . . . . . . . . . . . . . . . . . . . . . .5 OS21 tick duration . . . . . . . . . . . . . . . . . . . . . . .5 p profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 r register context . . . . . . . . . . . . . . . . . . . . . . . . . .7 t timeout timer . . . . . . . . . . . . . . . . . . . . . . . . . . .6 timer assignments . . . . . . . . . . . . . . . . . . . . . . . 5 timer0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timeslice timer . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OS21, arm 14/14 8083358 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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