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[ AK9720 ] rev.02 akm confidential 2012/11 - 1 - AK9720 (preliminary) ir sensor module with i2c i/f this specification is a design target, not guaranteed specifications for the final product. specifications are the subject to change without notice. d d e e s s c c r r i i p p t t i i o o n n the AK9720 is a slim and compact infrared-sensor module composed of a quantum ir sensor and an integrated circuit for characteristic compensation. the ic generates an analog signal that adjusts the infrared sensor?s offset and/or gain fluctuations and temperature characteristics. an integrated analog-to-digital converter provides a 16-bit data output. additional integrated features include a field of view limiter structure and an optical filter. the AK9720 enables new applications, including as remote temperature sensing, stationary human detection, and proximity detection. f f e e a a t t u u r r e e s s ? quantum-type ir sensor: ir1011 core ? low voltage operation v dd +1.71 to +3.63v digital i/f +1.65v to v dd ? low current consumption 100ua typ. @ 330ms sampling period ? 16bit-adc output to i 2 c bus ? digital output simplifies system integration ? fast response tbd ms @ sampling period ? selectable output: temperature compensated signal or bypass signal ? integrated temperature sensor output ? when the compensated signal is selected, the output has been adjusted for offset/gain variation and temperature sensitivity of ir sensors: => simplifies heat design => no host processing needed for temperature compensated output ? stationary human body detection algorithm available as reference software ? slim, compact package with field of view limiter structure and optical filter ? simplifies optical design ? linear output correlated to target temperature ? settings (including on/off control and sampling rate) programmed through i 2 c bus ? input level variations can be adjusted through a programmable gain stage ? int pin goes high when the adc output is ready to read ? can be used as read-trigger for single shot mode, or interrupt of signal level monitoring. ? integrated power-on reset, and oscillator ? 10pin son package
[ AK9720 ] rev.02 akm confidential 2012/11 - 2 - a a p p p p l l i i c c a a t t i i o o n n s s ? ? t t e e m m p p e e r r a a t t u u r r e e s s e e n n s s o o r r ? ? h h u u m m a a n n p p r r e e s s e e n n c c e e d d e e t t e e c c t t i i o o n n ? ? proximity detection ? ? m m o o t t i i o o n n s s e e n n s s o o r r ? ? e e t t c c ? ? r r e e c c o o m m m m e e n n d d e e d d c c o o n n n n e e c c t t i i o o n n
[ AK9720 ] rev.02 akm confidential 2012/11 - 3 - b b l l o o c c k k d d i i a a g g r r a a m m 1. block diagram 2. block functions block functions pd ir1011 ir sensor core i/v photocurrent of ir sensor is converted to voltage preamp programmable gain amplifier to adjust the output level. gain can also be adjusted by register settings. temperature compensation preamp output is compensated for the ambient temperature and linearized. temperature sensor built-in temperature sensor mux adc preamp output, linearized output, and built-in temperature sensor output are multiplexed prior to the adc. i 2 c interface interface to external host controller a flag is set when the measurement data is ready to be read. scl and sda pins are provided for i2c interface. the interface operates up to 400khz rate and down to 1.65v low voltage condition. eeprom eeprom. compensation data is stored in this non-volatile memory. osc internal oscillator por power on reset int pd tia preamp temperature sensor temperature compensation eeprom vss vdd dvdd i 2 c interface scl sda tout sout cad0 cad1 osc por mux/adc
[ AK9720 ] rev.02 akm confidential 2012/11 - 4 - p p i i n n / / l l o o c c a a t t i i o o n n s s p p i i n n / / f f u u n n c c t t i i o o n n s s pin no. name i/o function 1 tout o integrated temperature sensor analog output lpf can be formed by the output resistance and an external capacitor. 2 vdd - analog power supply pin 3 cad0 i slave address 0 cad should be connected to dvdd or vss. set up an address so that two or more same addresses of devices do not exist on the same bus. 4 cad1 i slave address 1 cad should be connected to dvdd or vss. set up an address so that two or more same addresses of devices do not exist on the same bus. 5 int o interrupt output ( ?h? active) function is selected by the interrupt pin select register (inten). int is high level, when read-out is ready or a target temperature is over upper limit or lower limit. 6 sda i/o i2c data output pin sda is a bidirectional pin which is used to transmit data into and out of the device. it is composed of a signal input and a open drain output (n-type transistor). sda is connected to the dvdd voltage through a pull-up resistance, and to open drain outputs or open collector outputs of the other devices as ?wire-ored?. 1 2 3 4 sout vdd scl dvdd vss 10 9 8 7 tout cad0 cad1 5 6 int sda
[ AK9720 ] rev.02 akm confidential 2012/11 - 5 - 7 scl i i2c clock input pin signal processing is executed at rising edge and falling edge of scl clock. therefore, observe rising time tr and falling time tf. 8 dvdd - digital i/f power supply pin 9 sout o analog signal output sout is preamp output or temperature compensated ir sensor output. sout should be connected to ?hi-z? input. lpf can be formed by the output resistance and an external capacitor. 10 vss - ground pin
[ AK9720 ] rev.02 akm confidential 2012/11 - 6 - d d i i g g i i t t a a l l / / a a n n a a l l o o g g o o u u t t p p u u t t s s e e l l e e c c t t f f u u n n c c t t i i o o n n digital/analog output select is controlled by cad1 pin and cad0 pin. when cad1 and cad0 are set up to cad1=cad0=1, the output of sout and tout are compulsorily set to ?on?, regardless of a setup of a register. sout outputs the temperature compensated analog signal. when cad1 and cad0 are set up so that they are not set up to cad1=cad0=1, digital signal can be used through i2c interface. when cad1 and cad0 are set up to cad1=cad0=1, although i2c interface can be accessed at a slave address 67h, the control by a register does not perform. when cad1 is set up to cad1=1, analog signal mode is selected, and on/off of output is selected by cad0. scl pin and sda pin should be fixed to high level. (don?t access to i2c interface in analog output mode.) if cad1 and cad0 are set up to cad1=cad0=1 at the time of power supply starting without using an i2c interface, and on/off of analog output is changed by cad0 after power supply starting, then analog output off is selected, AK9720 becomes power down mode, because ?mode[2:0] =000? is an initial value. cad1 cad0 digital output slave address analog output 0 0 enable 64h (off) 0 1 enable 65h (off) 1 0 enable 66h off 1 1 disabled (67h) on
[ AK9720 ] rev.02 akm confidential 2012/11 - 7 - a a b b s s o o l l u u t t e e m m a a x x i i m m u u m m r r a a t t i i n n g g parameter symbol min. typ. max. unit note power supply v sup -0.6 4.6 v input current i in -10 10 ma input voltage v in -0.6 v dd +0.6 and 4.6 v storage temperature t sto -40 85 ? c note) operation exceeding these ratings may cause permanent damage to device o o p p e e r r a a t t i i o o n n a a l l c c o o n n d d i i t t i i o o n n s s parameter symbol min. typ. max. unit note power supply v dd 1.71 3.0 3.6 v digital power supply dvdd 1.65 vdd v operating temperature ta -30 85 ? c
[ AK9720 ] rev.02 akm confidential 2012/11 - 8 - 0v psint1:300s psup1: 50ms port1: 300 s p ower d own mode v dd sdv1: 0.2 v power d own mode p p o o w w e e r r s s u u p p p p l l y y c c o o n n d d i i t t i i o o n n s s ac characteristics (1) parameter symbol min. typ. max. unit pin note power supply rise time psup1 50 ms vdd time until vdd pin is set to v dd from 0.2v *1 *2 power-on reset time port1 300 s time until AK9720 becomes power down mode after psup *1, *2 shutdown voltage sdv1 0.2 v vdd shutdown voltage for por re-starting *2 power supply interval time psint1 300 s vdd voltage retention time below sdv1 for por re-starting *1 *2 *1 reference data only, not tested *2 power-on reset circuit detects the rising edge of vdd, resets the internal circuit, and initializes the register. after power-on reset, power down mode is selected.
[ AK9720 ] rev.02 akm confidential 2012/11 - 9 - 0v psint2: 300s psup2: 50ms sdv2: 0.2 v dvdd ac characteristics (2) parameter symbol min. typ. max. unit pin note power supply rise time psup2 50 ms dvdd time until dvdd pin is set to dvdd from 0.2v *1 shutdown voltage sdv2 0.2 v dvdd shutdown voltage for power supply monitoring circuit re-starting power supply interval time psint2 300 s dvdd voltage retention time below sdv1 for power supply monitoring circuit re-starting *1 *1 reference data only, not tested
[ AK9720 ] rev.02 akm confidential 2012/11 - 10 - a a n n a a l l o o g g c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s unless otherwise specified, vdd = 1.71 to 3.63v, dvdd = 1.65v to vdd; ta = -30 to +85 normal mode selects linearized output for the adc. bypass mode selects preamp output. parameter symbol min. typ. max. unit note target temperature1 t obj 1 0 100 ? c t a = -30 ? c to 85 ? c normal mode target temperature2 t obj 2 0 40 ? c t a = 0 ? c to 60 ? c bypass mode preamp gain adjustment range tbd preamp gain adjustment accuracy 0.25 % for adjustment target ir output resolution 16 bits sout output code (sout ad code) -10 30 110 ? c normal mode, linear to target temperature (excludes noise) tbd tbd tbd code temperature output resolution 16 bits temperature sensor range -40 95 ? c tbd tbd code temperature sensor accuracy tbd ? c t a =30 ? c temperature sensor sensitivity tbd lsb/ ? c sout output resistance 1 0 k sout output resistance 1 0 k measurement time tbd ms single shot mode field of view 30 50% output (fwhm)
[ AK9720 ] rev.02 akm confidential 2012/11 - 11 - d d i i g g i i t t a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s 1) eeprom unless otherwise specified, vdd = 1.71 to 3.63v, dvdd = 1.65v to vdd; ta = -30 to +85 ? c item code min. typ. max. unit eeprom retention time @ta=85 ? c ehold 10 years 2) dc characteristics unless otherwise specified v dd = 1.71 to 3.63v, dvdd = 1.65 to v dd ; ta = -30 to +85 ? c parameter symbol conditions min. typ. max. unit note high level input voltage1 vih1 80%dvdd v cad1,cad0 low level input voltage1 vil1 20%dvd d v cad1,cad0 high level input voltage2 vih2 70%dvdd dvdd+0. 5 v scl,sda low level input voltage2 vil2 -0.5 30%dvd d v scl,sda hysteresis voltage (note) vhs dvdd>=2v 5%dvdd v scl,sda dvdd<2v 10%dvdd v scl,sda low level output voltage 1 vol1 iol = 3ma, dvdd >=2v - 0.4 v sda high level output voltage voh2 ioh = -200a 80%dvdd - v int low level output voltage 2 vol2 iol = 200a - 0.4 v int current consumption idd1 power down mode 55 a idd2 normal mode operation 1.3 ma idd3 bypass mode operation 1.0 ma averaged current consumption ( interval operation ) idd4 interval 1 normal mode 800 a min. interval (20ms) idd5 interval 2 normal mode 110 a max. interval (330ms) idd6 interval 1 bypass mode 560 a min. interval (20ms) idd7 interval 2 bypass mode 80 a max. interval (330ms) (note) reference data only, not tested
[ AK9720 ] rev.02 akm confidential 2012/11 - 12 - 3) digital ac characteristics (1) standard mode 100khz unless otherwise specified vdd = 1.71 to 3.63v, dvdd = 1.65 to vdd; ta = -30 to +85 ? c parameter code min. typ. max. unit scl frequency fscl 100 khz noise suppression time ti 50 ns sda bus idle time to the next command input tbuf 4.7 s start condition hold time thd:sta 4.0 s clock low period tlow 4.7 s clock high period thigh 4.0 s start condition set-up time tsu:sta 4.7 s data hold time thd:dat 0 s data setup time tsu:dat 250 ns rise time sda, scl note) tr 1.0 s fall time sda, scl note) tf 0.3 s stop condition setup time tsu:sto 4.0 s note) reference data only, not tested 4) digital ac characteristics (2) fast mode (400khz) unless otherwise specified, vdd = 1.71 to 3.63v, dvdd = 1.65 to vdd; ta = -30 to +85 ? c parameter code min. typ. max. unit scl frequency fscl 400 khz noise suppression time ti 50 ns sda bus idle time to the nest command input tbuf 1.3 s start condition hold time thd:sta 0.6 s clock low period tlow 1.3 s clock high period thigh 0.6 s start condition set-up time tsu:sta 0.6 s data in hold time thd:dat 0 s data in setup time tsu:dat 100 ns rise time sda, scl (note) tr 0.3 s fall time sda, scl (note) tf 0.3 s stop condition setup time tsu:sto 0.6 s note) reference data not tested
[ AK9720 ] rev.02 akm confidential 2012/11 - 13 - bus timing tbuf scl sda in sda out t su:sta t hd:dat thigh tlow thd:sta tsu:dat tf tr t su:sto tdh
[ AK9720 ] rev.02 akm confidential 2012/11 - 14 - f f u u n n c c t t i i o o n n a a l l d d e e s s c c r r i i p p t t i i o o n n s s 1. power supply state when v dd and dvdd turn on from the state of v dd = off (0v) and dvdd = off (0v), power on reset (por) is automatice all registers will be initialized, and the AK9720 will shift to power down mode. although all states of the following table can exist, the changes to state 3 from state 2 and the changes to state 2 from state 3 are prohibited. state v dd dvdd power supply state 1 off (0v) off(0v) off (0v) i2c bus is open. 2 off (0v) 1.65 to 3.63v off (0v) i2c bus is open. int pin = low level *this is not the recommended operational condition. 3 1.71 to 3.63v off(0v) off (0v). the current consumption is as same as power down mode. i2c bus is open. 4 1.71 to 3.63v 1.65v to v dd on 2. reset function when the power supply is in an on state, set up dvdd lower than v dd (dvdd<=v dd ) . power-on reset (por) works until v dd reaches the operating voltage (about 1.4v: design reference). after por, all registers are set to initial values, and power down mode is selected. when vdd is between 1.71v and 3.63v, por circuit and dvdd monitor circuit are operational. when dvdd=0v, the current consumption is identical to as reset state, because AK9720 is in reset state. AK9720 has three reset functions. (1) power-on reset (por) por circuit resets AK9720 by detecting vdd rising. (2)dvdd monitor when dvdd is in off (0v), AK9720 is reset. (3)soft reset when the srst bit is set, AK9720 is reset. when AK9720 is reset, all registers are set to initial values, and power down mode is selected.
[ AK9720 ] rev.02 akm confidential 2012/11 - 15 - 3. operating mode AK9720 has five operating modes as below. (1) power down mode (2) single shot mode (3) continuous mode1 (4) continuous mode2 (5) eeprom access mode operating mode can be selected by setting the mode [2:0] bit of cntl1 register. mode[2:0]=?001? mode[2:0]=?000? automatic shift mode[2:0]=?010? mode[2:0]=?000? mode[2:0]=?011? mode[2:0]=?000? mode[2:0]=?100? mode[2:0]=?000? digital mode cad1=1 cad1=0 and or cad0=1 cad0=0 power down mode continuous mode2 measurement is automatically repeated in an intermittent operation. power down mode is selected by setting mode[2:0] to?000? single shot mode measurement is done once, and power down mode is automatically selected after outputting the measurement data. eeprom access mode eeprom read-out circuit goes on. power down mode is selected by setting mode[2:0] to?000? continuous mode1 measurement is automatically repeated. power down mode is selected by setting mode[2:0] to?000? analog output mode regardless of the data in mode[2:0], mode status is masked to operation , and analog outputs are shown on sout,tout pins whatever stoben is. ( back from the analog output mode defined in mode[2:0] registers ) fig.1. operation mode when the power supply turns on, the AK9720 is in power down mode. according to mode[2:0] setup,, the AK9720 shifts to the selected mode, and starts operating. set the AK9720 to power down mode before changing this register setting.
[ AK9720 ] rev.02 akm confidential 2012/11 - 16 - 4. explanation for each operating mode 4.1 power down mode (mode [2:0] =?000?) power supply to most internal circuits is turned off. all registers can be accessed in power down mode. read/write register data are retained, and reset by software reset. however, eeprom data cannot be read. reading eeprom data must be done in eeprom access mode. 4.2 eeprom access mode (mode [2:0] =?100?) when mode [2:0] is changed from power down mode (mode [2:0] =?000?) to mode [2:0]=?100? , the AK9720 shifts to eeprom access mode. reading eeprom data should be done in eeprom access mode. measurement is not done in eeprom access mode. 4.3 single shot mode (mode [2:0] =?001?) when AK9720 is set to single shot mode (mode [2:0] =?001?), a measurement and signal processing are done, then the measurement data (irsl to tmph data) are stored to the measurement data registers, and the AK9720 shifts to power down mode automatically. when the AK9720 shifts to power down mode, mode [2:0] changes to ?000?. simultaneously, the drdy bit of st1 register changes to ?1?. this is called ?data ready?. if either the measurement data register (irsl to tmph) or st2 register is read out in ?data ready? state, the drdy bit changes to ?0?. when the AK9720 shifts from power down mode to other modes, the drdy bit retains ?1?. measurement data register retains previous data, within the measurement period. measurement data can be read out in the measurement period. when measurement data is read out in a measurement period, the previous data retained is read out. fig.2. single shot mode (when measurement data is read, out of the measurement period.) operating mode single measurement power down (1) (2) (3) measurement period measurement data register data(1) data(2) data(3) drdy read-out data data(1) data(3) st1 st2 st1 register write mode[2:0]="001" mode[2:0]="001" mode[2:0]="001"
[ AK9720 ] rev.02 akm confidential 2012/11 - 17 - operating mode single measurement power down (1) (2) (3) measurement period measurement data register data(1) data(2) data(3) drdy read-out data data(1) st1 st2 register write mode[2:0]="001" mode[2:0]="001" mode[2:0]="001" fig.3. single shot mode (when measurement data is read out within the measurement period.) 4.4 continuous measurement mode1 (mode [2:0] =?010?) when the AK9720 is set to continuous measurement mode1 (mode [2:0] =?010?), the measurement is automatically repeated. when a measurement and data processing have been done, the measurement data is stored to the measurement data register (irsl to tmph data), and the measurement is started again. measurement mode is finished by setting the AK9720 to power down mode (mode [2:0] =?000?). fig.4. continuous measurement mode1 (n-1) n (n+1) (n+2) (n+3) (n+4) measurement measurement measurement measurement measurement measurement
[ AK9720 ] rev.02 akm confidential 2012/11 - 18 - 4.5 continuous measurement mode2 (mode [2:0] =?011?) when the AK9720 is set to continuous measurement mode2 (mode [2:0] =?011?), the measurement is repeated according to the power down time ( tbd hz). when the measurement and data processing have been done, the measurement data is stored to the measurement data register (irsl to tmph data), and all circuits except those for the periodic measurement transition to stand-by(sb) state. the circuits that are in stand-by(sb) state are returned to active mode by detecting the next measurement time, and the measurement is started again. measurement mode is finished by setting the AK9720 to power down mode (mode [2:0] =?000?). (n-1) n (n+1) sb measurement sb measurement sb ( defined by ( defined by stb[2:0] ) frate[2:0] ) fig.5. continuous measurement mode2
[ AK9720 ] rev.02 akm confidential 2012/11 - 19 - 5. data ready when measurement data is stored to the measurement data registers, the drdy bit of the st1 register changes to ?1?. this state is called ?data ready?. it can be set up so that the int pin outputs "high", when the drdy bit is "1", by setting up the interruption register. read-out procedure is detailed here. (single shot mode is is used as an example.) the same procedure can also be applied to the continuous measurement mode1 and continuous measurement mode2. 5.1 normal read-out procedure (1) read-out st1 registers drdy: drdy shows whether the state is ?data ready? or not. drdy ="0" means ?no data ready?. drdy ="1" means ?data ready?. dor: dor shows whether there are any data which was not read out before initiating the current read. dor="0" means that there are no data which was not read out before initiating the current read. dor="1" means that there are data which was not read out before initiating the current read. (2) read the measurement data once a data read is initiated fromone of the measurement data registers (irsl to tmph) or the st2 register, the AK9720 recognizes that a data read-out has begun. when a data read-out is initiated, drdy and dor change to ?0?. (3) read st2 resisters (required operation) the AK9720 recognizes that a data read-out has finished by reading out the st2 registers. because the measurement data registers are protected while reading out, data is not updated. data protection of the measurement data register is canceled by reading out the st2 register. the st2 register must be read out after accessing the measurement data register. fig.6. normal read-out procedure (n-1) (n) (n+1) pd measurement pd measurement pd measurement data register data(n-1) data(n) data(n+1) drdy read-out data st1 data(n) st2 st1 data(n+1) st2
[ AK9720 ] rev.02 akm confidential 2012/11 - 20 - 5.2 read-out data within a measurement period the measurement data register is retained within a measurement period, so the data can be read out within the measurement period. when data is read out within the measurement period, the previous data retained is read out. fig.7. read-out data within a measurement period 5.3 skipping data when measurement data is not read out between the end points of (n+1) th and n th measurement, drdy is held the until measurement data is read out. in this case, because the n th data was skipped, the drdy bit is ?1?. (fig.8) when a data read begins after the end of the n th measurement, and when the data read cannot be completed until the end of the (n+1) th measurement, the measurement data registers are protected to read data normally. in this case, because the (n+1) th data has been skipped, the dor bit transitions to ?1?. (fig.9) in both of these cases, the dor bit changes to ?0? from ?1?, at the start of reading data if drdy is ?1?. fig.8. skipping data (n-1) (n) (n+1) pd measurement sd measurement sd measuremant data register data(n-1) data(n) drdy read-out data st1 data(n) st2 st1 data(n) st2 (n-1) (n) (n+1) pd measurement pd measurement pd measurement data registers data(n-1) data (n) data(n+1) drdy dor read-out data st1 data(n+1) st2
[ AK9720 ] rev.02 akm confidential 2012/11 - 21 - fig.9. when the data read cannot be completed until the beginning of the next measurement 5.4 end operation select power down mode (mode [2:0] =?000?) to complete the continuous measurement mode. (n-1) (n) (n+1) (n+2) pd measurement pd measurement pd measurement pd measurement data register data(n-1) data(n) data(n+2) data register is protected due to the reading drdy does not become "data ready", drdy becaus e data is not updated skip (n+1)th data dor read-out data st1 data(n) st2 st1 data(n+2)
[ AK9720 ] rev.02 akm confidential 2012/11 - 22 - s s e e r r i i a a l l i i n n t t e e r r f f a a c c e e the i 2 c bus interface of the AK9720 supports standard mode (max. 100khz) and high speed mode (max.400 khz). 1. data transfer initially, the start condition should be input to access the AK9720 through the bus. next, send a one byte slave address, which includes the device address. the the AK9720 compares the slave address, and if these addresses match, the AK9720 generates an acknowledge signal and executes a read/write instruction. the stop condition should be input after executing an instruction. 1.1 changing state of the sda line the sda line state should be changed only while the scl line is ?low?. the sda line state must be maintained while the scl line is ?high?. the sda line state can be changed while the scl line is ?high?, only when a start condition or a stop condition is input. fig.1. changing state of sda line 1.2 start/stop conditions a start condition is generated when the sda line state is changed from ?high? to ?low? while the scl line is ?high?. all instructions start from a start condition. a stop condition is generated when the sda line state is changed from ?low? to ?high? while the scl line is ?high?. all instructions end after a stop condition. fig.2. start/stop conditions scl sda constant changing state enable scl sda stop condition start condition
[ AK9720 ] rev.02 akm confidential 2012/11 - 23 - 1.3 acknowledge the device transmitting data will release the sda line after transmitting one byte of data (sda line state is ?high?). the device receiving data will pull the sda line to ?low? during the next clock. this operation is called ?acknowledge?. the acknowledge signal can be used to indicate successful data transfers. the AK9720 will output an acknowledge signal after receiving a start condition and the slave address. the AK9720 will output an acknowledge signal after receiving each byte, when the write instruction is transmitted. the AK9720 will transmit the data stored in the selected address after outputting an acknowledge signal, when a read instruction is transmitted. then the AK9720 will monitor the sda line after releasing the sda line. if the master device generates an acknowledge instead of a stop condition, the AK9720 transmits an 8-bit data stored in the next address. when the acknowledge is not generated, transmitting data is terminated. fig.3. acknowledge scl of mas ter device acknowledge data output of transmitter data output of receiver 1 9 8 start condition clocl pulse for acknowledge non-acknowledge
[ AK9720 ] rev.02 akm confidential 2012/11 - 24 - 1.4 slave address the slave address of the AK9720 can be selected from the following list by setting the cad0/1 pins. when the cad0/1 pins are connected to vss, the slave address bit is ?0?. when the cad0/1 pins are connected to dvdd, the slave address bit is ?1?. do not set up ?cad1=cad0=1? while the i2c interface is used, because the ?cad1=cad0=1? state is only for analog output mode. cad1 cad0 slave address 0 0 64h 0 1 65h 1 0 66h 1 1 analog output mode only table1. setting cad0/1 for slave address when the first one byte data including the slave address is transmitted after a start condition, the device, which is specified as the communicator by the slave address on the bus, is selected. after transmitting the slave address, the device that has the corresponding device address will execute a instruction after transmitting an acknowledge signal. the 8 th bit (least significant bit-lsb) of the first one byte is the r/w bit. when the r/w bit is set to ?1?, a read instruction is executed. when the r/w bit is set to ?0?, a write instruction is executed. msb lsb fig.4. slave address 1.5 write instruction when the r/w bit is set to ?0?, the AK9720 executes a write operation. the AK9720 will output an acknowledge signal and receive the second byte, after receiving a start condition and first one bit (slave address) in a write operation. the second byte has an msb-first configuration, and specifies the address of the internal control register. msb lsb a7 a6 a5 a4 a3 a2 a1 a0 fig.5. register address the AK9720 will generate an acknowledge and receive the third byte after receiving the second byte (register address). the data after the third byte is the control data. the control data consists of 8-bits and has an msb-first configuration. the AK9720 generates an acknowledge for each byte received. the data transfer is terminated by the stop condition, which is generated by the 1 1 0 0 1 cad1 cad0 r/w
[ AK9720 ] rev.02 akm confidential 2012/11 - 25 - master device. msb lsb d7 d6 d5 d4 d3 d2 d1 d0 fig.6. control data two or more bytes can be written to the AK9720 at once. the AK9720 generates an acknowledge and receives the next data after receiving the third byte (control data). when the following data is transmitted without a stop condition, after transmitting one byte, the internal address counter is automatically incremented, and data is written in the next address. the automatic increment function works in the address from 00h to 14h and the address from 15h to 18h. when the start address is ?00h?, the address is repeatedly incremented as follows: ?00h -> 01h -> ... -> 14h -> 00h -> 01h ...?. when the start address is ?15h?, the address is repeatedly incremented as follows: ?15h -> 16h -> ... -> 18h -> 15h -> 16h ...?. sda s t a r t a c k a c k s slave address a c k register address(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k a c k r/w=0 fig.7. write operation 2. read instruction when the r/w bit is set to ?1?, the AK9720 executes a read operation. when the AK9720 transmits the data from the specified address, and then the master device generates an acknowledge instead of a stop condition, the next address data can be read out. the AK9720 supports both current address read and random address read. the automatic increment function works in the address of 00h to 13h, and the address of 14h to 16h. when the address 13h is read out, the next address returns to 00h. when the address 16h is read out, the next address returns to 14h. 2.1 current address read the AK9720 has an integrated address counter. the data specified by the counter is read out in the current address read operation. the internal address counter retains the next address which is accessed at last. for example, when the address which was accessed last was ?n?, the data of address ?n+1? is read out by the current address read instruction. the AK9720 will generate an acknowledge after receiving a slave address for a read instruction (r/w bit =?1?) in the current address read operation. then, the AK9720 will start to transmit the data specified by the internal address counter at the next clock, and will increment the internal address counter by one. when the AK9720 generates a stop condition instead of an acknowledge after transmitting the one byte data, a read out operation is terminated.
[ AK9720 ] rev.02 akm confidential 2012/11 - 26 - sda s t a r t a c k a c k s slave address a c k data (n) data (n +1) p s t o p data (n+x) a c k data (n+2) a c k r/w= " 1 " fig.8. current address read 2.2 random read data from an arbitrary address can be read out by a random read operation. a random read requires the input of a dummy write instruction before the input of a slave address of a read instruction (r/w bit=?1?). to execute a random read, first generate a start condition, then input the slave address for a write instruction (r/w bit=?0?) and a read address, sequentially. after the AK9720 generates an acknowledge in response to this address input, generate a start condition and the slave address for a read instruction (r/w bit=?1?) again. the AK9720 generates an acknowledge in response to the input of this slave address. next, the AK9720 outputs the data at the specified address, then increments the internal address counter by one. when a stop condition from the master device is generated instead of an acknowledge after the AK9720 outputs data, the read operation stops. fig.9. random read sda s t a r t a c k a c k s slave address a c k register address (n) data (n) p s t o p data (n+x) a c k data (n+1) a c k r/w= " 0 " s t a r t a c k s slave address r/w= " 1 "
[ AK9720 ] rev.02 akm confidential 2012/11 - 27 - package information
[ AK9720 ] rev.02 akm confidential 2012/11 - 28 - spectrum sensitivity (reference) note) conditions; sensor temperature ts=25 ? c (298k), 1hz chopping
[ AK9720 ] rev.02 akm confidential 2012/11 - 29 - field of view (reference) item code min typ max unit remarks fov 30 50% output fwhm 0 0.2 0.4 0.6 0.8 1 1.2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 [degree] v s o u t / v m a x note) conditions: blackbody cavity: 227 ? c (500k), aperture diameter: 6.4mm, distance from sensor and blackbody cavity: 100mm, sensor temperature: ts=25 ? c (298k), 10hz chopping
[ AK9720 ] rev.02 akm confidential 2012/11 - 30 - a a p p p p l l i i c c a a t t i i o o n n n n o o t t e e s s 1 1 . . r r e e m m o o t t e e t t e e m m p p e e r r a a t t u u r r e e s s e e n n s s i i n n g g * * m m e e a a s s u u r r e e m m e e n n t t a a c c c c u u r r a a c c y y o o f f s s o o u u t t ( ( n n o o r r m m a a l l m m o o d d e e , , r r e e f f e e r r e e n n c c e e d d a a t t a a o o n n l l y y , , n n o o t t t t e e s s t t e e d d ) ) 3 3 ? c @ @ t t a a = = 0 0 c c t t o o 5 5 0 0 c c , , t t o o b b j j = = 2 2 0 0 c c t t o o 4 4 0 0 c c 5 5 ? c @ @ t t a a = = 0 0 c c t t o o 5 5 0 0 c c , , t t o o b b j j = = 0 0 c c t t o o 2 2 0 0 c c , , o o r r 4 4 0 0 c c t t o o 1 1 0 0 0 0 c c a a s s s s e e m m b b l l y y g g u u i i d d e e l l i i n n e e w w i i l l l l b b e e s s u u p p p p l l i i e e d d l l a a t t e e r r . . 2 2 . . s s t t a a t t i i o o n n a a r r y y h h u u m m a a n n b b o o d d y y d d e e t t e e c c t t i i o o n n * * d d e e t t e e c c t t i i o o n n a a l l g g o o r r i i t t h h m m r r e e f f e e r r e e n n c c e e s s o o f f t t w w a a r r e e i i s s a a v v a a i i l l a a b b l l e e b b y y r r e e q q u u e e s s t t 3 3 . . c c l l o o c c k k f f r r e e q q u u e e n n c c y y o o f f i i 2 2 c c i i n n t t e e r r f f a a c c e e ( ( r r e e f f e e r r e e n n c c e e ) ) w w h h e e n n t t h h e e c c l l o o c c k k f f r r e e q q u u e e n n c c y y o o f f t t h h e e i i 2 2 c c i i n n t t e e r r f f a a c c e e i i s s o o u u t t s s i i d d e e o o f f t t h h e e f f r r e e q q u u e e n n c c y y b b a a n n d d f f r r o o m m 3 3 3 3 3 3 . . 7 7 k k h h z z t t o o 4 4 0 0 0 0 k k h h z z , , n n o o i i s s e e m m a a y y i i n n c c r r e e a a s s e e . . 4 4 . . a a s s s s e e m m b b l l y y g g u u i i d d e e l l i i n n e e t t b b d d
[ AK9720 ] rev.02 akm confidential 2012/11 - 31 - important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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