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datasheet rl78/g10 renesas mcu true low power platform (as low as 46 a/mhz), 2.0 to 5.5v operation, 1 to 4 kbyte flash for general purpose applications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 1 of 32 r01ds0207ej0300 rev.3.00 nov 19, 2014 1. outline 1.1 features ultra-low power technology ? 2.0 to 5.5 v operation from a single supply ? stop (ram retained): 0.56 a ? operating: 46 a /mhz rl78-s1 core ? instruction execution: 78 % of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply: 8 x 8 to 16-bit result in 2 clock cycles ? 16-bit barrel shifter for shift & rotate in 2 clock cycle ? 1-wire on-chip debug function main flash memory ? density: 1 to 4 kbyte ? flash memory rewritable voltage: 4.5 to 5.5 v ram ? 128 to 512 byte size options ? supports operands or instructions ? back-up retention in all modes high-speed on-chip oscillator ? 20 mhz with +/-2 % accuracy over voltage (2.0 to 5.5 v) and temperature (-20 to +85c) ? pre-configured settings: 20 mhz, 10 mhz, 5 mhz, 2.5 mhz, and 1.25 mhz reset and supply management ? selectable power-on reset (spor) generator with 4 setting options multiple communication interfaces ? 1 x i 2 c master ? 1 x i 2 c multi-master (only for 16-pin product) ? 1 x uart (7-, 8-bit) ? up to 2 x csi/spi (7-, 8-bit) extended-function timers ? multi-function 16-bit timers: up to 4 channels ? interval timer: 12-bit, 1 channel (only for 16-pin product) ? 15 khz watchdog timer : 1 channel rich analog ? adc: up to 7 channels, 10-bit resolution, 3.4 s conversion time ? supports 2.4 v ? internal reference voltage (0.815 v (typ.)) ? comparator: 1 channel (only for 16-pin product) safety features ? detects execution of illegal instruction ? detects watchdog timer program loop general purpose i/o ? high-current (up to 20 ma per pin) ? open-drain, internal pull-up support external interrupt ? external interrupt input: up to 4 ? key interrupt input: 6 operating ambient temperature ? standard: -40 to +85c package type and pin count ? ssop: 10 and 16 pin
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 2 of 32 ? rom, ram capacities flash rom ram 10 pins 16 pins 4 kb 512 b r5f10y17 r5f10y47 2 kb 256 b r5f10y16 r5f10y46 1 kb 128 b r5f10y14 r5f10y44 note 16-pin products only remark the functions mounted de pend on the product. see 1.6 outline of functions .
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 3 of 32 1.2 list of part numbers figure 1-1. part number, memory size, and package of rl78/g10 part no. r 5 f 1 0 y 1 6 a s p #v0 package type: packaging style rom capacity: rl78/g10 group: 10y renesas mcu renesas semiconductor product sp: 10-pin, lssop, 0.65 mm pitch 16-pin, ssop, 0.65 mm pitch 4: 1 kb 6: 2 kb 7: 4 kb #v0: tray #x0: embossed tape #30: tray #50: embossed tape pin count: 1: 10-pin 4: 16-pin classification: a: consumer applications, operating ambient temperature : -40c to +85c d: industrial applications, operating ambient temperature : -40c to +85c memory type: f: flash memory table 1-1. list of ordering part numbers pin count package fields of application note 1 part number 10 pins 10-pin plastic lssop (4.4 ? note 2 r5f10y17dsp#30, r5f10y17dsp#50 r5f10y16dsp#v0, r5f10y16dsp#x0 r5f10y14dsp#v0, r5f10y14dsp#x0 16 pins 16-pin plastic ssop (4.4 ? note 2 r5f10y47dsp#30, r5f10y47dsp#50 r5f10y46dsp#30, r5f10y46dsp#50 r5f10y44dsp#30, r5f10y44dsp#50 (notes and caution are listed on the next page.)
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 4 of 32 notes 1. for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g10 . 2. under development caution the part number represents the number at the time of publication. be sure to review the latest part number through the target product page in the renesas electronics corp.website. 1.3 pin configuration (top view) 1.3.1 10-pin products ? 10-pin plastic lssop (4.4 3.6 mm, 0.65 mm pitch) 1 2 3 4 5 rl78/g10 (top view) 10 9 8 7 6 1 2 3 4 5 p04/ani3/ti01/to01/kr5 p03/ani2/to00/kr4/(intp1) p02/ani1/sck00/scl00/pclbuz0/kr3 p01/ani0/si00/rxd0/sda00/kr2 p00/so00/txd0/intp1 p40/kr0/tool0/(pclbuz0)/(ti01/to01) p125/kr1/reset p137/ti00/intp0 v ss v dd remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). see figure 4-6 format of peripheral i/o redirection register (pior) in the rl78/g10 user?s manual. 1.3.2 16-pin products ? 16-pin plastic ssop (4.4 5.0 mm, 0.65 mm pitch) 1 2 3 4 5 p41/ti03/intp2 p40/kr0/tool0/(pclbuz0)/(ti01/to01) p125/kr1/reset p137/ti00/intp0 p122/x2/exclk/(intp2) p121/x1/(intp3) v ss v dd 6 7 8 16 15 14 13 12 11 10 9 p07/sdaa0/to03/ani6/sck01 p06/scla0/intp3/ani5/si01 p05/ani4/ti02/to02/so01 p04/ani3/ti01/to01/kr5/ivref0 p03/ani2/to00/kr4/(intp1)/ivcmp0 p02/ani1/sck00/scl00/pclbuz0/kr3/vcout0 p01/ani0/si00/rxd0/sda00/kr2 p00/so00/txd0/intp1 rl78/g10 (top view) remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). see figure 4-6 format of peripheral i/o redirection register (pior) in the rl78/g10 user?s manual.
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 5 of 32 1.4 pin identification ani0 to ani6 : analog input intp0 to intp3 : interrupt request from peripheral kr0 to kr5 : key return p00 to p07 : port 0 p40, p41 : port 4 p121, p122, p125 : port 12 p137 : port 13 pclbuz0 : programmable clock output/ buzzer output exclk : external clock input x1, x2 : crystal oscillator (main system clock) ivcmp0 : comparator input vcout0 : comparator output ivref0 : comparator reference input reset : reset rxd0 : receive data sck00, sck01 : serial clock input/output scl00, scla0 : serial clock output sda00, sdaa0 : serial data input/output si00, si01 : serial data input so00, so01 : serial data output ti00 to ti03 : timer input to00 to to03 : timer output tool0 : data input/output for tool txd0 : transmit data v dd : power supply v ss : ground
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 6 of 32 1.5 block diagram 1.5.1 10-pin products port 0 p00 to p04 port 4 p40 port 12 p125 5 pclbuz0 clock generator + reset generator reset t ool0 sau0 (1 ch) ch01 ch00 tau0 (2 ch) uart0 on-chip debugger rl78-s1 interrupt control interrupt control 2 ch buzzer/clock output control key return 6 ch bcd adjustment selectable power-on- reset low-speed on-chip oscillator 15 khz high-speed on-chip oscillator 1.25 to 20 mhz iic00 csi00 scl00 sda00 rxd0 txd0 sck00 si00 so00 6 2 4 kr0 to kr5 intp0, intp1 ani0 to ani3 low-speed on-chip oscillator watchdog timer 8-/10-bit a/d converter 4 ch port 13 p137 ti00 /to00 ti01 /to01 ram 512 b code flash: 4 kb v dd v ss
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 7 of 32 1.5.2 16-pin products port 0 p00 to p07 port 4 port 12 p121, p122, p125 8 buzzer/clock output control pclbuz0 clock generator + reset generator reset tool0 bcd adjustment on-chip debugger high-speed on-chip oscillator 1.25 to 20 mhz low-speed on-chip oscillator 15 khz selectable power-on- reset sau0 (1 ch) uart0 iic00 scl00 sda00 rxd0 txd0 6 4 7 key return 6 ch kr0 to kr5 intp0 to intp3 ani0 to ani6 low-speed on-chip oscillator port 13 p137 8-/10-bit a/d converter 7 ch interrupt control 4 ch watchdog timer rl78-s1 interrupt control ram 512 b code flash: 4 kb v dd v ss p40, p41 2 3 x1 x2/exclk main osc 1 to 20 mhz iica0 scla0 sdaa0 comp ivcmp0 ivref0 vcout0 12-bit interval timer csi01 csi00 so01 si00 tau0 (4 ch) ch03 ch01 ch00 ch02 ti01 / to01 ti02 / to02 ti03 / to03 sck00 so00 si01 sck01 ti00 / to00
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 8 of 32 1.6 outline of functions this outline describes the fu nction at the time when peripheral i/o redi rection register (pior) is set to 00h. item 10-pin 16-pin r5f10y14 r5f10y16 r5f10y17 r5f10y44 r5f10y46 r5f10y47 code flash memory 1 kb 2 kb 4 kb 1 kb 2 kb 4 kb ram 128 b 256 b 512 b 128 b 256 b 512 b main system clock high-speed system clock ? x1, x2 (crystal/ceramic) oscillation, external main system clock input (exclk): 1 to 20 mhz: v dd = 2.7 to 5.5 v 1 to 5 mhz: v dd = 2.0 to 5.5 v note 3 high-speed on-chip oscillator clock ? 1.25 to 20 mhz (v dd = 2.7 to 5.5 v) ? 1.25 to 5 mhz (v dd = 2.0 to 5.5 v note 3 ) low-speed on-chip oscillator clock 15 khz (typ) general-purpose register 8-bit register ? 8 minimum instruction execution time 0.05 ? s (20 mhz operation) instruction set ? data transfer (8 bits) ? adder and subtractor/logical operation (8 bits) ? multiplication (8 bits ? 8 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 8 14 cmos i/o 6 (n-ch open-drain output (v dd tolerance): 2) 10 (n-ch open-drain output (v dd tolerance): 4) cmos input 2 4 timer 16-bit timer 2 channels 4 channels watchdog timer 1 channel 12-bit interval timer ? 1 channel timer output 2 channels (pwm output: 1) 4 channels (pwm outputs: 3 note 1 ) clock output/buzzer output 1 2.44 khz to 10 mhz: (peripheral hardware clock: f main = 20 mhz operation) comparator ? 1 8-/10-bit resolution a/d conv erter 4 channels 7 channels serial interface [10-pin prod ucts] csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel [16-pin products] csi: 2 channels/simplified i 2 c: 1 channel/uart: 1 channel i 2 c bus ? 1 channel vectored interrupt sources internal 8 14 external 3 5 key interrupt 6 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by selectable power-on-reset ? internal reset by illegal instruction execution note 2 ? internal reset by data retention lower limit voltage selectable power-on-reset circuit ? detection voltage rising edge (v spor ): 2.25 v/2.68 v/3.02 v/4.45 v (max.) falling edge (v spdr ): 2.20 v/2.62 v/2. 9 6 v/4.37 v (max.)
rl78/g10 1. outline r01ds0207ej0300 rev.3.00 nov 19, 2014 page 9 of 32 item 10-pin 16-pin r5f10y14 r5f10y16 r5f10y17 r5f10y44 r5f10y46 r5f10y47 on-chip debug function provided power supply voltage v dd = 2.0 to 5.5 v note 3 operating ambient temperature t a = - 40 to + 85 ? c notes 1. the number of outputs varies, depending on the setting of channels in use and t he number of the master (see 6.9.4 operation as multiple pwm output function in the rl78/g10 user?s manual). 2. the illegal instruction is generated when instruction co de ffh is executed. reset by the illegal instruction execution not issued by emulati on with the on-chip debug emulator. 3. use this product within the voltage range from 2.25 to 5.5 v because the detection voltage (v spor ) of the selectable power-on-reset (spor) circuit should also be considered.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 10 of 32 2. electrical specifications cautions 1. the rl78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug f unction in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and pr oduct reliability therefor e cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. the pins mounted depend on the product. refer to 2.1 port functions and 2.2.1 functions for each product in the rl78/g10 user?s manual. 3. use this product within the voltage range from 2.25 to 5.5 v because the detection voltage (v spor ) of the selectable power-on-reset (spor) circuit should also be considered.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 11 of 32 2.1 absolute maximum ratings (t a = 25 ? c) parameter symbols conditions ratings unit supply voltage v dd ? 0.5 to +6.5 v input voltage v i1 ?0.3 to v dd + 0.3 note v output voltage v o1 ?0.3 to v dd + 0.3 v output current, high i oh1 per pin ?40 ma total of all pins p40, p41 ?70 ma p00 to p07 ? 100 ma output current, low i ol1 per pin 40 ma total of all pins p40, p41 70 ma p00 to p07 100 ma operating ambient temperature t a ? 40 to +85 ? c storage temperature t stg ? 65 to +150 ? c note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remarks 1. unless specified otherwise, the characteristics of alternat e-function pins are the sa me as those of the port pins. 2. the reference voltage is v ss .
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 12 of 32 2.2 oscillator characteristics 2.2.1 x1 oscillato r characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 2.7 v ? v dd ? 5.5 v 1 20 mhz 2.0 v ? v dd < 2.7 v 1 5 mhz note indicates only permissible oscillator frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscilla tor circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator cloc k after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine th e oscillation stabilization time of the ostc register and the oscillation stabilization time select register (ost s) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator, refer to 5.4 system clock oscillator in the rl78/g10 user?s manual. 2.2.2 on-chip oscilla tor characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator oscillation clock frequency notes 1, 2 f ih 1.25 20 mhz high-speed on-chip oscillator oscillation clock frequency accuracy t a = -20 to +85 ? c -2.0 +2.0 % t a = -40 to -20 ? c -3.0 +3.0 % low-speed on-chip oscillator oscillation clock frequency f il 15 khz low-speed on-chip oscillator oscillation clock frequency accuracy -15 +15 % notes 1. high-speed on-chip oscillator frequency is select ed by bits 0 to 2 of option byte (000c2h). 2. this only indicates the oscillator characteristics. refe r to ac characteristics for instruction execution time.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 13 of 32 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for 10-pin products: p00 to p04, p40 16-pin products: p00 to p07, p40, p41 -10.0 note 2 ma total of 10-pin products: p40 16-pin products: p40, p41 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v -20.0 ma 2.7 v ? v dd ? 4.0 v -4.0 ma 2.0 v ? v dd ? 2.7 v -3.0 ma total of 10-pin products: p00 to p04 16-pin products: p00 to p07 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v -60.0 ma 2.7 v ? v dd ? 4.0 v -12.0 ma 2.0 v ? v dd ? 2.7 v -9.0 ma total of all pins (when duty ? 70% note 3 ) -80.0 ma output current, low note 4 i ol1 per pin for 10-pin products: p00 to p04, p40 16-pin products: p00 to p07, p40, p41 20.0 note 2 ma total of 10-pin products: p40 16-pin products: p40, p41 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v 40.0 ma 2.7 v ? v dd ? 4.0 v 6.0 ma 2.0 v ? v dd ? 2.7 v 1.2 ma total of 10-pin products: p00 to p04 16-pin products: p00 to p07 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v 80.0 ma 2.7 v ? v dd ? 4.0 v 12.0 ma 2.0 v ? v dd ? 2.7 v 2.4 ma total of all pins (when duty ? 70% note 3 ) 120.0 ma notes 1. value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. 2. do not exceed the total current value. 3. this is the output current value und er conditions where the duty factor ? 70%. the output current valu e when the duty factor ? 70% can be calculated with the following expression (when changing the duty factor to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80 % and i oh = - 10.0 ma total output current of pins = (- 10.0 0.7)/(80 0.01) ? - 8.7 ma ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80 % and i ol = 10.0 ma total output current of pins = (10.0 0.7)/(80 0.01) ? 8.7 ma however, the current that is allowed to flow in to one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. 4. value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to the v ss pin. caution p00, p01, p06, and p07 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characte ristics of alternate-function pins are the same as t hose of the port.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 14 of 32 (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 0.8 v dd v dd v input voltage, low v il1 0 0.2 v dd v output voltage, high note 1 v oh1 4.0 v ? v dd ? 5.5 v i oh = -10 ma v dd - 1.5 v i oh = -3.0 ma v dd - 0.7 v 2.7 v ? v dd ? 5.5 v i oh = -2.0 ma v dd - 0.6 v 2.0 v ? v dd ? 5.5 v i oh = -1.5 ma v dd - 0.5 v output voltage, low note 2 v ol1 4.0 v ? v dd ? 5.5 v i ol = 20 ma 1.3 v i ol = 8.5 ma 0.7 v 2.7 v ? v dd ? 5.5 v i ol = 3.0 ma 0.6 v i ol = 1.5 ma 0.4 v 2.0 v ? v dd ? 5.5 v i ol = 0.6 ma 0.4 v input leakage current, high i lih1 p00 to p07, p40, p41, p125, p137 v i = v dd 1 a i lih2 p121, p122 (x1, x2, exclk) v i = v dd in input port or external clock input 1 in resonator connection 10 input leakage current, low i lil1 p00 to p07, p40, p41, p125, p137 v i = v ss -1 a i lil2 p121, p122 (x1, x2, exclk) v i = v ss in input port or external clock input -1 in resonator connection -10 on-chip pull-up resistance r u v i = v ss 10 20 100 k ? notes 1. the value under the condition which sa tisfies the high-level output current (i oh1 ). 2. the value under the condition which sa tisfies the low-level output current (i ol1 ). caution the maximum value of v ih of p00, p01, p06, and p07 is v dd even in n-ch open-drain mode. p00, p01, p06, and p07 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characte ristics of alternate-function pins are the same as t hose of the port.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 15 of 32 2.3.2 supply current characteristics (1) flash rom: 1 and 2 kb of 10-pin products (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode basic operation f ih = 20 mhz v dd = 3.0 v, 5.0 v 0.91 ma normal operation f ih = 20 mhz v dd = 3.0 v, 5.0 v 1.57 2.04 f ih = 5 mhz v dd = 3.0 v, 5.0 v 0.85 1.15 i dd2 note 2 halt mode f ih = 20 mhz v dd = 3.0 v, 5.0 v 350 820 a f ih = 5 mhz v dd = 3.0 v, 5.0 v 290 600 i dd3 note 3 stop mode v dd = 3.0 v 0.56 2.00 a notes 1 . total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing in to the a/d converter, i/o port, and on-chip pull-up/pull-down resistors. 2. during halt instruction execution by flash memory. 3. not including the current flowing into the watchdog timer. remarks 1. f ih : high-speed on-chip oscillator clock frequency 2. temperature condition of the typical value is t a = 25 ?c
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 16 of 32 (2) flash rom: 4 kb of 10-pin products, and 16-pin products (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode basic operation f ih = 20 mhz note 4 v dd = 3.0 v, 5.0 v 0.92 ma normal operation f ih = 20 mhz note 4 v dd = 3.0 v, 5.0 v 1.59 2.14 f ih = 5 mhz note 4 v dd = 3.0 v, 5.0 v 0.87 1.20 f mx = 20 mhz notes 5, 6 v dd = 3.0 v, 5.0 v square wave input 1.43 1.93 resonator connection 1.54 2.13 f mx = 5 mhz notes 5, 6 v dd = 3.0 v, 5.0 v square wave input 0.67 1.02 resonator connection 0.72 1.12 i dd2 note 2 halt mode f ih = 20 mhz note 4 v dd = 3.0 v, 5.0 v 360 900 a f ih = 5 mhz note 4 v dd = 3.0 v, 5.0 v 310 660 f mx = 20 mhz notes 5, 6 v dd = 3.0 v, 5.0 v square wave input 200 700 resonator connection 300 900 f mx = 5 mhz notes 5, 6 v dd = 3.0 v, 5.0 v square wave input 100 440 resonator connection 150 540 i dd3 note 3 stop mode v dd = 3.0 v 0.61 2.25 a notes 1 . total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converte r, comparator (16-pin products only), i/o port, and on- chip pull-up/pull-down resistors. 2. during halt instruction execution by flash memory. 3. not including the current flowing into the 12-bit interval timer and watchdog timer. 4. when the high-speed system clock is stopped. 5. when the high-speed on-chip oscillator is stopped. 6. 16-pin products only remarks 1. f ih : high-speed on-chip oscillator clock frequency 2. f mx : high-speed system clock frequency (x1 clock oscillator frequency or external main system clock frequency) 3. temperature condition of the typical value is t a = 25 ?c
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 17 of 32 (3) peripheral functions (common to all products) (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-speed on- chip oscillator operating current i fil note 1 0.30 ? a 12-bit interval timer operating current i tmka notes 1, 2, 3 0.01 ? a watchdog timer operating current i wdt notes 1, 4 0.01 ? a a/d converter operating current i adc notes 1, 5 when conversion at maximum speed v dd = 5.0 v 1.30 1.90 ma v dd = 3.0 v 0.50 ma comparator operating current i cmp notes 1, 6 in high-speed mode v dd = 5.0 v 6.50 ? a in low-speed mode v dd = 5.0 v 1.70 ? a internal reference voltage operating current i vreg note 1 10 ? a notes 1. current flowing to v dd . 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the 12-bit interval timer (excl uding the operating current of the low-speed on-chip oscillator). the supply current of the rl78 microc ontrollers is the sum of the values of either i dd1, i dd2 or i dd3 and i fil and i tmka , when the 12-bit interval timer is in operation. 4. current flowing only to the watchdog timer (excluding the operating current of the low-speed on-chip oscillator). the supply current of the rl78 mi crocontrollers is the sum of i dd1 , i dd2 or i dd3 and i fil and i wdt when the watchdog timer is in operation. 5. current flowing only to the a/d converter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 6. current flowing only to the comparator. the supply current of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i cmp when the comparator is in operation. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. temperature condition of the typical value is t a = 25 ?c
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 18 of 32 2.4 ac characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy when high-speed on- chip oscillator clock (f ih ) is selected 2.7 v ? v dd ? 5.5 v 0.05 0.8 s ? 2.0 v ? v dd < 2.7 v 0.2 0.8 s ? when high-speed system clock (f mx ) is selected 2.7 v ? v dd ? 5.5 v 0.05 1.0 s ? 2.0 v ? v dd < 2.7 v 0.2 1.0 s ? external system clock frequency t ex 2.7 v ? v dd ? 5.5 v 1.0 20 mhz ? 2.0 v ? v dd < 2.7 v 1.0 5 mhz ? external system clock input high-level width, low-level width t exh , t exl 2.7 v ? v dd ? 5.5 v 24 ns ? 2.0 v ? v dd < 2.7 v 95 ns ? ti00 to ti03 input high-level width, low-level width t tih , t til noise filter is not used 1/f mck + 10 ns ? to00 to to03 output frequency f to 4.0 v ? v dd ? 5.5 v 10 mhz 2.7 v ? v dd ? 4.0 v 5 mhz 2.0 v ? v dd ? 2.7 v 2.5 mhz pclbuz0 output frequency f pcl 4.0 v ? v dd ? 5.5 v 10 mhz 2.7 v ? v dd ? 4.0 v 5 mhz 2.0 v ? v dd ? 2.7 v 2.5 mhz reset low-level width t rsl 10 s ? remark f mck : timer array unit operation clock frequency (operation clock to be set by the timer clock select register 0 (tps0) and the cks0n1 bit of timer mode register 0nh (tmr0nh). n: channel number (n = 0 to 3))
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 19 of 32 minimum instruction execution time during main system clock operation 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 0.05 0.2 0.8 cycle time t cy [s] when the high-speed on-chip oscillator clock is selected when the high-speed system clock is selected supply voltage v dd [v] t cy vs v dd ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol external system clock timing exclk 1/f ex t exl t exh
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 20 of 32 ti/to timing ti00 to ti03 t til t tih to00 to to03 1/f to reset input timing reset t rsl
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 21 of 32 2.5 serial interface characteristics ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol 2.5.1 serial array unit (1) uart mode (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate f mck /6 bps theoretical value of the maximum transfer rate f clk = f mck = 20 mhz 3.3 mbps uart mode connection diagram user's device txd0 rxd0 rx tx rl78 microcontroller uart mode bit width (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txd0 rx d 0 remark f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register 0 (sps0) and the cks0n bit of the serial mode register 0nh (smr0nh). n: channel number (n = 0, 1))
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 22 of 32 (2) csi mode (master mode, sckp... internal clock output) (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 t kcy1 ? 4/f clk 2.7 v ? v dd ? 5.5 v 200 ns 2.0 v ? v dd ? 5.5 v 800 ns sckp high-/low-level width t kh1 , t kl1 2.7 v ? v dd ? 5.5 v t kcy1 /2 - 18 ns 2.0 v ? v dd ? 5.5 v t kcy1 /2 - 50 ns sip setup time (to sckp ? ) note 1 t sik1 2.7 v ? v dd ? 5.5 v 47 ns 2.0 v ? v dd ? 5.5 v 110 ns sip hold time (from sckp ? ) note 1 t ksi1 19 ns delay time from sckp ? to sop output note 2 t kso1 c = 30 pf note 3 25 ns notes 1. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ck p0n = 1. the sip setup time becomes ?to sckp ? ? and sip hold time becomes ?from sckp ? ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the delay time to sop output becomes ?from sckp ? ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 3. c is the load capacitance of the sckp and sop output lines. (3) csi mode (slave mode, sckp... external clock input) (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy2 2.7 v ? v dd ? 5.5 v f mck > 16 mhz 8/f mck ns f mck ? 16 mhz 6/f mck ns 2.0 v ? v dd ? 5.5 v 6/f mck ns sckp high-/low-level width t kh2 , t kl2 2.0 v ? v dd ? 5.5 v t kcy2 / 2 - 18 ns sip setup time (to sckp ? ) note 1 t sik2 2.7 v ? v dd ? 5.5 v 1/f mck + 20 ns 2.0 v ? v dd ? 5.5 v 1/f mck + 30 ns sip hold time (from sckp ? ) note 1 t ksi2 2.0 v ? v dd ? 5.5 v 1/f mck + 31 ns delay time from sckp ? to sop output note 2 t kso2 c = 30 pf note 3 2.7 v ? v dd ? 5.5 v 2/f mck + 50 ns 2.0 v ? v dd ? 5.5 v 2/f mck + 110 ns notes 1. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ck p0n = 1. the sip setup time becomes ?to sckp ? ? and the sip hold time becomes ?from sckp ? ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the delay time to sop output becomes ?from sckp ? ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 3. c is the load capacitance of the sop output lines. remarks 1. p: csi number (p = 00, 01), n: channel number (n = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register 0 (sps0) and the cks0n bit of the serial mode register 0nh (smr0nh). n: channel number (n = 0, 1))
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 23 of 32 csi mode connection diagram rl78 microcontroller sck00 so00 sck si user's device si00 so csi mode serial transfer timing (when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1.) si00 input data output data so00 t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sck00 remark p: csi number (p = 00, 01), n: channel number (n = 0, 1)
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 24 of 32 (4) simplified i 2 c mode (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit sclr clock frequency f scl c b = 100 pf, r b = 3 k ? 400 note 1 khz hold time when sclr = "l" t low c b = 100 pf, r b = 3 k ? 1150 ns hold time when sclr = "h" t high c b = 100 pf, r b = 3 k ? 1150 ns data setup time (reception) t su: dat c b = 100 pf, r b = 3 k ? 1/f mck + 145 note 2 ns data hold time (transmission) t hd: dat c b = 100 pf, r b = 3 k ? 0 355 ns notes 1. the value must also be equal to or less than f mck /4. 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the n-ch open drain output (v dd tolerance) mode for the sdar pin by using the port output mode register 0 (pom0). simplified i 2 c mode connection diagram sda00 scl00 sda scl v b r b user's device rl78 microcontroller simplified i 2 c mode serial transfer timing sda00 t low t high t hd:dat scl00 t su:dat 1/f scl remarks 1. r b [? ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sclr, sdar) load capacitance 2. r: iic number (r = 00) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register 0 (sps0) and the cks0n bit of the serial mode register 0nh (smr0nh). n: channel number (n = 0))
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 25 of 32 2.5.2 serial interface iica (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions standard mode fast mode unit min. max. min. max. scla0 clock frequency f scl fast mode: f clk ? 3.5 mhz 0 400 khz standard mode: f clk ? 1 mhz 0 100 khz setup time of restart condition t su:sta 4.7 0.6 ? s hold time note 1 t hd:sta 4.0 0.6 ? s hold time when scla0 = ?l? t low 4.7 1.3 ? s hold time when scla0 = ?h? t high 4.0 0.6 ? s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 ? s setup time of stop condition t su:sto 4.0 0.6 ? s bus-free time t buf 4.7 1.3 ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark the maximum value of cb (communication line capacit ance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k ? fast mode: c b = 200 pf, r b = 1.7 k ?? ? iica serial transfer timing t low t r t buf t high t f t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:st o t hd:sta t hd:dat scla0 sdaa0
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 26 of 32 2.6 analog characteristics 2.6.1 a/d converter characteristics (target pin: ani0 to ani6, internal reference voltage) (t a = ? 40 to +85 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error notes 1, 2, 3 ainl 10-bit resolution v dd = 5 v ? 1.7 ?3.1 lsb v dd = 3 v ? 2.3 ?4.5 lsb conversion time t conv 10-bit resolution target pin: ani0 to ani6 2.7 v ? v dd ? 5.5 v 3.4 18.4 s ? 2.4 v ? v dd ? 5.5 v note 5 4.6 18.4 s ? 10-bit resolution target pin: internal reference voltage note 6 2.4 v ? v dd ? 5.5 v 4.6 18.4 s ? zero-scale error notes 1, 2, 3, 4 e zs 10-bit resolution v dd = 5 v ? 0.19 %fsr v dd = 3 v ? 0.39 %fsr full-scale error notes 1, 2, 3, 4 e fs 10-bit resolution v dd = 5 v ? 0.29 %fsr v dd = 3 v ? 0.42 %fsr integral linearity error notes 1, 2, 3 ile 10-bit resolution v dd = 5 v ? 1.8 lsb v dd = 3 v ? 1.7 lsb differential linearity error notes 1, 2, 3 dle 10-bit resolution v dd = 5 v ? 1.4 lsb v dd = 3 v ? 1.5 lsb analog input voltage v ain target pin: ani0 to ani6 0 v dd v target pin: internal reference voltage note 6 v reg note 7 v notes 1. typ. value is the average value at t a = 25 ? c. max. value is the average value ? 3 at normal distribution. 2. these values are the results of characteristic evaluation and are not checked for shipment. 3. excludes quantization error ( ? 1/2 lsb). 4. this value is indicated as a ratio (%fsr) to the full-scale value. 5. set the lv0 bit in the a/d converte r mode register 0 (adm0) to 0 when conversion is done in the operating voltage range of 2.4 v v dd < 2.7 v. 6. set the lv0 bit in the a/d converter mode register 0 (adm0) to 0 when the internal reference voltage is selected as the target for conversion. 7. refer to 2.6.3 internal reference voltage characteristics . cautions 1. arrange wiring and insert the capacitor so that no noise appears on the power supply/ground line. 2. do not allow any pulses that rapidly change such as digital signals to be input/output to/from the pins adjacent to the conversion pin during a/d conversion. 3. note that the internal reference voltage cannot be used as the reference voltage of the comparator when the internal reference voltage is selected as the target for a/d conversion.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 27 of 32 2.6.2 comparator characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage range i vref ivref0 pin input (when c0vfr bit = 0) 0 v dd - 1.4 v internal reference voltage (when c0vrf bit = 1) note 1 v reg note 2 v i vcmp ivcmp0 pin input -0.3 v dd + 0.3 v output delay t d v dd = 3.0 v, input slew rate > 50 mv/s high-speed mode 0.5 s low-speed mode 2.0 s operation stabilization wait time t cmp 100 s notes 1. when the internal reference voltage is selected as t he reference voltage of the comparator, the internal reference voltage cannot be used as the target for a/d conversion. 2. refer to 2.6.3 internal reference voltage characteristics . 2.6.3 internal reference voltage characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit internal reference voltage v reg 0.74 0.815 0.89 v operation stabilization wait time t amp when a/d converter is used (ads register = 07h) 5 s note the internal reference voltage cannot be simultaneously used by the a/d converter and the comparator; only one of them must be selected.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 28 of 32 2.6.4 spor circuit characteristics (t a = ? 40 to +85 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage power supply voltage level v spor0 power supply rise time 4.08 4.28 4.45 v power supply fall time 4.00 4.20 4.37 v v spor1 power supply rise time 2.76 2.90 3.02 v power supply fall time 2.70 2.84 2.96 v v spor2 power supply rise time 2.44 2.57 2.68 v power supply fall time 2.40 2.52 2.62 v v spor3 power supply rise time 2.05 2.16 2.25 v power supply fall time 2.00 2.11 2.20 v minimum pulse width note t lspw 300 s note time required for the reset operation by the spor when v dd becomes under v spor . caution set the detection voltage (v spor ) in the operating voltage range. the operating voltage range depends on the setting of the user option byte (000c2h). the operating voltage range is as follows: when the cpu operating frequenc y is from 1 mhz to 20 mhz: v dd = 2.7 to 5.5 v when the cpu operating frequenc y is from 1 mhz to 5 mhz: v dd = 2.0 to 5.5 v 2.6.5 power supply voltage rising slope characteristics (t a = ? 40 to +85 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms 2.7 ram data retention characteristics (t a = ? 40 to +85 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.9 5.5 v caution data in ram is retained until the power supply voltage becomes under the minimum value of the data retention power supply voltage (v dddr ). note that data in the resf register might not be cleared even if the power supply voltage becomes under the minimum value of the data retention power supply voltage (v dddr ). stop mode stop instruction execution spor reset period normal operation (retain data in ram and resf) v dd v dddr rising of v spor falling of v spdr
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 29 of 32 2.8 flash memory programming characteristics (t a = 0 to + 40 ? c, 4.5 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit code flash memory rewritable times notes 1, 2, 3 c erwr retained for 20 years. t a = +85 ? c 1000 times notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer. 3. these are the characteristics of the flash memory and the results obt ained from reliability testing by renesas electronics corporation. 2.9 dedicated flash memory programmer communication (uart) (t a = 0 to + 40 ? c, 4.5 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate 115,200 bps remark the transfer rate during flash memory programming is fixed to 115,200 bps.
rl78/g10 2. elec trical specifications r01ds0207ej0300 rev.3.00 nov 19, 2014 page 30 of 32 2.10 timing of entry to flash memory programming modes parameter symbol conditions min. typ. max. unit time to complete the communication for the initial setting after the external reset is released t suinit spor reset must be released before the external reset is released. 100 ms time to release the external reset after the tool0 pin is set to the low level t su spor reset must be released before the external reset is released. 10 s ? time to hold the tool0 pin at the low level after the external reset is released t hd spor reset must be released before the external reset is released. 1 ms reset tool0 <1> <2> <3 > t suinit t hd t su <4> 1-byte data for mode setting <1> the low level is input to the tool0 pin. <2> the external reset is released (spor reset must be released before the external reset is released.). <3> the tool0 pin is set to the high level. <4> setting of entry to the flash memory programming mode by uart reception is completed. remark t suinit : communication for the init ial setting must be completed within 100 ms after the external reset is released during this period. t su : time to release the exte rnal reset after the tool0 pi n is set to the low level t hd : time to hold the tool0 pin at the low level after the external reset is released
rl78/g10 3. package drawings r01ds0207ej0300 rev.3.00 nov 19, 2014 page 31 of 32 3. package drawings 3.1 10-pin products r5f10y17asp, r5f10y16asp, r5f10y14asp r5f10y17dsp note , r5f10y16dsp note , r5f10y14dsp note jeita package code renesas code p10ma-65-cac-2 6 10 1 v detail of lead end item dimensions a b c e f g h i j l m n d + 0.08 0.07 1.45 max. 0.50 0.13 0.10 k 0.17 p 3 + 5 3 (unit:mm) v w w a i f g e b k h j p u l t u v 0.25 max. w 0.15 max. 5 s c s n m d m t 2012 renesas electronics corporation. all rights reserved. note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 3.60 0.10 0.08 0.24 0.05 0.10 0.10 1.20 0.20 6.40 0.20 1.00 0.10 4.40 0.60 0.15 0.25 (t.p.) 0.65 (t.p.) 0.50 mass (typ.) [g] previous code plsp0010ja-a 0.05 p-lssop10-4.4x3.6-0.65 ? ? note under development
rl78/g10 3. package drawings r01ds0207ej0300 rev.3.00 nov 19, 2014 page 32 of 32 3.2 16-pin products r5f10y47asp, r5f10y46asp, r5f10y44asp r5f10y47dsp note , r5f10y46dsp note , r5f10y44dsp note jeita package code renesas code previous code mass(typ.)[g] p-ssop16-4.4x5-0.65 prsp0016jc-b p16ma-65-fab-1 0.08 d a b h 0.65 0.14 5.00 4.40 0.13 referance symbol min nom max dimension in millimeters 1.725 0.17 0.32 a 0.22 b a 0.24 c 0.20 c 0 0.175 0.17 z l 1 1 e d 1 e 0.125 0.15 1.00 4.85 5.15 4.60 4.20 2 1.50 1 8 6.20 6.40 6.60 e terminal cross section b p b 1 c c 1 0.075 16 1 8 s s detail of lead end a a a e y c z 9 m b x s e d d l a b d 5.20 5.05 5.35 x y 0.225 0.50 l 0.10 a b d p 2 h e l 1 1 0.35 0.65 1 1 p index mark note under development
c - 1 revision history rl78/g10 datasheet rev. date description page summary 1.00 apr 15, 2013 - first edition issued 2.00 jan 10, 2014 1, 2 modificati on of descriptions in 1.1 features 3 modification of description in 1.2 list of part numbers 4 modification of remark 2 in 1.3.1 10- pin products and 1.3.2 16-pin products 8, 9 addition of description of r5f 10y17asp in 1.6 outline of functions 11 modification of description in 2.1 absolute maximum ratings 12 modification of description in 2.2 oscillator characteristics 13, 14 modification of description, not es 1 to 4, and caution in 2.3.1 pin characteristics 16 addition of description, notes 1 to 6, and remarks 1 and 2 in (2) flash rom: 4 kb of 10-pin products, and 16-pin products 17 addition of description, notes 1 to 6, and remarks 1 to 3 in (3) peripheral functions (common to all products) 18 modification of description in 2.4 ac characteristics 19 addition of figure of minimum instru ction execution time during main system clock operation 19 addition of figure of external system clock timing 20 modification of ti/to timing 25 addition of description in 2.5.2 serial interface iica 26 modification of description and not es 1 to 6 in 2.6.1 a/d converter characteristics 27 addition of description, notes 1 and 2 in 2.6.2 comparator characteristics 27 addition of description and note in 2.6.3 internal reference voltage characteristics 28 addition of caution in 2.6.4 spor circuit characteristics 28 addition of figure in 2.6.6 data ret ention power supply voltage characteristics 31 addition of r5 f10y17asp in 3.1 10-pin products 32 modification of package drawing in 3.2 16-pin products 3.00 nov 19, 2014 3 addition of industrial applic ations in figure 1-1 pa rt number, memory size, and package of rl78/g10 3 addition of industrial applications in table 1-1 list of ordering part numbers 4 addition of description to pin configur ation in 1.3.1 10-pin products and 1.3.2 16-pin products 22 correction of error in 2.5.1 serial array unit, (3) csi mode (slave mode, sckp... external clock input) 28 renamed to 2.7 ram data retention characteristics and modification of figure 31 addition of industrial application in 3.1 10-pin products 32 addition of industrial application in 3.2 16-pin products and modification of package drawing all trademarks and registered trademarks ar e the property of their respective owners. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc.
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the corre ct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device.
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