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1 lt1671 60ns, low power, single supply, ground-sensing comparator overdrive (mv) 0 time (ns) 140 120 100 80 60 40 20 10 20 30 40 1671 ta02 50 v s = 5v v step = 100mv t a = 25 c r l = 1m falling edge (t pdhl ) rising edge (t pdlh ) propagation delay vs overdrive 1mhz crystal oscillator 1671 ta01 + lt1671 5v output 0.068 f 1671 ta01 2k 2k 2k 1mhz crystal (at-cut) , ltc and lt are registered trademarks of linear technology corporation. the lt ? 1671 is a low power 60ns comparator with comple- mentary outputs and latch. the input common mode range extends from 1.5v below the positive supply down to the negative supply rail. like the lt1394, lt1016 and lt1116, this comparator has complementary outputs designed to interface directly to ttl or cmos logic. the lt1671 may operate from either a single 5v supply or dual 5v supplies. low offset voltage specifications and high gain allow the lt1671 to be used in precision applications. the lt1671 is designed for improved speed and stability for a wide range of operating conditions. the output stage provides active drive in both directions for maximum speed into ttl, cmos or passive loads with minimal cross-conduction current. unlike other fast comparators, the lt1671 remains stable even for slow transitions through the active region, which eliminates the need to specify a minimum input slew rate. the lt1671 has an internal, ttl/cmos compatible latch for retaining data at the outputs. the latch holds data as long as the latch pin is held high. device parameters such as gain, offset and negative power supply current are not significantly affected by variations in negative supply voltage. n low power: 450 m a n fast: 60ns at 20mv overdrive 85ns at 5mv overdrive n low offset voltage: 0.8mv n operates off single 5v or dual 5v supplies n input common mode extends to negative supply n no minimum input slew rate requirement n complementary ttl outputs n inputs can exceed supplies without phase reversal n pin compatible with lt1394, lt1016 and lt1116 n output latch capability n available in 8-lead msop and so packages n high speed a/d converters n zero-crossing detectors n current sense for switching regulators n extended range v/f coverters n fast pulse height/width discriminators n high speed triggers n line receivers n high speed sampling circuits descriptio u features applicatio s u typical applicatio u
2 lt1671 absolute m axi m u m ratings w ww u (note 1) total supply voltage (v + to v C ) ............................... 12v positive supply voltage ............................................. 7v negative supply voltage .......................................... C 7v differential input voltage ....................................... 12v input and latch current (note 2) ........................ 10ma output current (continuous)(note 2) ................. 20ma operating temperature range ................ C 40 c to 85 c specified temperature range (note 3) ... C 40 c to 85 c junction temperature ........................................... 150 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec.)................. 300 c package/order i n for m atio n w u u order part number lt1671cms8 ltct 1 2 3 4 v + 8 7 6 5 q out q out gnd latch enable top view ms8 package 8-lead plastic msop +in ?n v t jmax = 150 c, q ja = 250 c/ w consult factory for military grade parts. ms8 part marking t jmax = 150 c, q ja = 190 c/ w s8 part marking lt1671cs8 lt1671is8 order part number 1671 1671i top view q out q out gnd v + +in ?n v s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 + latch enable symbol parameter conditions min typ max units v os input offset voltage r s 100 w (note 4) 0.8 2.5 mv l 4.0 mv d v os input offset voltage drift l 4 m v/ c d t i os input offset current 10 100 na l 150 na i b input bias current (note 5) 120 280 na l 350 na v cmr input voltage range (note 6) l C 5 3.5 v single 5v supply l 0 3.5 v cmrr common mode rejection ratio C 5v v cm 3.5v, t a > 0 c 55 100 db C5v v cm 3.3v, t a 0 c55 db single 5v supply 0v v cm 3.5v, t a > 0 c 55 100 db 0v v cm 3.3v, t a 0 c55 db psrr power supply rejection ratio 4.6v v + 5.4v l 50 85 db C7v v C C2v l 60 90 db a v small signal voltage gain 1v v out 2v 2500 5000 v/v electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v + = 5v, v C = C 5v, v out (q) = 1.4v, v latch = v cm = 0v unless otherwise noted.
3 lt1671 electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v + = 5v, v C = C 5v, v out (q) = 1.4v, v latch = v cm = 0v unless otherwise noted. symbol parameter conditions min typ max units v oh output voltage swing high v + 3 4.6v, i out = 400 m a l 2.7 3.1 v v + 3 4.6v, i out = 4ma l 2.4 3.0 v v ol output voltage swing low i out = C 400 m a l 0.3 0.5 v i out = C 4ma 0.4 v i + positive supply current 450 800 m a l 1000 m a i C negative supply current 75 200 m a l 250 m a v ih latch pin high input voltage l 2v v il latch pin low input voltage l 0.8 v i il latch pin current v latch = 0v l C 1000 C 250 na t pd1 propagation delay d v in = 100mv, v od = 20mv 60 80 ns l 110 ns t pd2 propagation delay (note 7) d v in = 100mv, v od = 5mv 85 100 ns l 130 ns d t pd differential propagation delay (note 7) d v in = 100mv, v od = 5mv 15 30 ns t lpd latch propagation delay (note 8) 60 ns t su latch setup time (note 8) C15 ns t h latch hold time (note 8) 35 ns t pw (d) minimum disable pulse width 30 ns note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: this parameter is guaranteed to meet specified performance through design and characterization. it has not been tested. note 3: the lt1671cs8 and lt1671cms8 are guaranteed to meet specified performance from 0 c to 70 c and are designed, characterized and expected to meet these extended temperature limits, but are not tested at C 40 c and 85 c. the lt1671is8 is guaranteed to meet the extended temperature limits. note 4: input offset voltage (v os ) is defined as the average of the two voltages measured by forcing first one output, then the other to 1.4v. note 5: input bias current (i b ) is defined as the average of the two input currents. note 6: input voltage range is guaranteed in part by cmrr testing and in part by design and characterization. note 7: t pd and d t pd cannot be measured in automatic handling equipment with low values of overdrive. the lt1671 is 100% tested with a 100mv step and 20mv overdrive. correlation tests have shown that t pd and d t pd limits can be guaranteed with this test, if additional dc tests are performed to guarantee that all internal bias conditions are correct. propagation delay (t pd ) is measured with the overdrive added to the actual v os . differential propagation delay is defined as: d t pd = t pdlh C t pdhl note 8: latch propagation delay (t lpd ) is the delay time for the output to respond when the latch pin is deasserted. latch setup time (t su ) is the interval in which the input signal must remain stable prior to asserting the latch signal. latch hold time (t h ) is the interval after the latch is asserted in which the input signal must remain stable.
4 lt1671 propagation delay vs load capacitance differential input voltage (mv) ? 3 output voltage (v) ? ? 0 1 1671 g01 2 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v s = 5v r l = 1m t a = 125 c t a = 25 c t a = 55 c gain characteristics output load capacitance (pf) 0 time (ns) 100 90 80 70 60 50 10 20 30 40 1671 g02 50 v s = 5v v step = 100mv v od = 5mv t a = 25 c r l = 1m falling edge (t pdhl ) rising edge (t pdlh ) propagation delay vs source resistance propagation delay vs input overdrive overdrive (mv) 0 time (ns) 140 120 100 80 60 40 20 10 20 30 40 1671 ta02 50 v s = 5v v step = 100mv t a = 25 c r l = 1m falling edge (t pdhl ) rising edge (t pdlh ) source resistance (k ) 0 time (ns) 51015 1671 g05 200 180 160 140 120 100 80 60 40 v s = 5v r l = 1m v od = 20mv t a = 25 c step size = 800mv step size = 100mv 400mv 200mv temperature ( c) ?0 time (ns) 100 90 80 70 60 50 40 30 20 10 0 0 50 75 1671 g06 ?5 25 100 125 t pdhl t pdlh v s = 5v v step = 100mv v od = 5mv r l = 1m positive supply voltage (v) 4.4 time (ns) 90 80 70 60 50 4.6 4.8 5.0 5.2 5.4 1671 g03 5.6 falling edge (t pdhl ) rising edge (t pdlh ) v = 5v v step = 100mv v od = 5mv t a = 25 c r l = 1m propagation delay vs positive supply voltage propagation delay vs temperature input bias current vs temperature input offset voltage vs temperature positive common mode limit vs temperature temperature ( c) ?0 voltage (mv) 4 3 2 1 0 ? ? ? 0 50 75 1671 g07 ?5 25 100 125 v s = 5v r l = 1m temperature ( c) ?0 input bias current (na) 500 400 300 200 100 0 0 50 75 1671 g08 ?5 25 100 125 v cm = 5v v cm = 3.5v v cm = 0v v s = 5v r l = 1m temperature ( c) ?0 voltage (v) 6 5 4 3 2 1 0 0 50 75 1671 g09 ?5 25 100 125 v s = 5v r l = 1m typical perfor m a n ce characteristics u w
5 lt1671 typical perfor m a n ce characteristics u w temperature ( c) ?0 input voltage (v) 1 0 ? ? ? ? ? ? 0 50 75 1671 g10 ?5 25 100 125 r l = 1m v s = single 5v supply v s = 5v negative common mode limit vs temperature output sink current (ma) 0 voltage (v) 12 1671 g11 48 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 6 10 14 v s = 5v v in = 30mv t a = 25 c t a = 125 c t a = 55 c output source current (ma) 0 output voltage (v) 12 1671 g12 48 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2 6 10 14 v s = 5v v in = 30mv t a = 25 c t a = 125 c t a = 55 c output high voltage (v oh ) vs output source current output low voltage (v ol ) vs output sink current supply voltage (v) current (ma) 1671 g13 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 5 13 6 7 8 t a = 125 c t a = 55 c t a = 25 c v = 0v v in = 60mv i out = 0 positive supply current vs v + supply voltage response to 15mhz 10mv sine wave 0v 3v q out 1v/div +in 20mv p-p 10mv/div 50ns/div 1671 g17 switching frequency (mhz) 0.1 current (ma) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 110 1671 g14 t a = 25 c t a = 125 c t a = 55 c v s = 5v v step = 50mv i out = 0 positive supply current vs switching frequency negative supply voltage (v) ? current ( a) 100 90 80 70 60 50 ? ? 0 1671 g15 ? ? ? ? ? t a = 25 c t a = 125 c t a = 55 c v + = 5v v in = 60mv i out = 0 negative supply current vs v supply voltage temperature ( c) ?0 current ( a) 1.0 0.8 0.6 0.4 0.2 0 0 50 75 1671 g16 ?5 25 100 125 v s = 5v latch pin current vs temperature
6 lt1671 typical perfor m a n ce characteristics u w t pd + response time to 5mv overdrive 5mv C 95mv 1.4v 0v +in q out t pd C response time to 5mv overdrive 5mv C 95mv 1.4v 0v +in q out v out latch enable t h t su t pd 1671 td02 v in v out v in d v in v od t pd 1671 td01 ti i g diagra s u w w pi n fu n ctio n s uuu v + (pin 1) : positive supply voltage. normally 5v. +in (pin 2): noninverting input. Cin (pin 3): inverting input. v C (pin 4): negative supply voltage. normally either 0v or C 5v. latch enable (pin 5): latch control pin. when high, the outputs remain in a latched condition, independent of the current state of the inputs. gnd (pin 6): ground. q out (pin 7): noninverting logic output. this pin is high when +in is above C in and latch enable is low. q out (pin 8): inverting logic output. this pin is low when +in is above C in and latch enable is low. v s = 5v 20ns/div v od = 5mv 1671 g18 v s = 5v 20ns/div v od = 5mv 1671 g19
7 lt1671 applicatio n s i n for m atio n wu u u common mode considerations the lt1671 is specified for a common mode range of C 5v to 3.5v on a 5v supply or a common mode range of 0v to 3.5v on a single 5v supply. a more general consider- ation is that the common mode range is 0v below the negative supply and 1.5v below the positive supply, inde- pendent of the actual supply voltage. the criterion for common mode limit is that the output still responds correctly to a small differential input signal. when either input signal falls below the negative common mode limit, the internal pn diode formed with the sub- strate can turn on, resulting in significant current flow through the die. an external schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the sub- strate diode from turning on. the zero crossing detector in figure 1 demonstrates the use of a fast clamp diode. the zero crossing detector terminates the transmission line at its 50 w characteristic impedance. negative inputs should not fall below C2v to keep the signal current within the clamp diodes maximum forward rating. positive inputs should not exceed the devices absolute maximum ratings nor the power rating on the terminating resistor. 5v 1671 f01 + lt1671 q q cable r t 50 w v in r s 50 w 1n5712 figure 1. fast zero crossing detector either input may go above the positive common mode limit without damaging the comparator. the upper voltage limit is determined by an internal diode from each input to the positive supply. the input may go above the positive supply as long as it does not go far enough above it to conduct more than 10ma. functionality will continue if the remaining input stays within the allowed common mode range. there will, however, be an increase in propagation delay as the input signal switches back into the common mode range. input bias current input bias current is measured with the output held at 1.4v. as with any pnp differential input stage, the lt1671 bias current flows out of the device. it will go to zero on an input which is high and double on an input which is low. latch pin dynamics the latch pin is intended to retain input data (output latched) when the latch pin goes high. the pin will float to a high state when disconnected, so a flow-through condition requires that the latch pin be grounded. the latch pin is designed to be driven with either a ttl or cmos output. it has no built-in hysteresis. to guarantee data retention, the input signal must remain valid at least 35ns after the latch goes high (hold time), and must be valid at least C 15ns before the latch goes high (setup time). the negative setup time simply means that the data arriving 15ns after (rather than before) the latch signal is valid. when the latch signal goes low, new data will appear at the output in approximately 60ns (latch propagation delay). measuring response time to properly measure the response of the lt1671 requires an input signal source with very fast rise times and exceptionally clean settling characteristics. the last requirement comes about because the standard compara- tor test calls for an input step size that is large compared to the overdrive amplitude. typical test conditions are 100mv step size with 5mv overdrive. this requires an input signal that settles to within 1% (1mv) of final value in only a few nanoseconds with no ringing or settling tail. ordinary high speed pulse generators are not capable of generating such a signal, and in any case, no ordinary oscilloscope is capable of displaying the waveform to check its fidelity. some means must be used to inherently generate a fast, clean edge with known final value. the circuit shown in figure 2 is the best electronic means of generating a fast, clean step to test comparators. it uses a very fast transistor in a common base configuration. the transistor is switched off with a fast edge from the genera- tor and the collector voltage settles to exactly 0v in just a few nanoseconds. the most important feature of this
8 lt1671 applicatio n s i n for m atio n wu u u circuit is the lack of feedthrough from the generator to the comparator input. this prevents overshoot on the com- parator input, which would give a false fast reading on comparator response time. to adjust the circuit for exactly 5mv overdrive, v1 is adjusted so that the lt1671 output under test settles to 1.4v (in the linear region). then v1 is changed by C 1v to set overdrive to 5mv. high speed design techniques a substantial amount of design effort has made the lt1671 relatively easy to use. it is much less prone to oscillation than some slower comparators, even with slow input signals. however, as with any high speed comparator, there are a number of problems which may arise because of pc board layout and design. the most common prob- lem involves power supply bypassing. bypassing is nec- essary to maintain low supply impedance. dc resistance and inductance in supply wires and pc traces can quickly build up to unacceptable levels. this allows the supply line to move with changing internal current levels of the connected devices. this will almost always result in improper operation. in addition, adjacent devices con- nected through an unbypassed supply can interact with each other through the finite supply impedances. bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, keeping supply impedances low. bypass capacitors should be as close as possible to the lt1671. a good high frequency capacitor such as a 0.1 m f ceramic is recommended, in parallel with a larger capaci- tor such as a 4.7 m f tantalum. poor trace routes and high source impedances are also common sources of problems. be sure to keep trace lengths as short as possible, and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. if output traces are longer than a few inches, be sure to terminate them with a resistor to eliminate any reflections that may occur. resistor values are typically 250 w to 400 w . also, be sure to keep source impedances as low as possible, preferably 1k w or less. about level shifts the lt1671s logic output will interface with many cir- cuits directly. many applications, however, require some form of level shifting of the output swing. with lt1671- based circuits this is not trivial because it is desirable to maintain very low delay in the level shifting stage. when designing level shifters, keep in mind that the ttl output of the lt1671 is a sink-source pair (figure 3) with good ability to drive capacitance (such as feedforward capaci- tors). figure 4 shows a noninverting voltage gain stage with a 15v output. when the lt1671 switches, the base- emitter voltages at the 2n2369 reverse, causing it to switch very quickly. the 2n3866 emitter-follower gives a low impedance output and the schottky diode aids cur- rent sink capability. + lt1671 1671 f02 fet probe fet probe * total lead length including device pin. socket and capacitor leads should be less than 0.5 in. use ground plane ** (v os + overdrive)/200 25 25 5v 0.01 f* 0.01 f 10k 50 v1** 2n3866 0v ?v ?v ?v 50 pulse in 750 400 0.1 f 130 0v 100mv q q figure 2. response time test circuit
9 lt1671 applicatio n s i n for m atio n wu u u figure 5 is a very versatile stage. it features a bipolar swing that is set by the output transistors supplies. this 3ns delay stage is ideal for driving fet switch gates. q1, a gated current source, switches the baker-clamped output transistor, q2. the heavy feedforward capacitor from the output = 0 ? +v (typically 3v to 4v) 1671 f03 +v 1671 f04 1k 12pf hp5082-2810 2n2369 2n3866 rise time = 4ns fall time = 5ns out 15v + 1k 1k lt1671 figure 3. simplified lt1671 output stage figure 4. level shift has noninverting voltage gain 1671 f05 output transistor supplies (shown in heavy lines) can be referenced anywhere between 15v and 15v 1000pf ?0v (typ) 1n4148 5v (typ) input 5v 5v ?0v + 0.1 f 820 lt1671 4.7k 820 rise time = 3ns fall time = 3ns 430 330 q1 2n2907 q2 2n2369 output hp5082-2810 figure 5. level shift with inverting voltage gainbipolar swing 1671 f06 1k 12pf 2n2369 2n3866 2n5160 power fet rise time = 7ns fall time = 9ns 15v + 1k 1k r l lt1671 figure 6. noninverting voltage gain level shift lt1671 is the key to low delay, providing q2s base with nearly ideal drive. this capacitor loads the lt1671s output transition, but q2s switching is clean with 3ns delay on the rise and fall of the pulse. figure 6 is similar to figure 4 except that a sink transistor has replaced the schottky diode. the two emitter-followers drive a power mosfet that switches 1a at 15v. most of the 7ns to 9ns delay in this stage occurs in the mosfet and the 2n2369. when designing level shifters, remember to use transis- tors with fast switching times and high f t . to get the kind of results shown, switching times in the nanosecond range and an f t approaching 1ghz are required.
10 lt1671 applicatio n s i n for m atio n wu u u crystal oscillators figure 7 shows a crystal oscillator circuit. in the circuit, the resistors at the lt1671s positive input set a dc bias point. the 2k-0.068 m f path sets up phase shifted feedback and the circuit looks like a wideband unity-gain follower at dc. the crystals path provides resonant positive feedback and stable oscillation occurs. figure 7. 1mhz to 10mhz crystal oscillator figure 8. switchable output crystal oscillator. biasing a or b high places associated crystal in feedback path. additional crystal branches are permissible + lt1671 2k 5v 2k 1mhz to 10mhz crystal (at-cut) 0.068 f output 1671 f07 2k 1671 f08 + lt1671 1k 5v 1k 1k 75pf d1 output b a logic inputs as many stages as desired xtal a 1k r x xtal b xtal x d2 d x 2k = 1n4148 ground xtal cases switchable output crystal oscillator figure 8 permits crystals to be electronically switched by logic commands. this circuit is similar to the previous examples, except that oscillation is only possible when one of the logic inputs is biased high.
11 lt1671 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) msop (ms8) 1197 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" ( 0.152mm ) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.040 0.006 (1.02 0.15) 0.012 (0.30) ref 0.006 0.004 (0.15 0.102) 0.034 0.004 (0.86 0.102) 0.0256 (0.65) typ 12 3 4 0.192 0.004 (4.88 0.10) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102) package descriptio n u dimensions in inches (millimeters) unless otherwise noted. ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660)
12 lt1671 ? linear technology corporation 1998 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com 1671fs, sn1671 lt/tp 0499 4k ? printed in usa typical applicatio n u part number description comments lt1016 ultrafast tm precision comparator industry standard 10ns comparator lt1116 12ns single supply ground-sensing comparator single supply version of lt1016 lt1394 ultrafast single supply comparator 7ns, 6ma single supply comparator lt1720 ultrafast dual single supply comparator dual 4.5ns, 4ma single supply comparator ultrafast is a trademark of linear technology corporation. related parts 4mhz adaptive trigger circuit line and fiber-optic receivers often require an adaptive trigger to compensate for variations in signal amplitude and dc offsets. the circuit in figure 9 triggers on 2mv to 175mv signal from 100hz to 4mhz while operating from a single 5v rail. a1, operating at a gain of 15, provides wideband ac gain. the output of this stage biases a 2-way peak detector (q1 through q4). the maximum peak is stored in q2s emitter capacitor, while the minimum excursion is retained in q4s emitter capacitor. the dc value of the midpoint of a1s output signal appears at the junction of the 500pf capacitor and the 3m w units. this point always sits midway between the signals excursions, regardless of absolute amplitude. this signal-adaptive voltage is buffered by a2 to set the trigger voltage at the figure 9. 4mhz single supply adaptive trigger. output comparators threshold varies ratiometrically with input amplitude, maintaining data integrity over >85:1 input amplitude range lt1671s positive input. the lt1671s negative input is biased directly from a1s output. the lt1671s output, the circuits output, is unaffected by > 85:1 signal amplitude variations. bandwidth limiting in a1 does not affect trig- gering because the adaptive trigger threshold varies ratiometrically to maintain circuit output. figure 10 shows operating waveforms at 4mhz. trace as input produces trace bs amplified output at a1. the comparators output is trace c. 5v + a1 lt1227 + a2 lt1006 input 5v 5v 5v trigger out 1671 f09 500pf 0.1 f 510 w 470 w 470 750 w 36 w 1 3 2 4 14 13 15 5 6 12 10 11 2k 10 f 2k 2k + 0.1 f 0.1 f 0.005 m f 0.005 f 100 f + q1, q2, q3, q4 = ca3096 array: tie substrate (pin 16) to ground = 1n4148 + lt1671 q1 q2 q3 q4 3m 3m figure 10. adaptive trigger responding to a 4mhz, 5mv input. input amplitude variations from 2mv to 175mv are accommodated a = 10mv/div b = 50mv/div c = 1mv/div 50ns/div 1671f10

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