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october 2006 rev. 3 1/26 26 STOTG04ES usb-otg full-speed transceiver feature summary meets the requirements of the universal serial bus specification revision 2.0 and the on-the- go supplement to the usb 2.0 specification analog car kit-compatible three operating modes: usb, uart and audio configurable using i 2 c serial interface capable of 12mbit/s full-speed and 1.5mbit/s low-speed modes of operation standard digital interface compliant with the otg transceiver specification supports the session request protocol (srp) and host negotiation protocol (hnp) 35ma typical v bus charge pump output current for 3.3v supply voltage ability to control external charge pump for higher v bus currents integrated pull-up/-down resistors 6kv esd protection on all usb pins (contact discharge) +1.6v to +3.6v digital power supply and +2.7v to +5.5v analog supply voltage range power-down mode with very low power consumption for battery powered devices ideal for system asics with built-in usb otg dual role core available in qfn-24 ?40c to +85c operating temperature range applications mobile phones pdas mp3 players digital cameras printers description the STOTG04ES is a usb on-the-go full-speed transceiver. it provides complete physical layer solution for any usb-otg device. it contains v bus charge pump and comparators, id line detector and interrupt generator, and the usb differential driver and receivers. the stotg04 transceiver is suitable for mobile and battery powered devices because of its low power consumption and power down operating mode. the transceiver is capable of operation in several different modes. it can operate in basic usb-otg mode, as an uart transceiver or in audio mode. behavior of the transceiver is fully configurable through the two-wire i 2 c serial bus. the transceiver supports session request protocol and host negotiation protocol. www.st.com qfn24 (4mmx4mm) order code part number package packaging STOTG04ESqtr qfn24 (4mm x 4mm) 4000 parts per reel
contents STOTG04ES 2/26 contents 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 charge pump characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 v bus comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 id line detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 driver and receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.6 control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7.1 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7.2 usb modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7.3 uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.7.4 audio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.9 i 2 c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.10 device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.11 bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.12 external charge pump switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STOTG04ES pin configuration 3/26 1 pin configuration table 1. pin description figure 1. pin connections (bottom view ) pln n symbol i/o name and function 1 adr_psw i/o least significant bit of the i 2 c address of the transceiver input latched on reset; psw output enabling or disabling an external charge pump 2 sda i/o i 2 c serial data (1) 3scli i 2 c clock 4 reset/ i active low logic reset 5 int/ o active low interrupt signal (open-drain) 6 speed i mode of the transceiver (0 = low-speed, 1 = full-speed) (2) 7 v trm power internal voltage regulator output; an external decoupling capacitor should be connected (3) 8 suspend i power down input (0 = active mode, 1 = power down) (see ta bl e 8 ) 9 oe_tp_int/ i/o output enable of the differential driver in the usb mode or interrupt output 10 vm o d? single-ended receiver output 11 vp o d+ single-ended receiver output 12 rcv o differential receiver output exppad - not connected 13 se0_vm i/o single-ended zero input/output in the dat_se0 mode transmit mode, negative data input/output in the single-ended transmit mode or txd in the uart mode 14 dat_vp i/o data input/output in the dat_se0 mode transmit mode, positive data input/ output in the single-ended transmit mode or rxd in the uart mode 15 d- i/o negative data line in the usb mode or serial data output in the uart mode 16 d+ i/o positive data line in the usb mode or serial data input in the uart mode 17 gnd power common analog and digital ground 18 id i/o id pin of the usb connector used for protocol identification 19 v bus i/o v bus line of the usb interface ? it needs an external capacitor of 4.7f 20 v bat power analog power supply voltage (+2.7v to +5.5v) 21 cap1 i/o external capacitor pin for the charge pump 22 cap2 i/o external capacitor pin for the charge pump
pin configuration STOTG04ES 4/26 (1) input and open-drain output (2) input with internal pull-up resistor (3) internal regulator can be bypassed by connecting v bat to this pin when the v bat is in range of 2.7v to 3.6v figure 2. functional diagram 23 cgnd power ground for the charge pump 24 v if power logic power supply (+1.6v to 3.6v) pln n symbol i/o name and function
STOTG04ES maximum ratings 5/26 2 maximum ratings table 2. absolute maximum ratings (*) in accordance to iec61000-4-2, level 3. absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these con- ditions is not implied. table 3. thermal data table 4. recommended operating condition table 5. esd performance symbol parameter value unit v if logic supply voltage -0.5 to + 4.5 v v bat analog supply voltage -0.5 to + 6.5 v v dcdig dc input voltage on any logic interface pin -0.5 to + 4.5 v t stg storage temperature range -65 to + 150 c v esd electrostatic discharge voltage on usb pins human body model 8 kv contact discharge (*) 6 symbol parameter value unit r thja thermal resistance junction-ambient 59 c/w symbol parameter min. typ. max. unit v if logic supply voltage 1.6 1.8 3.6 v v bat analog supply voltage 2.7 3.3 5.5 v t a operating temperature range -40 +85 c c ext charge pump external capacitor 100 220 470 nf c t charge pump tank capacitor 1 4.7 6.5 f c trm voltage regulator external capacitor 1 f r s data lines impedance matching resistor 20 ? symbol parameter value unit esd iec-61000-4-2 (d+, d-, vbus, id) air discharge (10 pulses) 8 kv contact discharge (10 pulses) 6 iec-61000-4-2 (other pins) air discharge (10 pulses) 2 contact discharge (10 pulses) 2
electrical characteristics STOTG04ES 6/26 3 electrical characteristics table 6. electrical characteristics characteristics measured over recommended operating conditions unless otherwise is noted. all typical values are referred to t a = 25c, v if = 1.8v, v bat = 3.3v, r s = 20 ? , c ext = 220nf, c t = 4.7f and c trm = 1f symbol parameter test conditions min. typ. max. unit i if digital part supply current active mode (1,2) 0.6 1.6 ma power down mode 1 a i bat operating supply current transceiver current while transmitting and receiving (1,2) 4.5 7 ma charge pump current, i load = 8ma 17 25 power down mode (3) 1 a logic inputs and outputs v oh high level output voltage i oh = -100a v if -0.15 v i oh = -2ma v if -0.40 v v ol low level output voltage i ol = 100a 0.15 v i ol = 2ma 0.40 v v ih high level input voltage 0.7v if v v il low level input voltage 0.3v if v i lkg input leakage current -1 1 a i oz off-state output current -5 5 a v bus v bus v bus output voltage i load = 8ma 4.4 4.9 5.25 v v bus_lkg v bus leakage voltage no load 3 200 mv v bus_rip v bus output ripple i load = 8ma, c t = 4.7f 30 60 mv f cp charge-pump switching frequency (2) 0.5 0.8 1.5 mhz r vbus v bus input impedance 40 76 100 k ? i vbus maximum v bus source current c ext = 220 nf, v bus > 4.4v 20 35 ma v bus_vld v bus valid comparator threshold low to high transition 4.40 v high to low transition 4.40 v ses_vld session valid comparator threshold for both a and b devices low to high transition 0.8 2.0 v high to low transition 0.8 2.0 r vbus_pu v bus charge pull-up resistance 281 640 ? r vbus_pd v bus discharge pull-down resistance 656 1260 ? id v id_bias id pin bias voltage r cp_id = 140k ?, v bat 5v 1.3 1.9 3.0 v r id_pu id pin pull-up resistance 70 105 130 k ? r id_gnd id line short resistance to detect id_gnd state 10 ? r id_float id line short resistance to detect id_float state 800 k ?
STOTG04ES electrical characteristics 7/26 (1) transmitting and receiving at 12mbit/s, loads of 50pf on d+ and d- pins, no capacitive loads on vp and vm pins (2) not tested in production; characterization only (3) see paragraph 6.7.1 differential driver z drv output impedance excluding external r s 81624 ? v oh_drv high level output voltage r lh = 14.25k ?, v trm = 3.3v 2.8 3.6 v r lh = 14.25k ?, v trm = 2.7v 2.6 3.0 v v ol_drv low level output voltage r ll = 1.425k ? 00.3v v crs driver crossover voltage c load = 50 to 600pf 1.3 1.67 2.0 v differential and single-ended receivers v di differential receiver input sensitivity (v d+ - v d- ) v cm = 0.8 to 2.5v -200 200 mv v se-th se receivers switching threshold low to high transition 0.8 1.6 2.0 v high to low transition 0.8 1.1 2.0 r in input resistance pu/pd resistor deactivated 1.5 m ? c in input capacitance 10 30 pf r pu_d+ data line pull-up resistance on pin d+ bus idle 900 1300 1575 ? receiving mode 1425 2200 3090 r pu_d- data line pull-up resistance on pin d- 900 1300 1575 ? r pd data line pull-down resistance 14.25 17.0 24.8 k ? v dt_lkg data line leakage voltage r pu_ext = 300k ? 200 342 mv car kit interrupt detector v cr_int_th car kit interrupt threshold 0.4 0.6 v uart mode ? d+ and d- pins v oh high level output voltage i oh = -2ma 2.4 3.6 v v ol low level output voltage i ol = 2ma 00.4v v ih high level input voltage 2.0 v v il low level input voltage 0.8 v voltage regulator v trm internal power supply voltage v bat = 3.3 to 5v, no load; uart_en=0 3.0 3.3 3.6 v v bat = 2.8 to 5v, no load; uart_en=1 2.6 2.75 2.9 v i trm voltage regulator output current v bat = 3.6v, v trm > 3v; uart_en=0 20 ma v bat = 3.0v, v trm >2.6v; uart_en=1 10 ma symbol parameter test conditions min. typ. max. unit
electrical characteristics STOTG04ES 8/26 table 7. switching characteristics over recommended operating conditions unless otherwise is noted. all the typical values are referred to t a = 25c, v if = 1.8v, v bat = 3.3v, r s = 20 ? , c ext = 220nf, c t = 4.7f, and c trm = 1f symbol parameter test conditions min. typ. max. unit t vbus_rise v bus rise time i load = 8ma, c t = 10f 1100ms differential driver t r data signal rise time full-speed mode, c load = 50pf 48.520 ns low-speed mode, c load = 600pf 75 110 300 t f data signal rise time full-speed mode, c load = 50pf 48.520 ns low-speed mode, c load = 600pf 75 110 300 t p_drv_r propagation delay of the driver, rising edge; dat_se0 mode full-speed mode, c load = 50pf 38 ns low-speed mode, c load = 600pf 280 propagation delay of the driver, rising edge; vp_vm mode full-speed mode, c load = 50pf 55 ns low-speed mode, c load = 600pf 300 t p_drv_f propagation delay of the driver, falling edge; dat_se0 mode full-speed mode, c load = 50pf 38 ns low-speed mode, c load = 600pf 280 propagation delay of the driver, rising edge; vp_vm mode full-speed mode, c load = 50pf 55 ns low-speed mode, c load = 600pf 300 t rfm rise and fall time matching (t r / t f ) excluding the first transition from the idle state full-speed mode 90 111.11 % low-speed mode 80 125 single-ended receivers t p_se_r propagation delay of the se receiver, rising edge full-speed mode, input slope 15ns 18 ns low-speed mode, input slope 150ns 18 t p_se_f propagation delay of the se receiver, falling edge full-speed mode, input slope 15ns 18 ns low-speed mode, input slope 150ns 18 differential receiver t p_dif_r propagation delay of the se receiver, rising edge full-speed mode, input slope 15ns 24 ns low-speed mode, input slope 150ns 24 t p_dif_f propagation delay of the se receiver, falling edge full-speed mode, input slope 15ns 24 ns low-speed mode, input slope 150ns 24 digital interface t set_oe output enable setup time 50 ns t ta _ o i output to input bus turnaround time (1, 2) 05ns t ta _ i o output to input bus turnaround time (1, 2) 05ns i 2 c bus (3) f scl scl clock frequency 100 khz t low low period of the scl clock 4.7 s t high high period of the scl clock 4.0 s t iicr rise time of both sda and scl signals 1000 ns
STOTG04ES electrical characteristics 9/26 note 1: parameter applies to the oe_tp_int/, dat_vp, and se0_vm signals note 2: not tested in production; characterization only note 3: requirements defined by the i2c-bus specification, version 2.1 t iicf fall time of both sda and scl signals 300 ns t su_sta setup time for a repeated start condition 4.7 s t hd_sta hold time for the start and repeated start conditions 4.0 s t su_dat data setup time 250 ns t hd_dat data hold time 0 s t su_sto setup time for the stop condition 4.0 s t buf bus free time between a stop and start condition 4.7 s symbol parameter test conditions min. typ. max. unit
charge pump characteristics STOTG04ES 10/26 4 charge pump characteristics figure 3. output characteristics figure 4. output ripple
STOTG04ES timing diagrams 11/26 5 timing diagrams figure 5. rise and fall times figure 6. differential driver propagation delay figure 7. differential receiver propagation delay
timing diagrams STOTG04ES 12/26 figure 8. output enable setup time figure 9. bus turnaround time figure 10. i 2 c bus timing t set_oe v il v ih oe_tp_int/ v il v ih dat_vp se0_vm usb idle state data to transmit t ta_oi v il v ih oe_tp_int/ v il v ih dat_vp se0_vm t ta_io output input output sr s p s scl sda t low t iic_f t high t iic_r t hd_sta t su_sto t buf t iic_r t su_sta t hd_dat t su_dat t hd_sta t iic_f
STOTG04ES timing diagrams 13/26 figure 11. block diagram charge pum p o s c illa to r bandgap reference vbus vbat vtrm d+ d- voltage regulator id vbat vtrm cap2 cap1 register set and control logic i2 c in te rfa c e scl adr_psw sda dat_vp se0_vm rcv vp vm oe_tp_int/ suspend speed in t / reset/ vbat vbat
block description STOTG04ES 14/26 6 block description the STOTG04ES integrates a charge pump and comparators for the v bus , id line detector and interrupt switch, differential data driver, differential and single-ended receivers, low dropout voltage regulator and control logic. the STOTG04ES provides a complete solution for connection of a digital usb otg controller to the physical universal serial bus. 6.1 charge pump the v bus line voltage is provided using the internal charge pump. it is capable of sourcing up to 35ma load current. the charge pump can be powered by voltage from 2.7v to 5.5v. it needs two capacitors for its operation: an external capacitor of 220nf connected between the cap1 and cap2 pins and a 4.7f decoupling tank capacitor on the v bus . in case when an application needs higher current than 35ma, it is possible to provide it using an external charge pump or switch controlled by the adr_psw pin. 6.2 v bus comparators these comparators monitor the v bus voltage. they provide current status information for the v bus line. v bus valid status means that the voltage is above v bus_vld . session valid status means that the v bus voltage is above v ses_vld level. 6.3 voltage regulator an internal low-dropout voltage regulator provides power supply for the bus drivers and receivers. the regulator needs an external capacitor of 1f on the v trm pin for its proper operation. the regulator can provide 3.3v or 2.75v output voltages according to the operating mode. the regulator can be bypassed in case when the analog supply voltage is in the range of 3.0v (or 2.7v) to 3.6v. it is necessary to tie the v trm pin to the v bat power supply voltage to bypass the regulator. 6.4 id line detector this block senses id line status. it is capable of detecting three different line states: pin floating; pin tied to ground; pin grounded via a 140k ? resistor. the id detector can also generate an interrupt by shorting the pin to ground. 6.5 driver and receivers the driver can operate in two different modes. it can act as a simple low-speed and full-speed differential usb driver or as two independent single-ended drivers in the uart mode. this block contains one differential receiver for the usb operation mode and two single-ended receivers for usb signaling as well as uart receivers.
STOTG04ES block description 15/26 6.6 control logic this block controls the behavior of whole chip. it communicates with the external environment via the i 2 c serial bus. the control logic block consists of i 2 c slave interface, configuration and status registers, and some glue logic. 6.7 modes of operation the STOTG04ES can operate in two different power modes and in three operating modes. they can be controlled by logic signals and control registers. 6.7.1 power modes to reduce power consumption when there is no need for the usb function, the stotg04 implements power-down mode. in this mode, the power consumption is strongly reduced. power mode of the device can be controlled by bit suspend of the control register 1 or/and the suspend pin as can be seen in table 8). table 8. power modes although in power down mode all analog blocks should be switched off, some of them could be turned on by bits in the control registers having higher priority than suspend bit. in order to obtain minimum power consumption in power down mode the device must be configured has shown in table 9. the digital part is fully static so that it almost does not consume power. all of the interrupts (except bdis_acon) are fully operational in power-down mode, as is the i 2 c interface. table 9. power down mode setup x = don?t care - = reserved bit order: 0...7 6.7.2 usb modes the STOTG04ES transceiver has two basic usb operational modes. these modes define how the digital io pins of the transceiver will be used. independently of usb operating mode, some signals always have the same function (see table 10). table 10. digital interface signals suspend bit suspend pin power mode 0x normal operation x0 1 1 power-down suspend bit suspend pin control register 1 control register 2 control register 3 1 1 x1x0xx0- 00xx00x0 -xxxx0xx signal function rcv differential receiver output vp d+ single-ended receiver output vm d- single-ended receiver output oe_tp_int/ output enable signal of the differential driver
block description STOTG04ES 16/26 the rcv signal is active in the vp_vm mode only. its output driver is controlled by the oe_tp_int/ signal. operating modes are described below. the meanings of the dat_vp and se0_vm signals depend on the mode of operation. both of these signals can be bidirectional or unidirectional. the direction is controlled by bidi_en bit of control register 3 (described later). when these signals are bidirectional, the direction is controlled by the oe_tp_int/ signal (see tables 11 and 12). the actual mode of operation is controlled by the dat_se0 bit of control register 1 (see tables 11 and 12) table 11. dat_se0 (dat_se0 = 1) table 12. vp_vm (dat_se0 = 0) * state of the oe_tp_int/ signal. in the usb mode of operation it is necessary to control the rise and fall times of the transmission driver. these times are different for low-speed and full-speed usb settings. selection of actual usb speed can be done using the bit speed of control register 1 or/and the speed pin (see table 13). table 13. usb speed selection 6.7.3 uart mode the actual mode of operation is selectable by the transp_en and uart_en bits of control register 1 (see table 14). table 14. transceiver modes (1) in reality, it is not possible to set both these bits at the same time. in this case, only uart_en bit will remain set. in the uart mode it is possible to select driver direction on both the d+ and d? pins. the selection is done using the bdir[1] and bdir[0] bits of control register 3 (see table 15). bidi_en oe/* dat_vp se0_vm 1 0 differential driver input se0 driver input 1 differential receiver output se0 detector output 0 x differential driver input se0 driver input bidi_en oe/* dat_vp se0_vm 1 0 d+ driver input d- driver input 1 d+ receiver output d- receiver output 0 x d+ driver input d- driver input speed bit speed pin usb mode 0x low-speed x0 1 1 full-speed transp_en uart_en stotg04 mode 00 usb 01 uart 1 0 forbidden 11 uart (1)
STOTG04ES block description 17/26 table 15. uart drivers direction 6.7.4 audio mode in this mode the transceiver has to release all of its drivers and pull-up/pull-down resistors on the d+, d- and id pins, leaving them in a high impedance state. this allows these lines to be used for transmission of audio signals. the transceiver should not provide voltage on its v bus output in this mode. conditions described in table 16 force the transceiver into the audio mode. table 16. audio mode setup 6.8 registers the STOTG04ES transceiver device is controlled using register settings (see table 17). these registers can be set and read via the i 2 c bus. table 17. register set (1) access type can be: read (r), set (s), clear (c). (2) the first address is to set, the second one to clear bits. when writing to the set address, any ?1? will set the associated bit to logic ?1?. when writing to the clear address, any ?1? will set the associated bit to logic ?0?. it is possible to read from any address, whether it is a set or clear address. see tables 18, 19, 20, 21 for bit setting details. bdir[1] bdir[0] dat_vp ? d+ se0_vm ? d- 00 01 10 11 transp_en bit uart_en bit oe_tp_int/ signal control register 2 0 0 1 00000000 register size (bits) acc (1) addr (2) description vendor id 16 r 00h stmicroelectronics id (0483h) - lsb first product id 16 r 02h id of the stotg04 (a0c4h) - lsb first control 1 8 r/s/c 04h 05h first control register control 2 8 r/s/c 06h 07h second control register control 3 8 r/s/c 12h 13h third control register interrupt source 8 r 08h current state of signals generating interrupts interrupt latch 8 r/s/c 0ah 0bh latched source that generated interrupt interrupt mask false 8 r/s/c 0ch 0dh enables interrupts on falling edge interrupt mask true 8 r/s/c 0eh 0fh enables interrupts on rising edge
block description STOTG04ES 18/26 table 18. control register 1 (1) state of the bit after reset. setting the bdis_acon_en bit enables automatic switching of the d+ pull-up resistor when the device receives an se0 longer than half of the bit period. this function should not be used in low-speed operation. table 19. control register 2 it is not possible to set vbus_drv, vbus_dischrg and vbus_chrg at the same time; the bit having higher priority will remain set while the others will be cleared. vbus_drv has higher priority than vbus_dischrg which has higher priority than vbus_chrg. table 20. control register 3 name bit r (1) description speed 0 1 0 = low-speed mode 1 = full-speed mode suspend 1 1 0 = normal operation 1 = power-down mode dat_se0 2 0 0 = vp_vm mode 1 = dat_se0 mode transp_en 3 0 reserved. for testing purpose bdis_acon_en 4 0 enable a-device to connect if b-device disconnect detected oe_int_en 5 0 when set and suspend = 1, then oe_tp_int/ becomes interrupt output uart_en 6 0 enables uart mode (higher priority than transp_en bit) and 2.7v voltage regulation 7 reserved name bit r description dp_pull-up 0 0 connect d+ pull-up dm_pull-up 1 0 connect d- pull-up dp_pull-down 2 1 connect d+ pull-down dm_pull-down 3 1 connect d- pull-down id_gnd_drv 4 0 connect id pin to ground vbus_drv 5 0 provide power to v bus vbus_dischrg 6 0 discharge v bus through a resistor to ground vbus_chrg 7 0 charge v bus through a resistor name bit r description 00reserved rec_bias_en 1 0 enables transmitter bias even during usb receive bidi_en 2 1 when set, then dat_vp and se0_vm pins become bidirectional otherwise they are inputs only bdir[0] 3 0 direction of the drivers between dat_vp ? dp and se0_vm ? dm in the uart mode bdir[1] 4 1 audio_en 5 0 enables car-kit interrupt detector psw_en 6 0 enables external charge pump control on the adr_psw pin 70reserved
STOTG04ES block description 19/26 table 21. interrupt registers (*) (*) bit order is the same for all four interrupt related registers. meaning of each regi ster is described in table 17. 6.9 i 2 c bus interface all of the stotg04 transceiver registers are accessible through the i 2 c bus (see figure 12). the device contains a slave controller which provides communication with an external master. the i 2 c interface consists of three pins: sda (serial data); scl (serial clock); adr_psw (is the lsb of the device address). 6.10 device address the usb-otg transceiver has following 7-bit i 2 c device address: the adr bit represents current state of the adr_psw device pin. it means that the address can be either 2ch or 2dh according to the adr_psw pin. 6.11 bus protocol any device that sends data to the bus is defined as the transmitter. any device that reads the data is the receiver. the device that controls data transfers is the bus master, while the transmitter or receiver is the slave device. the master initiates data transfers and provides the serial clock. the stotg04 is always the slave device. operation of the i 2 c bus is described by following figure 12. name bit r description vbus_vld 0 0 a-device v bus valid comparator sess_vld 1 0 session valid comparator dp_hi 2 0 d+ pin is asserted high during srp id_gnd 3 0 id pin grounded dm_hi 4 0 d- pin is asserted high id_float 5 0 id pin floating bdis_acon 6 0 set when bdis_acon_en bit is set and transceiver asserts dp_pull-up after detecting b-device disconnect cr_int 7 0 car-kit interrupt 010110adr
block description STOTG04ES 20/26 figure 12. basic operation of the i 2 c bus start condition is identified by a falling edge of the sda signal while the scl is stable at high level. the start condition must precede any data transfer on the bus. stop condition is identified by a rising edge of the sda signal while the scl is stable at high level. the stop condition terminates any communication between device and master. the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sda line after sending eight data bits. during the ninth clock period the receiver pulls the sda line low to acknowledge the receipt of the eight data bits. if the receiver is a slave device and it does not generate acknowledge bit then the bus master can generate the stop condition in order to abort the transfer. below is described format of i 2 c commands. all tables use common format and symbols. every data word consists of eight bits with most significant bit first and least significant bit last. symbols used in the tables are: s ? start condition p ? stop condition a ? acknowledge bit n ? negative acknowledge write command to the transceiver device is described by following table. it is possible to write into several consecutive registers during one write command. read command consists of dummy write to set proper address of a register followed by real read sequence. s device address 0 a reg. address k a data (k) a data (k+1) a .. data (k+n) a p s device address 0 a reg. address k a p s device address 1 a data (k) a data (k+1) a data (k+2) a ... data (k+n) n p
STOTG04ES block description 21/26 6.12 external charge pump switch the adr_psw pin has two functions. state of this pin is always latched into a register on the rising edge of the reset/ signal. the latched value is used as a least significant bit of the i 2 c address. after the address is latched, this pin can be set as an output by setting the psw_en bit of the control register 3. output value of the pin is low when the pin is high during reset; otherwise the output is high. example connection of an external charge pump is shown in following figure. when the charge pump control signal would be active high, the adr_psw pin should be pulled down instead of high. figure 13. external charge pump application
package mechanical data STOTG04ES 22/26 7 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
STOTG04ES package mechanical data 23/26 dim. mm. mils min. typ max. min. typ. max. a1.0039.4 a1 0.00 0.05 0.0 2.0 b 0.18 0.30 7.1 11.8 d 3.9 4.1 153.5 161.4 d2 1.95 2.25 76.8 88.6 e 3.9 4.1 153.5 161.4 e2 1.95 2.25 76.8 88.6 e0.50 19.7 l 0.40 0.60 15.7 23.6 qfn24 (4x4) mechanical data
package mechanical data STOTG04ES 24/26 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 99 101 3.898 3.976 t 14.4 0.567 ao 4.35 0.171 bo 4.35 0.171 ko 1.1 0.043 po 4 0.157 p 8 0.315 tape & reel qfnxx/dfnxx (4x4) mechanical data
STOTG04ES revision history 25/26 8 revision history table 22. revision history date revision description of change 13-jan-2006 1 first release. 01-feb-2006 2 mistake on table 1. 17-oct-2006 3 added details in paragraph 6.7.1, comments to table 19 and description in paragraph 6.12.
STOTG04ES 26/26 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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