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summary atmel's sam4l series is a member of a family of flash microcontrollers based on the high performance 32-bit arm cortex-m4 risc processor running at fre- quencies up to 48mhz. the sam4l series embeds state-of-the-art picopower technology for ultra-low power consumption. combined power control techniques are used to bring active current consumption down to 90a/mhz. the device allows a wide range of options between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. the wait and retention modes provide full logic and ram retention, associated with fast wake-up capability (<1.5s) and a very low consumption of, respectively, 3 a and 1.5 a. in addition, wait mode sup- ports sleepwalking features. in backup mode, cpu, peripherals and ram are powered off and, while consuming less than 0.9a with external interrupt wake- up supported. the sam4l series offers a wide range of peripherals such as segment lcd con- troller, embedded hardware capacitive touch (qtouch), usb device & embedded host, 128-bit aes and audio interfaces in addition to high spee d serial peripher- als such as usart, spi and i 2 c. additionally the peripheral event system and sleepwalking allows the peripherals to communicate directly with each other and make intelligent decisions and decide to wake-up the system on a qualified events on a peripheral level; such as i 2 c address match or and adc threshold. features ? core ? arm ? cortex tm -m4 running at up to 48mhz ? memory protection unit (mpu) ?thumb ? -2 instruction set ? picopower ? technology for ultra-low power consumption ? active mode downto 90a/mhz with configurable voltage scaling ? high performance and efficiency: 28 coremark/ma ? wait mode downto 3a with fast wake-up time (<1.5s) supporting sleepwalking ? full ram and logic retention mode downto 1.5a with fast wa ke-up time (<1.5s) ? ultra low power backup mode with/without rtc downto 1,5/0.9a ? memories ? from 128 to 512kbytes embedded flash, 64-bit wide access, ? 0 wait-state capa bility up to 24mhz ? up to 64kbytes embedded sram ? system functions ? embedded voltage linear and switching regulator for single supply operation ? two power-on-reset and two brown-out detectors (bod) ? quartz or ceramic resonator oscillators: 0.6 to 30mhz main power with failure detection and low power 32.768 khz for rtc or device clock ? high precision 4/8/12mhz factory trimmed internal rc oscillator ? slow clock internal rc o scillator as permanent low-power mode device clock ? high speed 80mhz internal rc oscillator ? low power 32khz internal rc oscillator ? pll up to 240mhz for device clock and for usb 42023gs?03/2014 atsam ---e arm-based flash mcu sam4l series summary
2 42023gs?sam?03/2014 atsam4l8/l4/l2 ? digital frequency locked loop (dfll) with wide input range ? up to 16 peripheral dma (pdca) channels ? peripherals ? usb 2.0 device and embedded host: 12 mbps, up to 8 bidirectional endpoints and multi-packet ping-pong mode. on- chip transceiver ? liquid crystal display (l cd) module with capacity up to 40 se gments and up to 4 common terminals ? one usart with iso7816, irda?, rs-485, spi, manchester and lin mode ? three usart with spi mode ? one picouart for extended uart wa ke-up capabilities in all sleep modes ? windowed watchdog timer (wdt) ? asynchronous timer (ast) with real-time clock ca pability, counter or ca lendar mode supported ? frequency meter (freqm) for accurate measuring of clock frequency ? six 16-bit timer/counter (tc) channels wi th capture, waveform, compare and pwm mode ? one master/slave serial peripheral inte rface (spi) with ch ip select signals ? four master and two slave two-wire in terfaces (twi), up to 3.4mbit/s i 2 c-compatible ? one advanced encryption system (aes) with 128-bit key length ? one 16-channel adc 300ksps (adc) with up to 12 bits resolution ? one dac 500ksps (dacc) with up to 10 bits resolution ? four analog comparators (acifc) with optional window detection ? capacitive touch module (catb) supporting up to 32 buttons ? audio bitstream dac (abdacb) suitable for stereo audio ? inter-ic sound (iisc) controller, compliant with inter-ic sound (i 2 s) specification ? peripheral event system for direct pe ripheral to periph eral communication ? 32-bit cyclic redundancy ch eck calculation unit (crccu) ? random generator (trng) ? parallel capture module (parc) ? glue logic controller (gloc) ? i/o ? up to 75 i/o lines with external interr upt capability (edge or level sensitivity), debouncing, glitch filtering and slew-rate control ? up to six high-drive i/o pins ? single 1.68-3.6v power supply ? packages ? 100-lead lqfp, 14 x 14 mm, pitch 0.5 mm/100-ball vfbga, 7x7 mm, pitch 0.65 mm ? 64-lead lqfp, 10 x 10 mm, pitch 0.5 mm/64-pad qfn 9x9 mm, pitch 0.5 mm ? 64-ball wlcsp, 4,314x4,434 mm, pitch 0.5 mm for sam4lc4/2 and sam4ls4/2 series ? 64-ball wlcsp, 5,270x5,194 mm, pitch 0.5 mm for sam4lc8 and sam4ls8 series ? 48-lead lqfp, 7 x 7 mm, pitch 0.5 mm/48-pad qfn 7x7 mm, pitch 0.5 mm
3 42023gs?sam?03/2014 atsam4l8/l4/l2 1. description atmel's sam4l series is a member of a family of flash microcontrollers based on the high per- formance 32-bit arm cortex-m4 risc processor running at frequencies up to 48mhz. the processor implements a memory protection unit (mpu) and a fast and flexible interrupt con- troller for supporting modern and real-time operating systems. the atsam4l8/l4/l2 embeds state-of-the-art picopower technology for ultra-low power con- sumption. combined power control techniques are used to bring active current consumption down to 90a/mhz. the device allows a wide range of options between functionality and power consumption, giving the user th e ability to reach the lowest po ssible power consumption with the feature set required for the application. on-chi p regulator improves pow er efficiency when used in swichting mode with an external inductor or can be used in linear mode if application is noise sensitive. the atsam4l8/l4/l2 supports 4 power saving strategies. the sleep mode put the cpu in idle mode and offers different sub-modes which automatically switch off/on bus clocks, pll, oscillators. the wait and retention modes prov ide full logic and ram retention, associated with fast wake-up capability (<1.5 s) and a very low consumption of, respectively, 3 a and 1.5 a. in addition, wait mode supports sleepwalking features. in backup mode, cpu, peripher- als and ram are powered off and, while consuming less than 0.5a, the device is able to wake- up from external interrupts. the atsam4l8/l4/l2 incorporates on-chip flash tightly coupled to a low power cache (lpcache) for active consumption optimization and sram memories for fast access. the lcd controller is intended for monochrome passive liquid crystal display (lcd) with up to 4 common terminals and up to 40 segments terminals. dedicated low power waveform, con- trast control, extended interrupt mode, selectable frame frequency and blink functionality are supported to offload the cpu, reduce interrupts and reduce power consumption. the controller includes integrated lcd buffers and integrated power supply voltage. the low-power and high performance capacitive touch module (catb) is introduced to meet the demand for a low power capacitive touch solution that could be used to handle buttons, sliders and wheels. the catb provides excellent si gnal performance, as well as autonomous touch and proximity detection for up to 32 sensors. this solution includes an advanced sequencer in addition to an hardware filtering unit. the advanced encryption standard module (aesa) is compliant with the fips (federal infor- mation processing standard) publication 197, advanced encryption standard (aes) , which specifies a symmetric block cipher that is used to encrypt and decrypt electronic data. encryp- tion is the transformation of a usable message, called the plaintext , into an unreadable form, called the ciphertext . on the other hand, decryption is the transformation that recovers the plain- text from the ciphertext. aesa supports 128 bits cryptographi c key sizes. the peripheral direct memory access (dma) controller enables data transfers between periph- erals and memories without processor involvement. the peripheral dma controller drastically reduces processing overhead when transferring continuous and large data streams. the peripheral event system (pes) allows peripherals to receive, react to, and send peripheral events without cpu intervention. asynchronous interrupts allow advanced peripheral operation in low power modes. the power manager (pm) improves design flexibility and securi ty. the power ma nager supports sleepwalking functionality, by which a module can be selectively activated based on peripheral
4 42023gs?sam?03/2014 atsam4l8/l4/l2 events, even in sleep modes where the module clock is stopped. power monitoring is supported by on-chip power-on reset (por18, por33), brown-out detectors (bod18, bod33). the device features several oscillators, such as phase locked loop (pll), digital frequency locked loop (dfll), oscillator 0 (osc0), internal rc 4,8,12mh z oscillator (rcfast), system rc oscillator (rcsys), internal rc 80mhz, in ternal 32khz rc and 32khz crystal oscillator. either of these oscillators can be used as source for the system clock. the dfll is a program- mable internal oscillator from 40 to 150mhz. it can be tuned to a high accuracy if an accurate reference clock is running, e.g. the 32khz crystal oscillator. the watchdog timer (wdt) will reset the device unless it is periodically serviced by the soft- ware. this allows the device to recover from a condition that has caused the system to be unstable. the asynchronous timer (ast) combined with the 32khz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeou t of up to 136 years. the ast can operate in counter or calendar mode. the frequency meter (freqm) allows accurate measuring of a clock frequency by comparing it to a known reference clock. the full-speed usb 2.0 device and embedded host interface (usbc) supports several usb classes at the same ti me utilizing the rich en d-point configuration. the device includes six identical 16-bit timer/counter (tc) channels. each channel can be inde- pendently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. the atsam4l8/l4/l2 also features many communi cation interfaces, like usart, spi, or twi, for communication intensive applications. the usart supports different communication modes, like spi mode and lin mode. a general purpose 16-channel adc is provided, as well as four analog comparators (acifc). the adc can operate in 12-bit mode at full speed. the analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. atmel offers the qtouch library for embedding capacitive touch buttons, sliders, and wheels functionality. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys as well as adjacent key suppression ? (aks ? ) technol- ogy for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop, and debug your own touch applications. the audio bitstream dac (abdacb) converts a 16- bit sample value to a digital bitstream with an average value proportional to the sample value. two channels are supported, making the abdac particularly suitable for stereo audio. the inter-ic sound controller (iis c) provides a 5-bit wide, bidi rectional, synchronous, digital audio link with external audio devices. the controll er is compliant with the inter-ic sound (i2s) bus specification.
5 42023gs?sam?03/2014 atsam4l8/l4/l2 2. overview 2.1 block diagram figure 2-1. block diagram biasl,biash caph,capl asynchronous timer peripheral dma controller hsb-pb bridge b hsb-pb bridge a s mm sm external interrupt controller high speed bus matrix generalpurpose i/os general purpose i/os pa pb pc extint[8..1] nmi pa pb pc spi dma miso, mosi npcs[3..0] usart0 usart1 usart2 usart3 dma rxd txd clk rts, cts watchdog timer sck jtag & serial wire tdo tdi tms configuration registers bus s arm cortex-m4 processor fmax 48 mhz in-circuit emulator nvic twi master 0 twi master 1 twi master 2 twi master 3 dma twi slave 0 twi slave 1 dma reset controller sleep controller clock controller tck twck twd twck twd usbc 8 endpoints dma inter-ic sound controller audio bitstream dac dma abdac[1..0] abdacn[1..0] isck iws isdi isdo imck clk m s d m dp system control interface gclk[3:0] vddcore vddout rcsys x i n 0 x o u t 0 osc0 dfll rc32k pll gclk_in[1:0] s memory protection unit instruction/ data system system tap hsb-pb bridge d s power manager resetn backup system control interface backup registers capacitive touch module backup power manager ldo/ switching regulator dma sense[69..0] dis glue logic controller in[7..0] out[1..0] timer/counter 0 timer/counter 1 a[2..0] b[2..0] clk[2..0] frequency meter 16-channel 12-bit adc interface dma trigger ad[14..0] advrefp ac interface acrefn acan[3..0] acap[3..0] hsb-pb bridge c rcfast parallel capture controller s backup domain pcck dma 32-bit crc calculation unit vddin true random generator 10-bit dac interface dma dacout picouart rxd pcen1,pcen2 pcdata[7..0] lcd controller seg[39..0] com[3..0] dma 128-bit aes s dma flash controller low power cache 512/256/128 kb flash hram controller 64/32 kb ram system management access port rc80m x i n 3 2 x o u t 3 2 osc32 peripheral event controller pad_evt[3..0] generic clock
6 42023gs?sam?03/2014 atsam4l8/l4/l2 2.2 configuration summary table 2-1. sub series summary feature atsam4lc atsam4ls segment lcd yes no aesa yes no usb device + host device only table 2-2. atsam4lc configuration summary feature atsam4lc8/4/2c atsam 4lc8/4/2b atsam4lc8/4/2a number of pins 100 64 48 max frequency 48mhz flash 512/256/128kb sram 64/32/32kb segment lcd 4x40 4x23 4x13 gpio 75 43 27 high-drive pins 6 3 1 external interrupts 8 + 1 nmi twi 2 masters + 2 masters/slaves 1 master + 1 master/slave usart 4 3 in lc sub series 4 in ls sub series picouart 1 0 peripheral dma channels 16 aesa 1 peripheral event system 1 spi 1 asynchronous timers 1 timer/counter channels 6 3 parallel capture inputs 8 frequency meter 1 watchdog timer 1 power manager 1 glue logic lut 2 1
7 42023gs?sam?03/2014 atsam4l8/l4/l2 . oscillators digital frequency locked loop 20-150mhz (dfll) phase locked loop 48-240mhz (pll) crystal oscillator 0.6-30mhz (osc0) crystal oscillator 32khz (osc32k) rc oscillator 80mhz (rc80m) rc oscillator 4,8,12mhz (rcfast) rc oscillator 115khz (rcsys) rc oscillator 32khz (rc32k) adc 15-channel 7-channel 3-channel dac 1-channel analog comparators 4 2 1 catb sensors 32 32 26 usb 1 audio bitstream dac 1 iis controller 1 packages tqfp/vfbga tqfp/qfn/ wlcsp tqfp/qfn table 2-3. atsam4ls configuration summary feature atsam4ls8/4/2c atsam 4ls8/4/2b atsam4ls8/4/2a number of pins 100 64 48 max frequency 48mhz flash 512/256/128kb sram 64/32/32kb segment lcd na gpio 80 48 32 high-drive pins 6 3 1 external interrupts 8 + 1 nmi twi 2 masters + 2 masters/slaves 1 master + 1 master/slave usart 4 3 in lc sub series 4 in ls sub series picouart 1 0 peripheral dma channels 16 aesa 1 peripheral event system 1 spi 1 asynchronous timers 1 table 2-2. atsam4lc configuration summary feature atsam4lc8/4/2c atsam 4lc8/4/2b atsam4lc8/4/2a
8 42023gs?sam?03/2014 atsam4l8/l4/l2 timer/counter channels 6 3 parallel capture inputs 8 frequency meter 1 watchdog timer 1 power manager 1 glue logic lut 2 1 oscillators digital frequency locked loop 20-150mhz (dfll) phase locked loop 48-240mhz (pll) crystal oscillator 0.6-30mhz (osc0) crystal oscillator 32khz (osc32k) rc oscillator 80mhz (rc80m) rc oscillator 4,8,12mhz (rcfast) rc oscillator 115khz (rcsys) rc oscillator 32khz (rc32k) adc 15-channel 7-channel 3-channel dac 1-channel analog comparators 4 2 1 catb sensors 32 32 26 usb 1 audio bitstream dac 1 iis controller 1 packages tqfp/vfbga tqfp/qfn/ wlcsp tqfp/qfn table 2-3. atsam4ls configuration summary feature atsam4ls8/4/2c atsam 4ls8/4/2b atsam4ls8/4/2a
9 42023gs?sam?03/2014 atsam4l8/l4/l2 3. package and pinout 3.1 package the device pins are multiplexed with peripheral functions as described in section 3.2 ?peripheral multiplexing on i/o lines? on page 19 . 3.1.1 atsam4lcx pinout figure 3-1. atsam4lc tqfp100 pinout pc00 1 pc01 2 pc02 3 pc03 4 pa00 5 pa01 6 gnd 7 vddio 8 pc04 9 pc05 10 pc06 11 pa02 12 reset_n 13 vddcore 14 gnd 15 vddout 16 vddin 17 tck 18 pa03 19 pb00 20 pb01 21 pb02 22 pb03 23 pa04 24 pa05 25 xin32 26 xout32 27 pb04 28 pb05 29 pa06 30 pa07 31 advrefn 32 gndana 33 advrefp 34 vddana 35 pc07 36 pc08 37 pc09 38 pc10 39 pc11 40 pc12 41 pc13 42 pc14 43 pa08 44 pb06 45 pb07 46 pa09 47 pa10 48 pa11 49 pa12 50 pb11 75 pb10 74 pb09 73 pb08 72 pc23 71 pc22 70 pc21 69 pc20 68 pa17 67 pa16 66 pa15 65 pa14 64 pa13 63 pc19 62 pc18 61 pc17 60 pc16 59 pc15 58 vlcdin 57 gnd 56 biasl 55 biash 54 vlcd 53 capl 52 caph 51 pa18 76 pa19 77 pa20 78 pc24 79 pc25 80 pc26 81 pc27 82 pc28 83 pc29 84 pc30 85 pc31 86 vddio 87 vddio 88 pb12 89 pb13 90 pa21 91 pa22 92 pb14 93 pb15 94 pa23 95 pa24 96 vddio 97 pa25 98 pa26 99 gnd 100
10 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-2. atsam4lc vfbga100 pinout 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k vdd core vddout pa05 gnd vddin pa04 pc00 gnd vddio pa02 xin32 xout32 pb04 pb05 pa06 pa07 gndana ad vrefp pc07 pc08 pc09 pc10 pc11 pc12 pc13 pc14 pa08 pb06 pb07 pa09 pa10 pa11 pa12 caph capl vlcd biash biasl gnd vlcdin pc15 pc16 pc17 pc18 pc19 pa13 pa14 pa15 pa16 pa17 pc20 pc21 pc22 pc23 pb08 pb09 pb10 pb11 pa18 pa19 pa20 pc24 pc25 pc26 pc27 pc28 pc29 pc30 pc31 vddio vddio pb12 pb13 pa21 pa22 pb14 pb15 pa23 pa24 vddio pa25 pa26 gnd pc01 pc02 pc03 pa00 pa01 pc04 pc05 pc06 reset_n tck pa03 pb00 pb01 pb02 pb03 ad vrefn vddana
11 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-3. atsam4lc wlcsp64 pinout 8 7 6 5 4 3 2 1 a b c d e f g h capl pa09 pb04 ad vrefp vddana gndana pa12 caph xin32 pb01 vddin pb03 pa05 pa04 pb00 pa03 tck pb02 vdd core pb05 reset_n pa02 pb14 gnd pa26 pa24 vddio pa22 pa25 pa23 pb15 pa00 pa21 pa01 vddio pa20 pb11 pa19 pa18 pa17 pb10 pa16 vlcdin pb09 pa15 gnd pa14 biasl pb08 biash pa13 pa11 vlcd pa07 pb07 pa10 pb06 pa08 xout32 pb12 pb13 pa06 vddout gnd
12 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-4. atsam4lc tqfp64/qfn64 pinout pa00 1 pa01 2 pa02 3 reset_n 4 vddcore 5 gnd 6 vddout 7 vddin 8 tck 9 pa03 10 pb00 11 pb01 12 pb02 13 pb03 14 pa04 15 pa05 16 xin32 17 xout32 18 pb04 19 pb05 20 pa06 21 pa07 22 gndana 23 advrefp 24 vddana 25 pa08 26 pb06 27 pb07 28 pa09 29 pa10 30 pa11 31 pa12 32 pb11 48 pb10 47 pb09 46 pb08 45 pa17 44 pa16 43 pa15 42 pa14 41 pa13 40 vlcdin 39 gnd 38 biasl 37 biash 36 vlcd 35 capl 34 caph 33 pa18 49 pa19 50 pa20 51 vddio 52 pb12 53 pb13 54 pa21 55 pa22 56 pb14 57 pb15 58 pa23 59 pa24 60 vddio 61 pa25 62 pa26 63 gnd 64
13 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-5. atsam4lc tqfp48/qfn48 pinout pa00 1 pa01 2 pa02 3 reset_n 4 vddcore 5 gnd 6 vddout 7 vddin 8 tck 9 pa03 10 pa04 11 pa05 12 xin32 13 xout32 14 pa06 15 pa07 16 gndana 17 advrefp 18 vddana 19 pa08 20 pa09 21 pa10 22 pa11 23 pa12 24 pa17 36 pa16 35 pa15 34 pa14 33 pa13 32 vlcdin 31 gnd 30 biasl 29 biash 28 vlcd 27 capl 26 caph 25 pa18 37 pa19 38 pa20 39 vddio 40 pa21 41 pa22 42 pa23 43 pa24 44 vddio 45 pa25 46 pa26 47 gnd 48
14 42023gs?sam?03/2014 atsam4l8/l4/l2 3.1.2 atsam4lsx pinout figure 3-6. atsam4ls tqfp100 pinout pc00 1 pc01 2 pc02 3 pc03 4 pa00 5 pa01 6 gnd 7 vddio 8 pc04 9 pc05 10 pc06 11 pa02 12 reset_n 13 vddcore 14 gnd 15 vddout 16 vddin 17 tck 18 pa03 19 pb00 20 pb01 21 pb02 22 pb03 23 pa04 24 pa05 25 xin32 26 xout32 27 pb04 28 pb05 29 pa06 30 pa07 31 advrefn 32 gndana 33 advrefp 34 vddana 35 pc07 36 pc08 37 pc09 38 pc10 39 pc11 40 pc12 41 pc13 42 pc14 43 pa08 44 pb06 45 pb07 46 pa09 47 pa10 48 pa11 49 pa12 50 pb11 75 pb10 74 pb09 73 pb08 72 pc23 71 pc22 70 pc21 69 pc20 68 pa17 67 pa16 66 pa15 65 pa14 64 pa13 63 pc19 62 pc18 61 pc17 60 pc16 59 pc15 58 pa31 57 pa30 56 vddio 55 gnd 54 pa29 53 pa28 52 pa27 51 pa18 76 pa19 77 pa20 78 pc24 79 pc25 80 pc26 81 pc27 82 pc28 83 pc29 84 pc30 85 pc31 86 vddio 87 vddio 88 pb12 89 pb13 90 pa21 91 pa22 92 pb14 93 pb15 94 pa23 95 pa24 96 vddio 97 pa25 98 pa26 99 gnd 100
15 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-7. atsam4ls vfbga100 pinout 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k vdd core vddout pa05 gnd vddin pa04 pc00 gnd vddio pa02 xin32 xout32 pb04 pb05 pa06 pa07 gndana ad vrefp pc07 pc08 pc09 pc10 pc11 pc12 pc13 pc14 pa08 pb06 pb07 pa09 pa10 pa11 pa12 pa27 pa28 pa29 gnd vddio pa30 pa31 pc15 pc16 pc17 pc18 pc19 pa13 pa14 pa15 pa16 pa17 pc20 pc21 pc22 pc23 pb08 pb09 pb10 pb11 pa18 pa19 pa20 pc24 pc25 pc26 pc27 pc28 pc29 pc30 pc31 vddio vddio pb12 pb13 pa21 pa22 pb14 pb15 pa23 pa24 vddio pa25 pa26 gnd pc01 pc02 pc03 pa00 pa01 pc04 pc05 pc06 reset_n tck pa03 pb00 pb01 pb02 pb03 ad vrefn vddana
16 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-8. atsam4ls wlcsp64 pinout 8 7 6 5 4 3 2 1 a b c d e f g h pa28 pa09 pb04 ad vrefp vddana gndana pa12 pa27 xin32 pb01 vddin pb03 pa05 pa04 pb00 pa03 tck pb02 vdd core pb05 reset_n pa02 pb14 gnd pa26 pa24 vddio pa22 pa25 pa23 pb15 pa00 pa21 pa01 vddio pa20 pb11 pa19 pa18 pa17 pb10 pa16 pa31 pb09 pa15 pa30 pa14 vddio pb08 gnd pa13 pa11 pa29 pa07 pb07 pa10 pb06 pa08 xout32 pb12 pb13 pa06 vddout gnd
17 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-9. atsam4ls tqfp64/qfn64 pinout pa00 1 pa01 2 pa02 3 reset_n 4 vddcore 5 gnd 6 vddout 7 vddin 8 tck 9 pa03 10 pb00 11 pb01 12 pb02 13 pb03 14 pa04 15 pa05 16 xin32 17 xout32 18 pb04 19 pb05 20 pa06 21 pa07 22 gndana 23 advrefp 24 vddana 25 pa08 26 pb06 27 pb07 28 pa09 29 pa10 30 pa11 31 pa12 32 pb11 48 pb10 47 pb09 46 pb08 45 pa17 44 pa16 43 pa15 42 pa14 41 pa13 40 pa31 39 pa30 38 vddio 37 gnd 36 pa29 35 pa28 34 pa27 33 pa18 49 pa19 50 pa20 51 vddio 52 pb12 53 pb13 54 pa21 55 pa22 56 pb14 57 pb15 58 pa23 59 pa24 60 vddio 61 pa25 62 pa26 63 gnd 64
18 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 3-10. atsam4ls tqfp48/qfn48 pinout see section 3.3 ?signals description? on page 31 for a description of the various peripheral signals. refer to ?electrical characteristics? on page 99 for a description of the electrical properties of the pin types used. pa00 1 pa01 2 pa02 3 reset_n 4 vddcore 5 gnd 6 vddout 7 vddin 8 tck 9 pa03 10 pa04 11 pa05 12 xin32 13 xout32 14 pa06 15 pa07 16 gndana 17 advrefp 18 vddana 19 pa08 20 pa09 21 pa10 22 pa11 23 pa12 24 pa17 36 pa16 35 pa15 34 pa14 33 pa13 32 pa31 31 pa30 30 vddio 29 gnd 28 pa29 27 pa28 26 pa27 25 pa18 37 pa19 38 pa20 39 vddio 40 pa21 41 pa22 42 pa23 43 pa24 44 vddio 45 pa25 46 pa26 47 gnd 48
19 42023gs?sam?03/2014 atsam4l8/l4/l2 3.2 peripheral multiplexing on i/o lines 3.2.1 multiplexed signals each gpio line can be assigned to one of the peripheral functions. the following tables ( section 3-1 ?100-pin gpio controller function multiplexing? on page 19 to section 3-4 ?48-pin gpio controller function mult iplexing? on page 28 ) describes the peripheral signals multiplexed to the gpio lines. peripheral functions that are not relevant in some parts of the family are grey-shaded. for description of differents s upply voltage source, refer to the section 6. ?power and startup considerations? on page 46 . table 3-1. 100-pin gpio controller function multiplexing (sheet 1 of 4) atsam4lc atsam4ls pin gpio supply gpio functions qfn vfbga qfn vfbga abcdefg 5 b9 5 b9 pa00 0 vddio 6 b8 6 b8 pa01 1 vddio 12 a7 12 a7 pa02 2 vddin s c i f gclk0 s p i npcs0 c a t b dis 19 b3 19 b3 pa03 3 vddin s p i miso 24 a2 24 a2 pa04 4 vddana a d c i f e ad0 u s a r t 0 clk e i c extint2 g l o c in1 c a t b sense0 25 a1 25 a1 pa05 5 vddana a d c i f e ad1 u s a r t 0 rxd e i c extint3 g l o c in2 a d c i f e trigger c a t b sense1 30 c3 30 c3 pa06 6 vddana d a c c vout u s a r t 0 rts e i c extint1 g l o c in0 a c i f c acan0 c a t b sense2 31 d3 31 d3 pa07 7 vddana a d c i f e ad2 u s a r t 0 txd e i c extint4 g l o c in3 a c i f c acap0 c a t b sense3 44 g2 44 g2 pa08 8 lcda u s a r t 0 rts t c 0 a0 pevc pad evt0 g l o c out0 lcdca seg23 c a t b sense4 47 f5 47 f5 pa09 9 lcda u s a r t 0 cts t c 0 b0 pevc pad evt1 pa r c pcdata0 lcdca com3 c a t b sense5 48 h2 48 h2 pa10 10 lcda u s a r t 0 clk t c 0 a1 pevc pad evt2 pa r c pcdata1 lcdca com2 c a t b sense6 49 h3 49 h3 pa11 11 lcda u s a r t 0 rxd t c 0 b1 pevc pad evt3 pa r c pcdata2 lcdca com1 c a t b sense7 50 j2 50 j2 pa12 12 lcda u s a r t 0 txd t c 0 a2 pa r c pcdata3 lcdca com0 c a t b dis 63 h5 63 h5 pa13 13 lcda u s a r t 1 rts t c 0 b2 s p i npcs1 pa r c pcdata4 lcdca seg5 c a t b sense8 64 k7 64 k7 pa14 14 lcda u s a r t 1 clk t c 0 clk0 s p i npcs2 pa r c pcdata5 lcdca seg6 c a t b sense9 65 g5 65 g5 pa15 15 lcda u s a r t 1 rxd t c 0 clk1 s p i npcs3 pa r c pcdata6 lcdca seg7 c a t b sense10
20 42023gs?sam?03/2014 atsam4l8/l4/l2 66 j7 66 j7 pa16 16 lcda u s a r t 1 txd t c 0 clk2 e i c extint1 pa r c pcdata7 lcdca seg8 c a t b sense11 67 h6 67 h6 pa17 17 lcda u s a r t 2 rts a b d a c b dac0 e i c extint2 pa r c pcck lcdca seg9 c a t b sense12 76 k10 76 k10 pa18 18 lcda u s a r t 2 clk a b d a c b dacn0 e i c extint3 pa r c pcen1 lcdca seg18 c a t b sense13 77 j10 77 j10 pa19 19 lcda u s a r t 2 rxd a b d a c b dac1 e i c extint4 pa r c pcen2 s c i f gclk0 lcdca seg19 c a t b sense14 78 h10 78 h10 pa20 20 lcda u s a r t 2 txd a b d a c b dacn1 e i c extint5 g l o c in0 s c i f gclk1 lcdca seg20 c a t b sense15 91 e9 91 e9 pa21 21 lcdc s p i miso u s a r t 1 cts e i c extint6 g l o c in1 t w i m 2 twd lcdca seg34 c a t b sense16 92 e10 92 e10 pa22 22 lcdc s p i mosi u s a r t 2 cts e i c extint7 g l o c in2 t w i m 2 twck lcdca seg35 c a t b sense17 95 d6 95 d6 pa23 23 lcdc s p i sck t w i m s 0 twd e i c extint8 g l o c in3 s c i f gclk in0 lcdca seg38 c a t b dis 96 d10 96 d10 pa24 24 lcdc s p i npcs0 t w i m s 0 twck g l o c out0 s c i f gclk in1 lcdca seg39 c a t b sense18 98 d9 98 d9 pa25 25 vddio u s b c dm u s a r t 2 rxd c a t b sense19 99 c9 99 c9 pa26 26 vddio u s b c dp u s a r t 2 txd c a t b sense20 51 k1 pa27 27 lcda s p i miso i i s c isck a b d a c b dac0 g l o c in4 u s a r t 3 rts c a t b sense0 52 j1 pa28 28 lcda s p i mosi i i s c isdi a b d a c b dacn0 g l o c in5 u s a r t 3 cts c a t b sense1 53 k2 pa29 29 lcda s p i sck i i s c iws a b d a c b dac1 g l o c in6 u s a r t 3 clk c a t b sense2 56 k4 pa30 30 lcda s p i npcs0 i i s c isdo a b d a c b dacn1 g l o c in7 u s a r t 3 rxd c a t b sense3 57 k5 pa31 31 lcda s p i npcs1 i i s c imck a b d a c b clk g l o c out1 u s a r t 3 txd c a t b dis 20 j3 20 j3 pb00 32 vddin t w i m s 1 twd u s a r t 0 rxd c a t b sense21 21 d5 21 d5 pb01 33 vddin t w i m s 1 twck u s a r t 0 txd e i c extint0 c a t b sense22 22 e5 22 e5 pb02 34 vddana a d c i f e ad3 u s a r t 1 rts a b d a c b dac0 i i s c isck a c i f c acbn0 c a t b sense23 23 c4 23 c4 pb03 35 vddana a d c i f e ad4 u s a r t 1 clk a b d a c b dacn0 i i s c isdi a c i f c acbp0 c a t b dis 28 c1 28 c1 pb04 36 vddana a d c i f e ad5 u s a r t 1 rxd a b d a c b dac1 i i s c isdo d a c c ext trig0 c a t b sense24 29 b1 29 b1 pb05 37 vddana a d c i f e ad6 u s a r t 1 txd a b d a c b dacn1 i i s c imck c a t b sense25 45 g3 45 g3 pb06 38 lcda u s a r t 3 rts g l o c in4 i i s c iws lcdca seg22 c a t b sense26 46 h1 46 h1 pb07 39 lcda u s a r t 3 cts g l o c in5 t c 0 a0 lcdca seg21 c a t b sense27 table 3-1. 100-pin gpio controller function multiplexing (sheet 2 of 4) atsam4lc atsam4ls pin gpio supply gpio functions qfn vfbga qfn vfbga abcdefg
21 42023gs?sam?03/2014 atsam4l8/l4/l2 72 g6 72 g6 pb08 40 lcda u s a r t 3 clk g l o c in6 t c 0 b0 lcdca seg14 c a t b sense28 73 g7 73 g7 pb09 41 lcda u s a r t 3 rxd p e v c pad evt2 g l o c in7 t c 0 a1 lcdca seg15 c a t b sense29 74 g8 74 g8 pb10 42 lcda u s a r t 3 txd p e v c pad evt3 g l o c out1 t c 0 b1 s c i f gclk0 lcdca seg16 c a t b sense30 75 k9 75 k9 pb11 43 lcda u s a r t 0 cts s p i npcs2 t c 0 a2 s c i f gclk1 lcdca seg17 c a t b sense31 89 e7 89 e7 pb12 44 lcdc u s a r t 0 rts s p i npcs3 pevc pad evt0 t c 0 b2 s c i f gclk2 lcdca seg32 c a t b dis 90 e8 90 e8 pb13 45 lcdc u s a r t 0 clk s p i npcs1 pevc pad evt1 t c 0 clk0 s c i f gclk3 lcdca seg33 c a t b sense0 93 d7 93 d7 pb14 46 lcdc u s a r t 0 rxd s p i miso t w i m 3 twd t c 0 clk1 s c i f gclk in0 lcdca seg36 c a t b sense1 94 d8 94 d8 pb15 47 lcdc u s a r t 0 txd s p i mosi t w i m 3 twck t c 0 clk2 s c i f gclk in1 lcdca seg37 c a t b sense2 1 a10 1 a10 pc00 64 vddio s p i npcs2 u s a r t 0 clk t c 1 a0 c a t b sense3 2 c8 2 c8 pc01 65 vddio s p i npcs3 u s a r t 0 rts t c 1 b0 c a t b sense4 3 c7 3 c7 pc02 66 vddio s p i npcs1 u s a r t 0 cts u s a r t 0 rxd t c 1 a1 c a t b sense5 4 b7 4 b7 pc03 67 vddio s p i npcs0 e i c extint5 u s a r t 0 txd t c 1 b1 c a t b sense6 9 c5 9 c5 pc04 68 vddio s p i miso e i c extint6 t c 1 a2 c a t b sense7 10 c6 10 c6 pc05 69 vddio s p i mosi e i c extint7 t c 1 b2 c a t b dis 11 b6 11 b6 pc06 70 vddio s p i sck e i c extint8 t c 1 clk0 c a t b sense8 36 f2 36 f2 pc07 71 vddana a d c i f e ad7 u s a r t 2 rts pevc pad evt0 t c 1 clk1 c a t b sense9 37 e3 37 e3 pc08 72 vddana a d c i f e ad8 u s a r t 2 clk pevc pad evt1 t c 1 clk2 u s a r t 2 cts c a t b sense10 38 f1 38 f1 pc09 73 vddana a d c i f e ad9 u s a r t 3 rxd a b d a c b dac0 i i s c isck a c i f c acan1 c a t b sense11 39 d4 39 d4 pc10 74 vddana a d c i f e ad10 u s a r t 3 txd a b d a c b dacn0 i i s c isdi a c i f c acap1 c a t b sense12 40 e4 40 e4 pc11 75 vddana a d c i f e ad11 u s a r t 2 rxd pevc pad evt2 c a t b sense13 41 f3 41 f3 pc12 76 vddana a d c i f e ad12 u s a r t 2 txd a b d a c b clk i i s c iws c a t b sense14 42 f4 42 f4 pc13 77 vddana a d c i f e ad13 u s a r t 3 rts a b d a c b dac1 i i s c isdo a c i f c acbn1 c a t b sense15 43 g1 43 g1 pc14 78 vddana a d c i f e ad14 u s a r t 3 clk a b d a c b dacn1 i i s c imck a c i f c acbp1 c a t b dis 58 j5 58 j5 pc15 79 lcda t c 1 a0 g l o c in4 lcdca seg0 c a t b sense16 table 3-1. 100-pin gpio controller function multiplexing (sheet 3 of 4) atsam4lc atsam4ls pin gpio supply gpio functions qfn vfbga qfn vfbga abcdefg
22 42023gs?sam?03/2014 atsam4l8/l4/l2 59 j6 59 j6 pc16 80 lcda t c 1 b0 g l o c in5 lcdca seg1 c a t b sense17 60 h4 60 h4 pc17 81 lcda t c 1 a1 g l o c in6 lcdca seg2 c a t b sense18 61 k6 61 k6 pc18 82 lcda t c 1 b1 g l o c in7 lcdca seg3 c a t b sense19 62 g4 62 g4 pc19 83 lcda t c 1 a2 g l o c out1 lcdca seg4 c a t b sense20 68 h7 68 h7 pc20 84 lcda t c 1 b2 lcdca seg10 c a t b sense21 69 k8 69 k8 pc21 85 lcda t c 1 clk0 pa r c pcck lcdca seg11 c a t b sense22 70 j8 70 j8 pc22 86 lcda t c 1 clk1 pa r c pcen1 lcdca seg12 c a t b sense23 71 h8 71 h8 pc23 87 lcda t c 1 clk2 pa r c pcen2 lcdca seg13 c a t b dis 79 j9 79 j9 pc24 88 lcdb u s a r t 1 rts e i c extint1 pevc pad evt0 pa r c pcdata0 lcdca seg24 c a t b sense24 80 h9 80 h9 pc25 89 lcdb u s a r t 1 clk e i c extint2 pevc pad evt1 pa r c pcdata1 lcdca seg25 c a t b sense25 81 g9 81 g9 pc26 90 lcdb u s a r t 1 rxd e i c extint3 pevc pad evt2 pa r c pcdata2 s c i f gclk0 lcdca seg26 c a t b sense26 82 f6 82 f6 pc27 91 lcdb u s a r t 1 txd e i c extint4 pevc pad evt3 pa r c pcdata3 s c i f gclk1 lcdca seg27 c a t b sense27 83 g10 83 g10 pc28 92 lcdb u s a r t 3 rxd s p i miso g l o c in4 pa r c pcdata4 s c i f gclk2 lcdca seg28 c a t b sense28 84 f7 84 f7 pc29 93 lcdb u s a r t 3 txd s p i mosi g l o c in5 pa r c pcdata5 s c i f gclk3 lcdca seg29 c a t b sense29 85 f8 85 f8 pc30 94 lcdb u s a r t 3 rts s p i sck g l o c in6 pa r c pcdata6 s c i f gclk in0 lcdca seg30 c a t b sense30 86 f9 86 f9 pc31 95 lcdb u s a r t 3 clk s p i npcs0 g l o c out1 pa r c pcdata7 s c i f gclk in1 lcdca seg31 c a t b sense31 table 3-1. 100-pin gpio controller function multiplexing (sheet 4 of 4) atsam4lc atsam4ls pin gpio supply gpio functions qfn vfbga qfn vfbga abcdefg table 3-2. 64-pin gpio controller function multiplexing (sheet 1 of 3) atsam4lc atsam4ls pin gpio supply gpio functions qfp qfn qfp qfn abcdefg 11pa000vddio 22pa011vddio 3 3 pa02 2 vddin s c i f gclk0 s p i npcs0 c a t b dis 10 10 pa03 3 vddin s p i miso
23 42023gs?sam?03/2014 atsam4l8/l4/l2 15 15 pa04 4 vddana a d c i f e ad0 u s a r t 0 clk e i c extint2 g l o c in1 c a t b sense0 16 16 pa05 5 vddana a d c i f e ad1 u s a r t 0 rxd e i c extint3 g l o c in2 adcife trigger c a t b sense1 21 21 pa06 6 vddana d a c c vout u s a r t 0 rts e i c extint1 g l o c in0 a c i f c acan0 c a t b sense2 22 22 pa07 7 vddana a d c i f e ad2 u s a r t 0 txd e i c extint4 g l o c in3 a c i f c acap0 c a t b sense3 26 26 pa08 8 lcda u s a r t 0 rts t c 0 a0 p e v c pad evt0 g l o c out0 lcdca seg23 c a t b sense4 29 29 pa09 9 lcda u s a r t 0 cts t c 0 b0 p e v c pad evt1 p a r c pcdata0 lcdca com3 c a t b sense5 30 30 pa10 10 lcda u s a r t 0 clk t c 0 a1 p e v c pad evt2 p a r c pcdata1 lcdca com2 c a t b sense6 31 31 pa11 11 lcda u s a r t 0 rxd t c 0 b1 p e v c pad evt3 p a r c pcdata2 lcdca com1 c a t b sense7 32 32 pa12 12 lcda u s a r t 0 txd t c 0 a2 p a r c pcdata3 lcdca com0 c a t b dis 40 40 pa13 13 lcda u s a r t 1 rts t c 0 b2 s p i npcs1 p a r c pcdata4 lcdca seg5 c a t b sense8 41 41 pa14 14 lcda u s a r t 1 clk t c 0 clk0 s p i npcs2 p a r c pcdata5 lcdca seg6 c a t b sense9 42 42 pa15 15 lcda u s a r t 1 rxd t c 0 clk1 s p i npcs3 p a r c pcdata6 lcdca seg7 c a t b sense10 43 43 pa16 16 lcda u s a r t 1 txd t c 0 clk2 e i c extint1 p a r c pcdata7 lcdca seg8 c a t b sense11 44 44 pa17 17 lcda u s a r t 2 rts a b d a c b dac0 e i c extint2 p a r c pcck lcdca seg9 c a t b sense12 49 49 pa18 18 lcda u s a r t 2 clk a b d a c b dacn0 e i c extint3 p a r c pcen1 lcdca seg18 c a t b sense13 50 50 pa19 19 lcda u s a r t 2 rxd a b d a c b dac1 e i c extint4 p a r c pcen2 s c i f gclk0 lcdca seg19 c a t b sense14 51 51 pa20 20 lcda u s a r t 2 txd a b d a c b dacn1 e i c extint5 g l o c in0 s c i f gclk1 lcdca seg20 c a t b sense15 55 55 pa21 21 lcdc s p i miso u s a r t 1 cts e i c extint6 g l o c in1 t w i m 2 twd lcdca seg34 c a t b sense16 56 56 pa22 22 lcdc s p i mosi u s a r t 2 cts e i c extint7 g l o c in2 t w i m 2 twck lcdca seg35 c a t b sense17 59 59 pa23 23 lcdc s p i sck t w i m s 0 twd e i c extint8 g l o c in3 s c i f gclk in0 lcdca seg38 c a t b dis 60 60 pa24 24 lcdc s p i npcs0 t w i m s 0 twck g l o c out0 s c i f gclk in1 lcdca seg39 c a t b sense18 62 62 pa25 25 vddio u s b c dm u s a r t 2 rxd c a t b sense19 63 63 pa26 26 vddio u s b c dp u s a r t 2 txd c a t b sense20 table 3-2. 64-pin gpio controller function multiplexing (sheet 2 of 3) atsam4lc atsam4ls pin gpio supply gpio functions qfp qfn qfp qfn abcdefg
24 42023gs?sam?03/2014 atsam4l8/l4/l2 33 pa27 27 lcda s p i miso i i s c isck a b d a c b dac0 g l o c in4 u s a r t 3 rts c a t b sense0 34 pa28 28 lcda s p i mosi i i s c isdi a b d a c b dacn0 g l o c in5 u s a r t 3 cts c a t b sense1 35 pa29 29 lcda s p i sck i i s c iws a b d a c b dac1 g l o c in6 u s a r t 3 clk c a t b sense2 38 pa30 30 lcda s p i npcs0 i i s c isdo a b d a c b dacn1 g l o c in7 u s a r t 3 rxd c a t b sense3 39 pa31 31 lcda s p i npcs1 i i s c imck a b d a c b clk g l o c out1 u s a r t 3 txd c a t b dis 11 11 pb00 32 vddin t w i m s 1 twd u s a r t 0 rxd c a t b sense21 12 12 pb01 33 vddin t w i m s 1 twck u s a r t 0 txd e i c extint0 c a t b sense22 13 13 pb02 34 vddana a d c i f e ad3 u s a r t 1 rts a b d a c b dac0 i i s c isck a c i f c acbn0 c a t b sense23 14 14 pb03 35 vddana a d c i f e ad4 u s a r t 1 clk a b d a c b dacn0 i i s c isdi a c i f c acbp0 c a t b dis 19 19 pb04 36 vddana a d c i f e ad5 u s a r t 1 rxd a b d a c b dac1 i i s c isdo d a c c ext trig0 c a t b sense24 20 20 pb05 37 vddana a d c i f e ad6 u s a r t 1 txd a b d a c b dacn1 i i s c imck c a t b sense25 27 27 pb06 38 lcda u s a r t 3 rts g l o c in4 i i s c iws lcdca seg22 c a t b sense26 28 28 pb07 39 lcda u s a r t 3 cts g l o c in5 t c 0 a0 lcdca seg21 c a t b sense27 45 45 pb08 40 lcda u s a r t 3 clk g l o c in6 t c 0 b0 lcdca seg14 c a t b sense28 46 46 pb09 41 lcda u s a r t 3 rxd pevc pa d e vt 2 g l o c in7 t c 0 a1 lcdca seg15 c a t b sense29 47 47 pb10 42 lcda u s a r t 3 txd pevc pa d e vt 3 g l o c out1 t c 0 b1 s c i f gclk0 lcdca seg16 c a t b sense30 48 48 pb11 43 lcda u s a r t 0 cts s p i npcs2 t c 0 a2 s c i f gclk1 lcdca seg17 c a t b sense31 53 53 pb12 44 lcdc u s a r t 0 rts s p i npcs3 p e v c pad evt0 t c 0 b2 s c i f gclk2 lcdca seg32 c a t b dis 54 54 pb13 45 lcdc u s a r t 0 clk s p i npcs1 p e v c pad evt1 t c 0 clk0 s c i f gclk3 lcdca seg33 c a t b sense0 57 57 pb14 46 lcdc u s a r t 0 rxd s p i miso t w i m 3 twd t c 0 clk1 s c i f gclk in0 lcdca seg36 c a t b sense1 58 58 pb15 47 lcdc u s a r t 0 txd s p i mosi t w i m 3 twck t c 0 clk2 s c i f gclk in1 lcdca seg37 c a t b sense2 table 3-2. 64-pin gpio controller function multiplexing (sheet 3 of 3) atsam4lc atsam4ls pin gpio supply gpio functions qfp qfn qfp qfn abcdefg
25 42023gs?sam?03/2014 atsam4l8/l4/l2 table 3-3. 64-pin gpio controller function multiplexing for wlcsp package (sheet 1 of 3) atsam4lc atsam4ls pin gpio supply gpio functions wlcsp wlcsp abcdefg g4 g4 pa00 0 vddio g5 g5 pa01 1 vddio f3 f3 pa02 2 vddin s c i f gclk0 s p i npcs0 c a t b dis e2 e2 pa03 3 vddin s p i miso d3 d3 pa04 4 vddana a d c i f e ad0 u s a r t 0 clk e i c extint2 g l o c in1 c a t b sense0 c3 c3 pa05 5 vddana a d c i f e ad1 u s a r t 0 rxd e i c extint3 g l o c in2 a d c i f e trigger c a t b sense1 c4 c4 pa06 6 vddana d a c c vout u s a r t 0 rts e i c extint1 g l o c in0 a c i f c acan0 c a t b sense2 c5 c5 pa07 7 vddana a d c i f e ad2 u s a r t 0 txd e i c extint4 g l o c in3 a c i f c acap0 c a t b sense3 b4 b4 pa08 8 lcda u s a r t 0 rts t c 0 a0 pevc pad evt0 g l o c out0 lcdca seg23 c a t b sense4 a5 a5 pa09 9 lcda u s a r t 0 cts t c 0 b0 pevc pad evt1 pa r c pcdata0 lcdca com3 c a t b sense5 b6 b6 pa10 10 lcda u s a r t 0 clk t c 0 a1 pevc pad evt2 pa r c pcdata1 lcdca com2 c a t b sense6 b7 b7 pa11 11 lcda u s a r t 0 rxd t c 0 b1 pevc pad evt3 pa r c pcdata2 lcdca com1 c a t b sense7 a8 a8 pa12 12 lcda u s a r t 0 txd t c 0 a2 pa r c pcdata3 lcdca com0 c a t b dis c7 c7 pa13 13 lcda u s a r t 1 rts t c 0 b2 s p i npcs1 pa r c pcdata4 lcdca seg5 c a t b sense8 d7 d7 pa14 14 lcda u s a r t 1 clk t c 0 clk0 s p i npcs2 pa r c pcdata5 lcdca seg6 c a t b sense9 e7 e7 pa15 15 lcda u s a r t 1 rxd t c 0 clk1 s p i npcs3 pa r c pcdata6 lcdca seg7 c a t b sense10 f7 f7 pa16 16 lcda u s a r t 1 txd t c 0 clk2 e i c extint1 pa r c pcdata7 lcdca seg8 c a t b sense11 g8 g8 pa17 17 lcda u s a r t 2 rts a b d a c b dac0 e i c extint2 pa r c pcck lcdca seg9 c a t b sense12 g7 g7 pa18 18 lcda u s a r t 2 clk a b d a c b dacn0 e i c extint3 pa r c pcen1 lcdca seg18 c a t b sense13 g6 g6 pa19 19 lcda u s a r t 2 rxd a b d a c b dac1 e i c extint4 pa r c pcen2 s c i f gclk0 lcdca seg19 c a t b sense14 h7 h7 pa20 20 lcda u s a r t 2 txd a b d a c b dacn1 e i c extint5 g l o c in0 s c i f gclk1 lcdca seg20 c a t b sense15 h5 h5 pa21 21 lcdc s p i miso u s a r t 1 cts e i c extint6 g l o c in1 t w i m 2 twd lcdca seg34 c a t b sense16 f5 f5 pa22 22 lcdc s p i mosi u s a r t 2 cts e i c extint7 g l o c in2 t w i m 2 twck lcdca seg35 c a t b sense17
26 42023gs?sam?03/2014 atsam4l8/l4/l2 h3 h3 pa23 23 lcdc s p i sck t w i m s 0 twd e i c extint8 g l o c in3 s c i f gclk in0 lcdca seg38 c a t b dis g3 g3 pa24 24 lcdc s p i npcs0 t w i m s 0 twck g l o c out0 s c i f gclk in1 lcdca seg39 c a t b sense18 h2 h2 pa25 25 vddio u s b c dm u s a r t 2 rxd c a t b sense19 g2 g2 pa26 26 vddio u s b c dp u s a r t 2 txd c a t b sense20 a7 pa27 27 lcda s p i miso i i s c isck a b d a c b dac0 g l o c in4 u s a r t 3 rts c a t b sense0 a6 pa28 28 lcda s p i mosi i i s c isdi a b d a c b dacn0 g l o c in5 u s a r t 3 cts c a t b sense1 b8 pa29 29 lcda s p i sck i i s c iws a b d a c b dac1 g l o c in6 u s a r t 3 clk c a t b sense2 e8 pa30 30 lcda s p i npcs0 i i s c isdo a b d a c b dacn1 g l o c in7 u s a r t 3 rxd c a t b sense3 f8 pa31 31 lcda s p i npcs1 i i s c imck a b d a c b clk g l o c out1 u s a r t 3 txd c a t b dis d2 d2 pb00 32 vddin t w i m s 1 twd u s a r t 0 rxd c a t b sense21 c2 c2 pb01 33 vddin t w i m s 1 twck u s a r t 0 txd e i c extint0 c a t b sense22 e3 e3 pb02 34 vddana a d c i f e ad3 u s a r t 1 rts a b d a c b dac0 i i s c isck a c i f c acbn0 c a t b sense23 b1 b1 pb03 35 vddana a d c i f e ad4 u s a r t 1 clk a b d a c b dacn0 i i s c isdi a c i f c acbp0 c a t b dis a1 a1 pb04 36 vddana a d c i f e ad5 u s a r t 1 rxd a b d a c b dac1 i i s c isdo d a c c ext trig0 c a t b sense24 d4 d4 pb05 37 vddana a d c i f e ad6 u s a r t 1 txd a b d a c b dacn1 i i s c imck c a t b sense25 b5 b5 pb06 38 lcda u s a r t 3 rts g l o c in4 i i s c iws lcdca seg22 c a t b sense26 c6 c6 pb07 39 lcda u s a r t 3 cts g l o c in5 t c 0 a0 lcdca seg21 c a t b sense27 d6 d6 pb08 40 lcda u s a r t 3 clk g l o c in6 t c 0 b0 lcdca seg14 c a t b sense28 e6 e6 pb09 41 lcda u s a r t 3 rxd p e v c pad evt2 g l o c in7 t c 0 a1 lcdca seg15 c a t b sense29 f6 f6 pb10 42 lcda u s a r t 3 txd p e v c pad evt3 g l o c out1 t c 0 b1 s c i f gclk0 lcdca seg16 c a t b sense30 h8 h8 pb11 43 lcda u s a r t 0 cts s p i npcs2 t c 0 a2 s c i f gclk1 lcdca seg17 c a t b sense31 d5 d5 pb12 44 lcdc u s a r t 0 rts s p i npcs3 pevc pad evt0 t c 0 b2 s c i f gclk2 lcdca seg32 c a t b dis table 3-3. 64-pin gpio controller function multiplexing for wlcsp package (sheet 2 of 3) atsam4lc atsam4ls pin gpio supply gpio functions wlcsp wlcsp abcdefg
27 42023gs?sam?03/2014 atsam4l8/l4/l2 e5 e5 pb13 45 lcdc u s a r t 0 clk s p i npcs1 pevc pad evt1 t c 0 clk0 s c i f gclk3 lcdca seg33 c a t b sense0 f4 f4 pb14 46 lcdc u s a r t 0 rxd s p i miso t w i m 3 twd t c 0 clk1 s c i f gclk in0 lcdca seg36 c a t b sense1 h4 h4 pb15 47 lcdc u s a r t 0 txd s p i mosi t w i m 3 twck t c 0 clk2 s c i f gclk in1 lcdca seg37 c a t b sense2 table 3-3. 64-pin gpio controller function multiplexing for wlcsp package (sheet 3 of 3) atsam4lc atsam4ls pin gpio supply gpio functions wlcsp wlcsp abcdefg
28 42023gs?sam?03/2014 atsam4l8/l4/l2 table 3-4. 48-pin gpio controller function multiplexing (sheet 1 of 2) atsam4lc atsam4ls pin gpio supply gpio functions abcdefg 1 1 pa00 0 vddio 2 2 pa01 1 vddio 3 3 pa02 2 vddin s c i f gclk0 s p i npcs0 c a t b dis 10 10 pa03 3 vddin s p i miso 11 11 pa04 4 vddana a d c i f e ad0 u s a r t 0 clk e i c extint2 g l o c in1 c a t b sense0 12 12 pa05 5 vddana a d c i f e ad1 u s a r t 0 rxd e i c extint3 g l o c in2 a d c i f e trigger c a t b sense1 15 15 pa06 6 vddana d a c c vout u s a r t 0 rts e i c extint1 g l o c in0 a c i f c acan0 c a t b sense2 16 16 pa07 7 vddana a d c i f e ad2 u s a r t 0 txd e i c extint4 g l o c in3 a c i f c acap0 c a t b sense3 20 20 pa08 8 lcda u s a r t 0 rts t c 0 a0 pevc pa d e vt 0 g l o c out0 l c d c a seg23 c a t b sense4 21 21 pa09 9 lcda u s a r t 0 cts t c 0 b0 pevc pa d e vt 1 parc pcdata0 l c d c a com3 c a t b sense5 22 22 pa10 10 lcda u s a r t 0 clk t c 0 a1 pevc pa d e vt 2 parc pcdata1 l c d c a com2 c a t b sense6 23 23 pa11 11 lcda u s a r t 0 rxd t c 0 b1 pevc pa d e vt 3 parc pcdata2 l c d c a com1 c a t b sense7 24 24 pa12 12 lcda u s a r t 0 txd t c 0 a2 parc pcdata3 l c d c a com0 c a t b dis 32 32 pa13 13 lcda u s a r t 1 rts t c 0 b2 s p i npcs1 parc pcdata4 l c d c a seg5 c a t b sense8 33 33 pa14 14 lcda u s a r t 1 clk t c 0 clk0 s p i npcs2 parc pcdata5 l c d c a seg6 c a t b sense9 34 34 pa15 15 lcda u s a r t 1 rxd t c 0 clk1 s p i npcs3 parc pcdata6 l c d c a seg7 c a t b sense10 35 35 pa16 16 lcda u s a r t 1 txd t c 0 clk2 e i c extint1 parc pcdata7 l c d c a seg8 c a t b sense11 36 36 pa17 17 lcda u s a r t 2 rts a b d a c b dac0 e i c extint2 parc pcck l c d c a seg9 c a t b sense12 37 37 pa18 18 lcda u s a r t 2 clk a b d a c b dacn0 e i c extint3 parc pcen1 l c d c a seg18 c a t b sense13 38 38 pa19 19 lcda u s a r t 2 rxd a b d a c b dac1 e i c extint4 parc pcen2 s c i f gclk0 l c d c a seg19 c a t b sense14 39 39 pa20 20 lcda u s a r t 2 txd a b d a c b dacn1 e i c extint5 g l o c in0 s c i f gclk1 l c d c a seg20 c a t b sense15 41 41 pa21 21 lcdc s p i miso u s a r t 1 cts e i c extint6 g l o c in1 t w i m 2 twd l c d c a seg34 c a t b sense16 42 42 pa22 22 lcdc s p i mosi u s a r t 2 cts e i c extint7 g l o c in2 t w i m 2 twck l c d c a seg35 c a t b sense17 43 43 pa23 23 lcdc s p i sck t w i m s 0 twd e i c extint8 g l o c in3 s c i f gclk in0 l c d c a seg38 c a t b dis
29 42023gs?sam?03/2014 atsam4l8/l4/l2 3.2.2 peripheral functions each gpio line can be assigned to one of several peripheral functions. the following table describes how the various peripheral functions are selected. the last listed function has priority in case multiple functions are enabled on the same pin. 3.2.3 jtag port connections if the jtag is enabled, the jtag will take control over a number of pins, irrespectively of the i/o controller configuration. 44 44 pa24 24 lcdc s p i npcs0 t w i m s 0 twck g l o c out0 s c i f gclk in1 l c d c a seg39 c a t b sense18 46 46 pa25 25 vddio u s b c dm u s a r t 2 rxd c a t b sense19 47 47 pa26 26 vddio u s b c dp u s a r t 2 txd c a t b sense20 25 pa27 27 lcda s p i miso i i s c isck a b d a c b dac0 g l o c in4 u s a r t 3 rts c a t b sense0 26 pa28 28 lcda s p i mosi i i s c isdi a b d a c b dacn0 g l o c in5 u s a r t 3 cts c a t b sense1 27 pa29 29 lcda s p i sck i i s c iws a b d a c b dac1 g l o c in6 u s a r t 3 clk c a t b sense2 30 pa30 30 lcda s p i npcs0 i i s c isdo a b d a c b dacn1 g l o c in7 u s a r t 3 rxd c a t b sense3 31 pa31 31 lcda s p i npcs1 i i s c imck a b d a c b clk g l o c out1 u s a r t 3 txd c a t b dis table 3-4. 48-pin gpio controller function multiplexing (sheet 2 of 2) atsam4lc atsam4ls pin gpio supply gpio functions abcdefg table 3-5. peripheral functions function description gpio controller function multiplexing gpio and gpio peripheral selection a to h jtag port connections jtag debug port oscillators osc0 table 3-6. jtag pinout 48-pin packages 64-pin qfp/qfn 64-pin wlscp 100-pin qfn 100-ball vfbga pin name jtag pin 10 10 e2 19 b3 pa03 tms 43 59 h3 95 d6 pa23 tdo 44 60 g3 96 d10 pa24 tdi 99f218b4tcktck
30 42023gs?sam?03/2014 atsam4l8/l4/l2 3.2.4 itm trace connections if the itm trace is enabled, the itm will take cont rol over the pin pa23, irrespectively of the i/o controller configuration. the serial wire trace signal is available on pin pa23 3.2.5 oscillator pinout the oscillators are not mapped to the normal gp io functions and their muxings are controlled by registers in the system control interface (scif) or backup system control interface (bscif). refer to the section 15. ?system control interface (scif)? on page 308 and section 15. ?backup system control interface (bscif)? on page 308 for more information about this. table 3-7. oscillator pinout 48-pin packages 64-pin qfn/qfp 64-pin wlcsp 100-pin packages 100-ball vfbga pin name oscillator pin 11g45b9 pa00 xin0 13 17 b2 26 b2 xin32 xin32 2 2 g5 6 b8 pa01 xout0 14 18 b3 27 c2 xout32 xout32
31 42023gs?sam?03/2014 atsam4l8/l4/l2 3.3 signals description the following table gives details on signal names classified by peripheral. table 3-8. signal descriptions list (sheet 1 of 4) signal name function type active level comments audio bitstream dac - abdacb clk d/a clock output output dac1 - dac0 d/a bitstream outputs output dacn1 - dacn0 d/a inverted bitstream outputs output analog comparator interface - acifc acan1 - acan0 analog comparator a negative references analog acap1 - acap0 analog comparator a positive references analog acbn1 - acbn0 analog comparator b negative references analog acbp1 - acbp0 analog comparator b positive references analog adc controller interface - adcife ad14 - ad0 analog inputs analog advrefp positive voltage reference analog trigger external trigger input backup system control interface - bscif xin32 32 khz crystal oscillator input analog/ digital xout32 32 khz crystal oscillator output analog capacitive touch module b - catb dis capacitive discharge line output sense31 - sense0 capacitive sense lines i/o dac controller - dacc dac external trigger dac external trigger input dac voltage output dac voltage output analog enhanced debug port for arm products - edp tck/swclk jtag / sw debug clock input tdi jtag debug data in input tdo/traceswo jtag debug data out / sw trace out output tms/swdio jtag debug mode select / sw data i/o external interrup t controller - eic extint8 - extint0 extern al interrupts input glue logic controller - gloc in7 - in0 lookup tables inputs input out1 - out0 lookup tables outputs output
32 42023gs?sam?03/2014 atsam4l8/l4/l2 inter-ic sound (i2s) controller - iisc imck i2s master clock output isck i2s serial clock i/o isdi i2s serial data in input isdo i2s serial data out output iws i2s word select i/o lcd controller - lcdca biasl bias voltage (1/3 vlcd) analog biash bias voltage (2/3 vlcd) analog caph high voltage end of flying capacitor analog capl low voltage end of flying capacitor analog com3 - com0 common terminals analog seg39 - seg0 segment terminals analog vlcd bias voltage analog parallel capture - parc pcck clock input pcdata7 - pcdata0 data lines input pcen1 data enable 1 input pcen2 data enable 2 input peripheral event controller - pevc pad_evt3 - pad_evt0 event inputs input power manager - pm reset_n reset input low system control interface - scif gclk3 - gclk0 generic clock outputs output gclk_in1 - gclk_in0 generic clock inputs input xin0 crystal 0 input analog/ digital xout0 crystal 0 output analog serial peripheral interface - spi miso master in slave out i/o mosi master out slave in i/o npcs3 - npcs0 spi peripheral chip selects i/o low sck clock i/o timer/counter - tc0, tc1 table 3-8. signal descriptions list (sheet 2 of 4) signal name function type active level comments
33 42023gs?sam?03/2014 atsam4l8/l4/l2 a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twims0, twims1, twim2, twim3 twck two-wire serial clock i/o twd two-wire serial data i/o universal synchronous asynchronous receiver transmitter - usart0, usart1, usart2, usart3 clk clock i/o cts clear to send input low rts request to send output low rxd receive data input txd transmit data output usb 2.0 interface - usbc dm usb full speed interface data - i/o dp usb full speed interface data + i/o power gnd ground ground gndana analog ground ground vddana analog power supply power input 1.68v to 3.6v vddcore core power supply power input 1.68v to 1.98v vddin voltage regulator input power input 1.68v to 3.6v vddio i/o pads power supply power input 1.68v to 3.6v. vddio must always be equal to or lower than vddin. vddout voltage regulator output power output 1.08v to 1.98v general purpose i/o table 3-8. signal descriptions list (sheet 3 of 4) signal name function type active level comments
34 42023gs?sam?03/2014 atsam4l8/l4/l2 note: 1. see ?power and startup considerations? section. 3.4 i/o line considerations 3.4.1 sw/jtag pins the jtag pins switch to the jtag functions if a rising edge is detected on tck low after the reset_n pin has been released. the tms, and tdi pins have pull-up resistors when used as jtag pins. the tck pin always has pull-up enabl ed during reset. the jtag pins can be used as gpio pins and multiplexed with peripherals when the jtag is disabled. refer to section 3.2.3 ?jtag port connections? on page 29 for the jtag port connections. for more details, refer to section 1.1 ?enhanced debug port (edp)? on page 3 . 3.4.2 reset_n pin the reset_n pin is a schmitt input and integrates a permanent pull-up resistor to vddin. as the product integrates a power-on reset detector, the reset_n pin can be left unconnected in case no reset from the system nee ds to be applied to the product. 3.4.3 twi pins when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and- inputs with inputs with spike-filtering. when used as gpio-pins or used for other peripherals, the pins have the same charac teristics as gpio pins. 3.4.4 gpio pins all the i/o lines integrate a pull-up/pull-down resistor and slew rate controller . programming these features is performed independently for eac h i/o line through the gpio controllers. after reset, i/o lines default as inputs with pull-up and pull-down resistors disabled and slew rate enabled. 3.4.5 high-drive pins the six pins pa02, pb00, pb01, pc04, pc05 a nd pc06 have high-drive output capabilities. refer to section 9.6.2 ?high-drive i/o pin : pa02, pc04, pc05, pc06? on page 115 for electrical characteristics. 3.4.6 usb pins when these pins are used for usb, the pins ar e behaving according to the usb specification. when used as gpio pins or used for other peripherals, the pins have the same behavior as other normal i/o pins, but the characteristics are different. refer to section 9.6.3 ?usb i/o pin : pa25, pa26? on page 116 for electrical characteristics. these pins are compliant to usb standard only when vddio power supply is 3.3 v nominal. pa31 - pa00 parallel i/o controller i/o port a i/o pb15 - pb00 parallel i/o controller i/o port b i/o pc31 - pc00 parallel i/o controller i/o port c i/o table 3-8. signal descriptions list (sheet 4 of 4) signal name function type active level comments
35 42023gs?sam?03/2014 atsam4l8/l4/l2 3.4.7 adc input pins these pins are regular i/o pins powered from the vddana.
36 42023gs?sam?03/2014 atsam4l8/l4/l2 4. cortex-m4 processor and core peripherals 4.1 cortex-m4 the cortex-m4 processor is a high performanc e 32-bit processor designed for the microcon- troller market. it offers significant benefits to developers, including: ? outstanding processing performance combined with fast interrupt handling ? enhanced system debug with extensiv e breakpoint and trace capabilities ? efficient processor core , system and memories ? ultra-low power consumption with integrated sleep modes ? platform security robustness, with inte grated memory protection unit (mpu). the cortex-m4 processor is built on a high-performance processor core, with a 3-stage pipeline harvard architecture, making it ideal for demanding embedded applications. the processor delivers exceptional power efficiency through an efficient instruction set and extensively opti- mized design, providing high-end processing hardware including a range of single-cycle and simd multiplication and multiply -with-accumulate capabilities, sa turating arithmetic and dedi- cated hardware division. to facilitate the design of cost-sensitive device s, the cortex-m4 processor implements tightly- coupled system components that reduce processo r area while significantly improving interrupt handling and system debug capabilitie s. the cortex-m4 processor implements a version of the thumb ? instruction set based on thumb-2 technology, ensuring high code density and reduced program memory requirements. the cortex-m4 instruction set provides the exceptional perfor- mance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. the cortex-m4 processor closely integrates a configurable nested vectored interrupt controller (nvic), to deliver industry-leading interrupt performance. the nvic includes a non-maskable interrupt (nmi), and provides up to 80 interrupt priority levels. the tight integration of the proces- nvic debug access port memory protection unit serial wire viewer bus matrix code interface sram and peripheral interface data watchpoints flash patch cortex-m4 processor processor core
37 42023gs?sam?03/2014 atsam4l8/l4/l2 sor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing the interrupt latency. this is achiev ed through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. interrupt handlers do not require wrapping in assembler code, removing any code overhead from the isrs. a tail-chain optimization also significantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic integrates with the sleep modes , that include a deep sleep function enabling the entire device to be rapidly powered down while still retaining pro- gram state. 4.2 system level interface the cortex-m4 processor provides multiple interfaces using amba ? technology to provide high speed, low latency memory accesses. it su pports unaligned data accesses and implements atomic bit manipulation that enables faster pe ripheral controls, system spinlocks and thread-safe boolean data handling. the cortex-m4 processor has an memory protection unit (mpu) that provides fine grain memory control, enabling applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task basis. such requirements are becoming critical in many embedded applications such as automotive. 4.3 integrated configurable debug the cortex-m4 processor implements a complete hardware debug solution. this provides high system visibility of the processor and memory through ei ther a traditional jt ag port or a 2-pin serial wire debug (swd) port that is ideal for microcon trollers and other small package devices. for system trace the proc essor integrates an instrumentation trace macrocell (itm) alongside data watchpoints an d a profiling unit. to enable simple and cost-effective pr ofiling of the system events these generate, a serial wire viewer (swv) can export a stream of software-generated messages, data trace, and profiling informati on through a single pin. the flash patch and breakpoint unit (fpb) provides 8 hardware breakpoint comparators that debuggers can use. the comparators in the fpb also provide remap functions of up to 8 words in the program code in the code memory region. this enables applications stored on a non- erasable, rom-based microcontroller to be patched if a small programmable memory, for exam- ple flash, is available in the device. during initia lization, the application in rom detects, from the programmable memory, whether a patch is required. if a patch is required, the application pro- grams the fpb to remap a number of addresses. when those addresses are accessed, the accesses are redirected to a remap table specified in the fpb configuration, which means the program in the non-modifiable rom can be patched. a specific peripheral debug (pdbg) register is implemented in the private peripheral bus address map. this register allows the user to configure the behavior of some modules in debug mode.
38 42023gs?sam?03/2014 atsam4l8/l4/l2 4.4 cortex-m4 processor features and benefits summary ? tight integration of system peripheral s reduces area and development costs ? thumb instruction set combines high co de density with 32-bit performance ? code-patch ability for rom system updates ? power control optimization of system components ? integrated sleep modes for low power consumption ? fast code execution permits slower proc essor clock or increases sleep mode time ? hardware division and fast digital-signal-processing orie ntated multiply accumulate ? saturating arithmetic for signal processing ? deterministic, high-performance interrupt handling for time-critical applications ? memory protection unit (mpu) for safety-cr itical applications ? extensive debug and trace capabilities: ? serial wire debug and serial wire trace reduce the number of pins required for debugging, tracing, and code profiling. 4.5 cortex-m4 core peripherals these are: nested vectored interrupt controller the nvic is an embedded interrupt controller that supports low latency interrupt processing. system control block the system control block (scb) is the programmers model interface to the processor. it pro- vides system implementation info rmation and system control, in cluding configuration, control, and reporting of system exceptions. system timer the system timer, systick, is a 24 -bit count-down timer. use this as a real time operating sys- tem (rtos) tick timer or as a simple counter. memory protection unit the memory protection unit (mpu) improves system reliability by defining the memory attributes for different memory regions. it provides up to eight different regions, and an optional predefined background region. the complete cortex-m4 user guide can be found on the arm web site: http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/dui0553a_cortex_m4_dgug.pdf
39 42023gs?sam?03/2014 atsam4l8/l4/l2 4.6 cortex-m4 implementations options this table provides the specific configurat ion options implemented in the sam4l series table 4-1. cortex-m4 implementation options 4.7 cortex-m4 interrupts map the table below shows how the interrupt re quest signals are connected to the nvic. option implementation inclusion of mpu yes inclusion of fpu no number of interrupts 80 number of priority bits 4 inclusion of the wic no embedded trace macrocell no sleep mode instruction only wfi supported endianness little endian bit-banding no systick timer yes register reset values no table 4-2. interrupt request signal map (sheet 1 of 3) line module signal 0 flash controller hflashc 1 peripheral dma controller pdca 0 2 peripheral dma controller pdca 1 3 peripheral dma controller pdca 2 4 peripheral dma controller pdca 3 5 peripheral dma controller pdca 4 6 peripheral dma controller pdca 5 7 peripheral dma controller pdca 6 8 peripheral dma controller pdca 7 9 peripheral dma controller pdca 8 10 peripheral dma controller pdca 9 11 peripheral dma controller pdca 10
40 42023gs?sam?03/2014 atsam4l8/l4/l2 12 peripheral dma controller pdca 11 13 peripheral dma controller pdca 12 14 peripheral dma controller pdca 13 15 peripheral dma controller pdca 14 16 peripheral dma controller pdca 15 17 crc calculation unit crccu 18 usb 2.0 interface usbc 19 peripheral event controller pevc tr 20 peripheral event controller pevc ov 21 advanced encryption standard aesa 22 power manager pm 23 system control interface scif 24 frequency meter freqm 25 general-purpose input/ou tput controller gpio 0 26 general-purpose input/ou tput controller gpio 1 27 general-purpose input/ou tput controller gpio 2 28 general-purpose input/ou tput controller gpio 3 29 general-purpose input/ou tput controller gpio 4 30 general-purpose input/ou tput controller gpio 5 31 general-purpose input/ou tput controller gpio 6 32 general-purpose input/ou tput controller gpio 7 33 general-purpose input/ou tput controller gpio 8 34 general-purpose input/ou tput controller gpio 9 35 general-purpose input/ou tput controller gpio 10 36 general-purpose input/ou tput controller gpio 11 37 backup power manager bpm 38 backup system control interface bscif 39 asynchronous timer ast alarm 40 asynchronous timer ast per 41 asynchronous timer ast ovf 42 asynchronous timer ast ready 43 asynchronous timer ast clkready 44 watchdog timer wdt 45 external interrupt controller eic 1 46 external interrupt controller eic 2 47 external interrupt controller eic 3 table 4-2. interrupt request signal map (sheet 2 of 3) line module signal
41 42023gs?sam?03/2014 atsam4l8/l4/l2 48 external interrupt controller eic 4 49 external interrupt controller eic 5 50 external interrupt controller eic 6 51 external interrupt controller eic 7 52 external interrupt controller eic 8 53 inter-ic sound (i2s) controller iisc 54 serial peripheral interface spi 55 timer/counter tc00 56 timer/counter tc01 57 timer/counter tc02 58 timer/counter tc10 59 timer/counter tc11 60 timer/counter tc12 61 two-wire master interface twim0 62 two-wire slave interface twis0 63 two-wire master interface twim1 64 two-wire slave interface twis1 65 universal synchronous asynchronous receiver transmitter usart0 66 universal synchronous asynchronous receiver transmitter usart1 67 universal synchronous asynchronous receiver transmitter usart2 68 universal synchronous asynchronous receiver transmitter usart3 69 adc controller interface adcife 70 dac controller dacc 71 analog comparator interface acifc 72 audio bitstream dac abdacb 73 true random number generator trng 74 parallel capture parc 75 capacitive touch module b catb 77 two-wire master interface twim2 78 two-wire master interface twim3 79 lcd controller a lcdca table 4-2. interrupt request signal map (sheet 3 of 3) line module signal
42 42023gs?sam?03/2014 atsam4l8/l4/l2 4.8 peripheral debug the pdbg register controls the behavior of asynchronous peripherals when the device is in debug mode.when the corres ponding bit is set, that peripheral will be in a frozenstate in debug mode. 4.8.1 peripheral debug name: pdbg access type: read/write address: 0xe0042000 reset value: 0x00000000 ? wdt: watchdog pdbg bit wdt = 0: the wdt counter is not frozen during debug operation. wdt = 1: the wdt counter is frozen dur ing debug operation when core is halted ? ast: asynchronous timer pdbg bit ast = 0: the ast prescaler and counter is not frozen during debug operation. ast = 1: the ast prescaler and counter is froz en during debug operation when core is halted. ? pevc: pevc pdbg bit pevc= 0: pevc is not frozen during debug operation. pevc= 1: pevc is frozen during debug operation when core is halted. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - pevc ast wdt
43 42023gs?sam?03/2014 atsam4l8/l4/l2 5. memories 5.1 product mapping figure 5-1. atsam4l8/l4/l2 product mapping system reserved reserved hramc1 global memory space peripherals code internal flash reserved 0x00000000 0x00800000 0x1fffffff code sram undefined peripherals reserved 0x00000000 0x20000000 0x40000000 0x60000000 0xffffffff 0x22000000 0x5fffffff sram hramc0 reserved 0x20000000 0x20010000 0x21000000 0x210007ff 0x21ffffff peripheral bridge a reserved peripheral bridge b peripheral bridge c peripheral bridge d aesa 0x400e0000 0x400f0000 0x40100000 0x400b0000 0x400a0000 0x40000000 0x400b0100 system controller twim2 catb dacc reserved reserved i2sc spi reserved tc0 tc1 twims0 twims1 usart0 usart1 usart2 usart3 reserved adcife acifc reserved gloc abdacb trng parc reserved 0x40000000 0x40004000 0x40008000 0x4000c000 0x40010000 0x40014000 0x40018000 0x4001c000 0x40020000 0x40024000 0x40028000 0x4002c000 0x40030000 0x40034000 0x40038000 0x4003c000 0x40040000 0x40044000 0x40060000 0x40064000 0x40068000 0x4006c000 0x40070000 0x40074000 0x40078000 twim3 0x4007c000 0x40080000 lcdca reserved 0x40084000 0x4009ffff picouart peripheral bridge c pm scif chipid freqm gpio reserved bpm bscif ast wdt eic reserved 0x400e0000 0x400e0740 0x400e0800 0x400e0c00 0x400e1000 0x400e1800 0x400f0000 0x400f0400 0x400f0800 0x400f0c00 0x400f1000 0x400f1400 peripheral bridge d 0x400fffff 0x400f1800 0x400effff peripheral bridge b flashcalw hmatrix smap crccu picocache reserved 0x400a0000 0x400a0400 0x400a1000 0x400a2000 0x400a3000 0x400a4000 0x400a5000 pdca usbc pevc 0x400a6000 0x400a6400 0x400affff peripheral bridge a itm dwt fpb reserved scs reserved tpiu reserved external ppb rom table 0xe0000000 0xe0000000 0xe0001000 0xe0002000 0xe0003000 0xe000e000 0xe000f000 0xe0040000 0xe0041000 0xe0042000 0xe00ff000 0xe0100000 reserved 0xffffffff system
44 42023gs?sam?03/2014 atsam4l8/l4/l2 5.2 embedded memories ? internal high-speed flash ? 512kbytes (atsam4lx8) ? 256kbytes (atsam4lx4) ? 128kbytes (atsam4lx2) ? pipelined flash architecture, allowing burst r eads from sequen tial flash loca tions, hiding penalty of 1 wait state access ? pipelined flash architecture typically reduce s the cycle penalty of 1 wait state operation compared to 0 wait state operation ? 100 000 write cycles, 15-year data retention capability ? sector lock capabilities, boot loader protection, security bit ? 32 fuses, erased during chip erase ? user page for data to be preserved during chip erase ? internal high-speed sram, sing le-cycle access at full speed ? 64kbytes (atsam4lx8) ? 32kbytes (atsam4lx4, atsam4lx2) 5.3 physical memory map the system bus is implemented as a bus matrix . all system bus addresses are fixed, and they are never remapped in any way, not even during boot. the 32-bit physical address space is mapped as follows: table 5-1. atsam4l8/l4/l2 physical memory map memory start address size size atsam4lx4 atsam4lx2 embedded flash 0x00000000 256kbytes 128kbytes embedded sram 0x20000000 32kbytes 32kbytes cache sram 0x21000000 4kbytes 4kbytes peripheral bridge a 0x40000000 64kbytes 64kbytes peripheral bridge b 0x400a0000 64kbytes 64kbytes aesa 0x400b0000 256 bytes 256 bytes peripheral bridge c 0x400e0000 64kbytes 64kbytes peripheral bridge d 0x400f0000 64kbytes 64kbytes memory start address size at s a m 4 l x 8 embedded flash 0x00000000 512kbytes embedded sram 0x20000000 64kbytes cache sram 0x21000000 4kbytes peripheral bridge a 0x40000000 64kbytes peripheral bridge b 0x400a0000 64kbytes
45 42023gs?sam?03/2014 atsam4l8/l4/l2 aesa 0x400b0000 256 bytes peripheral bridge c 0x400e0000 64kbytes peripheral bridge d 0x400f0000 64kbytes memory start address size at s a m 4 l x 8 table 5-2. flash memory parameters device flash size ( flash_pw ) number of pages ( flash_p )page size ( flash_w ) atsam4lx8 512kbytes 1024 512 bytes atsam4lx4 256kbytes 512 512 bytes atsam4lx2 128kbytes 256 512 bytes
46 42023gs?sam?03/2014 atsam4l8/l4/l2 6. power and startup considerations 6.1 power domain overview figure 6-1. atsam4ls power domain diagram asynchronous timer external interrupt controller watchdog timer backup power manager backup system control interface osc32k rc32k backup registers system control interface power manager frequency meter gpio por33 bod33 bod18 startup logic por18 pll dfll rcsys peripheral bridge c peripherals peripheral bridge a ahb peripherals peripheral bridge b bus matrix cortex m4 cpu flash pdca ram peripheral bridge d core domain vddana domain backup domain vddana gndana mposc ad0-ad14 advref ac0a-ac3a ac0b-ac3b xin32 xout32 extint0-extint8 usbc analog comparators adc rcfast rc80m vddin gnd vddout vddcore dual output trimmable voltage regulator buck/ldon (pa02) dac dacout vddio gnd vddio domain gpios usb pads
47 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 6-2. atsam4lc power domain diagram asynchronous timer external interrupt controller watchdog timer backup power manager backup system control interface osc32k rc32k backup registers system control interface power manager frequency meter gpio por33 bod33 bod18 startup logic por18 pll dfll rcsys peripheral bridge c peripherals peripheral bridge a ahb peripherals peripheral bridge b bus matrix cortex m4 cpu flash pdca ram peripheral bridge d core domain vddana domain backup domain vddana gndana mposc ad0-ad14 advref ac0a-ac3a ac0b-ac3b xin32 xout32 extint0-extint8 usbc analog comparators adc rcfast rc80m vddin gnd vddout vddcore dual output trimmable voltage regulator buck/ldon (pa02) dac dacout vlcdin gnd lcda domain gpios lcd vpump caph capl biash biasl vlcd vddio lcdb domain gpios vddio gpios lcdc domain vddio gnd vddio domain gpios usb pads
48 42023gs?sam?03/2014 atsam4l8/l4/l2 6.2 power supplies the atsam4l8/l4/l2 has several types of power supply pins: ? vddio: powers i/o lines, the general purpose oscillator (osc), the 80mhz integrated rc oscillator (rc80m) . voltage is 1.68v to 3.6v. ? vlcdin: (atsam4lc only) powers the lcd voltage pump. voltage is 1.68v to 3.6v. ? vddin: powers the internal voltage regulator. voltage is 1.68v to 3.6v. ? vddana: powers the adc, the dac, the analog comparators, the 32khz oscillator (osc32k), the 32khz integrated rc oscillator (rc32k)and the brown-out detectors (bod18 and bod33). voltage is 1.68v to 3.6v nominal. ? vddcore: powers the core, memories, peripherals, the pll, the dfll, the 4mhz integrated rc oscillator (rcf ast) and the 115khz integrat ed rc oscillator (rcsys). ? vddout is the output voltage of the regulator and must be connected with or without an inductor to vddcore. the ground pins gnd are common to vddcore, vddio, and vddin. the ground pin for vddana is gndana. for decoupling recommendations for the different power supplies, refer to the schematic document. 6.2.1 voltage regulator an embedded voltage regulator supplies all the digital logic in the core and the backup power domains. the regulator has two functionnal mode depending of buck/ldon (pa02) pin value. when this pin is low, the regulator is in linear mode and vddout must be connected to vddcore exter- nally. when this pin is high, it behaves as a s witching regulator and an inductor must be placed between vddout and vddcore. the value of this pin is sampled during the power-up phase when the power on reset 33 reaches v pot+ ( section 9.9 ?analog characteristics? on page 129 ) its output voltages in the core domain (v core ) and in the backup domain (v bkup ) are always equal except in backup mode where the core domain is not powered (v core =0). the backup domain is always powered. the voltage regulator features three different modes: ? normal mode: the regulator is configured as linear or switching regulator. it can support all different run and sleep modes. ? low power (lp) mode: the regulator consumes little static current. it can be used in wait modes. ? ultra low power (ulp) mode: the regulator consumes very little static current . it is dedicated to retention and backup modes. in backup mode, the regulator only supplies the backup domain.
49 42023gs?sam?03/2014 atsam4l8/l4/l2 6.2.2 typical powering schematics the atsam4l8/l4/l2 supports the single supply mode from 1.68v to 3.6v. depending on the input voltage range and on the final application frequency, it is recommended to use the follow- ing table in order to choose the most efficient power strategy figure 6-3. efficient power strategy: n/a possible but not efficient 1.68v 1.80v 2.00v 2.30v 3.60v optimal power efficiency linear mode (buck/ldon (pa02) =0) optimal power efficiency possible but not efficient switching mode (buck/ldon (pa02) =1) f cpumax 12mhz powerscaling ps1 (1) up to 36mhz in ps0 up to 12mhz in ps1 up to 48mhz in ps2 all vddin voltage typical power consumption in run mode 100a/mhz @ f cpu =12mhz(ps1) @ v vddin =3.3v 180a/mhz @ f cpu =48mhz(ps2) @ v vddin =3.3v 212a/mhz @ f cpu =12mhz(ps1) 306a/mhz @ f cpu = 48mhz(ps2) typical power consumption in ret mode 1.5a note 1. the sam4l boots in ps0 on rcsys(115khz), then the application must switch to ps1 before running on higher frequency (<12mhz)
50 42023gs?sam?03/2014 atsam4l8/l4/l2 the internal regulator is connected to the vddin pin and its outpu t vddout feeds vddcore in linear mode or through an inductor in switching mode. figure 6-4 shows the power schematics to be used. all i/o lines will be powered by the same power (v vddin =v vddio =v vddana ). figure 6-4. single supply mode 6.2.3 lcd power modes 6.2.3.1 principle lcd lines is powered using the device internal voltage sources provided by the lcdpwr block. when enabled, the lcdpwr blocks will generate the vl cd, biasl, biash voltages. lcd pads are splitted into three clusters that can be powered independently namely clusters a, b and c. a cluster can either be in gpio mode or in lcd mode. when a cluster is in gpio mode, its vddio pin must be powered externally. none of its gpio pin can be used as a lcd line when a cluster is in lcd mode, each clusters vddio pin can be either forced externally (1.8- 3.6v) or unconnected (nc). gpios in a cluster are not available when it is in lcd mode. a clus- ter is set in lcd mode by the lcdca controller when it is enabled depending on the number of segments configured. the lcdpwr block is po wered by the vlcdin pin inside cluster a when lcd feature is not used, vlcdin must be always powered (1.8-3.6v). vlcd, caph, capl, biash, biasl can be le ft unconnected in this case vddin vddio vddana vddcore regulator adc, dac, ac0/1, rc32k, osc32k, bod18, bod33 rc80m, osc, core domain: cpu, peripherals, ram, flash, rcsys, pll, dfll, rcfast backup domain: ast, wdt, eic, bpm, bscif main supply (1.68v-3.6v) vddout buck/ldon (pa02) vlcdin lcd vpump
51 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 6-5. lcd clusters in the device 6.2.3.2 internal lcd voltage in this mode the lcd voltages are internally generated. depending of the number of segments required by the application, lcdb and ldcc cl usters vddio pin must be unconnected (nc) or 1 2 3 4 5 6 gnd 7 vddio 8 9 10 11 12 13 14 gnd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 gndana 33 34 vddana 35 36 37 38 39 40 41 42 43 44 45 46 47 com2 48 com1 49 com0 50 seg17 75 seg16 74 seg15 73 seg14 72 seg13 71 seg12 70 seg11 69 seg10 68 seg9 67 seg8 66 seg7 65 seg6 64 seg5 63 seg4 62 seg3 61 seg2 60 seg1 59 seg0 58 vlcdin 57 gnd 56 biasl 55 biash 54 vlcd 53 capl 52 caph 51 seg18 76 seg19 77 seg20 78 seg24 79 seg25 80 seg26 81 seg27 82 seg28 83 seg29 84 seg30 85 seg31 86 vddio 87 vddio 88 seg32 89 seg33 90 seg34 91 seg35 92 seg36 93 seg37 94 seg38 95 seg39 96 97 98 99 gnd 100 vddout vddin vddcore com3 seg21 seg22 seg23 1 2 3 4 vddcore 5 gnd 6 vddout 7 vddin 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 gndana 23 24 vddana 25 26 27 28 29 seg14 30 seg13 31 seg12 32 seg8 48 seg7 47 seg6 46 seg5 45 seg4 44 seg3 43 seg2 42 seg1 41 seg0 40 vlcdin 39 gnd 38 biasl 37 biash 36 vlcd 35 capl 34 caph 33 seg9 49 seg10 50 seg11 51 vddio 52 53 54 55 56 57 58 59 60 vddio 61 62 63 gnd 64 com3 com2 com1 com0 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 1 2 3 4 vddcore 5 gnd 6 vddout 7 vddin 8 9 10 11 12 13 14 15 16 gndana 17 18 vddana 19 seg8 20 com3 21 com2 22 com1 23 com0 24 seg4 36 seg3 35 seg2 34 seg1 33 seg0 32 vlcdin 31 gnd 30 biasl 29 biash 28 vlcd 27 capl 26 caph 25 seg5 37 seg6 38 seg7 39 vddio 40 seg9 41 seg10 42 seg11 43 seg12 44 vddio 45 46 47 gnd 48 tqfp48/qfn48 tqfp64/qfn64 tqfp100 lcda cluster lcdb cluster lcdc cluster
52 42023gs?sam?03/2014 atsam4l8/l4/l2 connected to an external voltage source (1.8-3.6v). lcdb cluster is not available in 64 and 48 pin packages table 6-1. lcd powering when using the internal voltage pump package segments in use vddio lcdb vddio lcdc 100-pin packages [1,24] 1.8-3.6v 1.8-3.6v [1, 32] nc 1.8-3.6v [1, 40] nc nc 64-pin packages [1,15] - 1.8-3.6v [1, 23] -nc 48-pin packages [1,9] - 1.8-3.6v [1,13] -nc vlcdin gnd gpios lcd vpump caph capl biash biasl vlcd vddio lcdb domain gpios vddio gpios lcdc domain switch on switch on nc nc 1.8?3.6v vlcdin gnd gpios lcd vpump caph capl biash biasl vlcd vddio lcdb domain gpios vddio gpios lcdc domain switch on switch off nc 1.8?3.6v vlcdin gnd gpios lcd vpump caph capl biash biasl vlcd vddio lcdb domain gpios vddio gpios lcdc domain switch off switch off 1.8?3.6v 1.8?3.6v lcda domain lcda domain lcda domain 1.8?3.6v up to 4x40 segments no gpio in lcd clusters up to 4x32 segments up to 8 gpios in lcdc clusters up to 4x24 segments up to 16 gpios in lcdb & lcdc clusters
53 42023gs?sam?03/2014 atsam4l8/l4/l2 6.2.4 power-up sequence 6.2.4.1 maximum rise rate to avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in table 9-3 on page 100 . 6.2.4.2 minimum rise rate the integrated power-on reset (por33) circuitry monitoring the vddin powering supply requires a minimum rise rate for the vddin power supply. see table 9-3 on page 100 for the minimum rise rate value. if the application can not ensure that the minimum rise rate condition for the vddin power sup- ply is met, the following configuration can be used: ? a logic ?0? value is applied during power-up on pin reset_n until vddin rises above 1.6 v. 6.3 startup considerations this section summarizes the boot sequence of the atsam4l8/l4/l2. the behavior after power- up is controlled by the power manager. for specific details, refer to section 9. ?power manager (pm)? on page 677 . 6.3.1 starting of clocks after power-up, the device will be held in a reset state by th e power-up circuitry for a short time to allow the power to stabilize throughout the device. after re set, the device will use the system rc oscillator (rcsys) as clock source. refer to section 9. ?electrical characteristics? on page 99 for the frequency for this oscillator. on system start-up, the dfll and the plls are di sabled. only the necessa ry clocks are active allowing software execution. refer to section 3-6 ?maskable module clocks in at32uc3b.? on page 24 to know the list of peripheral clock r unning.. no clocks have a divided frequency; all parts of the system rece ive a clock with the same frequen cy as the system rc oscillator. 6.3.2 fetching of initial instructions after reset has been released, the cortex m4 cpu starts fetching pc and sp values from the reset address, which is 0x00000000. refer to the arm architecture reference manual for more information on cpu startup. this address points to the first address in the internal flash. the code read from the internal flash is free to configure the clock system and clock sources. 6.4 power-on-reset, brownout and supply monitor the sam4l embeds four features to monitor, warm, and/or reset the device: ? por33: power-on-reset on vddana ? bod33: brownout detector on vddana ? por18: power-on-reset on vddcore ? bod18: brownout detector on vddcore
54 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 6-6. supply monitor schematic 6.4.1 power-on-reset on vddana por33 monitors vddana. it is always activated and monitors voltage at startup but also during all the power save mode. if vddana goes below the threshold voltage, the entire chip is reset. 6.4.2 brownout detector on vddana bod33 monitors vddana. refer to section 15. ?backup system control interface (bscif)? on page 308 to get more details. 6.4.3 power-on-reset on vddcore por18 monitors the inte rnal vddcore. refer to section 15. ?backup system control interface (bscif)? on page 308 to get more details. 6.4.4 brownout detector on vddcore once the device is startup, the bod18 monitors the internal vddcore. refer to section 15. ?backup system control interface (bscif)? on page 308 to get more details. por33 bod33 bod18 vddana gndana vddana por18 dual output trimmable voltage regulator vddcore
55 42023gs?sam?03/2014 atsam4l8/l4/l2 7. low power techniques the atsam4l8/l4/l2 supports multiple power configurations to allow the user to optimize its power consumption in different use cases. the backup power manager (bpm) implements dif- ferent solutions to reduce the power consumption: ? the power save modes intended to reduce the logic activity and to adapt the power configuration. see ?power save modes? on page 55 . ? the power scaling intended to scale the power configuration (voltage scaling of the regulator). see ?power scaling? on page 60 . these two techniques can be combined together. figure 7-1. power scaling and power save mode overview 7.1 power save modes refer to section 6. ?power and startup considerations? on page 46 to get definition of the core and the backup domains. sleep1 wait1 ret1 bkup1 run1 power scaling max frequency = 36mhz normal speed flash nominal voltage bpm.pmcon.ps=0 max frequency = 12mhz normal speed flash reduced voltage bpm.pmcon.ps=1 reset run sleep0 wait0 ret0 bkup0 run0 sleep cpu clock off 4 sub-modes wait all clocks off sleepwalking retention all clocks off full chip retention backup core domain off power save modes max frequency = 48mhz high speed flash nominal voltage bpm.pmcon.ps=2 sleep2 wait2 ret2 bkup2 run2
56 42023gs?sam?03/2014 atsam4l8/l4/l2 at power-up or after a reset, the atsam4l8/l4/l2 is in the run0 mode. only the necessary clocks are enabled allowing software execution. the power manager (pm) can be used to adjust the clock frequencies and to enable and disable the peripheral clocks. when the cpu is entering a power save mode, the cpu stops executing code. the user can choose between four power save modes to optimize power consumption: ? sleep mode: the cortex-m4 core is stopped , optionally some cl ocks are stopped, peripherals are kept running if enabled by the user. ? wait mode: all clock sources are stopped, the core and all the peripherals are stopped except the modules running with the 32khz clock if enabled. this is the lowest power configuration where sleepwalking is supported. ? retention mode: similar to the wait mode in terms of clock activity. this is the lowest power configuration where the logic is retained. ? backup mode: the core domain is powered off, the backup domain is kept powered. a wake up source exits the system to the run mode from which the power save mode was entered. a reset source always exits the system from the power save mode to the run0 mode. the configuration of the i/o lines are maintained in all power save modes. refer to section 9. ?backup power manager (bpm)? on page 677 . 7.1.1 sleep mode the sleep mode allows power optimizati on with the fastes t wake up time. the cpu is stopped. to further reduce power consumption, the user can switch off modules- clocks and synchronous clock sources through the bpm.pmcon.sleep field (see table 7-1 ). the required modules will be halted regardless of the bit settings of the mask registers in the power manager (pm.ah bmask, pm.apbxmask). notes: 1. from modules with clock running. 2. osc32k and rc32k will only remain operational if pre-enabled. 7.1.1.1 entering sleep mode the sleep mode is en tered by executing the wfi instruction. additionally, if the sleeponexit bit in the cort ex-m4 system control register (scr) is set, the sleep mode will also be entered when the cortex-m4 exits the lowest priority isr. this table 7-1. sleep mode configuration bpm.psave.sleep cpu clock ahb clocks apb clocks gclk clock sources: osc, rcfast, rc80m, pll, dfll rcsys osc32k rc32k (2) wake up sources 0 stop run run run run run any interrupt 1 stop stop run run run run any interrupt (1) 2 stop stop stop run run run any interrupt (1) 3 stop stop stop stop run run any interrupt (1)
57 42023gs?sam?03/2014 atsam4l8/l4/l2 mechanism can be useful for applications that only require the processor to run when an inter- rupt occurs. before entering the sleep mode , the user must configure: ? the sleep mode configuration fiel d (bpm.pmcon.sleep), refer to table 7-1 . ? the scr.sleepdeep bit to 0. (see the power management section in the arm cortex-m4 processor chapter). ? the bpm.pmcon.ret bit to 0. ? the bpm.pmcon.bkup bit to 0. 7.1.1.2 exiting sleep mode the nvic wakes the system up when it detects any non-masked interrupt with sufficient priority to cause exception entry. the system goes ba ck to the run mode from which the sleep mode was entered. the cpu and affected modules are restarted. note that even if an interrupt is enabled in sleep mode, it will not trigge r if the source module is not clocked. 7.1.2 wait mode and retention mode the wait and retention modes allow achievin g very low power cons umption while main- taining the core domain powered-on. internal sram and registers contents of the core domain are preserved. in these modes, all clocks are stopped except the 32khz clocks (osc32k, rc32k) which are kept running if enabled. in retention mode, the sleepwalking featur e is not supported and must not be used. 7.1.2.1 entering wait or retention mode the wait or retention modes are entered by ex ecuting the wfi instruction with the follow- ing settings: ? set the scr.sleepdeep bit to 1. (see the po wer management section in the arm cortex- m4 processor chapter). ? set the bpm.psave.bkup bit to 0. ? set the bpm.pmcon.ret bit to retention or wait mode. sleeponexit feature is also available. see ?entering sleep mode? on page 56 . 7.1.2.2 exiting wait or retention mode in wait or retention modes, synchronous clocks are stopped preventing interrupt sources from triggering. to wakeup the system, asynchronous wake up sources (ast, eic, usbc ...) should be enabled in the peripheral (refer to the documentation of the peripheral). the pm.awen (asynchronous wake up enable) regi ster should also be enabled for all peripheral except for eic and ast. when the enabled asynchronous wake up event occurs and the system is waken-up, it will gen- erate either: ? an interrupt on the pm wake interr upt line if enabled (refer to section 9. ?power manager (pm)? on page 677 ). in that case, the pm.wcause register indicates the wakeup source. ? or an interrupt directly from the peripheral if enabled (refer to the section of the peripheral). when waking up, the system goes back to the run mode mode from which the wait or retention mode was entered.
58 42023gs?sam?03/2014 atsam4l8/l4/l2 7.1.3 backup mode the backup mode allows achieving the lowest po wer consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. the core domain is powered-off. the internal sram and register contents of the core domain are lost. the backup domain is kept powered- on. the 32khz clock (rc32k or osc32k) is kept running if enabled to feed modules that require clocking. in backup mode, the configuration of the i/o lines is preserved. refer to section 9. ?backup power manager (bpm)? on page 677 to have more details. 7.1.3.1 entering backup mode the backup mode is entered by using the wfi instruction with the following settings: ? set the scr.sleepdeep bit to 1. (see the po wer management section in the arm cortex- m4 processor chapter). ? set the bpm.psave.bkup bit to 1. 7.1.3.2 exiting backup mode exit from backup mode happens if a reset occurs or if an enabled wake up event occurs. the reset sources are: ? bod33 reset ? bod18 reset ? wdt reset ? external reset in reset_n pin the wake up sources are: ? eic lines (level transition only) ? bod33 interrupt ? bod18 interrupt ? ast alarm, periodic, overflow ? wdt interrupt the rc32k or osc32k should be used as clock source for modules if required. the pmcon.ck32s is used to select on e of these two 32khz clock sources. exiting the backup mode is triggered by: ? a reset source: an internal reset sequence is performed according to the reset source. once vddcore is stable and has the correct value according to run0 mode, the internal reset is released and program execution starts. the corresponding reset source is flagged in the reset cause register (rcause) of the pm. ? a wake up source: the backup domain is not reset. an internal reset is generated to the core domain, and the system switches back to the previous run mode. once vddcore is stable and has the correct value, the internal reset in the core domain is released and program execution starts. the bkup bit is set in the reset cause register (rcause) of the pm. it allows the user to discriminate between the reset cause and a wake up cause from the backup mode. the wake up cause can be found in the backup wake up cause register (bpm.bkupwcause).
59 42023gs?sam?03/2014 atsam4l8/l4/l2 7.1.4 wakeup time 7.1.4.1 wakeup time from sleep mode the latency depends on the clock sources wake up time. if the clock sources are not stopped, there is no latency to wake the clocks up. 7.1.4.2 wakeup time from wait or retention mode the wake up latency consists of: ? the switching time from the lo w power configuration to the run mode power configuration. by default, the switching time is completed when all the voltage regulation system is ready. to speed-up the startup time, the user can set the fast wakeup bit in bpm.pmcon register. ? the wake up time of the rc os cillator used to start the system up. by default, the rcsys oscillator is used to startup the system. the user can use another clock source (rcfast for example) to speed up the startup time by configuring the pm.fastwkup register. refer to section 9. ?power manager (pm)? on page 677 . ? the flash memory wake up time. to have the shortest wakeup time, the user should: - set the bpm.pmcon.fastwkup bit. - configure the pm.fastsleep.fastrcosc field to use the rcfast main clock. - enter the wait or retention mode upon a wakeup, this is required to keep the main clock connected to rcfast until the voltage regulation system is fully ready (when bpm.is r.psok bit is one). during this wakeup period, the flashcalw module is automatically configured to operate in ?1 wait state mode?. 7.1.4.3 wake time from backup mode it is equal to the core domain logic reset latency (similar to the reset latency caused by an exter- nal reset in reset_n pin) added to the time required for the voltage regulation system to be stabilized.
60 42023gs?sam?03/2014 atsam4l8/l4/l2 7.1.5 power save mode summary table the following table shows a summary of the main power save modes: 7.2 power scaling the power scaling technique consists of adjusting the internal regulator output voltage (voltage scaling) to reduce the power consumption. according to the requirements in terms of perfor- mance, operating modes, and current consumptio n, the user can select the power scaling configuration that fits the best with its application. the power scaling configuration field (pmcon.ps) is provided in the backup power manager (bpm) module. in run mode, the user can adjust on the fly the power scaling configuration the figure 7.1 summarizes the different combination of the power scaling configuration which can be applied according to the power save mode. power scaling from a current power configuration to a new power configuration is done by halt- ing the cpu execution power scaling occurs afte r a wfi instruction. the system is halted until the new power configu- ration is stabilized. after handling the pm interrupt, th e system resumes from wfi. to scale the power, the following sequence is required: ? check the bpm.sr.psok bit to make sure the current power configuration is stabilized. table 7-2. power save mode configuration summary mode mode entry wake up sources core domain backup domain sleep wfi scr.sleepdeep bit = 0 bpm.pmcon.bkup bit = 0 any interrupt cpu clock off other clocks off depending on the bpm.pmcon.sleep field see ?sleep mode? on page 56 clocks off depending on the bpm.pmcon.sleep field see ?sleep mode? on page 56 wait wfi scr.sleepdeep bit = 1 bpm.pmcon.ret bit = 0 bpm.pmcon.bkup bit = 0 pm wake interrupt all clocks are off core domain is retained all clocks are off except rc32k or osc32k if running retention wfi scr.sleepdeep bit = 1 bpm.pmcon.ret bit = 1 bpm.pmcon.bkup bit = 0 pm wake interrupt all clocks are off core domain is retained all clocks are off except rc32k or osc32k if running backup wfi + scr.sleepdeep bit = 1 + bpm.pmcon.bkup bit = 1 eic interrupt bod33, bod18 interrupt and reset ast alarm, periodic, overflow wdt interrupt and reset external reset on reset_n pin off (not powered) all clocks are off except rc32k or osc32k if running
61 42023gs?sam?03/2014 atsam4l8/l4/l2 ? set the clock frequency to be supported in both power configurations. ? set the high speed read mode of the flash to be supported in both power scaling configurations ? only relevant when entering or exiting bpm.pmcon.ps=2 ? configure the bpm.pmcon.ps field to the new power configuration. ? set the bpm.pmcon.pscreq bit to one. ? disable all the interrupts except the pm wcause interrupt and enable only the psok asynchronous event in the awen register of pm. ? execute the wfi instruction. ? wait for pm interrupt. the new power configuration is reached when the system is waken up by the pm interrupt thanks to the psok event. by default, all features are available in all po wer scaling modes. howe ver some specific fea- tures are not available in ps1 (bpm.pmcon.ps=1) mode : ?usb ?dfll ?pll ? programming/erasing in flash
62 42023gs?sam?03/2014 atsam4l8/l4/l2 8. debug and test 8.1 features ? ieee1149.1 compliant jtag debug port ? serial wire debug port ? boundary-scan chain on all digital pins for board-level testing ? direct memory access and programmi ng capabilities th rough debug ports ? flash patch and breakpoint (fpb) unit for im plementing breakpoints and code patches ? data watchpoint and trace (dwt) unit for implem enting watchpoints, da ta tracing, and system profiling ? instrumentation trace macrocell (itm) for support of printf style debugging ? chip erase command and status ? unlimited flash user page read access ? cortex-m4 core reset source ? crc32 of any memory accessible through the bus matrix ? debugger hot plugging 8.2 overview debug and test features are made available to external tools by: ? the enhanced debug port (edp) embedding: ? a serial wire debug port (sw-dp) part of the arm coresight architecture ? an ieee 1149.1 jtag debug debug port (jtag-dp) part of the arm coresight architecture ? a supplementary ieee 1149.1 jtag tap machine that implem ents the boundary scan feature ? the system manager acces port (smap) providing unlimited flash user page read access, crc32 of any memory accessible through the bus matrix and cortex-m4 core reset services ? the ahb access port (ahb-ap) providing dir ect memory access, pr ogramming capabilities and standard debugging functions ? the instrumentation trace macrocell part of the arm coresight architecture for more information on arm debug components, please refer to: ? armv7-m architectu re reference manual ? arm debug interface v5.1 architecture specification document ? arm coresight archit ecture specification ? arm etm architecture specification v3.5 ? arm cortex-m4 technical reference manual
63 42023gs?sam?03/2014 atsam4l8/l4/l2 8.3 block diagram figure 8-1. debug and test block diagram note: boxes with a plain corner are sam4l specific. 8.4 i/o lines description refer to section 1.1.4 ?i/o lines description? on page 4 . swj-dp ahb-ap tck reset_n reset controller bscan-tap tdo tdi tms por boundary scan smap core reset request smap enhanced debug port dap bus hot_plugging jtag-filter ahb cortex-m4 nvic fpb dwt itm core instr data private peripheral bus (ppb) tpiu port muxing htop apb ahb cortex-m4 core reset ahb m m s chip erase edp core reset request system bus matrix
64 42023gs?sam?03/2014 atsam4l8/l4/l2 8.5 product dependencies 8.5.1 i/o lines refer to section 1.1.5.1 ?i/o lines? on page 5 . 8.5.2 power management refer to section 1.1.5.2 ?power management? on page 5 . 8.5.3 clocks refer to section 1.1.5.3 ?clocks? on page 5 . 8.6 core debug figure 8-2 shows the debug architecture used in the sam4l. the cortex-m4 embeds four func- tional units for debug: ? fpb (flash patch breakpoint) ? dwt (data watchpoint and trace) ? itm (instrumentation trace macrocell) ? tpiu (trace port interface unit) the debug architecture information that follows is mainly dedicated to developers of swj-dp emulators/probes and debugging tool vendors for cortex-m4 based microcontrollers. for further details on swj-dp see the cortex-m4 technical reference manual. figure 8-2. debug architecture 8.6.1 fpb (flash patch breakpoint) the fpb: ? implements hardware breakpoints ? patches (on the fly) code and data being fetched by the cortex-m4 core from code space with data in the system space. definition of code and system spaces can be found in the system address map section of the armv7-m architecture reference manual. 4 watchpoints pc sampler data address sampler data sampler interrupt trace cpu statistics dwt 6 breakpoints fpb software trace 32 channels time stamping itm swd/jtag swj-dp swo trace tpiu
65 42023gs?sam?03/2014 atsam4l8/l4/l2 the fpb unit contains: ? two literal comparators for matching against literal loads from code space, and remapping to a corresponding area in system space. ? six instruction comparators for matching against instruction fetches from code space and remapping to a corresponding area in system space. ? alternatively, comparators can also be configured to generate a breakpoint instruction to the processor core on a match. 8.6.2 dwt (data watchpoint and trace) the dwt contains four comparators which can be configured to generate the following: ? pc sampling packets at set intervals ? pc or data watchpoint packets ? watchpoint event to halt core the dwt contains counters for the items that follow: ? clock cycle (cyccnt) ? folded instructions ? load store unit (lsu) operations ? sleep cycles ? cpi (all instruction cycles except for the first cycle) ? interrupt overhead 8.6.3 itm (instrumentation trace macrocell) the itm is an application driven trace source that supports printf style debugging to trace oper- ating system (os) and application events, and emits diagnostic system information. the itm emits trace information as packets which can be generated by three different sources with sev- eral priority levels: ? software trace : this can be done thanks to the printf style debugging. for more information, refer to section ?how to configure the itm:? . ? hardware trace : the itm emits packets generated by the dwt. ? time stamping : timestamps are emitted relative to packets. the itm contains a 21-bit counter to generate the timestamp. how to configure the itm: the following example describes how to output trace data in asynchronous trace mode. ? configure the tpiu for asynchronous trace mode (refer to section ?5.4.3. how to configure the tpiu? ) ? enable the write accesses into the itm registers by writing ?0xc5acce55? into the lock access register (address: 0xe0000fb0) ? write 0x00010015 into the trace control register: ?enable itm ? enable synchronization packets ? enable swo behavior
66 42023gs?sam?03/2014 atsam4l8/l4/l2 ? fix the atb id to 1 ? write 0x1 into the trace enable register: ? enable the stimulus port 0 ? write 0x1 into the trace privilege register: ? stimulus port 0 only accessed in privileged mode (clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) ? write into the stimulus port 0 register: tpiu (trace port interface unit) the tpiu acts as a bridge between the on-chip trace data and the instruction trace macro- cell (itm). the tpiu formats and transmits trace data off-chip at frequencies asynchronous to the core. asynchronous mode: the tpiu is configured in asynchronous mode, trace data are output using the single trac- eswo pin. the traceswo signal is multiplexed with the tdo signal of the jtag debug port. as a consequence, asynchronous trace mode is only available when the serial wire debug mode is selected since tdo signal is used in jtag debug mode. two encoding formats are avail able for the single pin output: ? manchester encoded stream. this is the reset value. ? nrz_based uart byte structure 5.4.3. how to configure the tpiu this example only concerns the asynchronous trace mode. ? set the trcena bit to 1 into the debug exception and monitor register (0xe000edfc) to enable the use of trace and debug blocks. ? write 0x2 into the selected pin protocol register ? select the serial wire output ? nrz ? write 0x100 into the formatter and flush control register ? set the suitable clock prescaler value into the async clock prescaler register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool).
67 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7 enhanced debug port (edp) rev.: 1.0.0.0 8.7.1 features ? ieee1149.1 compliant jtag debug port ? serial wire debug port ? boundary-scan chain on all digital pins for board-level testing ? debugger hot-plugging ? smap core reset request source 8.7.2 overview the enhanced debug port embeds a standard arm debug port plus some specific hardware intended for testability and activati on of the debug port features. all the inform ation related to the arm debug interface implementation can be found in the arm debug interface v5.1 architec- ture specification document. it features: ? a single debug port (swj-dp), that provides the external physical connection to the interface and supports two dp implementations: ? the jtag debug port (jtag-dp) ? the serial wire debug port (sw-dp) ? a supplementary jtag tap (bscan-tap) connected in parallel with the jtag-dp that implements the boundary scan instructions detailed in ? a jtag-filter module that mo nitors tck and reset_n pins to handle specific features like the detection of a debugger hot-plugging and the request of reset of the cortex-m4 at startup. the jtag-filter module detects the presence of a debugger. when present, jtag pins are automatically assigned to the enhanced debug port(edp). if the swj-dp is switched to the sw mode, then tdi and tdo alternate functions are released. the jtag-filter also implements a cpu halt mechanism. when trigge red, the cortex-m4 is maintained under reset after the exter- nal reset is released to prevent any system corruption during later programmation operations.
68 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7.3 block diagram figure 8-3. enhanced debug port block diagram 8.7.4 i/o lines description tck reset_n tdo tdi tms boundary_scan jtag-filter edp core reset request enhanced debug port dap bus sw-dp swj-dp jtag-dp bscan-tap traceswo swclk swdio tdo tck tms tdi tdo tck tms tdi tck reset_n test_tap_sel table 8-1. i/o lines description name jtag debug port swd debug port type description type description tck/swclk i debug clock i serial wire clock tdi i debug data in - na tdo/traceswo o debug data out o trace asynchronous data out tms/swdio i debug mode select i/o serial wire input/output reset_n i reset i reset
69 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7.5 product dependencies 8.7.5.1 i/o lines the tck pin is dedicated to the edp. the other debug port pins default after reset to their gpio functionality and are automatically reassigned to the jtag functionalities on detection of a debugger. in serial wire mode, tdi and tdo can be used as gpio functions . note that in serial wire mode tdo can be used as a single pin trace output. 8.7.5.2 power management when a debugger is present, the connection is k ept alive allowing debug operations. as a side effect, the power is never turned off. the hot plugging functionality is always available except when the system is in backup power save mode. 8.7.5.3 clocks the swj-dp uses the external tck pin as its cloc k source. this clock must be provided by the external jtag master device. some of the jtag instructions are used to a ccess an access port (smap or ahb-ap). these instructions require the cpu clock to be running. if the cpu clock is not present because the cpu is in a power save mode where this clock is not provided, the power manager(pm) will automatically restor e the cpu clock on detection of a debug access. the rcsys clock is used as cpu clock when the external reset is applied to ensure correct access port operations. 8.7.6 module initialization this module is enabled as soon as a tck falling edge is detected when reset_n is not asserted (refer to section 8.7.7 below). moreover, the module is synchronously reseted as long as the tap machine is in the test_logic_reset (tlr ) state. it is adv ised asserting tms at least 5 tck clock peri ods after the debugger has been detected to ensure the module is in the tlr state prior to any op eration. this module also has th e ability to maintain the cortex-m4 under reset (refer to the section 8.7.8 ?smap core reset request source? on page 70 ). 8.7.7 debugger hot plugging the tck pin is dedicated to the edp. after re set has been released, the edp detects that a debugger has been attached when a tc k falling edge arises. figure 8-4. debugger hot plugging detection timings diagram tck reset_n hot_plugging tck reset_n hot plugging
70 42023gs?sam?03/2014 atsam4l8/l4/l2 the debug port pins assignation is then forced to the edp function even if they were already assigned to another module. this allows to conn ect a debugger at any time without reseting the device. the connection is non-intrusive meaning that the chip will continue its execution without being disturbed. the cpu can of course be halted later on by issuing cortex-m4 ocd features. 8.7.8 smap core reset request source the edp has the ability to send a request to t he smap for a cortex-m4 co re reset. the proce- dure to do so is to hold tck low until reset_n is released. this mechanism aims at halting the cpu to prevent it from changing the system configuration while the smap is operating. figure 8-5. smap core reset request timings diagram the smap can de-assert the core reset request for this operation, refer to section 2.8.8 ?cortex- m4 core reset source? on page 57 . 8.7.9 swj-dp the cortex-m4 embeds a swj-dp debug port which is the standard coresight ? debug port. it combines serial wire debug port (sw-dp), from 2 to 3 pins and jtag debug port(jtag-dp), 5 pins. by default, the jtag debug port is active. if the host debugger wants to switch to the serial wire debug port, it must provide a dedicated jtag sequence on tms/swdio and tck/swclk which disables jtag-dp and enables sw-dp. when the edp has been switched to serial wire mode, tdo/traceswo can be used for trace (for more information refer to the section below). the asynchronous trace output (trac- eswo) is multiplexed with tdo. so the asynchro nous trace can only be used with sw-dp, not jtag-dp. the swj-dp provides access to the ahb-ap and smap access ports which have the following apsel value: refer to the arm debug interface v5.1 architec ture specification for more details on swj-dp. reset request tck reset_n edp c ore reset request figure 8-6. access ports apsel acces port (ap) apsel ahb-ap 0 smap 1
71 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7.10 sw-dp and jtag-dp selection mechanism after reset, the swj-dp is in jtag mode but it can be switched to the serial wire mode. debug port selection mechanism is done by sending specific swdiotms sequence. the jtag-dp is selected by default after reset. ? switch from jtag-dp to sw-dp. the sequence is: ? send more than 50 swclktck cycles with swdiotms = 1 ? send the 16-bit sequence on swdiotms = 0111100111100111 (0x79e7 msb first) ? send more than 50 swclktck cycles with swdiotms = 1 ? switch from swd to jtag. the sequence is: ? send more than 50 swclktck cycles with swdiotms = 1 ? send the 16-bit sequence on swdiotms = 0011110011100111 (0x3ce7 msb first) send more than 50 swclktck cycles with swdiotms = 1 note that the bscan-tap is not available w hen the debug port is switched to serial mode. boundary scan instructions are not available. 8.7.11 jtag-dp and bscan-tap selection mechanism after the dp has been enabled, the bscan-tap and the jtag-dp run simultaneously has long as the swj-dp remains in jtag mode. each tap captures simultaneously the jtag instruc- tions that are shifted. if an instruction is re cognized by the bscan-tap, then the bscan-tap tdo is selected instead of the swj-dp tdo. tdo selection changes dynamically depending on the current instruction held in the bscan-tap instruction register.
72 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7.12 jtag instructions summary the implemented jtag instructions are shown in the table below. table 8-2. implemented jtag instructions list ir instruction value instruction description availability when protected component b0000 extest select boundary-scan chain as data register for testing circuitry external to the device. yes bscan-tap b0001 sample_preload take a snapshot of external pin values without affecting system operation. yes b0100 intest select boundary-scan chain for internal testing of the device. yes b0101 clamp bypass device through bypass register, while driving outputs from boundary-scan register. yes b1000 abort arm jtag-dp instruction yes swj-dp (in jtag mode) b1010 dpacc arm jtag-dp instruction yes b1011 apacc arm jtag-dp instruction yes b1100 - reserved yes b1101 - reserved yes b1110 idcode arm jtag-dp instruction yes b1111 bypass bypass this device through the bypass register. yes
73 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7.13 security restrictions the sam4l provide a security rest rictions mechanism to lock ac cess to the device. the device in the protected state when the flash security bi t is set. refer to section flash controller for more details. when the device is in the protected state the ah b-ap is locked. full access to the ahb-ap is re- enabled when the protected state is released by issuing a chip erase command. note that the protected state will read as programmed only after the system has been reseted. 8.7.13.1 notation table 8-4 on page 73 shows bit patterns to be shifted in a format like " p01 ". each character cor- responds to one bit, and eight bits are grouped t ogether for readab ility. the least significant bit is always shifted first, and the most significant bit shifted last. the symbols used are shown in table 8-3 . in many cases, it is not required to shift all bits through the data register. bit patterns are shown using the full width of the shift register, but the suggested or required bits are emphasized using bold text. i.e. given the pattern " 01010101 xxxxxxxx xxxxxxxx xxxxxxxx", the shift register is 32 bits, but the test or debug unit may choose to shift only 8 bits " 01010101 ". the following describes how to interpret the fields in the instruction description tables: table 8-3. symbol description symbol description 0 constant low value - always reads as zero. 1 constant high value - always reads as one. p the chip protected state. x a don?t care bit. any value can be shifted in, and output data should be ignored. e an error bit. read as one if an error occurred, or zero if not. b a busy bit. read as one if the smap was busy, or zero if it was not. s startup done bit. read as one if the system has started-up correctly. table 8-4. instruction description instruction description ir input value shows the bit pattern to shift into ir in t he shift-ir state in order to select this instruction. the pattern is show both in binary and in hexadecimal form for convenience. example: 1000 (0x8) ir output value shows the bit pattern shifted out of ir in t he shift-ir state when this instruction is active. example: p00s
74 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7.14 jtag instructions refer to the arm debug interface v5.1 architecture specification for more details on abort, dpacc, apacc and idcode instructions. 8.7.14.1 extest this instruction selects the boundary-scan chain as data register for testing circuitry external to the chip package. the contents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir-register is loaded with the extest instruction. starting in run-test/idle, the extest instruction is accessed the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. in update-ir: the data from the boundary-scan chain is applied to the output pins. 5. return to run-test/idle. 6. select the dr scan path. 7. in capture-dr: the data on the external pins is sampled into the boundary-scan chain. 8. in shift-dr: the boundary-scan chain is shifted by the tck input. 9. in update-dr: the data from the scan chain is applied to the output pins. 10. return to run-test/idle. 8.7.14.2 sample_preload this instruction takes a snap-shot of the input/ output pins without affect ing the system operation, and pre-loading the scan chain without updating the dr-latch. the boundary-scan chain is selected as data register. starting in run-test/idle, the device identification register is accessed in the following way: dr size shows the number of bits in the data register chain when this instruction is active. example: 32 bits dr input value shows which bit pattern to shift into the data register in the shift-dr state when this instruction is active. dr output value shows the bit pattern shifted out of the dat a register in the sh ift-dr state when this instruction is active. table 8-4. instruction description (continued) instruction description table 8-5. extest details instructions details ir input value 0000 (0x0) ir output value p00s dr size depending on boundary-scan chain, see bsdl-file. dr input value depending on boundary-scan chain, see bsdl-file. dr output value depending on boundary-scan chain, see bsdl-file.
75 42023gs?sam?03/2014 atsam4l8/l4/l2 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in capture-dr: the data on the external pins are sampled into the boundary-scan chain. 7. in shift-dr: the boundary-scan chain is shifted by the tck input. 8. return to run-test/idle. 8.7.14.3 intest this instruction selects the boundary-scan chain as data register for testing internal logic in the device. the logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. the device output pins are driven from the boundary-scan chain. starting in run-test/idle, the intest instruction is access ed the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. in update-ir: the data from the boundary-scan chain is applied to the internal logic inputs. 5. return to run-test/idle. 6. select the dr scan path. 7. in capture-dr: the data on the internal logic is sampled into the boundary-scan chain. 8. in shift-dr: the boundary-scan chain is shifted by the tck input. 9. in update-dr: the data from the boundary-scan chain is applied to internal logic inputs. 10. return to run-test/idle. table 8-6. sample_preload details instructions details ir input value 0001 (0x1) ir output value p00s dr size depending on boundary-scan chain, see bsdl-file. dr input value depending on boundary-scan chain, see bsdl-file. dr output value depending on boundary-scan chain, see bsdl-file. table 8-7. intest details instructions details ir input value 0100 (0x4) ir output value p001 dr size depending on boundary-scan chain, see bsdl-file. dr input value depending on boundary-scan chain, see bsdl-file. dr output value depending on boundary-scan chain, see bsdl-file.
76 42023gs?sam?03/2014 atsam4l8/l4/l2 8.7.14.4 clamp this instruction selects the bypass register as data register. the device output pins are driven from the boundary-scan chain. starting in run-test/idle, the clamp instruction is acce ssed the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. in update-ir: the data from the boundary-scan chain is applied to the output pins. 5. return to run-test/idle. 6. select the dr scan path. 7. in capture-dr: a logic ?0? is loaded into the bypass register. 8. in shift-dr: data is scanned from tdi to tdo through the bypass register. 9. return to run-test/idle. table 8-8. clamp details instructions details ir input value 0101 (0x5) ir output value p00s dr size 1 dr input value x dr output value x
77 42023gs?sam?03/2014 atsam4l8/l4/l2 8.8 ahb-ap access port the ahb-ap is a memory access port (mem-ap) as defined in the arm debug interface v5 architecture specification. the ahb-ap provides access to all memory and registers in the sys- tem, including processor registers through the sy stem control space (scs). system access is independent of the processor status. either sw-d p or swj-dp is used to access the ahb-ap. the ahb-ap is a master into the bus matrix. transactions are made using the ahb-ap pro- grammers model (please refer to the arm co rtex-m4 technical reference manual), which generates ahb-lite transactions into the bus matrix. the ahb-ap does not perform back-to- back transactions on the bus, so all transactions are non-sequential. the ahb-ap can perform unaligned and bit-band transactions. the bus matrix handles these. the ahb-ap transactions are not subject to mpu lookups. ahb-ap transact ions bypass the fpb, and so the fpb cannot remap ahb-ap transactions. ahb-ap transactions are little-endian. note that while an external reset is applied, ahb-ap accesses are not possible. in addition, access is denied when the protected state is set. in order to discard the protected state, a chip erase operation is necessary.
78 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9 system manager access port (smap) rev.: 1.0.0.0 8.9.1 features ? chip erase command and status ? cortex-m4 core reset source ? 32-bit cyclic redundancy check of an y memory accessible through the bus matrix ? unlimited flash user page read access ? chip identification register 8.9.2 overview the smap provides memory-related services and also cortex-m4 core reset control to a debug- ger through the debug port. this makes possible to halt the cpu and program the device after reset. 8.9.3 block diagram figure 8-7. smap block diagram 8.9.4 initializing the module the smap can be accessed only if the cpu clock is running and the swj-dp has been acti- vated by issuing a cdbgpwrup request. for more details, refer to the arm debug interface v5.1 architecture specification. then it must be enabled by writing a one to the en bit of the cr register (cr.en) before writing or reading other re gisters. if the smap is not enabled it will discard any read or write operation. 8.9.5 stopping the module to stop the module, the user must write a one to the dis bit of the cr register (cr.dis). all the user interface and internal re gisters will be cleared and the internal clock will be stopped. smap core reset request dap bus system bus matrix ahb chip_erase flash controller ahb smap ahb_master core dap interface reset controller pm cortex-m4 core reset system reset
79 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.6 security considerations in protected state this module may access sensible information located in the device memories. to avoid any risk of sensible data extraction from the module registers, all operations are non interruptible except by a disable command triggered by writing a one to cr.dis. issuing this command clears all the interface and internal registers. some registers have some special protection: ? it is not possible to read or write the length register when the part is protected. ? in addition, when the part is protected and an operation is ongoing, it is not possible to read the addr and data registers. once an operation has started, the user has to wait until it has terminated by polling the done field in the status register (sr.done). 8.9.7 chip erase the chip erase operation consists in: 1. clearing all the volatile memories in the system 2. clearing the whole flash array 3. clearing the protected state no proprietary or sensitive information is left in volatile memories once the protected state is disabled. this feature is operated by writing a one to the ce bit of the control register (cr.ce). when the operation completes, sr.done is asserted. 8.9.8 cortex-m4 core reset source the smap processes the edp core hold reset requests (refer to section 1.1.8 ?smap core reset request source? on page 6 ). when requested, it instructs the power manager to hold the cortex-m4 core under reset. the smap can de-assert the core re set request if a one is written to the hold core reset bit in the status clear register (scr.hcr). this has t he effect of releasing the cpu from its reset state. to assert again this signal, a new rese t sequence with tck tied low must be issued. note that clearing hcr with this module is only possible when it is enabled, for more information refer to section 8.9.4 ?initializing the module? on page 78 . also note that asserting reset_n automatically clears hcr.
80 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.9 unlimited flash user page read access the smap can access the user page even if the protected state is set. prior to operate such an access, the user should check that the module is not busy by checking that sr.state is equal to zerp. once the offset of the word to access inside the page is written in addr.addr, the read operation can be initiate d by writing a one in cr.fspr. the sr.state field will indicate the fspr state. addresses written to addr.addr must be world aligned. failing to do so will result in unpredictable behavior. the result can be read in the data register as soon as sr.done rises. the addr field is used as an of fset in the page, bits outside a page boundary will be silently discarded. the ad dr register is automatically in cremented at the end of the read operation making possible to dump consecutive words without writing the next offset into addr.addr. 8.9.10 32-bit cyclic redundancy check (crc) the smap unit provides support for calculati ng a cyclic redundancy check (crc) value for a memory area. the algorithm used is the industry standard crc32 algorithm using the generator polynomial 0xedb88320. 8.9.10.1 starting crc calculation to calculate crc for a memory rang e, the start address must be wr itten into the addr register, and the size of the memory range into the length register. both the start address and the length must be word aligned. the initial value used for the crc calculation must be written to the data register. this value will usually be 0xffffffff , but can be e.g. the result of a previous crc calcul ation if generat- ing a common crc of separate memory blocks. once completed, the calculated crc value can be read out of the data register. the read value must be inverted to match standard crc32 implementations, or kept non-inverted if used as starting point for subsequent crc calculations. if the device is in protected state, it is only poss ible to calculate the crc of the whole flash array. in most cases this area will be the entire onboard nonvolat ile memory. the addr, length, and data registers will be forced to predefined values once the crc operation is started, and user-written values are ignored. this allows the us er to verify the contents of a protected device. the actual test is started by writing a one in cr.crc. a running cr c operation can be can- celled by disabling the module (write a one in cr.dis). this has the effect of resetting the module. the module has to be restarted by issuing an enable command (write a one in cr.en). 8.9.10.2 interpreting the results the user should monitor the sr register (refer to section 8.9.11.2 ?status register? on page 83 ). when the operation is completed sr.done is set. then the sr.berr and sr.fail must be read to ensure that no bus error nor functional error occured.
81 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11 smap user interface note: 1. the reset value for this register is device specific. refe r to the module configuration sect ion at the end of this chapt er. 2. cr.mbist is ignored 3. scr.hcr is ignored 4. access is not allowed when an operation is ongoing table 8-9. smap register memory map offset register register name access (unprotected) access (protected) reset 0x0000 control register cr write-only write-only (partial) (2) 0x00000000 0x0004 status register sr read-only read-only 0x00000000 0x0008 status clear register scr w rite-only write-only (partial) (3) 0x00000000 0x000c address register addr read/write read/write (partial) (4) 0x00000000 0x0010 length register length read/write denied 0x00000000 0x0014 data register data read/write read/write (partial) (4) 0x00000000 0x0028 version register version read-only read-only - (1) 0x00f0 chip id register cidr read-only read-only - (1) 0x00f4 chip id extension regi ster exid read-only read-only - (1) 0x00fc ap identification register idr read-only read-only 0x003e0000
82 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.1 control register name: cr access type: write-only offset: 0x00 reset value: 0x00000000 writing a zero to a bit in this register has no effect. ? ce: chip erase writing a one to this bit triggers the flash erase all (ea) operation which clears all volatile memories, the whole flash array , the general purpose fuses and the protected stat e. the status register done field indicates the completion of the operation. reading this bit always returns 0 ? fspr: flash user page read writing a one to this bit triggers a read operation in the user page. the word pointed by the addr register in the page is read and written to the data register. addr is post incremented a llowing a burst of reads without modifying addr. sr.done must be read high prior to reading the data register. reading this bit always returns 0 ? crc: cyclic redundancy code writing a one triggers a crc calculation over a memory area de fined by the addr and length registers. reading this bit always returns 0 note: this feature is restrict ed while in protected state ?dis: disable writing a one to this bit disables the module. disabling the module resets the whole module immediately. ? en: enable writing a one to this bit enables the module. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - ce fspr crc dis en
83 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.2 status register name: sr access type: read-only offset: 0x04 reset value: 0x00000000 ?state: state ? dbgp: debugger present 1: a debugger is present (tck falling edge detected) 0: no debugger is present ?prot: protected 1: the protected state is set. the only way to overcome this is to issue a chip erase command. 0: the protected state is not set ? en: enabled 1: the block is in ready for operation 0: the block is disabled. write operat ions are not possible until the block is enabled by writing a one in cr.en. ?lck: lock 1: an operation could not be performed because chip protected state is on. 0: no security issues have been detected sincle last clear of this bit ? fail: failure 1: the requested operation failed 0: no failure has been detected sincle last clear of this bit ? berr: bus error 1: a bus error occured due to the unability to access part of the requested memory area. 31 30 29 28 27 26 25 24 ----- state 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -----dbgpproten 76543210 - - - lck fail berr hcr done value state description 0 idle idle state 1 ce chip erase operation is ongoing 2 crc32 crc32 operation is ongoing 3 fspr flash user page read 4-7 - reserved
84 42023gs?sam?03/2014 atsam4l8/l4/l2 0: no bus error has been detected sincle last clear of this bit ? hcr: hold core reset 1: the cortex-m4 core is held under reset 0: the cortex-m4 core is not held under reset ? done: operation done 1: at least one operation has terminated since last clear of this field 0: no operation has terminated since last clear of this field
85 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.3 status clear register name: scr access type: write-only offset: 0x08 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit clears the corresponding sr bit note: writing a one to bit hcr while the chip is in protected state has no effect 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - lck fail berr hcr done
86 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.4 address register name: addr access type: read/write offset: 0x0c reset value: 0x00000000 ? addr: address value addess values are always world aligned 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr - -
87 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.5 length register name: length access type: read/write offset: 0x10 reset value: 0x00000000 ? length: length value, bits 1-0 are always zero 31 30 29 28 27 26 25 24 length 23 22 21 20 19 18 17 16 length 15 14 13 12 11 10 9 8 length 76543210 length - -
88 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.6 data register name: data access type: read/write offset: 0x14 reset value: 0x00000000 ? data: generic data register 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
89 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.7 module version name: version access type: read-only offset: 0x28 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 ---- version 76543210 version
90 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.8 chip identification register name: cidr access type: read-only offset: 0xf0 reset value: - note: refer to section chipid for more information on this register. 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version
91 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.9 chip identification extension register name: exid access type: read-only offset: 0xf4 reset value: - note: refer to section chipid for more information on this register. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid
92 42023gs?sam?03/2014 atsam4l8/l4/l2 8.9.11.10 identification register name: idr access type: read-only offset: 0xfc reset value: - ? revision: revision ? cc: jep-106 continuation code atmel continuation code is 0x0 ? ic: jep-106 identity code atmel identification code is 0x1f ? clss: class 0: this ap is not a memory access port 1: this ap is a memory access port ? apid: ap identification ? apidv: ap identification variant for more information about this register, refer to the arm debug interface v5.1 architecture specification document. 31 30 29 28 27 26 25 24 revision cc 23 22 21 20 19 18 17 16 ic clss 15 14 13 12 11 10 9 8 reserved 76543210 apid apidv
93 42023gs?sam?03/2014 atsam4l8/l4/l2 8.10 available features in protected state table 8-10. features availablility wh en in protected state feature provider availability when protected hot plugging edp yes system bus r/w access ahb-ap no flash user page read access smap yes core hold reset clear from the smap interface smap no crc32 of any memory accessible through the bus matrix smap restricted (limited to the entire flash array) chip erase smap yes idcode smap yes
94 42023gs?sam?03/2014 atsam4l8/l4/l2 8.11 functional description 8.11.1 debug environment figure 8-8 shows a complete debug environment example. the swj-dp interface is used for standard debugging functions, such as downloading code and single-stepping through the pro- gram and viewing core and peripheral registers. figure 8-8. application debug environment example 8.11.2 test environment figure 8-9 shows a test environment example (jtag boundary scan). test vectors are sent and interpreted by the tester. in this example, the ?board in test? is designed using a number of jtag-compliant devices. these devices can be connected to form a single scan chain. sam4 host debugger pc sam4-based application board swj-dp connector swj-dp emulator/probe
95 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 8-9. application test environment example 8.11.3 how to initialize test and debug features to enable the jtag pins a falling edge event must be detected on the tck pin at any time after the reset_n pin is released. certain operations requires that the system is prevented from running code after reset is released. this is done by holding low the tck pin after the reset_n is released. this makes the smap assert the core_hold_reset signal that hold the cortex-m4 core under reset. to make the cpu run again, clear the chr bit in the status register (s r.chr) to de-assert the core_hold_reset signal. independent of the initial state of the tap controller, the test-logic- reset state can always be entered by holding tms high for 5 tck clock periods. this sequence should always be applied at the start of a jtag session and after enabling the jtag pins to bring the tap controller into a defined state before applying jtag commands. applying a 0 on tms for 1 tck period brings the tap controller to the run-test/idle state, which is the starting point for jtag operations. 8.11.4 how to disable test and debug features to disable the jtag pins the tck pin must be held high while reset _n pin is released. 8.11.5 typical jtag sequence assuming run-test/idle is the present state, a typical scenario for using the jtag interface is: 8.11.5.1 scanning in jtag instruction at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register - shift-ir state. while in this state, shift the 4 bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 4 lsbs in order to remain in the shift-ir state. the jtag instruction selects a particular data register as path between tdi and tdo and controls the cir- cuitry surrounding the selected data register. chip 2 chip n chip 1 sam4 sam4-based application board in test jtag connector tester test adaptor jtag probe
96 42023gs?sam?03/2014 atsam4l8/l4/l2 apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. figure 8-10. scanning in jtag instruction 8.11.5.2 scanning in/out data at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register - shift-dr state. while in this state, upload the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held low. while the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states are only used for navigating the state machine. as shown in the state diagram, the run-test/idle state need not be entered between selecting jtag instruction and using data registers. 8.11.6 boundary-scan the boundary-scan chain ha s the capability of driving and obser ving the logic levels on the dig- ital i/o pins, as well as the boundary between di gital and analog logic for analog circuitry having off-chip connections. at system level, all ics having jtag capabilities ar e connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. the controller compares the received data with the expected result. in this way, boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the 4 tap signals only. the four ieee 1149.1 defined mandatory jtag in structions idcode, bypass, sample/pre- load, and extest can be used for testing the printed circuit board. initial scanning of the data register path will show th e id-code of the device, sinc e idcode is the default jtag instruction. it may be desirable to have the device in reset during test mode. if not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. entering reset, the outputs of any port pin will instantly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device c an be set in the reset state by pu lling the external reset_n pin low. the extest instruction is used for sampling external pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest tck tap state tlr rti seldr selir capir shir ex1ir updir rti tms tdi instruction tdo impldefined
97 42023gs?sam?03/2014 atsam4l8/l4/l2 instruction for the first time. sample/preload c an also be used for taking a snapshot of the external pins during normal operation of the part. when using the jtag interface for boundary-sc an, the jtag tck clock is independent of the internal chip clock, whic h is not required to run. note: for pins connected to 5v lines care should be taken to not drive the pins to a logic one using boundary scan, as this will cr eate a current flowing from the 3,3v driver to the 5v pullup on the line. optionally a series resistor can be added between the line and the pin to reduce the current. 8.11.7 flash programming typical procedure flash programming is performed by operating fl ash controller commands. the flash controller is connected to the syst em bus matrix and is then contro llable from the ahp-ap. the ahb-ap cannot write the flash page buffer while the core_hold_reset is asserted. the ahb-ap cannot be accessed when the device is in protected state. it is important to ensure that the cpu is halted prior to operating any flash programming operation to prevent it from corrupting the sys- tem configuration. the recommended sequence is shown below: 1. at power up, reset_n is driven low by a debugger. the on-chip regulator holds the system in a por state until the input supply is above the por threshold. the system continues to be held in this static state until the internally regulated supplies have reached a safe operating. 2. pm starts, clocks are switched to the slow clock (core clock, system clock, flash clock, and any bus clocks that do not have clock gate control). internal resets are maintained due to the external reset. ? the debug port (dp) and access ports (ap) receives a clock and leave the reset state, 3. the debugger maintains a low level on tck and release reset_n. ? the smap asserts the core_hold_reset signal 4. the cortex-m4 core remains in reset stat e, meanwhile the rest of the system is released. 5. the debugger then configures the nvic to catch the cortex-m4 core reset vector fetch. for more information on how to program the nvic, refer to the armv7-m architecture reference manual. 6. the debugger writes a one in the smap scr.hcr to release the cortex-m4 core reset to make the system bus matrix accessible from the ahb-ap. 7. the cortex-m4 core initializes the sp, then read the exception vector and stalls 8. programming is available through the ahb-ap 9. after operation is co mpleted, the chip can be restarte d either by asserting reset_n or switching power off/on or clearing scr.hcr. make sure that the tck pin is high when releasing reset_n not to halt the core.
98 42023gs?sam?03/2014 atsam4l8/l4/l2 8.11.8 chip erase typical procedure the chip erase operation is triggered by writing a one in the ce bit in the control register (cr.ce). this clears first all volatile memories in the system and second the whole flash array. note that the user page is not erased in this process. to ensure that the chip erase operation is completed, check the done bit in the status register (sr.done). also note that the chip erase operation depends on clocks and power management features that can be altered by the cpu. it is important to ensure that it is stopped. the recommended sequence is shown below: 1. at power up, reset_n is driven low by a debugger. the on-chip regulator holds the system in a por state until the input supply is above the por threshold. the system continues to be held in this static state until the internally regulated supplies have reached a safe operating. 2. pm starts, clocks are switched to the slow clock (core clock, system clock, flash clock, and any bus clocks that do not have clock gate control). internal resets are maintained due to the external reset. ? the debug port and access ports receives a clock and leave the reset state 3. the debugger maintains a low level on tck and release reset_n. ? the smap asserts the core_hold_reset signal 4. the cortex-m4 core remains in reset stat e, meanwhile the rest of the system is released. 5. the chip erase operation can be performed by issuing the smap chip erase com- mand. in this case: ? volatile memories are cleared first ? followed by the clearing of the flash array ? followed by the clearing of the protected state 6. after operation is completed, the chip must be restarted by either controling reset_n or switching power off/on. make sure that the tck pin is high when releasing reset_n not to halt the core. 8.11.9 setting the protected state this is done by issuing a specific flash controller command, for more information, refer to the flash controller chapter and to section 8.11.7flash programming typical procedure97. the pro- tected state is defined by a highly secure flash builtin mechanism. note that for this programmation to propagate, it is required to reset the chip.
99 42023gs?sam?03/2014 atsam4l8/l4/l2 9. electrical characteristics 9.1 absolute maximum ratings* 9.2 operating conditions all the electrical characteristics are applicable to the following conditions unless otherwise spec- ified : ? operating voltage range 1,68v to 3,6v for vddin, vddio & vddana ? power scaling 0 and 2 modes ? operating temperature range: ta = -40c to 85c and for a junction temperature up to tj = 100c. typical values are base on ta = 25c and v ddin,vddio,vddana = 3,3v unless otherwise specified 9.3 supply characteristics refer to section 6. ?power and startup considerations? on page 46 for details about power supply table 9-1. absolute maximum ratings operating temperature..................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature...................................... -60c to +150c voltage on input pins with respect to ground ..........................-0.3v to v vdd (1) +0.3v 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3-5 on page 13 for details total dc output current on all i/o pins vddio ......................................................................... 120 ma total dc output current on all i/o pins vddin ........................................................................ 100 ma total dc output current on all i/o pins vddana........................................................................ 50 ma maximum operating voltage vddio, vddin .................... 3.6v table 9-2. supply characteristics symbol conditions voltag e min max unit v vddio, v vddin, v vddana ps1 (fcpu<=12mhz) linear mode 1.68 3.6 v ps0 & ps2 (fcpu>12mhz) linear mode 1.8 switching mode 2.0 (1) 1. below 2.3v, linear mode is more power efficient than switching mode.
100 42023gs?sam?03/2014 atsam4l8/l4/l2 table 9-3. supply rise rates and order (1) vddio, vddin and vddana must be connected together and as a consequence, rise synchronously 1. these values are based on characterization. th ese values are not covered by test limits in production. symbol parameter rise rate min max unit comment v vddio dc supply peripheral i/os 0.0001 2.5 v/s v vddin dc supply peripheral i/os and internal regulator 0.0001 2.5 v/s v vddana analog supply voltage 0.0001 2.5 v/s
101 42023gs?sam?03/2014 atsam4l8/l4/l2 9.4 maximum clock frequencies table 9-4. maximum clock frequencies in po wer scaling mode 0/2 and run mode symbol parameter description max units f cpu cpu clock frequency 48 mhz f pba pba clock frequency 48 f pbb pbb clock frequency 48 f pbc pbc clock frequency 48 f pbd pbd clock frequency 48 f gclk0 gclk0 clock frequency dfllif main reference, gclk0 pin 50 f gclk1 gclk1 clock frequency dfllif dithering and ssg reference, gclk1 pin 50 f gclk2 gclk2 clock frequency ast, gclk2 pin 20 f gclk3 gclk3 clock frequency catb, gclk3 pin 50 f gclk4 gclk4 clock frequency flo and aesa 50 f gclk5 gclk5 clock frequency gloc, tc0 and rc32kifb_ref 80 f gclk6 gclk6 clock frequency abdacb and iisc 50 f gclk7 gclk7 clock frequency usbc 50 f gclk8 gclk8 clock frequency tc1 and pevc[0] 50 f gclk9 gclk9 clock frequency pll0 and pevc[1] 50 f gclk10 gclk10 clock frequency adcife 50 f gclk11 gclk11 clock frequency master generic clock. can be used as source for other generic clocks 150 f osc0 osc0 output frequency oscillator 0 in crystal mode 30 oscillator 0 in digital clock mode 50 f pll pll output frequency phase locked loop 240 f dfll dfll output frequency digital frequency locked loop 220 f rc80m rc80m output frequency internal 80mhz rc oscillator 80
102 42023gs?sam?03/2014 atsam4l8/l4/l2 table 9-5. maximum clock frequencies in po wer scaling mode 1 and run mode symbol parameter description max units f cpu cpu clock frequency 12 mhz f pba pba clock frequency 12 f pbb pbb clock frequency 12 f pbc pbc clock frequency 12 f pbd pbd clock frequency 12 f gclk0 gclk0 clock frequency dfllif main reference, gclk0 pin 16.6 f gclk1 gclk1 clock frequency dfllif dithering and ssgreference, gclk1 pin 16.6 f gclk2 gclk2 clock frequency ast, gclk2 pin 6.6 f gclk3 gclk3 clock frequency catb, gclk3 pin 17.3 f gclk4 gclk4 clock frequency flo and aesa 16.6 f gclk5 gclk5 clock frequency gloc, tc0 and rc32kifb_ref 26.6 f gclk6 gclk6 clock frequency abdacb and iisc 16.6 f gclk7 gclk7 clock frequency usbc 16.6 f gclk8 gclk8 clock frequency tc1 and pevc[0] 16.6 f gclk9 gclk9 clock frequency pll0 and pevc[1] 16.6 f gclk10 gclk10 clock frequency adcife 16.6 f gclk11 gclk11 clock frequency master generic clock. can be used as source for other generic clocks 51.2 f osc0 osc0 output frequency oscillator 0 in crystal mode 16 oscillator 0 in digital clock mode 16 f pll pll output frequency phase locked loop n/a f dfll dfll output frequency digital frequency locked loop n/a f rc80m rc80m output frequency internal 80mhz rc oscillator n/a
103 42023gs?sam?03/2014 atsam4l8/l4/l2 9.5 power consumption 9.5.1 power scaling 0 and 2 the values in table 9-6 are measured values of power consumption under the following condi- tions, except where noted: ? operating conditions for power scaling mode 0 and 2 ?v vddin = 3.3v ? power scaling mode 0 is used for cpu frequencies under 36mhz ? power scaling mode 2 is used for cpu frequencies above 36mhz ? wake up time from low power modes is measured from the edge of the wakeup signal to the first instruction fetched in flash. ? oscillators ? osc0 (crystal o scillator) stopped ? osc32k (32khz crystal oscillator) running with external 32khz crystal ? dfll using osc32k as reference and running at 48mhz ? clocks ? dfll used as main clock source ? cpu, ahb clocks undivided ? apbc and apbd clocks divided by 4 ? apba and apbb bridges off ? the following peripheral clocks running ? pm, scif, ast, flashcalw, apbc and apbd bridges ? all other peripheral clocks stopped ? i/os are inactive with internal pull-up ? cpu is running on flash with 1 wait state ? low power cache enabled ? bod18 and bod33 disabled table 9-6. atsam4l4/2 current consumption and wakeup time for power scaling mode 0 and 2 mode conditions t a typical wakeup time typ max (1) unit run cpu running a fibonacci algorithm linear mode 25c n/a 296 326 a/mhz 85c 300 332 cpu running a coremark algorithm linear mode 25c n/a 320 377 85c 326 380 cpu running a fibonacci algorithm switching mode 25c n/a 177 198 85c 179 200 cpu running a coremark algorithm switching mode 25c n/a 186 232 85c 195 239
104 42023gs?sam?03/2014 atsam4l8/l4/l2 sleep0 switching mode 25c 9 * main clock cycles 3817 4033 a 85c 3934 4174 sleep1 switching mode 25c 9 * main clock cycles + 500ns 2341 2477 85c 2437 2585 sleep2 switching mode 25c 9 * main clock cycles + 500ns 1758 1862 85c 1847 1971 sleep3 linear mode 25c 51 60 wait osc32k and ast running fast wake-up enable 1.5s 5.9 8.7 osc32k and ast stopped fast wake-up enable 4.7 7.6 retention osc32k running ast running at 1khz 1.5s 3.1 5.1 ast and osc32k stopped 2.2 4.2 backup osc32k running ast running at 1khz 1.5 3.1 ast and osc32k stopped 0.9 1.7 1. these values are based on characterization. these values are not covered by test limits in production. table 9-6. atsam4l4/2 current consumption and wakeup time for power scaling mode 0 and 2 mode conditions t a typical wakeup time typ max (1) unit table 9-7. atsam4l8 current consumption and wakeup time for power scaling mode 0 and 2 mode conditions t a typical wakeup time typ max (1) unit run cpu running a fibonacci algorithm linear mode 25c n/a 319 343 a/mhz 85c 326 350 cpu running a coremark algorithm linear mode 25c n/a 343 387 85c 351 416 cpu running a fibonacci algorithm switching mode 25c n/a 181 198 85c 186 203 cpu running a coremark algorithm switching mode 25c n/a 192 232 85c 202 239
105 42023gs?sam?03/2014 atsam4l8/l4/l2 9.5.2 power scaling 1 the values in table 34-7 are measured values of power consumption under the following condi- tions, except where noted: ? operating conditions for power scaling mode 1 ?v vddin = 3.3v ? wake up time from low power modes is measured from the edge of the wakeup signal to the first instruction fetched in flash. ? oscillators ? osc0 (crystal oscillator) and osc32k (32khz crystal o scillator) stopped ? rcfast running at 12mhz ? clocks ? rcfast used as main clock source ? cpu, ahb clocks undivided ? apbc and apbd clocks divided by 4 ? apba and apbb bridges off ? the following peripheral clocks running ? pm, scif, ast, flashcalw, apbc and apbd bridges sleep0 switching mode 25c 9 * main clock cycles 3817 4033 a 85c 4050 4507 sleep1 switching mode 25c 9 * main clock cycles + 500ns 2341 2477 85c 2525 2832 sleep2 switching mode 25c 9 * main clock cycles + 500ns 1758 1862 85c 1925 1971 sleep3 linear mode 25c 51 60 wait osc32k and ast running fast wake-up enable 1.5s 6.7 osc32k and ast stopped fast wake-up enable 5.5 retention osc32k running ast running at 1khz 1.5s 3.9 ast and osc32k stopped 3.0 backup osc32k running ast running at 1khz 1.5 3.1 ast and osc32k stopped 0.9 1.7 1. these values are based on characterization. these values are not covered by test limits in production. table 9-7. atsam4l8 current consumption and wakeup time for power scaling mode 0 and 2 mode conditions t a typical wakeup time typ max (1) unit
106 42023gs?sam?03/2014 atsam4l8/l4/l2 ? all other peripheral clocks stopped ? i/os are inactive with internal pull-up ? cpu is running on flash with 1 wait state ? low power cache enabled ? bod18 and bod33 disabled table 9-8. atsam4l4/2 current consumption and wakeup time for power scaling mode 1 mode conditions t a typical wakeup time typ max (1) unit run cpu running a fibonacci algorithm linear mode 25c n/a 205 224 a/mhz 85c 212 231 cpu running a coremark algorithm linear mode 25c n/a 213 244 85c 230 270 cpu running a fibonacci algorithm switching mode 25c n/a 95 112 85c 100 119 cpu running a coremark algorithm switching mode 25c n/a 100 128 85c 107 138 sleep0 switching mode 25c 9 * main clock cycles 527 627 a 85c 579 739 sleep1 switching mode 25c 9 * main clock cycles + 500ns 369 445 85c 404 564 sleep2 switching mode 25c 9 * main clock cycles + 500ns 305 381 85c 334 442 sleep3 linear mode 25c 46 55 wait osc32k and ast running fast wake-up enable 1.5s 4.7 7.5 osc32k and ast stopped fast wake-up enable 3.5 6.3 retention osc32k running ast running at 1khz 1.5s 2.6 4.8 ast and osc32k stopped 1.5 4 backup osc32k running ast running at 1khz 1.5 3.1 ast and osc32k stopped 0.9 1.7 1. these values are based on characterization. these values are not covered by test limits in production.
107 42023gs?sam?03/2014 atsam4l8/l4/l2 table 9-9. atsam4l8 current consumption and wakeup time for power scaling mode 1 mode conditions t a typical wakeup time typ max (1) unit run cpu running a fibonacci algorithm linear mode 25c n/a 222 240 a/mhz 85c 233 276 cpu running a coremark algorithm linear mode 25c n/a 233 276 85c 230 270 cpu running a fibonacci algorithm switching mode 25c n/a 100 112 85c 100 119 cpu running a coremark algorithm switching mode 25c n/a 104 128 85c 107 138 sleep0 switching mode 25c 9 * main clock cycles 527 627 a 85c 579 739 sleep1 switching mode 25c 9 * main clock cycles + 500ns 369 445 85c 404 564 sleep2 switching mode 25c 9 * main clock cycles + 500ns 305 381 85c 334 442 sleep3 linear mode 25c 46 55 wait osc32k and ast running fast wake-up enable 1.5s 5.5 osc32k and ast stopped fast wake-up enable 4.3 retention osc32k running ast running at 1khz 1.5s 3.4 ast and osc32k stopped 2.3 backup osc32k running ast running at 1khz 1.5 3.1 ast and osc32k stopped 0.9 1.7 1. these values are based on characterization. these values are not covered by test limits in production. table 9-10. typical power consumption running coremark on cpu clock sources (1) clock source conditions regulator frequency (mhz) typ unit
108 42023gs?sam?03/2014 atsam4l8/l4/l2 rcsys (mcsel = 0) power scaling mode 1 switching mode 0.115 978 a/mhz osc0 (mcsel = 1) power scaling mode 1 0.5 354 12 114 power scaling mode 0 12 228 30 219 osc0 (mcsel = 1) external clock (mode=0) power scaling mode 1 0.6 292 12 111 power scaling mode 0 12 193 power scaling mode 2 50 194 pll (mcsel = 2) power scaling mode 2 input freq = 4mhz from osc0 40 188 50 185 dfll (mcsel = 3) power scaling mode 0 input freq = 32khz from osc32k 20 214 power scaling mode 2 input freq = 32khz from osc32k 50 195 rc1m (mcsel = 4) power scaling mode 1 1 267 rcfast (mcsel = 5) power scaling mode 1 rcfast frequency is configurable from 4 to 12mhz 4153 12 114 rc80m (mcsel = 6) power scaling mode 2 f cpu = rc80m / 2 = 40mhz 40 211 1. these values are based on characterization. these values are not covered by test limits in production. table 9-10. typical power consumption running coremark on cpu clock sources (1)
109 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 9-1. typical power consumption runni ng coremark (from above table) note: for variable frequency oscillators, linear interpolation between high and low settings figure 9-2. measurement schematic, switching mode vddin vddout vddcore vddio vddana amp 0
110 42023gs?sam?03/2014 atsam4l8/l4/l2 9.5.3 peripheral power consumption in power scaling mode 0 and 2 the values in table 9-11 are measured values of power consumption under the following conditions: ? operating conditions, internal core supply ( figure 9-2 ) ?v vddin = 3.3v ?v vddcore supplied by the internal r egulator in switching mode ?t a = 25 c ? oscillators ? osc0 (crystal oscillator) stopped ? osc32k (32khz crystal oscillator) running with external 32khz crystal ? dfll running at 48mhz with osc32k as reference clock ? clocks ? dfll used as main clock source ? cpu, ahb, and pb clocks undivided ? i/os are inactive with internal pull-up ? flash enabled in high speed mode ? cpu in sleep0 mode ? bod18 and bod33 disabled consumption active is the added current consumption when the module clock is turned on.
111 42023gs?sam?03/2014 atsam4l8/l4/l2 9.5.4 . peripheral power consumption in power scaling mode 1 the values in table 9-13 are measured values of power consumption under the following conditions: table 9-11. typical current consumption by peripheral in power scaling mode 0 and 2 (1) 1. these numbers are valid for the measured condit ion only and must not be extrapolated to other frequencies peripheral typ consumption active unit iisc 1.0 a/mhz spi 1.9 tc 6.3 twim 1.5 twis 1.2 usart 8.5 adcife (2) 3.1 dacc 1.3 acifc (2) 2. includes the current consumption on vddana and advrefp. 3.1 gloc 0.4 abdacb 0.7 trng 0.9 pa r c 0 . 7 catb 3.0 lcdca 4.4 pdca 1.0 crccu 0.3 usbc 1.5 pevc 5.6 chipid 0.1 scif 6.4 freqm 0.5 gpio 7.1 bpm 0.9 bscif 4.6 ast 1.5 wdt 1.4 eic 0.6 picouart 0.3
112 42023gs?sam?03/2014 atsam4l8/l4/l2 ? operating conditions, internal core supply ( figure 9-2 ) ?v vddin = 3.3v ?v vddcore = 1.2 v, supplied by the internal regulator in switching mode ?t a = 25 c ? oscillators ? osc0 (crystal oscillator) stopped ? osc32k (32khz crystal oscillator) running with external 32khz crystal ? rcfast running @ 12mhz ? clocks ? rcfast used as main clock source ? cpu, ahb, and pb clocks undivided ? i/os are inactive with internal pull-up ? flash enabled in normal mode ? cpu in sleep0 mode ? bod18 and bod33 disabled consumption active is the added current consumption when the module clock is turned on
113 42023gs?sam?03/2014 atsam4l8/l4/l2 table 9-12. typical current consumption by peripheral in power scaling mode 1 (1) 1. these numbers are valid for the measured condit ion only and must not be extrapolated to other frequencies peripheral typ consumption active unit iisc 0.5 a/mhz spi 1.1 tc 3.1 twim 0.8 twis 0.7 usart 4.4 adcife (2) 1.6 dacc 0.6 acifc (2) 2. includes the current consumption on vddana and advrefp. 1.6 gloc 0.1 abdacb 0.3 trng 0.3 pa r c 0 . 3 catb 1.5 lcdca 2.2 pdca 0.4 crccu 0.3 usbc 0.9 pevc 2.8 chipid 0.1 scif 3.1 freqm 0.2 gpio 3.4 bpm 0.4 bscif 2.3 ast 0.8 wdt 0.8 eic 0.3 picouart 0.2
114 42023gs?sam?03/2014 atsam4l8/l4/l2 9.6 i/o pin c haracteristics 9.6.1 normal i/o pin table 9-13. normal i/o pin characteristics (1) 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3-5 on page 13 for details symbol parameter conditions min typ max units r pullup pull-up resistance (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization 40 k r pulldown pull-down resistance (2) 40 k v il input low-level voltage -0.3 0.2 * v vdd v v ih input high-level voltage 0.8 * v vdd v vdd + 0.3 v ol output low-level voltage 0.4 v oh output high-level voltage v vdd - 0.4 i ol output low-level current (3) odcr0=0 1.68v2.7v load = 25pf 17 mhz osrr0=1 15 mhz osrr0=0 odcr0=1, v vdd >2.7v load = 25pf 27 mhz osrr0=1 23 mhz i leak input leakage current (3) pull-up resistors disabled 0.01 1 a c in input capacitance (2) 5pf
115 42023gs?sam?03/2014 atsam4l8/l4/l2 3. these values are based on characterization. these values are not covered by test limits in production 9.6.2 high-drive i/o pin : pa02, pc04, pc05, pc06 table 9-14. high-drive i/o pin characteristics (1) symbol parameter conditions min typ max units r pullup pull-up resistance (2) 40 k r pulldown pull-down resistance (2) 40 k v il input low-level voltage -0.3 0.2 * v vdd v v ih input high-level voltage 0.8 * v vdd v vdd + 0.3 v ol output low-level voltage 0.4 v oh output high-level voltage v vdd - 0.4 i ol output low-level current (3) odcr0=0 1.68v2.7v load = 25pf 22 mhz osrr0=1 17 mhz osrr0=0 odcr0=1, v vdd >2.7v load = 25pf 35 mhz osrr0=1 26 mhz i leak input leakage current (3) pull-up resistors disabled 0.01 2 a c in input capacitance (2) 10 pf 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3-5 on page 13 for details 2. these values are based on simulation. these values are no t covered by test limits in production or characterization 3. these values are based on characterization. these values are not covered by test limits in production
116 42023gs?sam?03/2014 atsam4l8/l4/l2 9.6.3 usb i/o pin : pa25, pa26 9.6.4 twi pin : pa21, pa22, pa23, pa24, pb14, pb15 table 9-15. usb i/o pin characteristics in gpio configuration (1) 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3-5 on page 13 for details symbol parameter conditions min typ max units r pullup pull-up resistance (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization 40 k r pulldown pull-down resistance (2) 40 k v il input low-level voltage -0.3 0.2 * v vdd v v ih input high-level voltage 0.8 * v vdd v vdd + 0.3 v ol output low-level voltage 0.4 v oh output high-level voltage v vdd - 0.4 i ol output low-level current (3) 3. these values are based on characterization. these values are not covered by test limits in production odcr0=0 1.68v 117 42023gs?sam?03/2014 atsam4l8/l4/l2 i cs current source (3) driveh=0 0.5 ma driveh=1 1 driveh=2 1.5 driveh=3 3 f max max frequency (2) hsmode with current source; drivex=3, slew=0 cbus = 400pf, v vdd = 1.68v 3.5 6.4 mhz t rise rise time (2) hsmode mode, drivex=3, slew=0 cbus = 400pf, rp = 440ohm, v vdd = 1.68v 28 38 ns t fall fall time (2) standard mode, drivex=3, slew=0 cbus = 400pf, rp = 440ohm, v vdd = 1.68v 50 95 ns hsmode mode, drivex=3, slew=0 cbus = 400pf, rp = 440ohm, v vdd = 1.68v 50 95 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3-5 on page 13 for details 2. these values are based on simulation. these values are no t covered by test limits in production or characterization 3. these values are based on characterization. these values are not covered by test limits in production table 9-16. twi pin characteristics in twi configuration (1) symbol parameter conditions min typ max units table 9-17. twi pin characteristics in gpio configuration (1) symbol parameter conditions min typ max units r pullup pull-up resistance (2) 40 k r pulldown pull-up resistance (2) 40 k v il input low-level voltage -0.3 0.2 * v vdd v v ih input high-level voltage 0.8 * v vdd v vdd + 0.3 v v ol output low-level voltage 0.4 v v oh output high-level voltage v vdd - 0.4 i ol output low-level current (3) odcr0=0 1.68v 118 42023gs?sam?03/2014 atsam4l8/l4/l2 t rise rise time (2) osrr0=0 odcr0=0 1.68v 119 42023gs?sam?03/2014 atsam4l8/l4/l2 9.6.5 high drive twi pin : pb00, pb01 table 9-19. high drive twi pin characteristics in twi configuration (1) 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3-5 on page 13 for details symbol parameter conditions min typ max units r pullup pull-up resistance (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization pb00, pb01 40 k r pulldown pull-down resistance (2) 40 k v il input low-level voltage -0.3 0.3 * v vdd v v ih input high-level voltage 0.7 * v vdd v vdd + 0.3 v ol output low-level voltage 0.4 v oh output high-level voltage v vdd - 0.4 i ol output low-level current (3) 3. these values are based on characterization. these values are not covered by test limits in production drivel=0 0.5 ma drivel=1 1.0 drivel=2 1.6 drivel=3 3.1 drivel=4 6.2 drivel=5 9.3 drivel=6 15.5 drivel=7 21.8 i cs current source (2) driveh=0 0.5 ma driveh=1 1 driveh=2 1.5 driveh=3 3 f max max frequency (2) hsmode with current source; drivex=3, slew=0 cbus = 400pf, v vdd = 1.68v 3.5 6.4 mhz t rise rise time (2) hsmode mode, drivex=3, slew=0 cbus = 400pf, rp = 440ohm, v vdd = 1.68v 28 38 ns t fall fall time (2) standard mode, drivex=3, slew=0 cbus = 400pf, rp = 440ohm, v vdd = 1.68v 50 95 ns hsmode mode, drivex=3, slew=0 cbus = 400pf, rp = 440ohm, v vdd = 1.68v 50 95
120 42023gs?sam?03/2014 atsam4l8/l4/l2 table 9-20. high drive twi pin characterist ics in gpio configuration (1) symbol parameter conditions min typ max units r pullup pull-up resistance (2) 40 k r pulldown pull-up resistance (2) 40 k v il input low-level voltage -0.3 0.2 * v vdd v v ih input high-level voltage 0.8 * v vdd v vdd + 0.3 v ol output low-level voltage 0.4 v oh output high-level voltage v vdd - 0.4 i ol output low-level current (3) odcr0=0 1.68v 121 42023gs?sam?03/2014 atsam4l8/l4/l2 9.7 oscillator characteristics 9.7.1 oscillator 0 (osc0) characteristics 9.7.1.1 digital clock characteristics the following table describes the characteristics for the oscillator when a digital clock is applied on xin. 9.7.1.2 crystal oscilla tor characteristics the following table describes the characteristics for the oscillator when a crystal is connected between xin and xout as shown in figure 9-3 . the user must choose a crystal oscillator where the crystal load capacitance c l is within the range given in the table. the exact value of c l can be found in the crystal datasheet. the capacitance of the external capacitors (c lext ) can then be computed as follows: where c stray is the capacitance of the pins and pcb, c shunt is the shunt capacitance of the crystal. table 9-22. digital clock ch aracteristics symbol parameter conditions min typ max units f cpxin xin clock frequency (1) 50 mhz t cpxin xin clock duty cycle (1) 40 60 % t startup startup time n/a cycles 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. c lext 2c l c stray c shunt ? ? () = table 9-23. crystal oscillator characteristics symbol parameter conditions min typ max unit f out crystal oscillator frequency (1) 0.6 30 mhz esr crystal equivalent series resistance (2) f = 0.455mhz, c lext = 100pf scif.oscctrl.gain = 0 17000 f = 2mhz, c lext = 20pf scif.oscctrl.gain = 0 2000 f = 4mhz, c lext = 20pf scif.oscctrl.gain = 1 1500 f = 8mhz, c lext = 20pf scif.oscctrl.gain = 2 300 f = 16mhz, c lext = 20pf scif.oscctrl.gain = 3 350 f = 30mhz, c lext = 18pf scif.oscctrl.gain = 4 45
122 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 9-3. oscillator connection c l crystal load capacitance (1) 618 pf c shunt crystal shunt capacitance (1) 7 c xin parasitic capacitor load (2) tqfp100 package 4.91 c xout parasitic capacitor load (2) 3.22 t startup startup time (1) scif.oscctrl.gain = 2 30 000 (3) cycles i osc current consumption (1) active mode, f = 0.6mhz, scif.oscctrl.gain = 0 30 a active mode, f = 4mhz, scif.oscctrl.gain = 1 130 active mode, f = 8mhz, scif.oscctrl.gain = 2 260 active mode, f = 16mhz, scif.oscctrl.gain = 3 590 active mode, f = 30mhz, scif.oscctrl.gain = 4 960 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. 2. these values are based on characterization. these values are not covered by test limits in production. 3. nominal crystal cycles. table 9-23. crystal oscillator characteristics symbol parameter conditions min typ max unit c shunt l m r m c m c stray c lext c lext xin xout crystal
123 42023gs?sam?03/2014 atsam4l8/l4/l2 9.7.2 32khz crystal oscillator (osc32k) characteristics figure 9-3 and the equation above also applies to t he 32khz oscillator connection. the user must choose a crystal oscillator wh ere the crystal load capacitance c l is within the range given in the table. the exact value of c l can then be found in the crystal datasheet. table 9-24. digital clock ch aracteristics symbol parameter conditions min typ max units f cpxin32 xin32 clock frequency (1) 6mhz xin32 clock duty cycle (1) 40 60 % t startup startup time n/a cycles 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. table 9-25. 32 khz crystal oscilla tor characteristics symbol parameter conditions min typ max unit f out crystal oscillator frequency 32 768 hz t startup startup time (1) r m = 100k , c l = 12.5pf 30000 (2) cycles c l crystal load capacitance (1) 612.5 pf c shunt crystal shunt capacitance (1) 0.8 1.7 c xin parasitic capacitor load (3) tqfp100 package 3.4 c xout parasitic capacitor load (3) 2.72 i osc32k current consumption (1) 350 na esr xtal crystal equivalent series resistance (1) f=32.768khz oscctrl32.mode=1 safety factor = 3 oscctrl32.selcurr=0 c l =6pf 28 k oscctrl32.selcurr=4 72 oscctrl32.selcurr=8 114 oscctrl32.selcurr=15 313 oscctrl32.selcurr=0 c l =9pf 14 k oscctrl32.selcurr=4 36 oscctrl32.selcurr=8 100 oscctrl32.selcurr=15 170 crystal equivalent series resistance (3) f=32.768khz oscctrl32.mode=1 safety factor = 3 oscctrl32.selcurr=4 c l =12.5pf 15.2 k oscctrl32.selcurr=6 61.8 oscctrl32.selcurr=8 101.8 oscctrl32.selcurr=10 138.5 oscctrl32.selcurr=15 228.5 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. 2. nominal crystal cycles. 3. these values are based on characterization. these values are not covered by test limits in production.
124 42023gs?sam?03/2014 atsam4l8/l4/l2 9.7.3 phase locked loop (pll) characteristics 9.7.4 digital frequency locked loop (dfll) characteristics table 9-26. phase locked loop characteristics symbol parameter conditions min typ max unit f out output frequency (1) 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. pll is not availabe in ps1 48 240 mhz f in input frequency (1) 416 i pll current consumption (1) fout=80mhz 200 a fout=240mhz 500 t startup startup time, from enabling the pll until the pll is locked (1) wide bandwidth mode disabled 8 s wide bandwidth mode enabled 30 table 9-27. digital frequency locked loop characteristics symbol parameter conditions min typ max unit f out output frequency (1) dfll is not availabe in ps1 20 150 mhz f ref reference frequency (1) 8 150 khz accuracy (1) fine lock, f ref = 32khz, ssg disabled (2) 0.1 0.5 % accurate lock, f ref = 32khz, dither clk rcsys/2, ssg disabled (2) 0.06 0.5 fine lock, f ref = 8-150khz, ssg disabled (2) 0.2 1 accurate lock, f ref = 8-150khz, dither clk rcsys/ 2, ssg disabled (2) 0.1 1 i dfll power consumption (1) range 0 96 to 220mhz coarse=0, fine=0, div=0 430 509 545 a range 0 96 to 220mhz coarse=31, fine=255, div=0 1545 1858 1919 range 1 50 to 110mhz coarse=0, fine=0, div=0 218 271 308 range 1 50 to 110mhz coarse=31, fine=255, div=0 704 827 862 range 2 25 to 55mhz coarse=0, fine=0, div=1 140 187 226 range 2 25 to 55mhz coarse=31, fine=255, div=1 365 441 477 range 3 20 to 30mhz coarse=0, fine=0, div=1 122 174 219 range 3 20 to 30mhz coarse=31, fine=255, div=1 288 354 391
125 42023gs?sam?03/2014 atsam4l8/l4/l2 9.7.5 32khz rc oscillator (rc32k) characteristics 9.7.6 system rc oscillator (rcsys) characteristics t startup startup time (1) within 90% of final values 100 s t lock lock time (1) f ref = 32khz, fine lock, ssg disabled (2) 600 f ref = 32khz, accurate lock, dithering clock = rcsys/2, ssg disabled (2) 1100 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. 2. spread spectrum generator (ssg) is disabled by writin g a zero to the en bit in the scif.dfll0ssg register. table 9-28. 32khz rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 1. these values are based on characterization. these values are not covered by test limits in production. calibrated against a 32.768khz reference temperature compensation disabled 20 32.768 44 khz i rc32k current consumption (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization. without temperature compensation 0.5 a temperature compensation enabled 2 a t startup startup time (1) 1 cycle table 9-29. system rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 1. these values are based on characterization. these values are not covered by test limits in production. calibrated at 85 c 110 113.6 116 khz i rcsys current consumption (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization. 12 a t startup startup time (1) 25 38 63 s duty duty cycle (1) 49.6 50 50.3 % table 9-27. digital frequency locked loop characteristics symbol parameter conditions min typ max unit
126 42023gs?sam?03/2014 atsam4l8/l4/l2 9.7.7 1mhz rc oscillator (rc1m) characteristics 9.7.8 4/8/12mhz rc oscillator (rcfast) characteristics table 9-30. rc1m oscillator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 1. these values are based on characterization. these values are not covered by test limits in production. 0.91 1 1.12 mhz i rc1m current consumption (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization. 35 a duty duty cycle (1) 48.6 49.9 54.4 % table 9-31. rcfast oscillator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 1. these values are based on characterization. these values are not covered by test limits in production. calibrated, frange=0 4 4.3 4.6 mhz calibrated, frange=1 7.8 8.2 8.5 calibrated, frange=2 11.3 12 12.3 i rcfast current consumption (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization. calibrated, frange=0 90 110 a calibrated, frange=1 130 150 calibrated, frange=2 180 205 duty duty cycle (1) calibrated, frange=0 48.8 49.6 50.1 % calibrated, frange=1 47.8 49.2 50.1 calibrated, frange=2 46.7 48.8 50.0 t startup startup time (1) calibrated, frange=2 0.1 0.31 0.71 s
127 42023gs?sam?03/2014 atsam4l8/l4/l2 9.7.9 80mhz rc oscillator (rc80m) characteristics 9.8 flash characteristics table 9-33 gives the device maximum operating frequency depending on the number of flash wait states and the flash read mode. the fws bi t in the flashcalw fcr register controls the number of wait states used wh en accessing the flash memory. table 9-32. internal 80mhz rc oscill ator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 1. these values are based on characterization. these values are not covered by test limits in production. after calibration note that rc80m is not available in ps1 60 80 100 mhz i rc80m current consumption (2) 2. these values are based on simulation. these values are no t covered by test limits in production or characterization. 330 a t startup startup time (1) 0.57 1.72 3.2 s duty duty cycle (2) 45 50 55 % table 9-33. maximum operating frequency (1) powerscaling mode flash read mode flash wait states maximum operating frequency unit 0 low power (hsdis) + flash internal reference: bpm.pmcon.fastwkup=1 112 mhz low power(hsdis) 018 136 1 low power (hsdis) + flash internal reference: bpm.pmcon.fastwkup=1 112 low power (hsdis) 08 112 2 high speed (hsen) 024 148 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. table 9-34. flash characteristics (1) symbol parameter conditions min typ max unit t fpp page programming time f clk_ahb = 48mhz 4.38 ms t fpe page erase time 4.38 t ffp fuse programming time 0.63 t fea full chip erase time (ea) 5.66 t fce jtag chip erase time (chip_erase) f clk_ahb = 115khz 304
128 42023gs?sam?03/2014 atsam4l8/l4/l2 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. table 9-35. flash endurance and data retention (1) symbol parameter conditions min typ max unit n farray array endurance (write/page) f clk_ahb > 10mhz 100k cycles n ffuse general purpose fuses endurance (write/bit) f clk_ahb > 10mhz 10k t ret data retention 15 years 1. these values are based on simulation. these values are no t covered by test limits in production or characterization.
129 42023gs?sam?03/2014 atsam4l8/l4/l2 9.9 analog characteristics 9.9.1 voltage regulator characteristics table 9-36. vreg electrical characteristics in linear and switching modes symbol parameter conditions min typ max units i out dc output current (1) power scaling mode 0 & 2 1. these values are based on simulation. these valu es are not covered by test limits in production. low power mode (wait) 2000 3600 5600 a ultra low power mode (retention) 100 180 300 dc output current (1) power scaling mode 1 low power mode (wait) 4000 7000 10000 ultra low power mode (retention) 200 350 600 v vddcore dc output voltage all modes 1.9 v table 9-37. vreg electrical characte ristics in linear mode symbol parameter conditions min typ max units v vddin input voltage range i out =10ma 1.68 3.6 v i out =50ma 1.8 3.6 v vddcore dc output voltage (1) power scaling mode 0 & 2 1. these values are based on characterization. these values are not covered by test limits in production. i out = 0 ma 1.777 1.814 1.854 i out = 50 ma 1.75 1.79 1.83 i out dc output current (1) v vddcore > 1.65v 100 ma output dc load regulation (1) transient load regulation i out = 0 to 80ma, v vddin = 3v -34 -27 -19 mv output dc regulation (1) i out = 80 ma, v vddin = 2v to 3.6v 10 28 48 mv i q quescient current (1) i out = 0 ma run and sleepx modes 88 107 128 a table 9-38. external components requirements in linear mode symbol parameter technology typ units c in1 input regulator capacitor 1 33 nf c in2 input regulator capacitor 2 100 c in3 input regulator capacitor 3 10 f c out1 output regulator capacitor 1 100 nf c out2 output regulator capacitor 2 tantalum or mlcc 0.5 130 42023gs?sam?03/2014 atsam4l8/l4/l2 note: 1. refer to section 6. on page 46 . i out dc output current (1) v vddcore > 1.65v 55 ma output dc load regulation (1) transient load regulation i out = 0 to 50ma, v vddin = 3v -136 -101 -82 mv output dc regulation (1) i out = 50 ma, v vddin = 2v to 3.6v -20 38 99 mv i q quescient current (1) v vddin = 2v, i out = 0 ma 97 186 546 a v vddin > 2.2v, i out = 0 ma 97 111 147 p eff power efficiency (1) i out = 5ma, 50ma reference power not included 82.7 88.3 95 % 1. these values are based on characterization. these values are not covered by test limits in production. table 9-40. decoupling requirement s in switching mode symbol parameter technology typ units c in1 input regulator capacitor 1 33 nf c in2 input regulator capacitor 2 100 c in3 input regulator capacitor 3 10 f c out1 output regulator capacitor 1 x7r mlcc 100 nf c out2 output regulator capacitor 2 x7r mlcc (ex : grm31cr71a475) 4.7 f l ext external inductance (ex: murata lqh3npn220mj0) 22 h r dclext serial resistance of l ext 0.7 isat lext saturation current of l ext 300 ma table 9-39. vreg electrical characte ristics in switching mode symbol parameter conditions min typ max units
131 42023gs?sam?03/2014 atsam4l8/l4/l2 9.9.2 power-on reset 33 characteristics figure 9-4. por33 operating principle 9.9.3 brown out detectors characteristics table 9-41. por33 characteristics (1) 1. these values are based on characterization. these values are not covered by test limits in production. symbol parameter conditions min typ max units v pot+ voltage threshold on v vddin rising 1.25 1.55 v v pot- voltage threshold on v vddin falling 0.95 1.30 reset v vddin v pot+ v pot- time table 9-42. bod18 characteristics (1) symbol parameter conditions min typ max units step size, between adjacent values in bscif.bod18level (1) 10.1 mv v hyst bod hysteresis (1) t = 25 c340 t det detection time (1) time with v vddcore < bod18.level necessary to generate a reset signal 1.2 s i bod current consumption (1) on vddin 7.4 14 a on vddcore 7 t startup startup time (1) 4.5 s
132 42023gs?sam?03/2014 atsam4l8/l4/l2 the values in table 9-43 describe the values of the bod33.level in the flash user page fuses. 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. table 9-43. bod33.level values bod33.level value min typ max units 16 2.08 v 20 2.18 24 2.33 28 2.48 32 2.62 36 2.77 40 2.92 44 3.06 48 3.21 table 9-44. bod33 characteristics (1) symbol parameter conditions min typ max units step size, between adjacent values in bscif.bod33level (1) 34.4 mv v hyst hysteresis (1) 45 170 t det detection time (1) time with vddin < v th necessary to generate a reset signal s i bod33 current consumption (1) normal mode 36 a t startup startup time (1) normal mode 6 s 1. these values are based on simulation. these values are no t covered by test limits in production or characterization.
133 42023gs?sam?03/2014 atsam4l8/l4/l2 9.9.4 analog- to digital converter characteristics figure 9-5. maximum input common mode voltage table 9-45. operating conditions symbol parameter conditions min typ max units temperature range -40 +85 c resolution (1) 1. these values are based on characterization. these values are not covered by test limits in production max 12 12 (2) 2. single ended or using divide by two max resolution: 11 bits bit sampling clock (3) 3. these values are based on simulation. these valu es are not covered by test limits in production differential modes, gain=1x 5 300 khz unipolar modes, gain=1x 5 250 f adc adc clock frequency (3) differential modes 0.03 1.8 mhz unipolar modes 0.03 1.5 t samplehold sampling time (3) differential modes 16.5 277 s unipolar modes 16.5 333 conversion rate (1) 1x gain, differential 300 ksps internal channel conversion rate (3) v vdd /10, bandgap and temperature channels 125 ksps conversion time (latency) differential mode (no windowing) 1x gain, (resolution/2)+gain (4) 4. see figure 9-5 6 cycles 2x and 4x gain 7 8x and 16x gain 8 32x and 64x gain 9 64x gain and unipolar 10 m ax in p u t co m m o n m o de v o lta g e 0 0.5 1 1.5 2 2.5 3 1.6 3.6 vcc icmr vc m _ vr ef= 3v vc m _ vr ef= 1v
134 42023gs?sam?03/2014 atsam4l8/l4/l2 table 9-46. dc characteristics symbol parameter conditions min typ max units vddana supply voltage (1) 1.6 3.6 v reference range (2) differential mode 1.0 vddana -0.6 v unipolar and window modes 1.0 1.0 using divide by two function (differential) 2.0 vddana absolute min, max input voltage (2) -0,1 vddana +0.1 v start up time (2) adc with reference already enabled 12 24 cycles no gain compensation reference buffer 5s gain compensation reference buffer 60 cycles r sample input channel source resistance (2) 0.5 k c sample sampling capacitance (2) 2.9 3.6 4.3 pf reference input source resistance (2) gain compensation 2 k no gain compensation 1 m adc reference settling time (2) after changing reference/mode (3) 5 60 cycles 1. these values are based on characterization. these values are not covered by test limits in production 2. these values are based on simulation. these valu es are not covered by test limits in production 3. requires refresh/flush otherwise conversion time (latency) + 1 table 9-47. differential mode, gain=1 symbol parameter conditions min typ max units accuracy without compensation (1) 7enob accuracy after compensation (1) (inl, gain and offset) 11 enob inl integral non linearity (2) after calibration, gain compensation 1.2 1.7 lsbs dnl differential non linearity (2) after calibration 0.7 1.0 lsbs gain error (2) external reference -5.0 -1.0 5.0 mv vddana/1.6 -40 40 vddana/2.0 -40 40 bandgap after calibration -30 30 gain error drift vs voltage (1) external reference -2 2 mv/v gain error drift vs temperature (1) after calibration + bandgap drift if using onchip bandgap 0.08 mv/k offset error (2) external reference -5.0 5.0 mv vddana/1.6 -10 10 vddana/2.0 -10 10 bandgap after calibration -10 10 offset error drift vs voltage (1) -4 4 mv/v
135 42023gs?sam?03/2014 atsam4l8/l4/l2 offset error drift vs temperature (1) 0.04 mv/k conversion range (2) vin-vip -vref vref v icmr (1) see figure 9-5 psrr (1) fvdd=1hz, ext advrefp=3.0v v vdd =3.6v 100 db fvdd=2mhz, ext advrefp=3.0v v vdd =3.6 50 dc supply current (2) vddana=3.6v, advrefp=3.0v 1.2 ma vddana=1.6v, advrefp=1.0v 0.6 1. these values are based on simulation only. these values are not covered by test limits in production or characterization 2. these values are based on characterization and not tested in production, and valid for an input voltage between 10% to 90% of reference voltage. table 9-48. unipolar mode, gain=1 symbol parameter conditions min typ max units accuracy without compensation (1) 7enob accuracy after compensation (1) 11 enob inl integral non linearity (2) after calibration dynamic tests no gain compensation 3 lsbs after calibration dynamic tests gain compensation 3 dnl differential non linearity (2) after calibration 2.8 lsbs gain error (2) external reference -15 15 mv vddana/1.6 -50 50 vddana/2.0 -30 30 bandgap after calibration -10 10 gain error drift vs voltage (1) external reference -8 8 mv/v gain error drift temperature (1) + bandgap drift if using bandgap 0.08 mv/k offset error (2) external reference -15 15 mv vddana/1.6 -15 15 vddana/2.0 -15 15 bandgap after calibration -10 10 offset error drift (1) -4 4 mv/v offset error drift temperature (1) 00.04mv/k conversion range (1) vin-vip -vref vref v icmr (1) see figure 9-5 table 9-47. differential mode, gain=1
136 42023gs?sam?03/2014 atsam4l8/l4/l2 9.9.4.1 inputs and sample and hold acquisition times the analog voltage source must be able to charge the sample and hold (s/h) capacitor in the adc in order to achieve maximum accuracy. seen externally the adc input consists of a resis- tor ( ) and a capacitor ( ). in addition, the source resistance ( ) must be taken into account when calculating the required sample and hold time. figure 9-6 shows the adc input channel equivalent circuit. figure 9-6. adc input to achieve n bits of accuracy, the capacitor must be charged at least to a voltage of the minimum sampling time for a given can be found using this formula: for a 12 bits accuracy : where psrr (1) fvdd=100khz, vddio=3.6v 62 db fvdd=1mhz, vddio=3.6v 49 dc supply current (1) vddana=3.6v 1 2 ma vddana=1.6v, advrefp=1.0v 11.3 1. these values are based on simulation. these values are no t covered by test limits in production or characterization. 2. these values are based on characterization and not tested in production, and valid for an input voltage between 10% to 90% of reference voltage. table 9-48. unipolar mode, gain=1 r sample c sample r source r source r sample analog input adx c sample v in vddana/2 c sample v csample v in 12 n 1 + () ? ? () t samplehold r source t samplehold r sample r + source () c sample () n 1 + () 2 () ln t samplehold r sample r + source () c sample () 9 02 , t samplehold 1 2 fadc ----------------------- - =
137 42023gs?sam?03/2014 atsam4l8/l4/l2 9.9.5 digital to analog converter characteristics 9.9.6 analog comparator characteristics table 9-49. operating conditions symbol parameter conditions min typ max units analog supply voltage (1) 1. these values are based on simulation. these values are no t covered by test limits in production or characterization on vddana 2.4 3 3.6 v digital supply voltage (1) on vddcore 1.62 1.8 1.98 v resolution (2) 2. these values are based on characterization. these values are not covered by test limits in production 10 bits clock frequency (1) cload = 50pf ; rload = 5k 500 khz load (1) cload 50 pf rload 5 k inl integral non linearity (1) best fit-line method 2 lsbs dnl differential non linearity (1) best fit-line me thod -0.9 +1 lsbs zero error (offset) (1) cdr[9:0] = 0 1 5 mv gain error (1) cdr[9:0] = 1023 5 10 mv total harmonic distortion (1) 80% of vddana @ fin = 70khz -56 7 db delay to vout (1) cdr[9:0] = 512/ cload = 50 pf / rload = 5 k 2s startup time (1) cdr[9:0] = 512 5 9 s output voltage range (advrefp < vddana ? 100mv) is mandatory 0 advrefp v advrefp voltage range (1) (advrefp < vddana ? 100mv) is mandatory 2.3 3.5 v advrefn voltage range (1) advrefp = gnd 0 v standby current (1) on vddana 500 na on vddcore 100 dc current consumption (1) on vddana (no rload) 485 660 a on advrefp (cdr[9:0] = 512) 250 295 table 9-50. analog comparator characteristics symbol parameter conditions min typ max units positive input voltage range 0.1 vddio-0.1 v negative input voltage range 0.1 vddio-0.1 offset (1) v acrefn =0.1v to vddio-0.1v, hysteresis = 0 (2) fast mode -12 13 mv v acrefn =0.1v to vddio-0.1v, hysteresis = 0 (2) low power mode -11 12 mv
138 42023gs?sam?03/2014 atsam4l8/l4/l2 hysteresis (1) v acrefn =0.1v to vddio-0.1v, hysteresis = 1 (2) fast mode 10 55 mv v acrefn =0.1v to vddio-0.1v, hysteresis = 1 (2) low power mode 10 68 mv v acrefn =0.1v to vddio-0.1v, hysteresis = 2 (2) fast mode 26 83 mv v acrefn =0.1v to vddio-0.1v, hysteresis = 2 (2) low power mode 19 91 mv v acrefn =0.1v to vddio-0.1v, hysteresis = 3 (2) fast mode 43 106 mv v acrefn =0.1v to vddio-0.1v, hysteresis = 3 (2) low power mode 32 136 mv propagation delay (1) changes for v acm =vddio/2 100mv overdrive fast mode 67 ns changes for v acm =vddio/2 100mv overdrive low power mode 315 ns t startup startup time (1) enable to ready delay fast mode 1.19 s enable to ready delay low power mode 3.61 s i ac channel current consumption (3) low power mode, no hysteresis 4.9 8.7 a fast mode, no hysteresis 63 127 1. these values are based on characterization. these values are not covered by test limits in production 2. hystac.confn.hys field, refer to the analog comparator interface chapter 3. these values are based on simulation. these values are no t covered by test limits in production or characterization table 9-50. analog comparator characteristics symbol parameter conditions min typ max units
139 42023gs?sam?03/2014 atsam4l8/l4/l2 9.9.7 liquid crystal display controler characteristics 9.9.7.1 liquid crystal controler supply current the values in table 9-52 are measured values of power consumption under the following condi- tions, except where noted: ? t=25c, wait mode, low power waveform, frame rate = 32hz from osc32k ? configuration: 4comx40seg, 1/4 duty, 1/3 bias, no animation ? all segments on, load = 160 x 22pf between each com and each seg. ? lcdca current based on i lcd = i wait (lcd on) - i wait (lcd off) table 9-51. liquid crystal display co ntroler characteristics symbol parameter conditions min typ max units seg segment terminal pins 40 com common terminal pins 4 f frame lcd frame frequency f clklcd 31.25 512 hz c flying flying capacitor 100 nf v lcd lcd regulated voltages (1) cfg.fcst=0 1. these values are based on simulation. these values are no t covered by test limits in production or characterization c flying = 100nf 100nf on v lcd , bias2 and bias1 pins 3 v bias2 2*v lcd /3 bias1 v lcd /3 table 9-52. liquid crystal display controler supply current symbol conditions min typ max units i lcd internal voltage generation cfg.fcst=0 v vddin = 3.6v 8.85 a v vddin = 1.8v 6.16 external bias v lcd =3.0v v vddin = 3.3v 0.98 v vddin = 1.8v 1.17
140 42023gs?sam?03/2014 atsam4l8/l4/l2 9.10 timing characteristics 9.10.1 reset_n timing 9.10.2 usart in spi mode timing 9.10.2.1 master mode figure 9-7. usart in spi master mode with (cpo l= cpha= 0) or (cpol= cpha= 1) figure 9-8. usart in spi master mode with (cpol= 0 and cpha= 1) or (cpol= 1 and cpha= 0) table 9-53. reset_n waveform parameters (1) 1. these values are based on simulation. these valu es are not covered by test limits in production. symbol parameter conditions min max units t reset reset_n minimum pulse length 10 ns uspi0 uspi1 miso spck mosi uspi2 uspi3 uspi4 miso spck mosi uspi5
141 42023gs?sam?03/2014 atsam4l8/l4/l2 notes: 1. these values are based on simulation. these va lues are not covered by test limits in production. 2. where: table 9-54. usart0 in spi mode timing, master mode (1) symbol parameter conditions min max units uspi0 miso setup time before spck rises v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 123.2 + t sample (2) ns uspi1 miso hold time after spck rises 24.74 -t sample (2) uspi2 spck rising to mosi delay 513.56 uspi3 miso setup time befo re spck falls 125.99 + t sample (2) uspi4 miso hold time after spck falls 24.74 -t sample (2) uspi5 spck falling to mosi delay 516.55 table 9-55. usart1 in spi mode timing, master mode (1) symbol parameter conditions min max units uspi0 miso setup time before spck rises v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 69.28 + t sample (2) ns uspi1 miso hold time after spck rises 25.75 -t sample (2) uspi2 spck rising to mosi delay 99.66 uspi3 miso setup time be fore spck falls 73.12 + t sample (2) uspi4 miso hold time after spck falls 28.10 -t sample (2) uspi5 spck falling to mosi delay 102.01 table 9-56. usart2 in spi mode timing, master mode (1) symbol parameter conditions min max units uspi0 miso setup time before spck rises v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 69.09 + t sample (2) ns uspi1 miso hold time after spck rises 26.52 -t sample (2) uspi2 spck rising to mosi delay 542.96 uspi3 miso setup time be fore spck falls 72.55 + t sample (2) uspi4 miso hold time after spck falls 28.37 -t sample (2) uspi5 spck falling to mosi delay 544.80 table 9-57. usart3 in spi mode timing, master mode (1) symbol parameter conditions min max units uspi0 miso setup time before spck rises v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 147.24 + t sample (2) ns uspi1 miso hold time after spck rises 25.80 -t sample (2) uspi2 spck rising to mosi delay 88.23 uspi3 miso setup time be fore spck falls 154.9 + t sample (2) uspi4 miso hold time after spck falls 26.89 -t sample (2) uspi5 spck falling to mosi delay 89.32 t sample t spck t spck 2 t clkusart ------------------------------------ 1 2 -- - ?? ?? t clkusart ? =
142 42023gs?sam?03/2014 atsam4l8/l4/l2 maximum spi frequency, master output the maximum spi master output frequenc y is given by the following formula: where is the mosi delay, uspi2 or uspi5 depending on cpol and ncpha. is the maximum frequency of the spi pins. refer to the i/o pin characteristics section for the maxi- mum frequency of the pins. is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. maximum spi frequency, master input the maximum spi master input frequenc y is given by the following formula: where is the miso setup and hold time, uspi0 + uspi1 or uspi3 + uspi4 depending on cpol and ncpha. is the spi slave response time. refer to the spi slave datasheet for . is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. 9.10.2.2 slave mode figure 9-9. usart in spi slave mode with (cpol= 0 and cpha= 1) or (cpol= 1 and cpha= 0) f spckmax min f pinmax 1 spin ------------ f clkspi 2 9 ---------------------------- - , (, ) = spin f pinmax f clkspi f spckmax min 1 spin t valid + ----------------------------------- - f clkspi 2 9 ---------------------------- - (,) = spin t valid t valid f clkspi uspi7 uspi8 miso spck mosi uspi6
143 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 9-10. usart in spi slave mode with (cpol= cpha= 0) or (cpol= cpha= 1) figure 9-11. usart in spi slave mode, npcs timing uspi10 uspi11 miso spck mosi uspi9 uspi14 uspi12 uspi15 uspi13 nss spck, cpol=0 spck, cpol=1 table 9-58. usart0 in spi mode timing, slave mode (1) symbol parameter conditions min max units uspi6 spck falling to miso delay v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 740.67 ns uspi7 mosi setup time before spck rises 56.73 + t sample (2) + t clk_usart uspi8 mosi hold time after spck rises 45.18 -( t sample (2) + t clk_usart ) uspi9 spck rising to miso delay 670.18 uspi10 mosi setup time before spck falls 56.73 +( t sample (2) + t clk_usart ) uspi11 mosi hold time after spck falls 45.18 -( t sample (2) + t clk_usart ) uspi12 nss setup time before spck rises 688.71 uspi13 nss hold time after spck falls -2.25 uspi14 nss setup time before spck falls 688.71 uspi15 nss hold time after spck rises -2.25
144 42023gs?sam?03/2014 atsam4l8/l4/l2 table 9-59. usart1 in spi mode timing, slave mode (1) symbol parameter conditions min max units uspi6 spck falling to miso delay v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 373.58 ns uspi7 mosi setup time before spck rises 4.16 + t sample (2) + t clk_usart uspi8 mosi hold time after spck rises 46.69 -( t sample (2) + t clk_usart ) uspi9 spck rising to miso delay 373.54 uspi10 mosi setup time before spck falls 4.16 +( t sample (2) + t clk_usart ) uspi11 mosi hold time after spck falls 46.69 -( t sample (2) + t clk_usart ) uspi12 nss setup time before spck rises 200.43 uspi13 nss hold time after spck falls -16.5 uspi14 nss setup time before spck falls 200.43 uspi15 nss hold time after spck rises -16.5 table 9-60. usart2 in spi mode timing, slave mode (1) symbol parameter conditions min max units uspi6 spck falling to miso delay v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 770.02 ns uspi7 mosi setup time before spck rises 136.56 + t sample (2) + t clk_usart uspi8 mosi hold time after spck rises 47.9 -( t sample (2) + t clk_usart ) uspi9 spck rising to miso delay 570.19 uspi10 mosi setup time before spck falls 136.73 +( t sample (2) + t clk_usart ) uspi11 mosi hold time after spck falls 47.9 -( t sample (2) + t clk_usart ) uspi12 nss setup time before spck rises 519.87 uspi13 nss hold time after spck falls -1.83 uspi14 nss setup time before spck falls 519.87 uspi15 nss hold time after spck rises -1.83
145 42023gs?sam?03/2014 atsam4l8/l4/l2 notes: 1. these values are based on simulation. these va lues are not covered by test limits in production. 2. where: maximum spi frequency, slave input mode the maximum spi slave input frequency is given by the following formula: where is the mosi setup and hold time, uspi7 + uspi8 or uspi10 + uspi11 depending on cpol and ncpha. is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. maximum spi frequency, slave output mode the maximum spi slave output frequency is given by the following formula: where is the miso delay, uspi6 or uspi9 depending on cpol and ncpha. is the spi master setup time. refer to the spi master datasheet for . is the maxi- mum frequency of the clk_spi. refer to the spi chapter for a description of this clock. is the maximum frequency of the spi pins. refer to the i/o pin characteristics section for the maximum frequency of the pins. table 9-61. usart3 in spi mode timing, slave mode (1) symbol parameter conditions min max units uspi6 spck falling to miso delay v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 593.9 ns uspi7 mosi setup time before spck rises 45.93 + t sample (2) + t clk_usart uspi8 mosi hold time after spck rises 47.03 -( t sample (2) + t clk_usart ) uspi9 spck rising to miso delay 593.38 uspi10 mosi setup time before spck falls 45.93 +( t sample (2) + t clk_usart ) uspi11 mosi hold time after spck falls 47.03 -( t sample (2) + t clk_usart ) uspi12 nss setup time before spck rises 237.5 uspi13 nss hold time after spck falls -1.81 uspi14 nss setup time before spck falls 237.5 uspi15 nss hold time after spck rises -1.81 t sample t spck t spck 2 t clkusart ------------------------------------ 1 2 -- - + ?? ?? t clkusart ? = f spckmax min f clkspi 2 9 ---------------------------- - 1 spin ------------ (,) = spin f clkspi f spckmax min f clkspi 2 9 ---------------------------- - f pinmax , 1 spin t setup + ------------------------------------ (,) = spin t setup t setup f clkspi f pinmax
146 42023gs?sam?03/2014 atsam4l8/l4/l2 9.10.3 spi timing 9.10.3.1 master mode figure 9-12. spi master mode with (cpol= nc pha= 0) or (cpol= ncpha= 1) figure 9-13. spi master mode with (cpol= 0 and ncpha= 1) or (cpol= 1 and ncpha= 0) note: 1. these values are based on simulation. these val ues are not covered by test limits in production. maximum spi frequency, master output spi0 spi1 miso spck mosi spi2 spi3 spi4 miso spck mosi spi5 table 9-62. spi timing, master mode (1) symbol parameter conditions min max units spi0 miso setup time before spck rises v vddio from 2.85v to 3.6v, maximum external capacitor = 40pf 9 ns spi1 miso hold time after spck rises 0 spi2 spck rising to mosi delay 9 21 spi3 miso setup time before spck falls 7.3 spi4 miso hold time after spck falls 0 spi5 spck falling to mosi delay 9 22
147 42023gs?sam?03/2014 atsam4l8/l4/l2 the maximum spi master output frequenc y is given by the following formula: where is the mosi delay, spi2 or spi5 depending on cpol and ncpha. is the maximum frequency of the spi pins. refer to the i/o pin characteristics section for the maximum frequency of the pins. maximum spi frequency, master input the maximum spi master input frequenc y is given by the following formula: where is the miso setup and hold time, spi0 + spi1 or spi3 + spi4 depending on cpol and ncpha. is the spi slave response time. refer to the spi slave datasheet for . 9.10.3.2 slave mode figure 9-14. spi slave mode with (cpol= 0 and ncpha= 1) or (cpol= 1 and ncpha= 0) figure 9-15. spi slave mode with (cpol= ncp ha= 0) or (cpol= ncpha= 1) f spckmax min f pinmax 1 spin ------------ (,) = spin f pinmax f spckmax 1 spin t valid + ----------------------------------- - = spin t valid t valid spi7 spi8 miso spck mosi spi6 spi10 spi11 miso spck mosi spi9
148 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 9-16. spi slave mode, npcs timing note: 1. these values are based on simulation. these val ues are not covered by test limits in production. maximum spi frequency, slave input mode the maximum spi slave input frequency is given by the following formula: where is the mosi setup and hold time, spi7 + spi8 or spi10 + spi11 depending on cpol and ncpha. is the maximum frequency of the clk_spi. refer to the spi chap- ter for a description of this clock. maximum spi frequency, slave output mode the maximum spi slave output frequency is given by the following formula: spi14 spi12 spi15 spi13 npcs spck, cpol=0 spck, cpol=1 table 9-63. spi timing, slave mode (1) symbol parameter conditions min max units spi6 spck falling to miso delay v vddio from 2.85v to 3.6v, maximum external capacitor = 40pf 19 47 ns spi7 mosi setup time before spck rises 0 spi8 mosi hold time after spck rises 5.4 spi9 spck rising to miso delay 19 46 spi10 mosi setup time before spck falls 0 spi11 mosi hold time after spck falls 5.3 spi12 npcs setup time before spck rises 4 spi13 npcs hold time after spck falls 2.5 spi14 npcs setup time before spck falls 6 spi15 npcs hold time after spck rises 1.1 f spckmax min f clkspi 1 spin ------------ (,) = spin f clkspi f spckmax min f pinmax 1 spin t setup + ------------------------------------ (, ) =
149 42023gs?sam?03/2014 atsam4l8/l4/l2 where is the miso delay, spi6 or spi9 depending on cpol and ncpha. is the spi master setup time. refer to the spi master datasheet for . is the maximum frequency of the spi pins. refer to the i/o pin characteristics section for the maximum frequency of the pins. 9.10.4 twim/twis timing figure 9-64 shows the twi-bus timing requirements and the compliance of the device with them. some of these requirements (t r and t f ) are met by the device without requiring user inter- vention. compliance with the other requirements (t hd-sta , t su-sta , t su-sto , t hd-dat , t su-dat-twi , t low- twi , t high , and f twck ) requires user intervention through appropriate programming of the relevant twim and twis user interface registers. refer to the twim and twis sections for more information. notes: 1. standard mode: ; fast mode: . spin t setup t setup f pinmax table 9-64. twi-bus timing requirements symbol parameter mode minimum maximum unit requirement device requirement device t r twck and twd rise time standard (1) - 1000 ns fast (1) 20 + 0.1c b 300 t f twck and twd fall time standard - 300 ns fast 20 + 0.1c b 300 t hd-sta (repeated) start hold time standard 4 t clkpb - s fast 0.6 t su-sta (repeated) start set-up time standard 4.7 t clkpb - s fast 0.6 t su-sto stop set-up time standard 4.0 4t clkpb - s fast 0.6 t hd-dat data hold time standard 0.3 (2) 2t clkpb 3.45 () 15t prescaled + t clkpb s fast 0.9 () t su-dat-twi data set-up time standard 250 2t clkpb -ns fast 100 t su-dat --t clkpb -- t low-twi twck low period standard 4.7 4t clkpb - s fast 1.3 t low --t clkpb -- t high twck high period standard 4.0 8t clkpb - s fast 0.6 f twck twck frequency standard - 100 khz fast 400 1 12t clkpb ----------------------- - f twck 100 khz f twck 100 khz >
150 42023gs?sam?03/2014 atsam4l8/l4/l2 2. a device must internally provide a hold time of at least 300 ns for twd with reference to the falling edge of twck. notations: c b = total capacitance of one bus line in pf t clkpb = period of twi peripheral bus clock t prescaled = period of twi internal prescaled clock (see chapters on twim and twis) the maximum t hd;dat has only to be met if the device does not stretch the low period (t low-twi ) of twck. 9.10.5 jtag timing figure 9-17. jtag interface signals jtag2 jtag3 jtag1 jtag4 jtag0 tms/tdi tck tdo jtag5 jtag6 jtag7 jtag8 jtag9 jtag10 boundary scan inputs boundary scan outputs
151 42023gs?sam?03/2014 atsam4l8/l4/l2 note: 1. these values are based on simulation. these val ues are not covered by test limits in production. 9.10.6 swd timing figure 9-18. swd interface signals table 9-65. jtag timings (1) symbol parameter conditions min max units jtag0 tck low half-period v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 21.8 ns jtag1 tck high half-period 8.6 jtag2 tck period 30.3 jtag3 tdi, tms setup before tck high 2.0 jtag4 tdi, tms hold after tck high 2.3 jtag5 tdo hold time 9.5 jtag6 tck low to tdo valid 21.8 jtag7 boundary scan inputs setup time 0.6 jtag8 boundary scan inputs hold time 6.9 jtag9 boundary scan outputs hold time 9.3 jtag10 tck to boundary scan outputs valid 32.2 stop park tri state acknowledge tri state tri state parity start data data stop park tri state acknowledge tri state start read cycle write cycle tos thigh tlow tis data data parity tri state tih from debugger to swdio pin from debugger to swdclk pin swdio pin to debugger from debugger to swdio pin from debugger to swdclk pin swdio pin to debugger
152 42023gs?sam?03/2014 atsam4l8/l4/l2 note: 1. these values are based on simulation. these values are not covered by test limits in production or characterization. table 9-66. swd timings (1) symbol parameter conditions min max units thigh swdclk high period v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 10 500 000 ns tlow swdclk low period 10 500 000 tos swdio output skew to falling edge swdclk -5 5 tis input setup time required between swdio 4 - tih input hold time required between swdio and rising edge swdclk 1-
153 42023gs?sam?03/2014 atsam4l8/l4/l2 10. mechanical characteristics 10.1 thermal considerations 10.1.1 thermal data table 10-1 summarizes the thermal resistance data depending on the package. 10.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 10-1 . ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 10-1 . ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in section 9.5 on page 103 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 10-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air tqfp100 48.1 ? c/w jc junction-to-case thermal resistance tqfp100 13.3 ja junction-to-ambient thermal resistance still air vfbga100 31.1 ? c/w jc junction-to-case thermal resistance vfbga100 6.9 ja junction-to-ambient thermal resistance still air wlcsp64 26.9 ? c/w jc junction-to-case thermal resistance wlcsp64 0.2 ja junction-to-ambient thermal resistance still air tqfp64 49.6 ? c/w jc junction-to-case thermal resistance tqfp64 13.5 ja junction-to-ambient thermal resistance still air qfn64 22.0 ? c/w jc junction-to-case thermal resistance qfn64 1.3 ja junction-to-ambient thermal resistance still air tqfp48 51.1 ? c/w jc junction-to-case thermal resistance tqfp48 13.7 ja junction-to-ambient thermal resistance still air qfn48 24.9 ? c/w jc junction-to-case thermal resistance qfn48 1.3 t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
154 42023gs?sam?03/2014 atsam4l8/l4/l2 10.2 package drawings figure 10-1. vfbga-100 package drawing table 10-2. device and package maximum weight 120 mg table 10-3. package characteristics moisture sensitivity level msl3 table 10-4. package reference jedec drawing reference n/a jesd97 classification e1
155 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-2. tqfp-100 package drawing table 10-5. device and package maximum weight 500 mg table 10-6. package characteristics moisture sensitivity level msl3 table 10-7. package reference jedec drawing reference ms-026 jesd97 classification e3
156 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-3. wlcsp64 sam4lc4/2 package drawing table 10-8. device and package maximum weight 14.8 mg table 10-9. package characteristics moisture sensitivity level msl3 table 10-10. package reference jedec drawing reference ms-026 jesd97 classification e1
157 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-4. wlcsp64 sam4ls4/2 package drawing table 10-11. device and package maximum weight 14.8 mg table 10-12. package characteristics moisture sensitivity level msl3 table 10-13. package reference jedec drawing reference ms-026 jesd97 classification e1
158 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-5. wlcsp64 sam4lc8 package drawing table 10-14. device and package maximum weight 14.8 mg table 10-15. package characteristics moisture sensitivity level msl3 table 10-16. package reference jedec drawing reference ms-026 jesd97 classification e1
159 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-6. wlcsp64 sam4ls8 package drawing table 10-17. device and package maximum weight 14.8 mg table 10-18. package characteristics moisture sensitivity level msl3 table 10-19. package reference jedec drawing reference ms-026 jesd97 classification e1
160 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-7. tqfp-64 package drawing table 10-20. device and package maximum weight 300 mg table 10-21. package characteristics moisture sensitivity level msl3 table 10-22. package reference jedec drawing reference ms-026 jesd97 classification e3
161 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-8. qfn-64 package drawing note: the exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliabil ity. table 10-23. device and package maximum weight 200 mg table 10-24. package characteristics moisture sensitivity level msl3 table 10-25. package reference jedec drawing reference mo-220 jesd97 classification e3
162 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-9. tqfp-48 (atsam4lc4/2 and atsam4ls4/2 only) package drawing table 10-26. device and package maximum weight 140 mg table 10-27. package characteristics moisture sensitivity level msl3 table 10-28. package reference jedec drawing reference ms-026 jesd97 classification e3
163 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-10. qfn-48 package drawing for atsam4lc4/2 and atsam4ls4/2 note: the exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliabil ity. table 10-29. device and package maximum weight 140 mg table 10-30. package characteristics moisture sensitivity level msl3 table 10-31. package reference jedec drawing reference mo-220 jesd97 classification e3
164 42023gs?sam?03/2014 atsam4l8/l4/l2 figure 10-11. qfn-48 package drawing for atsam4lc8 and atsam4ls8 note: the exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliabil ity. table 10-32. device and package maximum weight 140 mg table 10-33. package characteristics moisture sensitivity level msl3 table 10-34. package reference jedec drawing reference mo-220 jesd97 classification e3
165 42023gs?sam?03/2014 atsam4l8/l4/l2 10.3 soldering profile table 10-35 gives the recommended soldering profile from j-std-20. a maximum of three reflow passes is allowed per component. table 10-35. soldering profile profile feature green package average ramp-up rate (217c to peak) 3c/s max preheat temperature 175c 25c 150-200c time maintained above 217c 60-150 s time within 5 ? c of actual peak temperature 30 s peak temperature range 260c ramp-down rate 6c/s max time 25 ? c to peak temperature 8 minutes max
166 42023gs?sam?03/2014 atsam4l8/l4/l2 11. ordering information table 11-1. atsam4lc8 sub serie ordering information ordering code flash (kbytes) ram (kbytes) package conditioning package type temperature operating range atsam4lc8ca-au 512 64 tqfp100 tr ay green industrial -40c to 85c atsam4lc8ca-aur reel atsam4lc8ca-cfu vfbga100 tr ay atsam4lc8ca-cfur reel atsam4lc8ba-au tqfp64 tr ay atsam4lc8ba-aur reel atsam4lc8ba-mu qfn64 tr ay atsam4lc8ba-mur reel atsam4lc8ba-uur wlcsp64 reel atsam4lc8aa-mu qfn48 tr ay atsam4lc8aa-mur reel table 11-2. atsam4lc4 sub serie ordering information ordering code flash (kbytes) ram (kbytes) package conditioning package type temperature operating range atsam4lc4ca-au-es 256 32 tqfp100 es green n/a atsam4lc4ca-au tray industrial -40c to 85c atsam4lc4ca-aur reel atsam4lc4ca-cfu vfbga100 tr ay industrial -40c to 85c atsam4lc4ca-cfur reel atsam4lc4ba-au-es tqfp64 es n/a atsam4lc4ba-au tray industrial -40c to 85c atsam4lc4ba-aur reel atsam4lc4ba-mu-es qfn64 es n/a atsam4lc4ba-mu tray industrial -40c to 85c atsam4lc4ba-mur reel atsam4lc4ba-uur wlcsp64 reel industrial -40c to 85c atsam4lc4aa-au-es tqfp48 es n/a atsam4lc4aa-au tray industrial -40c to 85c atsam4lc4aa-aur reel atsam4lc4aa-mu-es qfn48 es n/a atsam4lc4aa-mu tray industrial -40c to 85c atsam4lc4aa-mur reel
167 42023gs?sam?03/2014 atsam4l8/l4/l2 table 11-3. atsam4lc2 sub serie ordering information ordering code flash (kbytes) ram (kbytes) package conditioning package type temperature operating range atsam4lc2ca-au 128 32 tqfp100 tr ay green industrial -40c to 85c atsam4lc2ca-aur reel atsam4lc2ca-cfu vfbga100 tr ay atsam4lc2ca-cfur reel atsam4lc2ba-au tqfp64 tr ay atsam4lc2ba-aur reel atsam4lc2ba-mu qfn64 tr ay atsam4lc2ba-mur reel atsam4lc2ba-uur wlcsp64 reel atsam4lc2aa-au tqfp48 tr ay atsam4lc2aa-aur reel atsam4lc2aa-mu qfn48 tr ay atsam4lc2aa-mur reel table 11-4. atsam4ls8 sub serie or dering information ordering code flash (kbytes) ram (kbytes) package conditioning package type temperature operating range atsam4ls8ca-au 512 64 tqfp100 tr ay green industrial -40c to 85c atsam4ls8ca-aur reel atsam4ls8ca-cfu vfbga100 tr ay atsam4ls8ca-cfur reel atsam4ls8ba-au tqfp64 tr ay atsam4ls8ba-aur reel atsam4ls8ba-mu qfn64 tr ay atsam4ls8ba-mur reel atsam4ls8ba-uur wlcsp64 reel atsam4ls8aa-mu qfn48 tr ay atsam4ls8aa-mur reel
168 42023gs?sam?03/2014 atsam4l8/l4/l2 table 11-5. atsam4ls4 sub serie or dering information ordering code flash (kbytes) ram (kbytes) package conditioning package type temperature operating range atsam4ls4ca-au-es 256 32 tqfp100 es green n/a atsam4ls4ca-au tray industrial -40c to 85c atsam4ls4ca-aur reel atsam4ls4ca-cfu vfbga100 tr ay industrial -40c to 85c atsam4ls4ca-cfur reel atsam4ls4ba-au-es tqfp64 es n/a atsam4ls4ba-au tray industrial -40c to 85c atsam4ls4ba-aur reel atsam4ls4ba-mu-es qfn64 es n/a atsam4ls4ba-mu tray industrial -40c to 85c atsam4ls4ba-mur reel atsam4ls4ba-uur wlcsp64 reel industrial -40c to 85c atsam4ls4aa-au-es tqfp48 es n/a atsam4ls4aa-au tray industrial -40c to 85c atsam4ls4aa-aur reel atsam4ls4aa-mu-es qfn48 es n/a atsam4ls4aa-mu tray industrial -40c to 85c atsam4ls4aa-mur reel table 11-6. atsam4ls2 sub serie or dering information ordering code flash (kbytes) ram (kbytes) package conditioning package type temperature operating range atsam4ls2ca-au 128 32 tqfp100 tr ay green industrial -40c to 85c atsam4ls2ca-aur reel atsam4ls2ca-cfu vfbga100 tr ay atsam4ls2ca-cfur reel atsam4ls2ba-au tqfp64 tr ay atsam4ls2ba-aur reel atsam4ls2ba-mu qfn64 tr ay atsam4ls2ba-mur reel atsam4ls2ba-uur wlcsp64 reel atsam4ls2aa-au tqfp48 tr ay atsam4ls2aa-aur reel atsam4ls2aa-mu qfn48 tr ay atsam4ls2aa-mur reel
169 42023gs?sam?03/2014 atsam4l8/l4/l2 12. errata 12.1 atsam4l4 /2 rev. b & atsam4l8 rev. a 12.1.1 general ps2 mode is not supported by engineering samples ps2 mode support is supported only by part s with calibration version higher than 0. fix/workaround the calibration version can be checked by re ading a 32-bit word at address 0x0080020c. the calibration version bitfield is 4-bit wide and located from bit 4 to bit 7 in this word. any value higher than 0 ensures that the part supports the ps2 mode 12.1.2 scif pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 12.1.3 wdt wdt control register does not have synchronization feedback when writing to the timeout pr escale select (psel), time ban prescale select (tban), enable (en), or wdt mode (mode) fieldss of the wdt control register (ctrl), a synchro- nizer is started to propagate the values to the wdt clcok domain. this synchronization takes a finite amount of time, but only the status of the synchronization of the en bit is reflected back to the user. writing to the synch ronized fields during synchronization can lead to undefined behavior. fix/workaround -when writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the wdt peripheral bus clock and the selected wdt clock source. -when doing writes that changes the en bit, the en bit can be read back until it reflects the written value. 12.1.4 spi spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. spi disable does not work in slave mode spi disable does not work in slave mode.
170 42023gs?sam?03/2014 atsam4l8/l4/l2 fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst). disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 12.1.5 tc channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 12.1.6 usbc in usb host mode, entering suspend mode for low speed device can fail when the usb freeze (usbcon.frzclk=1) is done just after uhcon.sofe=0. fix/workaround when entering suspend mode (uhcon.sofe is cleared), check that usbfsm.drdstate is not equal to three before freezing the clock (usbcon.frzclk=1). in usb host mode, the asynchronous attach detection (udint.hwupi) can fail when the usb clock freeze (usbcon.frzclk=1) is done just after setting the usb- sta.vbusrq bit. fix/workaround after setting usbsta.vbusrq bit, wait until the usbfsm register value is ?a_wait_bcon? before setting the usbcon.frzclk bit.
171 42023gs?sam?03/2014 atsam4l8/l4/l2 12.1.7 flashcalw corrupted data in flash may happen after flash page write operations. after a flash page write operation, reading (data read or code fetch) in flash may fail. this may lead to an expecption or to others errors derived from this corrupted read access. fix/workaround before any flash page write operation, each 64-bit doublewords write in the page buffer must preceded by a 64-bit doublewords write in the page buffer with 0xffffffff_ffffffff content at any address in the page. note that special care is required when loading page buffer, refer to section 2.5.9 ?page buffer operations? on page 11 .
172 42023gs?sam?03/2014 atsam4l8/l4/l2 13. datasheet revision history note that the referring page numbers in this section are referred to this document. the referring revision in this section are referring to the document revision. 13.1 rev. a ? 09/12 13.2 rev. b ? 10/12 13.3 rev. c ? 02/13 13.4 rev. d ? 03/13 1. initial revision. 1. fixed ordering code 2. changed bod18ctrl and bod33ctrl action field from ?reserved? to ?no action? 1. fixed ball pitch for vfbga100 package 2. added vfbga100 and wlcsp64 pinouts 3. added power scaling mode 2 for high frequency support 4. minor update on several modules chapters 5. major update on electrical characteristics 6. updated errata 7. fixed gpio multiplexing pin numbers 1. removed wlcsp package information 2. added errata text for detecting whether a part supports ps2 mode or not 3. removed temperature sensor feature (not supported by production flow) 4. fixed mux selection on positive adc input channel table 5. added information about twi instances capabilities 6. added some details on errata corrupted data in flash may happen after flash page write operations.171
173 42023gs?sam?03/2014 atsam4l8/l4/l2 13.5 rev. e ? 07/13 13.6 rev. f? 12/13 13.7 rev. g? 03/14 1. added atsam4l8 derivatives and wlcsp packages for atsam4l4/2 2. added operating conditions details in electrical characteristics chapter 3. fixed ?supply rise rates and order? 4. added number of usart available in sub-series 5. fixed io line considerations for usb pins 6. removed useless information about cpu local bus which is not implemented 7. removed useless information about modem support which is not implemented 8. added information about unsupported features in power scaling mode 1 9. fixed spi timings 1. fixed table 3-6 - tdi is connected to pin g3 in wlcsp package 2. changed table 42-48 -adcife electricals in unipolar mode : psrr & dc supply current typical values 3. fixed spi timing characteristics 4. fixed bod33 typical step size value 1. added wlcsp64 packages for sam4lc8 and sam4ls8 sub-series 2. removed unsuppported swap feature in lcd module 3. added mnimal value for adc reference range
174 42023gs?sam?03/2014 atsam4l8/l4/l2 table of contents summary............... ................ .............. ............... .............. .............. ............ 1 features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 3 2 overview ............ ................ ................ ............... .............. .............. ............ 5 2.1 block diagram ...................................................................................................5 2.2 configuration summary .....................................................................................6 3 package and pinout ................. ................ ................. ................ ............... 9 3.1 package .............................................................................................................9 3.2 peripheral multiplexing on i/o lines .................................................................19 3.3 signals description ..........................................................................................31 3.4 i/o line considerations ...................................................................................34 4 cortex-m4 processor and core peripherals ... .............. .............. .......... 36 4.1 cortex-m4 ........................................................................................................36 4.2 system level interface .....................................................................................37 4.3 integrated configurable debug .........................................................................37 4.4 cortex-m4 processor features and benefits summary .....................................38 4.5 cortex-m4 core peripherals .............................................................................38 4.6 cortex-m4 implementations options ................................................................39 4.7 cortex-m4 interrupts map ................................................................................39 4.8 peripheral debug .............................................................................................42 5 memories ............... .............. .............. ............... .............. .............. .......... 43 5.1 product mapping .............................................................................................43 5.2 embedded memories ......................................................................................44 5.3 physical memory map .....................................................................................44 6 power and startup considerat ions ........ ................. ................ ............. 46 6.1 power domain overview .................................................................................46 6.2 power supplies ................................................................................................48 6.3 startup considerations ....................................................................................53 6.4 power-on-reset, brownout and supply monitor .............................................53 7 low power techniques ........... ................ ................. ................ ............. 55 7.1 power save modes .........................................................................................55 7.2 power scaling ..................................................................................................60
175 42023gs?sam?03/2014 atsam4l8/l4/l2 8 debug and test ................. ................ ............... .............. .............. .......... 62 8.1 features ..........................................................................................................62 8.2 overview ..........................................................................................................62 8.3 block diagram ..................................................................................................63 8.4 i/o lines description .......................................................................................63 8.5 product dependencies .....................................................................................64 8.6 core debug ......................................................................................................64 8.7 enhanced debug port (edp) ..........................................................................67 8.8 ahb-ap access port .......................................................................................77 8.9 system manager access port (smap) ............................................................78 8.10 available features in protected state .............................................................93 8.11 functional description .....................................................................................94 9 electrical characteristics ... .............. ............... .............. .............. .......... 99 9.1 absolute maximum ratings* ...........................................................................99 9.2 operating conditions .......................................................................................99 9.3 supply characteristics .....................................................................................99 9.4 maximum clock frequencies ........................................................................101 9.5 power consumption ......................................................................................103 9.6 i/o pin characteristics ...................................................................................114 9.7 oscillator characteristics ...............................................................................121 9.8 flash characteristics .....................................................................................127 9.9 analog characteristics ...................................................................................129 9.10 timing characteristics ...................................................................................140 10 mechanical characteristics ..... ................ ................. ................ ........... 153 10.1 thermal considerations ................................................................................153 10.2 package drawings .........................................................................................154 10.3 soldering profile ............................................................................................165 11 ordering information .......... .............. ............... .............. .............. ........ 166 12 errata ........... ................ ................ ................. ................ .............. ........... 169 12.1 atsam4l4 /2 rev. b & atsam4l8 rev. a ..................................................169 13 datasheet revision history .. ................ ................. ................ ............. 172 13.1 rev. a ? 09/12 ...............................................................................................172 13.2 rev. b ? 10/12 ...............................................................................................172 13.3 rev. c ? 02/13 ...............................................................................................172
42023gs?sam?03/2014 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 16f, shin osaki kangyo bldg. 1-6-4 osaka shinagawa-ku tokyo 104-0032 japan tel : (+81) 3-6417-0300 fax : (+81) 3-6417-0370 ? 2013 atmel corporation. all rights reserved. 124152 atmel ? , atmel logo and combinations thereof, picopower ? , adjacent key suppression ? ,aks ? , qtouch ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. arm ? , amba ? ,thumb ? , cortex tm are registered trademarks or trademarks of arm ltd. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life. 13.4 rev. d ? 03/13 ...............................................................................................172 13.5 rev. e ? 07/13 ...............................................................................................173 13.6 rev. f? 12/13 ................................................................................................173 13.7 rev. g? 03/14 ...............................................................................................173 table of contents........ ................ ................. ................ .............. ........... 174

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