pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 /1 3 page 1 features ? frequency r ange 10mhz to 13 4 mhz ? output options: o 5 outputs pl123 - 05 o 9 outputs pl123 - 09 ? zero input - output delay ? optional drive strength: standard (8ma) pl 123 - 05/ - 09 high (12ma) pl 123 - 05h/ - 09 h ? 3.3v , 10% operation ? available in commercial and indu strial temperature ranges ? available in 16 - pin sop or tssop (pl123 - 09), and 8 - pin sop (pl123 - 05 ) packages description the pl 123 - 05/ - 09 ( - 05h/ - 09 h for high drive) are high performance, low skew, low jitter zero delay buffer s designed to distri b ute high spee d clocks . they have one (pl123 - 05 ) or two (pl123 - 09 ) low - skew output banks , of 4 outputs each , that a re synchronized with the input. the pl123 - 09 allows c ontrol of the banks of outputs by using the s1 and s2 inputs as shown in the selector defin i tion tab le on page 2. the synchronization is esta b lished via clkout feed back to the input of the pll. since the skew between the input and ou t put is less than ? 100 ps, the device acts as a zero delay buffer. the input output propag a- tion delay can be advanced or d elayed by adjusting the load on the clkout pin. these parts are not intended for 5v input - tolerant a p- plications. block diagram pll ref clkout clka 1 clka 2 clka 3 clka 4 mux clkb 1 clkb 2 clkb 3 clkb 4 s 1 s 2 1 ref clka 1 clka 2 vdd clkout clka 4 clka 3 vdd p l 1 2 3 - 0 9 gnd clkb 4 clkb 3 s 1 10 11 12 13 14 15 16 9 8 7 6 5 4 3 2 s 2 clkb 2 clkb 1 gnd b a n k b b a n k a selector inputs ( pl 123 - 09 only ) 1 2 3 4 ref 5 6 7 8 clka 2 clka 1 gnd clkout clka 4 vdd clka 3 p l 1 2 3 - 0 5
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 2 pin descriptions name pl123 - 09 pl123 - 05 type description tssop - 16l sop - 16l sop - 8l ref [1] 1 1 1 i input reference fr e quency. clk a 1 [2] 2 2 3 o buffered clock ou t put, bank a clk a 2 [2] 3 3 2 o buffered clock ou t put, bank a vdd 4,13 4,13 6 p vdd c onnection gnd 5,12 5,12 4 p gnd c onnection clk b1 [2] 6 6 - o buffered clock ou t put, bank b clk b2 [2] 7 7 - o buffered clock o u t put, bank b s2 [3] 8 8 - i selector i nput s1 [3] 9 9 - i selector i nput clk b3 [2] 10 10 - o buffered clock ou t put, bank b clk b4 [2] 11 11 - o buffered clock ou t put, bank b clk a 3 [2] 14 14 5 o buffered clock ou t put, bank a clk a 4 [2] 15 15 7 o buffered clo ck ou t put, bank a clkout [2] 16 16 8 o buffered clock output. internal fee d back on this pin. notes: 1: weak pull - down. 2: weak pull - down on all outputs. 3: weak pull - up on s1 and s2 selector definition for pl123 - 09 s2 s1 clock a 1 C a 4 (bank a ) clock b1 C b4 (bank b ) clkou t output source pll shu t down 0 0 three - state three - state driven pll n 0 1 driven three - state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n input / output skew co n trol the pl 123 - 05/ - 09 will achieve zero delay from input to output when all the outputs are loaded equally . adjus t- ments to the i n put/output delay can be made by adding additional loading to the clkout pin. please contact micrel for more inform a tion.
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 3 layout recommendations the following gu idelines are to assist you with a pe r formance optimized pcb design: signal integrity and termination consider a tions - keep traces short! - trace = inductor. with a capacitive load this equals ringing! - long trace = transmission line. without proper term i- nation this will cause reflections ( looks like rin g ing ). - design long traces as striplines or m i crostrips with defined impedance. - match trace at one side to avoid reflections bounc in g back and forth. decoupling and power supply co n siderati ons - place decoupling capacitors as close as possible to the vdd pin(s) to limit noise from the power supply - addition of a ferrite bead in series with vdd can help prevent noise from other board sources - value of decoupling capacitor is frequency d e- pen dant. typical values to use are 0.1 ? f for d e- signs using frequencies < 50mhz and 0.01 ? f for designs using fr e quencies > 50mhz. t y p i c a l c m o s t e r m i n a t i o n p l a c e s e r i e s r e s i s t o r a s c l o s e a s p o s s i b l e t o c m o s o u t p u t c m o s o u t p u t b u f f e r ( t y p i c a l b u f f e r i m p e d a n c e 2 0 ? ? ? t o c m o s i n p u t c o n n e c t a 3 3 ? ? s e r i e s r e s i s t o r a t e a c h o f t h e o u t p u t c l o c k s t o e n h a n c e t h e s t a b i l i t y o f t h e o u t p u t s i g n a l 5 0 ? l i n e
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 4 absolute maximum cond i tions supply voltage to ground potential ...... C 0.5v to 4.6v dc input voltage ........................... v ss C 0.5v to 4.6v storage tempe rature ........................ C 65c to 150c junction temper a ture.. 150c static discharge voltage (per mil - std - 883, method 3015) .. > 2000v operating conditions parameter description min. max. unit v dd supply voltage 3.0 3.6 v t a commercial operating temperatur e (ambient te m perature) 0 70 ? c industrial operating temperature (ambient te m perature) - 40 85 ? c c l load capacitance, below 100 mhz D 30 pf load capacitance, above 100 mhz D 10 pf c in input capacitance D 7 pf t pu power - up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 2 50 ms electrical characteri s tics parameter description test conditio ns min. max. unit v il input low vol t age C 0.8 v v ih input high vol t age 2.5 C v i il input low cu r rent v in = 0v C 50 a i ih input high cu r rent v in = v dd C 100 a v ol output low vol t age [ 4 ] i ol = 8 ma i ol = 12 ma C 0.4 v v oh output high vol t age [ 4 ] i oh = C 8 ma i ol = C 12 ma 2.4 C v i dd supply current (unloaded outputs) 66.67mhz with unloaded outputs commercial temp. C 32 ma 66.67mhz with unloaded outputs industrial temp. C 45 ma notes: 4 . parameter is guaranteed by design and c haracterization. not 100% tested in produ c tion .
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 5 switching characteristics [ 5 ] param e ter name test cond i tions min. typ. max. unit t 1 output fr e quency 30 - pf load 10 C 100 mhz 1 0 - pf load 10 C 13 4 mhz duty cycle [4] = t2 t1 mea s ured at 1.4v , f out = 66.6 7 mhz 40 50 60 % duty cycle [4] = t2 t1 mea s ured at 1.4v, f out <50 mhz 45 50 55 % t 3 rise time [4] measured b e tween 0.8v and 2.0v C C 2.5 ns rise time [4] ( high drive ) measured b e tween 0.8v and 2.0v C C 1.5 ns t 4 fall time [4] me asured between 0.8v and 2.0v C C 2.5 ns fall time [4] (high drive ) measured b e tween 0.8v and 2.0v C C 1.5 ns t 5 output to output skew all ou t puts equally loaded C C 2 5 0 ps t 6 a delay, ref rising edge to clkout rising edge [4] mea s ured at vdd/2 C 0 3 5 0 ps t 6 b delay, ref rising edge to clkout rising edge [4] measured at vdd/2 . mea s ured in pll bypass mode, pl123 - 09 only . 1 5 8. 5 n s t 7 device to d e vice skew [4] measured at vdd/2 on the clkout pin C 0 700 ps t 8 output slew rate [4] measured betwe en 0.8v and 2.0v using test circuit #2 1 C C v/ns t j cycle to cycle ji t ter [4] measured at 66.67 mhz, loaded ou t puts C 75 200 ps t lock pll lock time [4] s table power supply, valid clock pr e sented on ref pin C C 1 ms notes: 4 . parameter is guar anteed by design and cha r acterization. not 100% tested in production . 5 . all parameters are specified with loaded ou t puts .
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 6 switching waveforms 1.4v 1.4v t 2 t 1 vdd/2 input t 6 output vdd/2 1.4v output t 5 output 1.4v duty cycle ti m ing all outputs rise/fall time output - output skew input - output propagation d e lay t 3 t 4 output 0.8v 2.0v 0 v 3.3v v 0.8v 2.0v vdd/2 clkout, d e vice 1 t 7 clkout, d e vice 2 vdd/2 device - device skew
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 7 test circuits vdd vdd gnd gnd outputs c load clk 0.1 ? f 0.1 ? f test circuit #1 vdd vdd gnd gnd outputs 0.1 ? f 0.1 ? f test circuit # 2 10 pf 1k? 1k?
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 8 package drawings ( green package compl iant) s op 8l sy m bol dimension in mm min. max. a 1. 35 1.7 5 a1 0.1 0 0.25 a2 1.25 1.50 b 0.33 0.5 3 c 0.19 0.27 d 4.8 0 5.00 e 3.8 0 4.0 0 h 5.80 6.20 l 0. 40 0.89 e 1.27 bsc c l a sop - 16 l and tssop - 16 l ( mm ) sop tssop symbol min . max . min . max . a 1 . 35 1 . 75 - 1 . 20 a 1 0 . 10 0 . 25 0 . 05 0 . 15 b 0 . 33 0 . 51 0 . 19 0 . 30 c 0 . 19 0 . 25 0 . 09 0 . 20 d 9 . 80 10 . 00 4 . 90 5 . 10 e 3 . 80 4 . 00 4 . 30 4 . 50 h 5 . 80 6 . 20 6 . 40 bsc l 0 . 40 1 . 27 0 . 45 0 . 75 e 1 . 27 bsc 0 . 65 bsc e h d a 1 e b c l a 2 e h d a 1 e b a
pl123 - 05/ - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 4 / 2 2 / 1 3 page 9 ordering information micrel inc., reserves the right to make changes in its products or specifications, or both at any time without notice. the information furnished by mic rel is believed to be accurate and reliable. however, micrel makes no guarantee or warranty concerning the accuracy of said info rm ation and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : micrels products are not authorized for use as critical components in life support devices or syste ms without the express written approval of the president of micrel inc. for part ordering, please contact our sales department: 2 1 80 fortune drive , san jose, ca 95131 , usa tel: (408) 944 - 0800 fax: (408) 474 - 1 000 part number the order number for this device is a combinati on of the following: part number, package type and operating temperature range part/order nu m ber (commercial) mar k ing* (commercial) part/order nu m ber (industrial) mar k ing* (industrial) package o p tion pl123 - 05sc p12305 s c lllll pl123 - 05si p12305 s i lllll 8 - pin sop tube pl123 - 05sc - r pl123 - 05si - r 8 - pin sop (tape and reel) pl123 - 05hsc p12305h s c lllll pl123 - 05hsi p12305h s i lllll 8 - pin sop tube pl123 - 05hsc - r pl123 - 05hsi - r 8 - pin sop (tape and reel) pl123 - 09oc p12309 o c lllll pl123 - 09oi p12309 o i lllll 16 - pin tssop tube pl123 - 09oc - r pl123 - 09oi - r 16 - pin tssop (tape and reel) pl123 - 09hoc p123 09h o c lllll pl123 - 09hoi p123 09h o i lllll 16 - pin tssop tube pl123 - 09hoc - r pl123 - 09hoi - r 16 - pin tssop (tape and reel) pl123 - 09 s c p123 09 s c lllll pl123 - 09 s i p123 09 s i lllll 16 - pin sop tube pl123 - 09 s c - r pl123 - 09 s i - r 16 - pin sop (tape and reel) pl123 - 09hsc p123 09h s c lllll pl123 - 09hsi p123 09h s i lllll 16 - pin sop tube pl123 - 09hsc - r pl123 - 09hsi - r 16 - pin sop (tape and reel) *note : lll ll designates lot number p l 1 2 3 - 0 x ( h ) x x - x p a r t n u m b e r h = h i g h d r i v e n o n e = s t a n d a r d d r i v e p a c k a g e t y p e o = t s s o p s = s o p n o n e = t u b e s r = t a p e & r e e l t e m p e r a t u r e r a n g e c = c o m m e r c i a l ( 0 c t o 7 0 c ) i = i n d u s t r i a l ( - 4 0 c t o 8 5 c )
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