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PS20063 image reject mopll with if agc amplifier preliminary information data sheet 291305 issue 1 jun-11 ordering information PS20063c1q1at 48 qfn tape & reel PS20063c1q1a5 48 qfn trays -20 c to +85 c description the PS20063 is a 3 band mopll with if agc amplifier. it down-converts the rf channel to a standard if with image rejection, simplifying front-end filtering. this is followed by a saw filter and if agc amplification for the digital channel. each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank circuit. an if level detector is included for control of the rf agc. the take over point (top) and time constant are both programmable. the PS20063 has excellent signal level handling performance in the presence of high level unwanted signals. all chip control is via an i 2 c compatible interface. an alternative part, ps20060 , is available without image reject do wn conversion. equivalent parts: ce5063 features ? mixer/oscillator pll and if agc amplifier with image rejection for multi band analog / digital terrestrial tuners and/or cable tuners ? typically >30db image rejection ? low phase noise pll frequency synthesizer ? agc output level detect with digital controlled threshold ? >50 db desired/undesired ratio without pre filtering ? separate analog and digital if outputs ? >41 db if agc control range ? power down modes to support power reduction initiatives ? four independent switching ports ? 48 pin qfn package applications ? atsc and dcr receiver systems ? dvb-t receiver systems ? dvb-c cable receiver systems ? terrestrial analog receivers data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 1
ps 20063 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 rf converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 saw driver amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 agc detector and adc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 if agc amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 vco. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 pll frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 general purpose switching ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.0 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 programmable features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 pll registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 control register - byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 control register - byte 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 control register - byte 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 applications information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.0 pin circuit information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.0 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.0 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 2
PS20063 list of figures figure 1 - basic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3 - detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4 - typical agc characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5 - low band (vhf1) external tank circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6 - mid band (vhf3) external tank circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7 - high band (uhf) external tank circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8 - typical application circuit (atsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9 - typical application circuit (dvbt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10 - crystal oscillator circuit (4 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11 - interstage filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 3
PS20063 data sheet list of tables table 1 - pin names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2 - programmable features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3 - control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 - address bit ma1 and ma0 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5 - byte 2- lo divider (msb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6 - byte 3 lo divider (lsb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7 - byte 4 pll control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8 - charge pump current selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9 - reference divide ratio settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10 - byte 5 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11 - band selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12 - internal circuit block control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13 - gppo output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 14 - byte 6 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15 - agc decay current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 16 - agc threshold selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 17 - byte 7 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 18 - adc input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 19 - test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 20 - read data format (msb is transmitted first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 21 - agc activity flag settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 22 - adc output values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 23 - optimum cp and lo trim settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 4
PS20063 figure 2 - pin diagram pin no. port name function 1 ifagc if amplifier agc input 2 sab analog saw filter driv er differential outputs 3sa 4 adc external adc input 5sda i 2 c bus serial data input/output 6scl i 2 c bus serial clock input 7 add i 2 c bus address selection input 8 agcop agc output 9 cnopb converter differential outputs 10 cnop 11 cont paddle (ground) 12 vccrf rf section supply 13 sipb saw filter driver differential inputs 14 sip 15 gpp0 general purpose switching port 16 gpp1 general purpose switching port table 1 - pin names agcop ps2 0063 cnop cnopb adc scl sda lhopb lhipb veeosc lmopb lhop lhip lmop veerf gpp2 ipref gpp0 gpp1 sipb sip loip sa ifagc sab vccosc ifip ifipb veeif ifopb ifop xtal vccif sdb vccif sd pump vccdig 1 vccrf cont llopb llop hiipb gpp3 xcap drive hiip midip add vee (package paddle) data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 5
PS20063 17 gpp2 general purpose switching port 18 veerf rf section ground 19 loip low band (vhf1) input 20 ipref reference input for low and mid band inputs 21 midip mid band (vhf3) input 22 hiip high band (uhf) differential inputs 23 hiipb 24 gpp3 general purpose switching port 25 llop low band local oscillator outputs 26 llopb 27 lmop mid band local oscillator outputs 28 lmopb 29 lhip high band local oscillator input 30 lhop high band local oscillator outputs 31 lhopb 32 lhipb high band local o scillator inverse input 33 veeosc oscillator section ground 34 vccosc oscillator supply 35 ifip if agc amplifier differential inputs 36 ifipb 37 drive pll loop amplifier drive output 38 pump pll loop amplifier charge pump output 39 vccdig digital section supply 40 sd digital saw filter driv er differential outputs 41 sdb 42 vccif if amplifier section supply 43 xcap reference osc illator feedback input 44 xtal reference oscillator crystal drive 45 vccif if amplifier section supply 46 veeif if section ground 47 ifop if agc amplifier differential outputs 48 ifopb paddle vee global ground pin no. port name function table 1 - pin names (continued) data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 6
PS20063 figure 3 - detailed block diagram 1.0 functional description the ps2 0063 is a three-band rf mixer oscillator with im age rejec tion, with on-board frequency synthesizer and if agc amplifier, integrati ng all tuner active circuitry after the tracking filter into a single package. it is intended for use in all band terrestrial tuners, and requires a minimum external co mponent count. it contains all elements required for rf down conversion to a standard if , with the exception of external vco tank circuits. in normal applications, the rf input is interfaced to the selected mixer oscill ator preamplifier through the tuner pre- filter and agc stages. the ps2 0063 provides an rf agc co ntrol signal, which can be used to control the rf gain. the preamplifier output feeds the image rejection mixer stage where the required channel is down converted to the if frequency. the local osc illator frequency for the down conversion is obtained from the on board pll and local oscillator, with an external varactor tuned tank. the downconverted signal is then passed through an external filter into a saw filter driv er amplifier. this provides two output channels for hybrid ana log and digital applications. sdb xc ap port in terf ace gp p 2 gp p 3 i2 c int erf ace gp p 1 gp p 0 ref di vi der prog di vi der xtal drive pump lhopb lho p lhip lh ipb lmo pb lmop sd scl add sda agcop cn op cnopb llopb ll op sip sipb agc det adc ipref hi ip mid ip loip vccdig veerf vccsa quadrat ure generat or adc ifout ifoutb if i p ifipb ifagc vccif vccif veeif swi tch sab sa veeosc vccosc co nt hi ipb (paddle) vee data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 7
PS20063 an agc if amplifier is included which provides an output signal to a digital demodulator. the device is controlled through an i 2 c compatible interface. 1.1 rf converter the ps2 0063 contains three input stages to cover the vhf1, vhf3 and uhf frequency bands. the inputs would normally be driv en by front end amplifie rs and tracking fi lters. all three inputs are di fferential, however, the vhf1 and vhf3 inputs would normally be driven single ende d. these inputs therefore can share a common input reference pin. the uhf input should be driven with a differential signal. the inputs are all high impedance. the differential converter if output is then passed through an external interstage filter. this can be tuned for 44 mhz for atsc applications but can also be used at 36 mhz to be compatible with other tv standards. the recommended filter circuit is shown in figure 11. the design of this filter provides an imped ance transformation as well as rejection of adjacent channels. a 0.5 db chebychev filter with 10 mhz bandwidth is recommended. this gives a flat response across the pass band and takes into account normal component tolerances. 1.2 saw driver amplifier the output of the interstage filter then passes to the saw f ilter drive amplifier. this pr ovides further amplification and interfaces to the saw filter. two saw filter drive ou tputs are provided for hybrid analog and digital applications. both output stages are identical, ho wever, the digital output (sd, sdb) should always be used for digital applications, as the pin out of t he device has been optimized to give the best isolation performance in this configuration. output selection is programmable howev er it should be noted that the unselected output is not powered off but operates at a lower power level which means that a signal will st ill be present on the output, but with reduced output drive capability. the differential outputs will drive a balanced saw filter wi th a tuning inductor to resonate with the saw filter input capacitance. the saw filter can also be driven without the tuning inductor but this r equires the addition of 360 ohm resistors to ground on the saw driver outputs to increase the output drive capability. this will increase total current consumption by approximately 14 ma. 1.3 agc detector and adc the ps2 0063 contains a broadband agc detector circuit whic h provides an output to provide gain control for the rf frontend gain stages. the detector input signal is derived from the signal level in the saw driver amplifier. the composite signal at this point is the wanted signal plus adjacent channels (n +/- 1, n +/- 2, n +/- 3). the agc detector threshold point at which the agc output becomes active can be programmed to one of eight levels via the i 2 c interface. when the composite level reaches the agc threshold, the agc output pin will be active. the agc attack current is fixed, however, the decay current can be programmed to two levels. the agc output can only drive a high impedance e.g., a dual gate fet. if rf gain co ntrol uses a pin diode then a simple buffer circuit will be required. an agc flag output is also available through the i 2 c interface. this indicates when the agc output is active i.e., less than 4 volts. the agc output level can also be monitored by an on chip 3 bit adc. although the adc is 3 bits, only 5 levels are available. alternativ ely the adc can be programmed to measure the voltage on an external pin (adc pin 4). 1.4 if agc amplifier the agc amplifier amplifies the output of the saw filter for the digital channel and prov ides a differential output to the demodulator. the analog gain control signal is normally derived from the demodulator. at least 41 db of gain control is provided. the agc amplifier can be powered down independently of the re st of the device if not r equired. this mode could be used in analog applications to reduce overall power consumption. data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 8
PS20063 figure 4 - typical agc characteristic 1.5 vco separate vco?s are provided for each band. the oscillator circuits are on ch ip, however, the tank circuitry is external. all three oscillators are differen tial. the typical external tank circuits are shown in figures 5, 6 and 7. it is essential to take care to minimize track lengths and parasitics when designing the pcb layout to obtain best performance. the close-in phase noise of the local os cillator can be optimized at the programmed operating frequency by a programming bit which increases bias current in the vco. . figure 5 - low band (vhf1) external tank circuit 0 10 20 30 40 50 60 70 00 . 511 . 522 . 533 . 54 agc voltage (v) gain (db) maximum gain minimum gain gain variation over -20 to +85c at vagc = 1.2v and 2.2v llopb llop vvar r_bias r_bias cs pf l1 nh data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 9
PS20063 figure 6 - mid band (vhf3) external tank circuit figure 7 - high band (uhf) external tank circuit 1.6 pll frequency synthesizer the pll frequency synthesizer section contains all the el ements necessary, with the exception of a frequency reference and loop filter to control a varicap tuned local oscillator, to form a complete pll frequency synthesized source. the device allows operation with a high comparis on frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. it can be operated with comparison frequencies appropriate for frequency offsets as re quired in digital terrestrial (dtt) receivers. the lo input signal from the selected oscillator section is routed to an internal preamplif ier, which provides gain and reverse isolation from the divider signals. the output of the preamplifie r interfaces directly to the 15-bit programmable divider, which is of mn+a architecture, with a 16/17 dual modulus prescaler. the a counter is 4-bits, and the m counter is 11 bits. the output of the programmable divider is fed to the phas e detector together with the comparison frequency, which is derived either from the on-board crystal controlled oscill ator, or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider, which is programmable into 1 of 16 ratios. the output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external loop filter, integrates the current pulses into the varactor control voltage. test modes allow both the divider outputs to be moni tored via output port gpp0 for debug and test purposes. lmopb lmop vvar r_bias r_bias cs pf l1 nh lhipb lhopb lhop lhip vva r r_bias r_bias cs pf l1 nh cp r_damp cp cp cp data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 10
PS20063 the pll includes a lock detect circuit. the lock detect out put is available by reading the status byte on the i 2 c interface 1.7 general purpose switching ports the ps2 0063 has four output switching ports. three of these p orts (gpp[3:1]) incorporate a 10 kohm pull up resistor. the remaining port (gpp0) is an open collector switch. these ports can be used for switching external rf input stages for example. ports gpp[1:0] can also be used as test outputs for debug purposes. 1.8 i 2 c interface the ps2 0063 is controlled by an i 2 c data bus and is compatible with both 3.3 v and 5 v control levels. data and cloc k are fed in on the sda and sc l lines respectively as defined by i 2 c bus format. the device can either accept data (write mo de), or send data (read mode). the lsb of t he address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. the device can be programmed to respond to 1 of 4 addresses, which enables the use of more than one device in an i 2 c bus system. the address is selected by applying a voltage to the ?add? input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes ar e received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this peri od, the device generates an internal stop condition, whic h inhibits further reading. data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 11
PS20063 2.0 programming the ps2 0063 is fully programmable through the i 2 c interface. the device can also output data to the controller. 2.1 programmable features 2.2 register map there are a total of 7 write registers, the first of which is the address regist er. the control registers are described in detail in the following section. the m sb of each register is written first. after reception and acknowledgement of a correct addre ss (byte 1), the msb of the following byte determines whether that byte is interpreted as a byte 2 or byte 4; a logic '0' indicating byte 2, and a logic '1' indicating byte 4. the next data byte will then be interpreted as byte 3 or byte 5 respectively. byte 5 can be followed by byte 6 and byte 7 if required. a stop condition can be generated after any data byte, however, if it occurs during a byte transmission, the previous byte data is retained. to facilitate smooth tuning, the frequency data by tes are only accepted by the device after all 15 bits of frequency data (i.e. bytes 2 and 3) have been received, or after the generation of a stop condition. it should also be noted that if it is necessary to program bytes 6 or 7, then bytes 4 and 5 must be programmed at the same time feature description rf programmable divider programs pll main divider reference programmable divider programs pll reference divider to set required frequency step band selection selects rf input and appropriate lo oscillator. agc threshold sets the input power level threshold at which the agc detector starts to generate a control level. agc decay sets the agc decay current. charge pump current selects one of t he four charge pump current settings. if amplifier function the if amplifier can be enabled independently of other circuit blocks. sawf output select select the analog or digital saw driver output. ports gpp[3:1] these are configured as npn buf fers with 10 kohm pull-up resistors to v cc . logic ?1? = on logic ?0? = off; default on power up port gpp0 this is configured as a npn open collector buffer. logic ?1? = on logic ?0? = off; default on power up lo trim allows adjustment of vco bias curren t and lo gain to provide optimum phase noise performance. adc input select select either the internal agc detec t output level or the exter nal level applied to the adc input pin. programmable power the ps2 0063 has various power saving modes. test modes test modes to monitor and control internal pll signals. table 2 - programmable features data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 12
PS20063 details of the programming re gisters are shown in the following sectio ns. default values on power up are also shown. msb lsb ack 76543210 address 11000ma1ma00a byte 1 programmable divider 0 d14 d13 d12 d11 d10 d9 d8 a byte 2w programmable divider d7 d6 d5 d4 d3 d2 d1 d0 a byte 3w control data 1 c1c0r4r3r2r1r0 a byte 4w control data bs1bs0sl1sl0p3p2p1p0 a byte 5w control data lo1 lo0 atc ife x at2 at1 at0 a byte 6w control data sas x agd ads t3 t2 t1 t0 a byte 7w table 3 - control registers a acknowledge bit ma1, ma0 address bits d14-d0 programmable divisi on ratio control bits r4-r0 reference division ratio select c1, c0 charge pump current select bs1-bs0 band select bits sl1-sl0 power down modes sas sawf drive output select p3-p0 p3-p0 port output states ads adc input select atc agc decay current agd agc disable at2:at0 agc onset threshold control lo1:lo0 lo trim control bits t3-t0 test mode control bits ife if agc amplifier enable x don?t care data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 13
PS20063 2.3 address register the ps2 0063 address (ma1, ma0) are determined by the volt age se t at the address pin (add) as shown in table 4. 2.4 pll registers bytes 2,3 and 4 are used to program the pll. the lo frequency will not be updated until both byte 1 and byte 2 have been programmed. address select (byte 1) ma1 ma0 address input voltage level 0 0 0 - 0.1vcc (connect to v ee ) 0 1 0.2v cc ? 0.3v cc (open circuit) 10 0.4 v cc ? 0.6 v cc (30k ? to v cc ) 110 . 9 v cc - 1.0 v cc (connect to v cc ) table 4 - address bit ma1 and ma0 settings bit field name default description 7 - 0 must be set to 0 (byte 2) 6:0 d[14:8] 0 msb bits of lo divider register. table 5 - byte 2- lo divider (msb) bit field name default description 7:0 d[7:0] 0 lsb bits of lo divider register. table 6 - byte 3 lo divider (lsb) bit field name default description 7 - 1 must be set to 1 (byte 4) 6:5 c[1:0] 0 charge pump current. 4:0 r[4:0] 10011 reference divider control. table 7 - byte 4 pll control data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 14
PS20063 the charge pump current values are selected from the following table : the reference divider ratio can be selected from the following table: c1 c0 current a 0 0 +-155 0 1 +-330 1 0 +-690 1 1 +-1450 default state on power up = 00 table 8 - charge pump current selection r4 r3 r2 r1 r0 ratio 0001116 0010032 0010164 00110128 0101120 0110040 0110180 01110160 1001124 1010048 1010196 10110192 1101128 1110056 11101112 11110224 default state on power up = 10011 table 9 - reference divide ratio settings data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 15
PS20063 2.5 control register - byte 5 the band switching is controlled as shown below: the various power-up modes are shown below. the if agc amplifier is controlled separately by ife bit (see table 14). the i 2 c interface and crystal oscillator circuit are active in all modes . the ps2 0063 has four output ports. ports gpp[3:1] each have an intern al 10 kohm pull up resistor to vcc. gpp0 is open collector. bit field na me default description 7:6 bs[1:0] 11 band switching 5:4 sl[1:0] 01 power-up modes 3:0 p[3:0] 0 general purpose output ports table 10 - byte 5 control bs1 bs0 band selected 0 0 lo band 0 1 mid band 1 0 hi band 1 1 all off default state on power up = 11 table 11 - band selection power mode section status sl1 sl0 i 2 c interface and registers crystal oscillator pll & vco converter and if stages 0 x sleep enabled enabled disabled disabled 1 0 pll and vco enabled enabled enabled enabled disabled 1 1 full enabled enabled enabled enabled table 12 - internal circuit block control function bit 0 1 gpp0 output enable p0 off (high impedance) on (current sink) gpp1 output enable p1 off on (current sink) gpp2 output enable p2 off on (current sink) gpp3 output enable p3 off on (current sink) table 13 - gppo output port control data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 16
PS20063 2.6 control register - byte 6 the vco bias trim adjusts the vco bias to give optimum cl ose-in phase noise. in general this should be set to 1 for the lower third of the vco frequency range. the lo gain adjust increases the gain of the lo drive ci rcuit. setting this bit to ?1? can improve the far-out phase noise performance. the agc attack current is fixed at 100 a, however, the agc decay current can be programmed to one of two values as shown below. if the pll is unlocked (fl = 0), then the atc control is over-ridden and the agc decay current is set to 10 a. when the pll locks (fl = 1) the decay current reverts to the programmed atc value. the decay current is always present even when the at tack current is on. this means that if the 10 a decay current is selected, then the effective attack current is reduced to 90 a the agc threshold can be programmed using the at[2:0] bits. note that the programmed value is db v peak. this is the signal level at the saw driver outputs. bit field name default description 7l o 10v c o b i a s t r i m 6 lo0 0 lo gain adjust 5 atc 0 agc decay current select 4 ife 0 if agc amplifier enable (1 = on) 3 x 0 not used 2:0 at[2:0] 0 agc threshold select table 14 - byte 6 control atc agc decay current ( a) 01 0 . 0 10 . 3 table 15 - agc decay current setting at2 at1 at0 agc threshold (peak signal in db v into detector) 0 0 0 120 001 118 010 116 011 114 100 112 101 110 1 1 0 107 1 1 1 104 default state on power up = 000 table 16 - agc threshold selection data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 17
PS20063 2.7 control register - byte 7 the adc input selection is shown in the table below the test bits t[3:0] allow internal pll signals to be monitored and also to manually control charge pump current and agc detector output. this facility may be useful during debug. the test bit selection is shown below. the reserved test modes should not be used. bit field name default description 7 sas 1 digital saw drive output select (1 = digital) 6 x 0 not used 5 agd 1 agc detector enable (0 = enabled) 4 ads 0 adc input select 3:0 t[3:0] 0 test bits table 17 - byte 7 control ads adc function 0 agc output 1 external adc input table 18 - adc input selection t3 t2 t1 t0 test mode description 0 0 0 0 normal operation 0 0 0 1 reserved test mode 0010agc sink, force i agc = -100 a 0 0 1 1 agc source, force i agc = 10 a p0 = output of agc bias dac 0 1 0 0 reserved test mode 0 1 0 1 reserved test mode 0 1 1 0 reserved test mode 0 1 1 1 reserved test mode 1 0 0 0 reserved test mode 1 0 0 1 charge pump sink * status byte fl set to logic ?0? 1 0 1 0 charge pump source * status byte fl set to logic ?0? 1 0 1 1 charge pump disabled * status byte fl set to logic ?1? 1100port p0 = f pd /2 1 1 0 1 charge pump sink * status byte fl set to logic ?0? port p0 = f comp table 19 - test modes data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 18
PS20063 2.8 read mode when the device is in read mode, the status byte read from the device takes the form shown in table 20. the following data read is accessed from the read byte; bit 7 (por) is the power-on reset indicator, and this is set to a logic '1' if the v cc supply to the device has dropped below 3 v (at 25 c), e.g., when the device is init ially turned on. the por is reset to '0' when the read sequence is terminated by a stop command. when por is set high th is indicates that the programmed information may have been corrupted and the device reset to power up condition. bit 6 (fl ) is the pll lock flag and indicates whether the device is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. the fl bit is set after 64 consecutive comparison cycles in lock. bit 3 (agf) is the agc detector flag and indica tes if rf agc control is active . 1 1 1 0 charge pump source * status byte fl set to logic ?0? port p0 = f comp 1 1 1 1 charge pump disabled * status byte fl set to logic ?1? port p0 = f comp msb lsb ack 76543210 address 11000ma1ma01a byte 1 status byte por fl 0 0 agf v2 v1 v0 a byte 2r table 20 - read data format (msb is transmitted first) agf agc activity flag 0 agc active, v agc < 4 v external rf lna gain is reduced 1 agc not active, v agc >4 v external rf lna gain is at maximum table 21 - agc activity flag settings t3 t2 t1 t0 test mode description table 19 - test modes (continued) data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 19
PS20063 bits 2:0 (v2:v0) contain the adc output data. the adc output is sampled on the ack clock of the read address byte. input level (v) v2 v1 v0 < 0 . 3 2 v c c 000 0.32vcc to 0.48vcc 0 0 1 0.48vcc to 0.64vcc 0 1 0 0.64vcc to 0.80vcc 0 1 1 > 0 . 8 0 v c c 100 table 22 - adc output values data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 20
PS20063 3.0 applications information typical application circuits for the ps20 063 are shown in the following diagrams. figure 8 - typical application circuit (atsc) c14 2p2f c13 2p2f c12 2p2f c11 2p2f l6 2n5h (air) c16 27pf r6 3k3 c17a 330nf c20 2.2nf r7 5.1k gnd r8 20k +30v r9 1k c21 82nf gnd +5v +5v l4 12n5h (ai r) d2 bb640 c10 68pf l2 100nh (air) c2 100pf d1 bb640 r1 1k r4 3k3 r5 1k c3 100pf c4 15pf c5 1nf c6 15pf c7 1nf c8 1nf r3 1k gnd gnd c30 10nf c32 100pf c33 10nf c34 10nf c35 10nf +30 v + c56 10uf +5v c22 10nf c23 10nf r2 3k3 gnd gnd d3 bb555 gnd gnd gnd rf in (uhf) rf in (vhf 3) rf in (vhf 1) gnd l9 390nf gnd +5v c38 22pf l10 390nh c25 22pf c39 6.8pf in+ 2 in- 1 op+ 4 gnd 3 op- 5 sf1 epcos x6964d gnd c37 10nf l13 1.5uh c24 1nf c26 1nf c27 1nf gnd r13 0r pll loop filter c15 10nf l11 390nf gnd gnd c40 100pf tp3 tp gnd + c36 2u2f gnd c51 10nf gnd c46 100nf c47 100pf +5v gnd lhip 29 lhop 30 lhopb 31 lhipb 32 vccosc 34 vccif 45 ifo p 47 ifo pb 48 ifagc 1 vccifo 42 vccrf 12 vccdig 39 co ntin uity 11 drive 37 pump 38 sda 5 xcap 43 xtal 44 gp p0 15 scl 6 hiipb 23 sab 2 sd 40 adc 4 ifin 35 gp p3 24 agco ut 8 add 7 veeif 46 sdb 41 cnop 10 cnop b 9 veerf 18 loip 19 midip 21 rfinb 20 hiip 22 ll op 25 llopb 26 ve eosc 33 gnd 0 gp p1 16 sa 3 gp p2 17 ifinb 36 sip b 13 sip 14 lmop 27 lmop b 28 zl1006x ic1 ps2 0063 c48 22pf c49 10nf r15 6r8 r14 6r8 c50 10nf c19 47pf c18 150pf gnd x1 4.000mhz +5v c1 10nf c28 27pf gnd gnd gnd x3 nm x5 nm x7 0r gnd gnd x2 nm x4 nm x6 0r gnd 1 2 3 4 ifa gc adc ifa gc c53 10nf gnd r26 nm r27 nm gnd coil data l2: 100n h as 8.5 tur ns 24 swg ( 0. 56mm) en cu on 2.5mm di a l4: 12. 5nh as 30mm 24 swg en cu for med i nto 2.5 tur ns on 2m m di a l6: 2n5h as 16mm 24 sw g en cu formed into 5/4 turns on 2mm di a space wound cl ose wound space wound tr1 bcw33 c54 100pf gnd +5v 1 2 3 4 6 r16 18k scl sda i2c ag c out gp p3 gp p2 gp p1 gp p0 interstage filter if output to digital demodulator analog saw driver output data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 21
PS20063 figure 9 - typical appl ication circuit (dvbt) c14 2p2f c13 2p2f c12 2p2f c11 2p2f l6 2n5h (air) c16 27pf r6 3k3 c17a 10nf c20 220pf r7 10k gnd r8 20k +30v r9 1k c21 8.2nf gnd +5v +5v l4 12n5h (ai r) d2 bb640 c10 68pf l2 100nh (air) c2 100pf d1 bb640 r1 1k r4 3k3 r5 1k c3 100pf c4 18pf c5 1nf c6 18pf c7 1nf c8 1nf r3 1k gnd gnd c30 10nf c32 100pf c33 10nf c34 10nf c35 10nf +30 v + c56 10uf +5v c22 10nf c23 10nf r2 3k3 gnd gnd d3 bb555 gnd gnd gnd rf in (uhf) rf in (vhf 3) rf in (vhf 1) gnd l9 680nf gnd +5v c38 12pf l10 680nh c25 12pf c39 12pf in+ 2 in- 1 op+ 4 gnd 3 op- 5 sf1 epcos x6874d gnd c37 10nf l13 1.5uh c24 1nf c26 1nf c27 1nf gnd r13 0r pll loop filter c15 10nf l11 680nf gnd gnd c40 100pf tp3 tp gnd + c36 2u2f gnd c51 10nf gnd c46 100nf c47 100pf +5v gnd lhip 29 lhop 30 lhopb 31 lhipb 32 vccosc 34 vccif 45 ifo p 47 ifo pb 48 ifagc 1 vccifo 42 vccrf 12 vccdig 39 co ntin uity 11 drive 37 pump 38 sda 5 xcap 43 xtal 44 gp p0 15 scl 6 hiipb 23 sab 2 sd 40 adc 4 ifin 35 gp p3 24 agco ut 8 add 7 veeif 46 sdb 41 cnop 10 cnop b 9 veerf 18 loip 19 midip 21 rfinb 20 hiip 22 ll op 25 llopb 26 ve eosc 33 gnd 0 gp p1 16 sa 3 gp p2 17 ifinb 36 sip b 13 sip 14 lmop 27 lmop b 28 zl1006x ic1 ps2 0063 c48 12pf c49 10nf r15 6r8 r14 6r8 c50 10nf c19 47pf c18 150pf gnd x1 4.000mhz +5v c1 10nf c28 27pf gnd gnd gnd x3 nm x5 nm x7 0r gnd gnd x2 nm x4 nm x6 0r gnd 1 2 3 4 ifa gc adc ifa gc c53 10nf gnd r26 nm r27 nm gnd coil data l2: 100n h as 8.5 tur ns 24 swg ( 0. 56mm) en cu on 2.5mm di a l4: 12. 5nh as 30mm 24 swg en cu for med i nto 2.5 tur ns on 2m m di a l6: 2n5h as 16mm 24 sw g en cu formed into 5/4 turns on 2mm di a space wound cl ose wound space wound tr1 bcw33 c54 100pf gnd +5v 1 2 3 4 6 r16 18k scl sda i2c ag c out gp p3 gp p2 gp p1 gp p0 interstage filter if output to digital demodulator analog saw driver output data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 22
PS20063 the low (vhf1) and mid (vhf3) bands are single ended, however, the high band (uhf) should be differential. all if signals are differential. it is essential to have good rf layout around the rf sta ges, i.e., rf inputs and the vcos. track lengths around the vco?s should be minimized to reduce track inductance. the layout should be organized to give good isolation bet ween the if signal paths. in particular good isolation is required between the outputs and inputs of the if agc amplifier. isolation across the saw filter is also important to ensure rejection of unwanted adjacent signals. this c an be achieved by routing input and output tracks on opposite sides of the board. it is also important to have good is olation between the hi gh level if signal and the crystal oscillator circuit to minimize any interactions. care should be taken when loca ting if tuning inductors to en sure there is no radiation to other parts of the circuit. the crystal oscillator can also provide a clock signal to the demodulator. this can be done by taking the oscillator signal from the crystal series capacitor (27 pf) as shown in the following diagram. figure 10 - crystal oscillator circuit (4 mhz) 150pf 27pf 47pf xcap xtal to demodulator data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 23
PS20063 the interstage filter between the converter outputs provi des some additional rejection of adjacent channels (n +/- 2).the recommended values are shown in figure 11. the choice of components is important not only to give a flat response but also to provide an impedance transformat ion between the converter output and saw driver input stages. figure 11 - interstage filter cnopb cnop sipb sip l1 l1 cc cc l2 c1 c1 rterm rterm sawf drive amplifier input c2 r source r source vcc c1 type if 0.5 db bw component values mhz mhz r source w r term l1 nh l2 nh c1 pf cc pf c2 pf 0.5 db chebychev 44 10 500 250 390 390 22 15 7.5 0.5 db chebychev 36 10 500 250 680 680 12 18 12 data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 24
PS20063 the optimum charge pump and lo trim settings for the appl ication circuits shown in figure 8 and 9, are shown in table 23 below. these give the optimum phase noise performance for the circuit shown. the changes in charge pump current compensate for frequency and vco gain variations. frequency range charge pump setting cp lo trim lo1 lo trim lo0 vhf1 50 -110 mhz 01 1 1 vhf1 100 -160 mhz 10 1 1 vhf3 160 - 250 mhz 10 1 1 vhf3 250 - 350 mhz 01 1 1 vhf3 350 - 450 mhz 10 0 1 uhf 450 - 500 mhz 00 1 1 uhf 500 - 700 mhz 01 1 1 uhf 700 - 800 mhz 10 1 1 uhf 800 - 850 mhz 11 1 1 table 23 - optimum cp and lo trim settings data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 25
ps0063 4.0 pin circuit information pin no. pin name port sense function schematic 1 ifagc input if agc control 2, 3 sab, sa output, output saw filter driver output a inverse saw filter driver output a 4 adc input adc input 5 sda bi-directional i 2 c bus serial data input/output 6 scl input i 2 c bus serial clock input v ref 3k 3k ifagc 50 vcc sa sab vcc adc vcc sda vcc sda vcc scl data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 26
PS20063 7 add input i 2 c address select 8 agcop output agc output 9, 10 cnopb, cnop output, output converter output inverse converter output 11 cont - paddle - 12 vccrf supply rf section supply - 13, 14 sipb sip input, input saw filter driver input inverse, saw filter driver input 15 gpp0 output switching port/test output 1 pin no. pin name port sense function schematic vcc add 3k 63k 21k vcc agcop 100 1k vcc cnopb cnop 500 500 sip 250 1.1k vcc sipb gpp0 data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 27
PS20063 16 gpp1 output switching port/test output 2 17 gpp2 output switching port as gpp1 (pin16) 18 veerf supply rf section ground - 19, 20, 21 loip ipref midip input, input, input low band input, mid- and low-band i/p reference, mid-band input 22, 23 hiip, hiipb input, input hi-band input, hi-band input inverse 24 gpp3 output switching port as gpp1 (pin16) 25, 26 llop, llopb output low band oscillator output, low-band oscillator output inverse 27, 28 lmop, lmopb output, output mid-band oscillator output, mid-band oscillator output inverse pin no. pin name port sense function schematic gpp1 gpp2 gpp3 10k vcc ipref loip midip hiipb hiip llop llopb lmop lmopb data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 28
PS20063 29, 30, 31, 32 lhip, lhop, lhopb, lhipb input, output, output, input high band osc illator input, high-band oscillator output, high-band oscillator output inverse, high-band oscillato r input inverse 33 veeosc supply lo ground - 34 vccosc supply lo supply - 35, 36 ifip, ifipb input, input if agc amp input, if agc amp input inverse 37, 38 drive, pump output, output loop amplifier drive output, loop amp charge pump output 39 vccdig supply digital section supply - 40, 41 sd, sdb output, output saw filter driver output d, saw filter driver o/p d inverse 42 vccif supply sawf output supply - 43 xcap input reference osc feedback input 44 xtal output reference osc crystal drive see xcap (pin 43) pin no. pin name port sense function schematic vcc lhip lhipb 350 350 lhopb lhop ifipb ifip pump 340 vcc drive 50 vcc sd sdb 0.2 ma 110 xtal xcap vcc data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 29
PS20063 45 vccif supply if agc supply - 46 veeif supply if agc ground - 47, 48 ifop, ifopb output, output if agc amp output, if agc amp inverse output paddle vee - - - pin no. pin name port sense function schematic ifop vcc data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 30
PS20063 5.0 absolute maximum ratings all voltages are referred to v ee at 0 v. note 1: the v ccosc , v ccdig (pins 39,42) can be operated at a lower supply voltage than the remaining v cc pins, but the voltage differential must not exceed the figure quoted in the table above. 6.0 operating range all voltages are referred to v ee at 0 v. characteristic min. max. units conditions supply voltage -0.3 6 v supply voltage differential 0.4 v note 1 rf input voltage 117 db v maximum voltage on sda, scl 5.5 v v cc = 0 to 5.5v max voltage on all remaining signal pins -0.3 v cc +0.3 v the voltage on any pin must not exceed 6 v to t a l p o r t c u r r e n t 2 0 m a storage temperature -55 150 o c junction temperature 125 o c power applied package thermal resistance (chip to ambient) 27 o c/w package paddle soldered to ground esd protection 2.0 kv all pins except 9,10 mil-std 883b method 3015 cat1 1.25 kv pins 9, 10 only characteristic min. max. units. conditions supply voltage 4.5 5.5 v functional operation, specification not guaranteed supply voltage (v ccrf and v ccif ) 4.75 5.25 v full specification supply voltage (v ccdig and v ccosc) 4.60 5.25 v ambient temperature -20 85 o c low band input frequency 50 170 mhz mid band input frequency 140 460 mhz high band input frequency 400 900 mhz data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 31
PS20063 7.0 electrical characteristics test conditions (unless otherwise stated). t = 25 o c, v ee = 0 v, v cc = 5 v, if frequency = 44 mhz. all signals are differential with the exception of vhf1 and vhf3 inputs. characteristic min. typ. max. units conditions supply current normal operation 160 195 ma total current ? uhf band all switching ports off all sections active 156 190 ma total current - vhf bands all switching ports off all sections active except agc if amplifier 135 ma uhf band. switching ports off 131 ma vhf bands. switching ports off sleep mode 9 ma crystal oscillator and data interface enabled 50 ma pll and crystal oscillator enabled composite system to saw filter driver outputs vhf1 band conversion gain 31 34 37 db rfin = 54 mhz. single ended input conversion gain 31 34 37 db rfin = 155 mhz. single ended input noise figure 12.5 14 db rs = 50 ? . opip3 135 146 db v two output tones at 110 db v output level causing 1% cross modulation 113 120 db vnote 2 output level causing 1.5 khz fm 113 120 db vnote 3 i 2 c bus transmission induced lo frequency modulation 2.5 khz transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 khz scl rate n+7 direct modulation of vco -40 dbc local oscillator sidebands induced by an input signal at 80 db v offset from local oscillator by 100 khz supply ripple spurious -40 dbc residual fm induced on local oscillator by 20 mv p-p ripple on v cc at 500 khz local oscillator leakage to any band input 45 db v ipip2 134 155 db v two input tones at 87 db v at 92 mhz and 66 mhz with local oscillator at 110 mhz data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 32
PS20063 ipip3 112 120 db v desired = 54 mhz at 41 db v undesired = 60 and 72 mhz at 87 db v ipip3 112 118 db v desired = 162 mhz at 41 db v undesired = 168 and 180 mhz at 87 db v p1db 93 106 db v output impedance 100 ? 10 nh phase noise, ssb pll loop bandwidth ~ 300 hz f comp = 62.5 khz 1khz -76 dbc/hz 10 khz -100 -86 dbc/hz 100 khz -115 -106 dbc/hz 10 mhz -135 dbc/hz noise floor reference spurs -90 -50 dbc phase noise, ssb pll loop bandwidth ~ 3khz f comp = 166.7 khz 1 khz -90 -70 dbc/hz 10 khz -95 -86 dbc/hz image rejection 23 36 db composite system to saw filter driver outputs vhf3 band conversion gain 31 34 37 db rfin = 164 mhz single ended input conversion gain 31 34 37 db rfin = 442 mhz single ended input noise figure 12.5 14 db rs = 50 ? opip3 135 146 db v two output tones at 110 db v output level causing 1% cross modulation 113 120 db vnote 2 output level causing 1.5 khz fm 113 120 db vnote 3 i 2 c bus transmission induced lo frequency modulation 2.5 khz transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 khz scl rate characteristic min. typ. max. units conditions data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 33
PS20063 n+7 direct modulation of vco -40 dbc local oscillator sidebands induced by an input signal at 80 db v offset from local oscillator by 100 khz. supply ripple spurious -40 dbc residual fm induced on local oscillator by 20 mv p-p ripple on v cc at 500 khz local oscillator leakage to any band input 45 db v ipip2 122 143 db v two input tones at 89 db v at 198 mhz and 390 mhz with local oscillator at 242 mhz ipip3 112 118 db v desired = 165 mhz at 45 db v undesired = 171 and 183 mhz at 89 db v ipip3 112 121 db v desired = 438 mhz at 45 db v undesired = 444 and 456 mhz at 89 db v p1db -95 107 db v output impedance 100 ? 10 nh phase noise, ssb pll loop bandwidth ~ 300 hz f comp = 62.5 khz 1khz -71 dbc/hz 10 khz -95 -86 dbc/hz 100 khz -115 -106 dbc/hz 10 mhz -135 dbc/hz noise floor reference spurs -82 -50 dbc phase noise, ssb pll loop bandwidth ~ 3khz f comp = 166.7 khz 1 khz -87 -70 dbc/hz 10 khz -92 -86 dbc/hz image rejection 23 38 db composite system to saw filter driver outputs uhf band conversion gain 31 34 37 db rfin = 450 mhz conversion gain 30 34 37.5 db rfin = 866 mhz noise figure 11 14 db rs = 50 ?, no image correction characteristic min. typ. max. units conditions data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 34
PS20063 opip3 135 146 db v two output tones at 110 db v output level causing 1% cross modulation 113 120 db vnote 2 output level causing 1.5 khz fm 113 120 db vnote 3 i 2 c bus transmission induced lo frequency modulation 2.5 khz transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 khz scl rate n+7 direct modulation of vco -30 dbc local oscillator sidebands induced by an input signal at 80 db v offset from local oscillator by 100 khz. wanted input signal = 750mhz supply ripple spurious -40 dbc residual fm induced on local oscillator by 20 mv p-p ripple on v cc at 500 khz local oscillator leakage to any band input 60 db v ipip2 125 159 db v two input tones at 89 db v at 438 mhz and 882 mhz with local oscillator at 486 mhz ipip3 114 120 db v desired = 438 mhz at 45 db v undesired = 444 and 456 mhz at 91 db v ipip3 114 121 db v desired = 858 mhz at 45 db v undesired = 864 and 876 mhz at 91 db v p1db 97 107 db v output impedance 100 ? 10 nh phase noise, ssb pll loop bandwidth ~ 300 hz f comp = 62.5 khz 1khz -67 dbc/hz 10 khz -92 -86 dbc/hz 100 khz -113 -106 dbc/hz 10 mhz -135 dbc/hz noise floor reference spurs -80 -50 dbc characteristic min. typ. max. units conditions data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 35
PS20063 phase noise, ssb pll loop bandwidth ~ 3khz f comp = 166.7 khz 1 khz -78 -70 dbc/hz 10 khz -89 -84 dbc/hz image rejection 23 37 dbc/hz agc detector and adc operating frequency range 16 72 mhz agc threshold level 120 db v at[2:0] = 0 adc leakage current 75 na v adc = 4.0 v -60 na v adc = 0.5v agc source current 6.8 10 13.3 a see table 15 0.25 0.35 0.45 a agc sink current -65 -100 -145 a agc attack current, triggered by detected level exceeding agc attack point agc sink current 90% rise and fall time 1 sec agc input level response 1 db change in input level for agc sink current to change from high impedance to 90% of maximum value, with agc operative agcop output impedance 20 m ? agc inactive agcop output voltage range 0.5 v minimum gain required 4 v maximum gain required external agc voltage 0.5 v cc - 0.4 v maximum external voltage range which can be applied to agcop when disabled agcop leakage current -50 50 n a over normal operating range adc step size, lsb 0.16 x v cc v see table 22 adc step size accuracy 0.01 x v cc v see table 22 agcout_flag high threshold v cc - 0.66 v agf flag set to 1 agcout_flag low threshold v cc - 0.76 agf flag set to 0 characteristic min. typ. max. units conditions data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 36
PS20063 if amplifier supply current 25 ma frequency range 16 72 mhz input impedance 1.5 2 2.8 k ? 1.5 pf gain (voltage conversion gain, differential source to maximum load) 60 66 db v ifagc = 3.0 v 17 22 db v ifagc = 0.5 v noise figure 6.3 8.5 rs=50 ? gain control range 41 48 db see figure 4 gain control slope 25 31 38 db/v 1.2 v agc 2.2 gain variation with temperature t = -20c to 85c -1 +1 db v agc = 1.2v and 2.2v gain slope variation with temperature t = -20c to 85c -1 +1 db/v v agc = 1.2v to 2.2v gain variation within channel 0.25 db channel bandwidth 8 mhz within operating frequency range, with maximum load as defined below opip3 130 141 db v two output tones at 109 db v within output channel gain range = 21 db to maximum agc input current 50 a output impedance 120 ? maximum load condition 4.7 k ? differential load 15 pf i 2 c bus sda scl input high voltage 2.55 5.5 v input low voltage 0 1.4 v input current high 10 av in =5.5 v, v cc =5.25 v 10 av in =5.5 v, v cc =0 v input current low -10 av in = 0 v, v cc =5.25 v hysteresis 0.4 v characteristic min. typ. max. units conditions data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 37
PS20063 note 1: 0 dbm =107 db v. all input levels are specified as voltage that would be present if input signal generator was terminated in 50 ohms note 2: wanted signal (picture carrier) = 101 dbmv at output. undesired signal (sound carrier) at 5.25 mhz offset modulated with 1 khz 80% am. increase undesired signal to give 1% am on wanted signal. note 3: wanted signal at 101 dbmv. unwanted signal at 5.25 mhz offset modulated with 1 khz 50% am. increase undesired signal to give 1.5 khz fm on wanted signal note 4: current into pump pin with 20 a current from drive pin sda output voltage 0.4 v i sink =3 ma 0.6 v i sink =6 ma scl clock rate 400 khz add (address) select see table 4 input high current 1 ma v in =v ccd input low current -0.5 ma v in =v ee pll synthesizer charge pump output current see table 8 v pump =2 v charge pump output leakage 3 10 na note 4 charge pump drive output current 0.5 ma v drive =0.7 v crystal frequency 4 16 mhz application as in figure 10 with 4 mhz crystal recommended crystal series esr 25 70 150 ? 4 mhz parallel resonant crystal external reference input frequency 4 20 mhz sine wave coupled through 10 nf capacitor external reference drive level 0.2 2 v pp sine wave coupled through 10nf capacitor 0.5 v pp recommended level for optimum phase noise at 4 mhz phase detector comparison frequency 31.25 250 khz rf division ratio 240 32767 switching ports gpp3-gpp0 sink current 10 ma v port = 0.4 pull up resistor gpp3- gpp1 10 k ? leakage current 10 av port = v cc, port p0 only characteristic min. typ. max. units conditions data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 38
PS20063 for further information about this and other products, please visit: www.plesseysemiconductors.com ? ? legal notice product information provided by plessey semiconductors limited ( ?plessey?) in this document is believed to be correct and a ccurate. plessey reserves the right to change/ correct the specifications and other data or information relating to products without notice but plessey accepts no liability for errors that may appear in th is document, howsoever occuring, or liabilit y arising from the use or application of any information or data provided herein. neither the supply of such information, nor t he purchase or use of products c onveys any licence or permission under patent, copyright, trademark or other intellectual property right of plessey or third parties. products sold by plessey are subject to its standard terms and conditions of sale that are av ailable on request. no warranty is given that products do not infringe the intellectual property rights of third parties, and furthermore, the use of products in certain wa ys or in combination with plessey, or non-plessey furnished equipments/components may infringe intellectual property rights of plessey. the purpose of this document is to provide information only and it may not be used, applied or reproduced (in whole or in part ) for any purpose nor be taken as a representation relating to the produc ts in question. no warranty or guarantee express or implied is made concerning the capability, performance or suitability of any product, and in formation concerning possible app lications or methods of use is provided for guidance only and not as a recommendation. the user is solely responsible for determining the performance and suitability of the product in any application and checking that any specification or data it seeks to rely on has not been superceded. products are intended for normal commercia l applications. for applicati ons requiring unusual environment al requirements, extend ed temperature range, or high reliability capability (eg military, or medical applications) , spec ial processing/testing/conditio ns of sale may be available on application to plessey. data sheet 291305 issue 1 plessey semiconductors ltd. design & technology centre, delta 500, delta business park, great western way, swindon, uk sn5 7xe tel: +44 1793 518000 fax: +44 1793 518030 web: www.plesseysemi.com 39

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