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| Datasheet File OCR Text: |
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c-mos dram address generator
-top view- CXD8840Q ( 1/3 )
il00 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
gnd 52
53
54
55
56
57
58
59
60
61
62
63
64
gnd
v dd(+5v) 32
31
30
29
28
27
26
25
24
23
22
21
20
v dd(+5v)
gnd 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
gnd 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 o
o
o
o
o
o
o
o
o
? o
o
o
i
i
o radd8
radd7
radd6
radd5
radd4
radd3
radd2
radd1
radd0
gnd
rrasn
rcasn
rsw
floe
vdn
f1n pin
no. i/o signal 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 o
i
i
i
i
i
i
i
? ? o
o
i
i
i
i f2n
ck3dly
ck3inv
ck3
invfld
absely
abselc
ck2
gnd
v dd
rowoe
pshdtw
rowtest
coltest
twtestw
twtestr pin
no. i/o signal 33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 o
o
o
o
o
o
o
o
o
? o
o
o
o
o
o wadd8
wadd7
wadd6
wadd5
wadd4
wadd3
wadd2
wadd1
wadd0
gnd
wras0
wras1
wras2
wras3
wras4
wcas0 pin
no. i/o signal 49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64 o
o
o
o
o
o
o
o
? ? i
i
i
i
i
i wcas1
wcas2
wcas3
wcas4
wsw
ck3o
abseloy
abseloc
gnd
v dd
ck1
wclrn
rclrn
hdn
pshdnr
pshdnc pin
no. i/o signal ( v dd = +5v )
CXD8840Q ( 2/3 ) 15 62 63 64 21 14 22 23 60 61 29 30 31 32 18 19 59 24 20 vdn hdn pshdnr pshdnc invfld floe absely abselc wclrn rclrn rowtest coltest twtestw twtestr ck3dly ck3inv ck1 ck2 ck3 radd8 radd7 radd6 radd5 radd4 radd3 radd2 radd1 radd0 wadd8 wadd7 wadd6 wadd5 wadd4 wadd3 wadd2 wadd1 wadd0 wras4 wras3 wras2 wras1 wras0 wcas4 wcas3 wcas2 wcas1 wcas0 rrasn rcasn wsw rsw f1n f2n abseloy abseloc rowoe pshdtw ck3o 1 2 3 4 5 6 7 8 9 33 34 35 36 37 38 39 40 41 47 46 45 44 43 52 51 50 49 48 11 12 53 13 16 17 55 56 27 28 54 input abselc absely ck1 ck2 ck3 ck3dly ck3inv coltest floe hdn invfld pshdnc pshdnr rclrn rowtest twtestr twtestw vdn wclrn output abseloc abseloy ck3o f1n f2n pshdtw radd0 - radd8 rcasw rowoe rrasn rsw wadd0 - wadd8 wcas0 - wcas4 wras0 - wras4 wsw ; absel for c-in ; absel for y-in ; 27.0 mh z / 28.6 mh z ; 13.5 mh z / 14.3 mh z ; ck3 in ; ck3 delay ; ck3 invert ; column add test ; field odd / even ; h-scan sync ; absel invert ; v-scan sync ; v-scan sync ; read add clear ; row add test ; read add test ; write add test ; field clear ; write add clear ; absel for c-out ; absel for y-out ; ck3 out ; field1-low ; field2-low ; pshdn odd / even ; read address ; read address-cas ; row-add odd / even ; read address-ras ; read add switching ; write address ; write address-cas ; write address-ras ; write add switchng wadd rowadd counter wadd coladd counter timing pulse gen radd rowadd counter 1/2 divider radd coladd counter timing pulse gen write address generation block read address generation block wclrn 60 hdn rst rst en pshdnc 64 rclrn 61 rst rst en co pshdnr 63 ck2 24 co en co 62 wras0 43 wras1 44 wras2 45 wras3 46 wras4 47 wcas0 48 wcas1 49 wcas2 50 wcas3 51 wcas4 52 wadd0-wadd8 33-41 9 rrasn rcasn 11 12 radd0-radd8 1-9 9 CXD8840Q ( 3/3 ) en co |
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