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november 2008 i ? 2008 actel corporation proasic ? 3 nano flash fpgas features and benefits wide range of features ? 10 k to 250 k system gates ? up to 36 kbits of true dual-port sram ? up to 71 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal (6 copper), flash-based cmos process ? live at power-up (lapu) level 0 support ? single-chip solution ? retains programmed design when powered off high performance ? 350 mhz system performance in-system programming (isp) and security ? secure isp using on-chip 128-bit advanced encryption standard (aes) decryption via jtag (ieee 1532?compliant) ? ?flashlock ? to secure fpga contents low power ? low-power proasic3 nano products ? 1.5 v core voltage for low power ? support for 1.5 v-only systems ? low-impedance flash switches high-performance routing hierarchy ? segmented, hierarchical routing and clock structure advanced i/os ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?up to 4 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v ? wide range power supply voltage support per jesd8-b, allowing i/os to operate from 2.7 v to 3.6 v ? i/o registers on input, output, and enable paths ? selectable schmitt trigger inputs ? hot-swappable and cold-sparing i/os ? programmable output slew rate ? and drive strength ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible packages across the proasic3 family clock conditioning circuit (ccc) and pll ? ? up to six ccc blocks, one with an integrated pll ? configurable phase shift, multiply/divide, delay capabilities and external feedback ? wide input frequency range (1.5 mhz to 350 mhz) embedded memory ? 1 kbit of flashrom user nonvolatile memory ? srams and fifos with variab le-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations) ? ? true dual-port sram (except 18 organization) ? enhanced commercial temperature range ? ?20c to +70c ? ? a3pn030 and smaller devices do not support this feature. proasic3 nano devices proasic3 nano devices a3pn010 a3pn015 a3pn020 a3pn030 1 a3pn060 a3pn125 a3pn250 system gates 10 k 15 k 20 k 30 k 60 k 125 k 250 k typical equivalent macrocells 86 128 172 256 512 1,024 2,048 versatiles (d-flip-flops) 260 384 520 768 1,536 3,072 6,144 ram kbits (1,024 bits) 2 ? ? ? ? 18 36 36 4,608-bit blocks 2 ? ? ? ? 488 flashrom bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k secure (aes) isp 2 ? ? ? ? yes yes yes integrated pll in cccs 2 ? ? ? ? 111 versanet globals 3 4 4 4 6 18 18 18 i/o banks 2 3 3 2 224 maximum user i/os 34 49 52 81 71 71 68 maximum user i/os (known good die) 34 ? 52 83 717168 package pins qfn vqfp qn48 qn68 qn68 qn48, qn68 vq100 qn100 vq100 qn100 vq100 qn100 vq100 notes: 1. a3pn030 is available in the z feature grade only and offers package compatibility with the lower density nano devices. refer to "proasic3 nano ordering information" on page iii . 2. a3pn030 and smaller devices do not support this feature. 3. six chip (main) and three quadrant global networks are available for a3pn060 and above. 4. for higher densities and support of additional featur es, refer to the proasic3 and proasic3e handbooks. advance v0.3
proasic3 nano flash fpgas ii advance v0.3 i/os per package proasic3 nano devices a3pn010 a3pn015 a3pn020 a3pn030 1 a3pn060 a3pn125 a3pn250 known good die 34 ? 52 83 71 71 68 qn48 34 34 qn68 49 49 49 qn100 71 71 68 vq100 77 71 71 68 notes: 1. a3pn030 is available in the z feature grade only and offers package compatibility with the lower density nano devices. refer to "proasic3 nano ordering information" on page iii . 2. when considering migrating your design to a lower- or higher -density device, refer to the proasic3 handbook to ensure compliance with design and board migration requirements. 3. "g" indicates rohs-compliant packages. refer to "proasic3 nano ordering information" on page iii for the location of the "g" in the part number. for nano devices, the vq100 package is offere d in both leaded and rohs-compliant versions. all other packages are rohs-compliant only. proasic3 nano fpgas package sizes dimensions packages qn48 qn68 qn100 vq100 length width (mm\mm) 6 x 6 8 x 8 8 x 8 14 x 14 nominal area (mm 2 ) 36 64 64 196 pitch (mm) 0.40.40.50.5 height (mm) 0.90 0.90 0.85 1.20
proasic3 nano flash fpgas advance v0.3 iii proasic3 nano ordering information proasic3 nano product available in the z feature grade notes: 1. the dc and switching characte ristics for the ?f speed grade targets are ba sed only on simulation . the characteristics provided for the ?f speed grad e are subject to change after establishing fpga specifications. some restrictions might be added and will be reflected in future revisions of this docu ment. the ?f speed grade is su pported only in the commercial temperature range. 2. for the a3pn060, a3pn125, and a3pn250, the z feature grade do es not support the enhanced nano features of schmitt trigger input, cold-spari ng, and hot-swap i/o capability. the a3pn030 z feature grade does not support schmitt trigger input. for the vq100, cs81, uc81, qn68, and qn48 packages, the z feature grade and the n part number are not marked on the device. devices a3pn030 a3pn060 a3pn125 a3pn250 packages qn48 ? ? ? qn68 ? ? ? ? qn100 qn100 ? vq100 vq100 vq100 vq100 a3pn010 = 10,000 s ystem g ates a3pn015 = 15,000 s ystem g ates a3pn020 = 20,000 s ystem g ates a3pn030 = 30,000 s ystem g ates a3pn0 6 0 = 6 0,000 s ystem g ates a3pn125 = 125,000 s ystem g ates a3pn250 = 250,000 s ystem g ates s pee d g ra d e blank = s tan d ar d blank = s tan d ar d f = 20% s lower than s tan d ar d feature g ra d e z = nano d evi c es without enhan c e d features a3pn250 z 1 vq _ part num b er proa s ic3 nano devi c e s pa c ka g e type vq = very thin qua d flat pa c k (0.5 mm pit c h) dielot = known g oo d die qn = qua d flat pa c k no lea d s (0.4 mm an d 0.5 mm pit c hes) 100 i pa c ka g e lea d c ount g lea d -free pa c ka g in g appli c ation (temperature ran g e) blank = c ommer c ial ( ? 20 c to +70 c am b ient temperature) i= in d ustrial ( ? 40 c to +85 c am b ient temperature) blank = s tan d ar d pa c ka g in g g = roh s - c ompliant pa c ka g in g pp = pre-pro d u c tion e s =en g ineerin g s ample (room temperature only) 2 1 1 = 15% faster than s tan d ar d 2 = 25% faster than s tan d ar d
proasic3 nano flash fpgas iv advance v0.3 temperature grade offerings speed grade and temperature grade matrix contact your local actel represen tative for device availability: http://www.actel.com/contact/default.aspx . proasic3 nano devices a3pn010 a3pn015 a3pn020 a3pn030 a3pn060 a3pn125 a3pn250 qn48 c, i ? ? c, i ? ? ? qn68 ? c, i c, i c, i ? ? ? qn100 ? ? ? ? c, i c, i c, i vq100 ? ? ? c, i c, i c, i c, i notes: 1. c = commercial temperature range: ?20c to 70c ambient temperature 2. i = industrial temperature range: ?40c to 85c ambient temperature temperature grade ?f 1 std. c 2 ?? i 3 ? ? notes: 1. the characteristics provided for the ?f speed grade are subject to change afte r establishing fpga specifications. some restrictions might be added and will be reflected in future revisions of this document. the ?f speed grade is supported only in the commercial temperature range. 2. c = commercial temperature range: ?20c to 70c ambi ent temperature. 3. i = industrial temperature range: ?40c to 85c ambient temperature.
advance v0.3 1-1 1 ? proasic3 nano device overview general description proasic3, the third-generation family of acte l flash fpgas, offers performance, density, and features beyond those of the proasic plus ? family. nonvolatile flash technology gives proasic3 nano devices the advantage of being a secure, low-power, single-chip solution that is live at power- up (lapu). proasic3 nano devices are reprogra mmable and offer time-to-market benefits at an asic-level unit cost. these features enable design ers to create high-density systems using existing asic or fpga design flows and tools. proasic3 nano devices offer 1 kb it of on-chip, reprogrammable, nonvolatile flashrom storage as well as clock conditioning circuitry based on an integrated phase-locked loop (pll). a3pn030 and smaller devices do not have pll or ram support. proasic3 nano devices have up to 250,000 system gates, supported with up to 36 kbits of tr ue dual-port sram and up to 71 user i/os. proasic3 nano devices increase th e breadth of the proasic3 product line by adding new features and packages for greater custome r value in high volume consum er, portable, and battery-backed markets. added features include sma ller footprint packages designed with two- layer pcbs in mind, low power, hot-swap capability, and schmitt trigger for greater fl exibility in low-cost and power- sensitive applications. flash advantages reduced cost of ownership advantages to the designer extend beyond lo w unit cost, performance, and ease of use. unlike sram-based fpgas, flash-based proa sic3 nano devices allow all functionality to be live at power- up; no external boot pr om is required. on-board security mechanisms prevent access to all the programming information an d enable secure remote updates of the fpga logic. designers can perform secure remote in-system reprogramming to supp ort future design iterations and field upgrades with confidence that valuable intellectual property (ip) cannot be compromised or copied. secure isp can be performed using the industry-standard aes algorithm. the proasic3 nano device architecture mitigate s the need for asic migration at higher user volumes. this makes the proasic3 nano device a cost-effective asic re placement solution, especially for applications in the consumer, networking/communication s, computing, and avionics markets. with a variety of devices un der $1, actel proasic3 nano fpgas enable cost-effective implementation of programmable l ogic and quick time to market. security nonvolatile, flash-based proasic3 nano devices do not require a boot prom, so there is no vulnerable external bitstream that can be ea sily copied. proasic3 nano devices incorporate flashlock, which provides a unique combination of reprogrammability and de sign security without external overhead, advantages th at only an fpga with nonvolatile flash programming can offer. proasic3 nano devices utilize a 128-bit flash- based lock and a separate aes key to secure programmed intellectual property and configur ation data. in addition, all flashrom data in proasic3 nano devices can be encrypted prior to loading, using the industry-leading aes-128 (fips192) bit block cipher encryption standard . the aes standard was adopted by the national institute of standards and technology (nist) in 2000 and replaces the 1977 des standard. proasic3 nano devices have a built-in ae s decryption engine and a flash-based aes key that make them the most comprehensive programmable lo gic device security solution available today. proasic3 nano devices with aes-based security allow for secure, re mote field updates over public networks such as the internet, and ensure that valuable ip remain s out of the hands of system overbuilders, system cloners, and ip thieves. the contents of a programmed proasic3 nano device cannot be read back, although secure design verificati on is possible.
proasic3 nano device overview 1-2 advance v0.3 security, built into the fpga fabric, is an inhere nt component of proasic3 nano devices. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely diff icult. proasic3 nano devices, with flashlock and aes security, are unique in being highly resistan t to both invasive and noninvasive attacks. your valuable ip is protected and secure, making remo te isp possible. a proasi c3 nano device provides the most impenetrable security for programmable logic designs. single chip flash-based fpgas store their configuration information in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga structure, and no external configuration data needs to be loaded at system power-up (u nlike sram-based fpgas). therefore, flash-based proasic3 nano fpgas do not require system configuration components such as eeproms or microcontrollers to load device configuration da ta. this reduces bill-of-materials costs and pcb area, and increases securi ty and system reliability. live at power-up actel flash-based proasic3 nano devices support le vel 0 of the lapu classification standard. this feature helps in system component initialization, executio n of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock genera tion, and bus activity management. the lapu feature of flash-based pr oasic3 nano devices greatly simplifies total system design and reduces total system cost, of ten eliminating the need for cplds and clock generation plls that are used for these purposes in a system. in addition, glitches and brownouts in system power will not corrupt the proasic3 nano device's flash configuration, and unlike sram- based fpgas, the device will not have to be reload ed when system power is restored. this enables the reduction or complete re moval of the configuration prom, expensive voltage monitor, brownout detection, and clock generator devices from the pcb design. fl ash-based proasic3 nano devices simplify total system de sign and reduce cost and design risk while increasing system reliability and improving system initialization time. firm errors firm errors occur most commonly when high-energ y neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energy of the coll ision can change the state of the configuration cell and thus change the logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prev ent in sram fpgas. the consequenc e of this type of error can be a complete system failure. firm errors do not ex ist in the configuration memory of proasic3 nano flash-based fpgas. once it is programmed, the fl ash cell configuration element of proasic3 nano fpgas cannot be altered by high -energy neutrons and is therefor e immune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. low power flash-based proasic3 nano devices exhibit power ch aracteristics similar to an asic, making them an ideal choice for power-sensitive applications. proasic3 nano devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many fpgas. proasic3 nano devices also have low dynamic power consumption to fu rther maximize power savings.
proasic3 nano device overview advance v0.3 1-3 advanced flash technology proasic3 nano devices offer many benefits, incl uding nonvolatility and re programmability through an advanced flash-based, 130-nm lvcmos proces s with seven layers of metal. standard cmos design techniques are used to implement logic and control functions. the combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromi sing device routability or perf ormance. logic functions within the device are interconnected thro ugh a four-level routing hierarchy. advanced architecture the proprietary proasic3 nano architecture prov ides granularity comparable to standard-cell asics. the proasic3 nano device consists of five distinct and programmabl e architectural features ( figure 1-3 to figure 1-4 on page 1-5 ): ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory ? extensive cccs and plls ? advanced i/o structure note: *bank 0 for the a3pn030 device figure 1-1 ? proasic3 device architecture overvi ew with two i/o banks and no ram (a3pn010 and a3pn030) versatile i/os user nonvolatile flashrom charge pumps bank 1* bank 1 bank 0 bank 1 ccc-gl
proasic3 nano device overview 1-4 advance v0.3 figure 1-2 ? proasic3 nano architecture o verview with three i/o banks an d no ram (a3pn015 and a3pn020) . figure 1-3 ? proasic3 nano device architecture overview with two i/o banks (a3pn060 and a3pn125) versatile i/os user nonvolatile flashrom charge pumps bank 1 bank 2 bank 0 bank 1 ccc-gl ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1
proasic3 nano device overview advance v0.3 1-5 the fpga core consists of a sea of versatiles. ea ch versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. the ve rsatility of the proasic3 nano co re tile as eith er a three-input lookup table (lut) equivalent or as a d-flip-flop /latch with enable allows for efficient use of the fpga fabric. the versatile capability is unique to the actel proasic3 fami ly of third-generation architecture flash fpgas. versatiles are connected wi th any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming . maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circ uitry allows for rapid, single-voltage (3.3 v) programming of proasic3 nano device s via an ieee 1532 jtag interface. versatiles the proasic3 nano core consists of versatiles, which have been enhanced beyond the proasic plus ? core tiles. the proasic3 nano versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-5 for versatile configurations. figure 1-4 ? proasic3 nano device arch itecture overview with four i/o banks (a3pn250) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 figure 1-5 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
proasic3 nano device overview 1-6 advance v0.3 user nonvolatile flashrom actel proasic3 nano devices have 1 kbit of on-c hip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business mode ls (for example, set-top boxes) ? secure key storage for secu re communicati ons algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using th e standard proasic3 nano ieee 1532 jtag programming interface. the core can be individually pr ogrammed (erased and written), an d on-chip aes decryption can be used selectively to securely load data over p ublic networks (except in the a3pn030 and smaller devices), as in security keys stored in the flashrom fo r a user design. the flashrom can be programmed via the jtag pr ogramming interf ace, and its contents can be read back either throug h the jtag programming interface or vi a direct fpga core addressing. note that the flashrom can only be programmed fro m the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bi ts; however, reading is performed on a byte-by- byte basis using a synchronous interface. a 7-bit address from the fpga core defines which of the 8 banks and which of the 16 bytes within that ba nk are being read. the th ree most sign ificant bits (msbs) of the flashrom address determine the bank , and the four least sign ificant bits (lsbs) of the flashrom address define the byte. the actel proasic3 nano developm ent software solutions, libero ? integrated design environment (ide) and designer, have extensive support for th e flashrom. one such feature is auto-generation of sequential programmin g files for applicat ions requiring a unique se rial number in each part. another feature enables the inclus ion of static data for system version control. data for the flashrom can be generated quickl y and easily using actel libero ide and designer software tools. comprehensive programming file su pport is also included to allo w for easy programming of large numbers of parts with di ffering flashrom contents. sram and fifo proasic3 nano devices (except the a3pn030 and smaller devices) have embedded sram blocks along their north and south sides. each variable-aspect-ratio sram block is 4,608 bits in size. available memory configurations are 25618, 512 9, 1k4, 2k2, and 4k1 bits. the individual blocks have independent read and write ports that can be configured with different bit widths on each port. for example, data can be sent through a 4-bit port and read as a single bitstream. the embedded sram blocks can be initialized via th e device jtag port (rom emulation mode) using the ujtag macro (except in a3pn030 and smaller devices). in addition, every sram block has an embedded fifo control unit. the control unit allows the sram block to be configured as a synchronous fi fo without using additional core versatiles. the fifo width and depth are programmable. the fifo also features programmable almost empty (aempty) and almost full (afull) flags in additi on to the normal empt y and full flags. the embedded fifo control unit cont ains the counters necessary for ge neration of the read and write address pointers. the embedded sram /fifo blocks can be cascaded to create larger configurations. pll and ccc higher density proasic3 nano devi ces using either the two i/o bank or four i/o bank architectures provide the designer with very flexible clock conditioning capabilities. a3pn060, a3pn125, and a3pn250 contain six cccs. one ccc (center west si de) has a pll. the a3pn030 and smaller devices use different cccs in their arch itecture. these ccc-gls contain a global mux but do not have any plls or progra mmable delays. for devices using the six ccc block architecture, these six ccc blocks are located at the four corners and the centers of the east and west sides.
proasic3 nano device overview advance v0.3 1-7 all six ccc blocks are usable; the four corner cccs and the east ccc allow simple clock delay operations as well as clock spine access. the in puts of the six ccc blocks are accessible from the fpga core or from dedicated conn ections to the ccc block, which are located near the ccc. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz to 350 mhz ? output frequency range (f out_ccc ) = 0.75 mhz to 350 mhz ? clock delay adjustment via programmable and fixed delays from ?7.56 ns to +11.12 ns ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270 . output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50 % 1.5 % or better (for pll only) ? low output jitter: worst case < 2.5 % clock period peak-to-peak period jitter when single global network used (for pll only) ? maximum acquisition time = 300 s (for pll only) ? low power consumption of 5 mw ? exceptional tolerance to input period jitter?allowable input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment betw een adjacent phases of 40 ps (350 mhz / f out_ccc ) (for pll only) global clocking proasic3 nano devices have exte nsive support for multiple clocki ng domains. in ad dition to the ccc and pll support described above, there is a comprehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the ve rsanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-s kew clock signals or for rapid distribution of high fanout nets. i/os with advanced i/o standards proasic3 nano fpgas feature a flex ible i/o structure, supporting a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). the i/os are organized into banks, with two, thr ee, or four banks per device. the configuration of these banks determines the i/o standards supported. each i/o module contains several input, output , and enable registers. these registers allow the implementation of various single -data-rate applications for all versions of nano devices and double-data-rate applicatio ns for the a3pn060, a3pn125, and a3pn250 devices. proasic3 nano devices support lvttl and lvcmos i/o standards, are hot-swappable, and support cold-sparing and schmitt trigger. wide range i/o support actel nano devices support jedec-defined wide range i/o operation. proasic nano supports the jesd8-b specification, covering both 3 v and 3.3 v supplies, for an effective operating range of 2.7 v to 3.6 v. wider i/o range means designers can eliminate po wer supplies or power co nditioning components from the board or move to less costly components with greater tolerances. wide range eases i/o bank management and provides enhanced protecti on from system voltage spikes, while providing the flexibility to easily ru n custom voltage applications.
proasic3 nano device overview 1-8 advance v0.3 part number and revision date part number 51700111-001-2 revised november 2008 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in curr ent version (advance v0.3) page advance v0.2 (october 2008) the a3pn030 device was added to produc t tables and replaces a3p030 entries that were formerly in the tables. i to iv the "wide range i/o support" section is new. 1-7 advance v0.1 (october 2008) the "i/os per package" table was updated to add the following information to table note 4: "for nano de vices, the vq100 package is offered in both leaded and rohs-compliant versions. all other packages are rohs-compliant only." ii the "proasic3 nano product available in the z feature grade" section was updated to remove qn100 for a3pn250. iii the "general description" section was updated to give co rrect information about number of gates and dual-port ram for proasic3 nano devices. 1-1 the device archit ecture figures, figure 1-3 proasic3 nano device architecture overview with two i/o banks (a3pn060 and a3pn125) through figure 1-4 proasic3 nano device architec ture overview with four i/o banks (a3pn250) , were revised. figure 1-1 proasic3 device architecture overview with two i/o banks and no ram (a3pn010 and a3pn030) is new. 1-3 through 1-5 the "pll and ccc" section was revised to include in formation about ccc-gls in a3pn020 and smaller devices. 1-6
proasic3 nano device overview advance v0.3 1-9 datasheet categories categories in order to provide the latest information to desi gners, some datasheets are published before data has been fully characterized. datasheets are designated as "product brief," "advance," "preliminary," and "production." the definiti on of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advance or production) and contains general product information. this document give s an overview of specific device and family information. advance this version contains initial estimated information based on simulation, ot her products, devices, or speed grades. this information can be used as estimates, but not for production. this label only applies to the dc and switching characteristics chapte r of the datasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on si mulation and/or initia l characterization. the information is believed to be co rrect, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this do cument are subject to the expo rt administration regulations (ear). they could require an ap proved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status document may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information.

advance v0.2 2-1 2 ? proasic3 nano dc and switching characteristics general specifications the z feature grade does not support the enhanced nano features of schmitt trigger input, cold- sparing, and hot-swap i/o capability. re fer to the ordering information in the proasic3 nano product brief for more information. dc and switching characteristic s for ?f speed grade targets ar e based only on simulation. the characteristics provided for the ?f speed grad e are subject to change after establishing fpga specifications. some restri ctions might be added and will be re flected in future revisions of this document. the ?f speed grade is only suppo rted in the commercial temperature range. operating conditions stresses beyond those listed in table 2-1 may cause permanent damage to the device. exposure to absolute maximum rati ng conditions for extended period s may affect device reliability. absolute maximum ratings are stress ratings only; fu nctional operation of the device at these or any other conditions beyond those listed unde r the recommended operat ing conditions specified in table 2-2 on page 2-2 is not implied. table 2-1 ? absolute maxi mum ratings symbol parameter limits units v cc dc core supply vo ltage ?0.3 to 1.65 v v jtag jtag dc voltage ?0.3 to 3.75 v v pump programming voltage ?0.3 to 3.75 v v ccpll analog power supply (pll) ?0.3 to 1.65 v v cci dc i/o output buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v v t stg 1 storage temperature ?65 to +150 c t j 1 junction temperature +125 c notes: 1. for flash programming and rete ntion maximum limits, refer to table 2-3 on page 2-2 , and for recommended operatin g limits, refer to table 2-2 on page 2-2 . 2. the device should be operated with in the limits specified by the datash eet. during transi tions, the input signal may undershoot or overshoot according to the limits shown in table 2-4 on page 2-3 .
proasic3 nano dc and switching characteristics 2-2 advance v0.2 table 2-2 ? recommended operating conditions 1, 2 symbol parameter extended commercial industrial units t a ambient temperature ?20 to +70 2 ?40 to +85 2 c t j junction temperature ?20 to +85 ?40 to +100 c v cc 3 1.5 v dc core supply voltage 1.425 to 1.575 1.425 to 1.575 v v jtag jtag dc voltage 1.425 to 3.6 1.425 to 3.6 v v pump 4 programming voltage programmi ng mode 0 to 3.45 0 to 3.45 v operation 4 0 to 3.6 0 to 3.6 v v ccpll 5 analog power supply (pll) 1.5 v dc core supply voltage 3 1.425 to 1.575 1.425 to 1.575 v v cci and vmv 7 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v 3.3 v wide range supply voltage 6 2.7 to 3.6 2.7 to 3.6 v notes: 1. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 2. to ensure targeted reliability sta ndards are met across ambient and ju nction operating temperatures, actel recommends that the user follow best design practices using actel?s ti ming and power simulation tools. 3. the ranges given here are for power supplies only. th e recommended input voltage ranges specific to each i/o standard are given in table 2-14 on page 2-15 . vmv and v cci should be at the same voltage within a given i/o bank. 4. v pump can be left floating during operation (not programming mode). 5. v ccpll pins should be tied to v cc pins. see pin descriptions for further information. 6. 3.3 v wide range is compliant to the jesd8-b specification and supports 3.0 v v cci operation. 7. vmv pins must be connected to the corresponding v cci pins. see pin descriptions for further information. table 2-3 ? flash programming limits ? retention, storage and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operating junction temperature t j (c) 2 commercial 500 20 years 110 100 industrial 500 20 years 110 100 notes: 1. this is a stress rating only; functional operation at any condition other than t hose indicated is not implied. 2. these limits apply for program/ data retention only. refer to table 2-1 on page 2-1 and table 2-2 for device operating conditions and absolute limits.
proasic3 nano dc and switching characteristics advance v0.2 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circ uitry is designed into every proasic ? 3 device. these circuits ensure eas y transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any se quence with minimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-4 . there are five regions to consider during power-up. proasic3 i/os are activated only if all of the following thre e conditions are met: 1. v cc and v cci are above the minimum specified trip points ( figure 2-1 on page 2-4 ). 2. v cci > v cc ? 0.75 v (typical) 3. chip is in the operating mode. v cci trip point: ramping up: 0.6 v < tr ip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v v cc trip point: ramping up: 0.6 v < tr ip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v v cc and v cci ramp-up trip points are about 100 mv hi gher than ramp-dow n trip points. this specifically built-in hysteresis pr events undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tri stated and weakly pulled up to v cci . ? jtag supply, pll power supplies, and charge pump v pump supply have no influence on i/o behavior. pll behavior at br ownout condition actel recommends using monotonic power supplies or voltage regula tors to ensure proper power- up behavior. power ramp-up should be monotonic at least until v cc and v ccpllx exceed brownout activation levels. the v cc activation level is specified as 1.1 v worst-case (see figure 2-1 on page 2-4 for more details). when pll power supply voltage and/or v cc levels drop below the v cc brownout levels (0.75 v 0.25 v), the pll output lock sign al goes low and/or the output clock is lost. refer to the power-up/-down behavior of low-power flash devices chapter of the handbo ok for information on clock and lock recovery. table 2-4 ? overshoot and undershoot limits 1 v cci and vmv average v cci ?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10 % 1.4 v 5 % 1.49 v 3 v 10 % 1.1 v 5 % 1.19 v 3.3 v 10 % 0.79 v 5 % 0.88 v 3.6 v 10 % 0.45 v 5 % 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of six clock cycles. if the ove rshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undersho ot has to be reduced by 0.15 v.
proasic3 nano dc and switching characteristics 2-4 advance v0.2 internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns de lay from input buffer activation figure 2-1 ? i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification. v cc = v cci + vt
proasic3 nano dc and switching characteristics advance v0.2 2-5 thermal characteristics introduction the temperature variable in the actel designer software refers to the junction temperature, not the ambient temperature. this is an important distinction be cause dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. eq 2-1 can be used to calculate junction temperature. t j = junction temperature = t + t a eq 2-1 where: t a = ambient temperature t = temperature gradient between junction (silicon) and ambient t = ja * p ja = junction-to-ambient of the package. ja numbers are located in table 2-5 . p = power dissipation package thermal characteristics the device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja . the thermal characteristics for ja are shown for two air flow rates. the absolute maximum junction temperature is 100c. eq 2-2 shows a sample calculation of the absolute maximum power dissipation allo wed for a 484-pin fbga package at commercial temperature and in still air. eq 2-2 temperature and voltage derating factors maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -------- 100 c70 c ? 20.5 c/w ------------------------------------ 1 . 4 6 3 w = = = table 2-5 ? package thermal resistivities package type device pin count jc ja units still air 200 ft./min. 500 ft./min. quad flat no lead (qfn) a ll devices 48 tbd tbd tbd tbd c/w 68 tbd tbd tbd tbd c/w 100 tbd tbd tbd tbd c/w very thin quad flat pack (vqf p) all devices 100 10.0 35.3 29.4 27.1 c/w table 2-6 ? temperature and voltage derating factors for timing delays (normalized to t j = 70c, v cc = 1.425 v) array voltage v cc (v) junction temperature (c) ?40c ?20c 0c 25c 70c 85c 110c 1.425 0.968 0.973 0.979 0.991 1.000 1.006 1.013 1.500 0.888 0.894 0.899 0.910 0.919 0.924 0.930 1.575 0.836 0.841 0.845 0.856 0.864 0.870 0.875
proasic3 nano dc and switching characteristics 2-6 advance v0.2 calculating power dissipation quiescent supply current power per i/o pin table 2-7 ? quiescent supply current characteristics a3pn010 a3pn015 a3pn020 a3pn060 a3pn125 a3pn250 typical (25c) 1 ma 1 ma 1 ma 2 ma 2 ma 3 ma max. (commercial) 5 ma 5 ma 5 ma 10 ma 10 ma 20 ma max. (industrial) 8 ma 8 ma 8 ma 15 ma 15 ma 30 ma notes: 1. i dd includes v cc , v pump , and v cci , currents. values do not include i/o static contribution, which is shown in table 2-9 . 2. ?f speed grade devices may ex perience higher standby i dd of up to five ti mes the standard i dd and higher i/o leakage. table 2-8 ? summary of i/o input buffer power (per pin) ? default i/o software settings v cci (v) dynamic power p ac9 (w/mhz) * single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 16.26 3.3 v lvttl / 3.3 v lvcmos ? schmitt trigger 3.3 18.95 2.5 v lvcmos 2.5 4.59 2.5 v lvcmos ? schmitt trigger 2.5 6.01 1.8 v lvcmos 1.8 1.61 1.8 v lvcmos ? schmitt trigger 1.8 1.70 1.5 v lvcmos (jesd8-11) 1.5 0.96 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 0.90 note: *p ac9 is the total dynamic power measured on v cci . table 2-9 ? summary of i/o output buffer power (p er pin) ? default i/o software settings 1 c load (pf) 2 v cci (v) dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 10 3.3 162.43 2.5 v lvcmos 10 2.5 92.49 1.8 v lvcmos 10 1.8 47.48 1.5 v lvcmos (jesd8-11) 10 1.5 32.75 notes: 1. dynamic power consumption is given for standa rd load and software default drive strength and output slew. 2. values are for a3pn020, a3pn015, and a3pn 010. a3pn060, a3pn125, and a3pn250 have a default loading of 35 pf. 3. p ac10 is the total dynamic power measured on v cci .
proasic3 nano dc and switching characteristics advance v0.2 2-7 power consumption of vari ous internal resources table 2-10 ? different components contributing to dynamic power consumption in proasic3 nano devices parameter definition device specific dy namic contributions (w/mhz) a3pn250 a3pn125 a3pn060 a3pn020 a3pn015 a3pn010 p ac1 clock contribution of a glob al rib 11.03 11.03 9.3 tbd tbd tbd p ac2 clock contribution of a global spine 1.58 0.81 0.81 tbd tbd tbd p ac3 clock contribution of a versatile row 0.81 p ac4 clock contribution of a versatile used as a sequential module 0.12 p ac5 first contribution of a versatile used as a sequential module 0.07 p ac6 second contribution of a versatile used as a sequential module 0.29 p ac7 contribution of a versatile used as a combinatorial module 0.29 p ac8 average contribution of a routing net 0.70 p ac9 contribution of an i/o input pin (standard-dependent) see table 2-8 on page 2-6 . p ac10 contribution of an i/o output pin (standard-dependent) see table 2-9 on page 2-6 . p ac11 average contribution of a ram block during a read operation 25.00 n/a p ac12 average contribution of a ram block during a write operation 30.00 n/a p ac13 dynamic contribution for pll 2.60 n/a note: *for a different output load, drive strength, or slew rate, actel recommends using the actel power spreadsheet calculator or smartpower tool in libero ? integrated design environment (ide) software. table 2-11 ? different components contributing to the static power consumption in pr oasic3 nano devices parameter definition device specific static power (mw) a3pn250 a3pn125 a3pn060 a3pn020 a3pn015 a3pn010 p dc1 array static power in active mode see table 2-7 on page 2-6 . p dc4 static pll contribution 1 2.55 n/a p dc5 bank quiescent power (v cci -dependent) see table 2-7 on page 2-6 . notes: 1. minimum contribution of the pll when running at lowest frequency. 2. for a different output load, drive strength, or slew rate, actel recommen ds using the actel power spreadsheet calculator or smar tpower tool in libero ide.
proasic3 nano dc and switching characteristics 2-8 advance v0.2 power calculation methodology this section describes a simplified method to estimate power consumptio n of an application. for more accurate and deta iled power estima tions, use the smartpower tool in actel libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number and the frequency of each output clock generated ? the number of combinatorial and se quential cells used in the design ?the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-12 on page 2-10 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-13 on page 2-10 . ? read rate and write rate to the memory?guide lines are provided for typical applications in table 2-13 on page 2-10 . the calculation should be repeat ed for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = p dc1 + n inputs * p dc2 + n outputs * p dc3 n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (p ac1 + n spine *p ac2 + n row *p ac3 + n s-cell * p ac4 ) * f clk n spine is the number of global spines used in the user design?guidelines are provided in table 2-12 on page 2-10 . n row is the number of versatile rows used in the design?guidelines are provided in table 2-12 on page 2-10 . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. p ac1 , p ac2 , p ac3 , and p ac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (p ac5 + 1 / 2 * p ac6 ) * f clk n s-cell is the number of versatiles used as sequen tial modules in the de sign. when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-12 on page 2-10 . f clk is the global clock signal frequency.
proasic3 nano dc and switching characteristics advance v0.2 2-9 combinatorial cells contribution?p c-cell p c-cell = n c-cell * 1 / 2 * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-12 on page 2-10 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * 1 / 2 * p ac8 * f clk n s-cell is the number of versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-12 on page 2-10 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * 2 / 2 * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle ra te?guidelines are provided in table 2-12 on page 2-10 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * 2 / 2 * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle ra te?guidelines are provided in table 2-12 on page 2-10 . 1 is the i/o buffer enable rate?guidelines are provided in table 2-13 on page 2-10 . f clk is the global clock signal frequency. ram contribution?p memory p memory = p ac11 * n blocks * f read-clock * 2 + p ac12 * n block * f write-clock * 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory r ead clock frequency. 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. 3 is the ram enable rate for write op erations?guidelines are provided in table 2-13 on page 2-10 . pll contribution?p pll p pll = p dc4 + p ac13 *f clkout f clkout is the output clock frequency. 1 1. the pll dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the pll, and the frequency of each output clock. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution.
proasic3 nano dc and switching characteristics 2-10 advance v0.2 guidelines toggle rate definition a toggle rate defines the frequency of a net or logi c element relative to a clock. it is a percentage. if the toggle rate of a net is 100 % , this means that this net switch es at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100 % because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25 % : ? bit 0 (lsb) = 100 % ? bit 1 = 50 % ? bit 2 = 25 % ?? ? bit 7 (msb) = 0.78125 % ? average toggle rate = (100 % + 50 % + 25 % + 12.5 % + . . . + 0.78125 % ) / 8 enable rate definition output enable rate is the average percentage of time during which tris tate outputs are enabled. when nontristate output buffers are us ed, the enable rate should be 100 % . table 2-12 ? toggle rate guidelines reco mmended for power calculation component definition guideline 1 toggle rate of versatile outputs 10 % 2 i/o buffer toggle rate 10 % table 2-13 ? enable rate guidelines reco mmended for power calculation component definition guideline 1 i/o output buffer enable rate 100 % 2 ram enable rate for read operations 12.5 % 3 ram enable rate for write operations 12.5 %
proasic3 nano dc and switching characteristics advance v0.2 2-11 user i/o characteristics timing model figure 2-2 ? timing model operating conditions: ?2 speed, commercial temperature range (t j = 70c), worst case v cc = 1.425 v, with default loading at 10 pf dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvcmos 2.5v output drive strength = 8 ma high slew rate input lvcmos 2.5 v lvcmos 1.5 v lvttl 3.3 v output drive strength = 8 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 2 ma high slew rate lvttl output drive strength = 4 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 0.56 ns t pd = 0.49 ns t dp = 2.25 ns t pd = 0.87 ns t dp = 2.87 ns t pd = 0.51 ns t dp = 2.21 ns t pd = 0.47 ns t dp = 3.02 ns t pd = 0.47 ns t py = 0.84 ns t clkq = 0.55 ns t oclkq = 0.59 ns t sud = 0.43 ns t osud = 0.31 ns t dp = 2.21 ns t py = 0.84 ns t py = 1.14 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 0.84 ns t iclkq = 0.24 ns t isud = 0.26 ns t py = 1.04 ns
proasic3 nano dc and switching characteristics 2-12 advance v0.2 figure 2-3 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50 % 50 % v ih v cc v il t dout (r) din gnd t dout (f) 50 % 50 % v cc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
proasic3 nano dc and switching characteristics advance v0.2 2-13 figure 2-4 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) v trip v trip v oh v cc d 50 % 50 % v cc 0 v dout 50 % 50 % 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
proasic3 nano dc and switching characteristics 2-14 advance v0.2 figure 2-5 ? tristate output buffer timing model and delays (example) d clk q d clk q 10 % v cci t zl v trip 50 % t hz 90 % v cci t zh v trip 50 % 50 % t lz 50 % eout pad d e 50 % t eout (r) 50 % t eout (f) pad dout eout d i/o interface e t eout t zls v trip 50 % t zhs v trip 50 % eout pad d e 50 % 50 % t eout (r) t eout (f) 50 % v cc v cc v cc v cci v cc v cc v cc v oh v ol v ol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
proasic3 nano dc and switching characteristics advance v0.2 2-15 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-14 ? summary of maximum and minimu m dc input and output levels applicable to commercial and industria l conditions?software default settings i/o standard drive strength slew rate v il v ih v ol v oh i ol 1 i oh 1 min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 3.3 v lvcmos wide range any 2 high ?0.3 0.8 2 3.6 0.2 v cci ? 0.2 100 a 100 a 2.5 v lvcmos 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 1.5 v lvcmos 2 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 22 notes: 1. currents are measured at 85c junction temperature. 2. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. table 2-15 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions dc i/o standards commercial 1 industrial 2 i il 3 i ih 4 i il 3 i ih 4 a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 3.3 v lvcmos wide range 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 notes: 1. commercial range (?20c < t a < 70c) 2. industrial range (?40c < t a < 85c) 3. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 4. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges.
proasic3 nano dc and switching characteristics 2-16 advance v0.2 summary of i/o timing characteristics ? defaul t i/o software settings table 2-16 ? summary of ac measuring points standard measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 3.3 v lvcmos wide range 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v table 2-17 ? i/o ac parameter definitions parameter parameter definition t dp data to pad delay thro ugh the output buffer t py pad to data delay thro ugh the input buffer t dout data to output buffer dela y through the i/o interface t eout enable to output buffer tristate co ntrol delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
proasic3 nano dc and switching characteristics advance v0.2 2-17 table 2-18 ? summary of i/o timing cha racteristics?software default settings (at 35 pf) std speed grade, commerc ial-case conditions: t j = 70c, worst case v cc = 1.425 v for a3pn060, a3pn125, and a3pn250 i/o standard drive strength (ma) slew rate capacitive load (pf) t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) 3.3 v lvttl / 3.3 v lvcmos 8 high 35 0.60 4.85 0.04 1.12 tbd 0.43 4.17 3.40 2.69 3.14 3.3 v lvcmos wide range any 1 high 35 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2.5 v lvcmos 8 high 35 0.60 5.11 0.04 1.39 tbd 0.43 4.24 4.16 2.69 2.97 1.8 v lvcmos 4 high 35 0.60 6.75 0.04 1.31 tbd 0.43 4.96 5.40 2.74 2.84 1.5 v lvcmos 2 high 35 0.60 8.10 0.04 1.52 tbd 0.43 5.78 6.45 2.80 2.79 notes: 1. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-19 ? summary of i/o timing cha racteristics?software default settings (at 10 pf) std speed grade, commerc ial-case conditions: t j = 70c, worst case v cc = 1.425 v for a3pn020, a3pn015, and a3pn010 i/o standard drive strength (ma) slew rate capacitive load (pf) t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) 3.3 v lvttl / 3.3 v lvcmos 8 high 10 0.60 2.97 0.04 1.12 1.51 0.43 2.60 2.02 2.69 3.14 3.3 v lvcmos wide range any 1 high 10 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2.5 v lvcmos 8 high 10 0.603.010.041.391.610.432.642.252.692.97 1.8 v lvcmos 4 high 10 0.603.490.041.311.890.433.042.702.742.84 1.5 v lvcmos 2 high 10 0.604.040.041.522.140.433.503.112.802.79 notes: 1. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-18 advance v0.2 detailed i/o dc characteristics table 2-20 ? input capacitance symbol definition conditions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 2-21 ? i/o output buffer maximum resistances 1 standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 3.3 v lvcmos wide range 100 a tbd tbd 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 1.5 v lvcmos 2 ma 200 224 notes: 1. these maximum values are prov ided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, te mperature, and process. for board design considerations and detailed out put buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.co m/download/ibi s/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec table 2-22 ? i/o weak pull-up/pu ll-down resistances minimum and maximum w eak pull-up/pull-down resistance values v cci r (weak pull-up) 1 ( ) r (weak pull-down) 2 ( ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-up-max) = (v olspec ) / i (weak pull-up-min) 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i (weak pull-up-min)
proasic3 nano dc and switching characteristics advance v0.2 2-19 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 8 ma i/ o setting, which is the worst case for this type of analysis. for example, at 110c, the short current condition would have to be sustain ed for more than three months to cause a reliability concern. the i/o desi gn does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-23 ? i/o short currents i osh /i osl drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 3.3 v lvcmos wide range 100 a tbd tbd 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 1.5 v lvcmos 2 ma 13 16 * t j = 100c table 2-24 ? duration of short circui t event before failure temperature time before failure ?40c > 20 years ?20c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months 110c 3 months table 2-25 ? schmitt trigger input hysteresis hysteresis voltage value (typ.) for schmitt mode input buffers input buffer configuratio n hysteresis value (typ.) 3.3 v lvttl / lvcmos (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmi tt trigger mode) 80 mv 1.5 v lvcmos (schmi tt trigger mode) 60 mv table 2-26 ? i/o input rise time, fall time, and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos no requirement 10 ns * 20 years (110c) * the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, then the rise time and fall time of input buffers ca n be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
proasic3 nano dc and switching characteristics 2-20 advance v0.2 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-27 ? minimum and maximum dc input and output levels 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-6 ? ac loading table 2-28 ? 3.3 v lvttl/lvcmos ac wa veforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.410 notes: 1. measuring point = v trip. see table 2-16 on page 2-16 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
proasic3 nano dc and switching characteristics advance v0.2 2-21 timing characteristics table 2-29 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 10.48 0.04 1.12 t bd 0.43 8.86 7.41 2.40 2.47 ns ?1 0.51 8.91 0.04 0.95 tbd 0.36 7.54 6.30 2.04 2.10 ns ?2 0.45 7.83 0.03 0.84 tbd 0.32 6.62 5.53 1.79 1.84 ns 4 ma std. 0.60 10.48 0.04 1.12 t bd 0.43 8.86 7.41 2.40 2.47 ns ?1 0.51 8.91 0.04 0.95 tbd 0.36 7.54 6.30 2.04 2.10 ns ?2 0.45 7.83 0.03 0.84 tbd 0.32 6.62 5.53 1.79 1.84 ns 6 ma std. 0.60 7.45 0.04 1.12 tbd 0.43 6.48 5.53 2.69 3.00 ns ?1 0.51 6.33 0.04 0.95 tbd 0.36 5.51 4.70 2.29 2.55 ns ?2 0.45 5.56 0.03 0.84 tbd 0.32 4.84 4.13 2.01 2.24 ns 8 ma std. 0.60 7.45 0.04 1.12 tbd 0.43 6.48 5.53 2.69 3.00 ns ?1 0.51 6.33 0.04 0.95 tbd 0.36 5.51 4.70 2.29 2.55 ns ?2 0.45 5.56 0.03 0.84 tbd 0.32 4.84 4.13 2.01 2.24 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-30 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 7.53 0.04 1.12 tbd 0.43 6.15 5.18 2.39 2.61 ns ?1 0.51 6.41 0.04 0.95 tbd 0.36 5.23 4.41 2.04 2.22 ns ?2 0.45 5.63 0.03 0.84 tbd 0.32 4.60 3.87 1.79 1.95 ns 4 ma std. 0.60 7.53 0.04 1.12 tbd 0.43 6.15 5.18 2.39 2.61 ns ?1 0.51 6.41 0.04 0.95 tbd 0.36 5.23 4.41 2.04 2.22 ns ?2 0.45 5.63 0.03 0.84 tbd 0.32 4.60 3.87 1.79 1.95 ns 6 ma std. 0.60 4.85 0.04 1.12 tbd 0.43 4.17 3.40 2.69 3.14 ns ?1 0.51 4.13 0.04 0.95 tbd 0.36 3.55 2.89 2.29 2.67 ns ?2 0.45 3.63 0.03 0.84 tbd 0.32 3.11 2.54 2.01 2.34 ns 8 ma std. 0.60 4.85 0.04 1.12 tbd 0.43 4.17 3.40 2.69 3.14 ns ?1 0.51 4.13 0.04 0.95 tbd 0.36 3.55 2.89 2.29 2.67 ns ?2 0.45 3.63 0.03 0.84 tbd 0.32 3.11 2.54 2.01 2.34 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-22 advance v0.2 table 2-31 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 6.08 0.04 1.12 1. 51 0.43 5.20 4.48 2.40 2.47 ns ?1 0.51 5.17 0.04 0.95 1.28 0.36 4.43 3.81 2.04 2.10 ns ?2 0.45 4.54 0.03 0.84 1.13 0.32 3.88 3.35 1.79 1.84 ns 4 ma std. 0.60 6.08 0.04 1.12 1. 51 0.43 5.20 4.48 2.40 2.47 ns ?1 0.51 5.17 0.04 0.95 1.28 0.36 4.43 3.81 2.04 2.10 ns ?2 0.45 4.54 0.03 0.84 1.13 0.32 3.88 3.35 1.79 1.84 ns 6 ma std. 0.60 4.76 0.04 1.12 1. 51 0.43 4.25 3.83 2.69 3.00 ns ?1 0.51 4.05 0.04 0.95 1.28 0.36 3.61 3.26 2.29 2.55 ns ?2 0.45 3.56 0.03 0.84 1.13 0.32 3.17 2.86 2.01 2.24 ns 8 ma std. 0.60 4.76 0.04 1.12 1. 51 0.43 4.25 3.83 2.69 3.00 ns ?1 0.51 4.05 0.04 0.95 1.28 0.36 3.61 3.26 2.29 2.55 ns ?2 0.45 3.56 0.03 0.84 1.13 0.32 3.17 2.86 2.01 2.24 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-32 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 3.84 0.04 1.12 1. 51 0.43 3.09 2.44 2.39 2.61 ns ?1 0.51 3.27 0.04 0.95 1.28 0.36 2.63 2.07 2.04 2.22 ns ?2 0.45 2.87 0.03 0.84 1.13 0.32 2.31 1.82 1.79 1.95 ns 4 ma std. 0.60 3.84 0.04 1.12 1. 51 0.43 3.09 2.44 2.39 2.61 ns ?1 0.51 3.27 0.04 0.95 1.28 0.36 2.63 2.07 2.04 2.22 ns ?2 0.45 2.87 0.03 0.84 1.13 0.32 2.31 1.82 1.79 1.95 ns 6 ma std. 0.60 2.97 0.04 1.12 1. 51 0.43 2.60 2.02 2.69 3.14 ns ?1 0.51 2.52 0.04 0.95 1.28 0.36 2.21 1.72 2.29 2.67 ns ?2 0.45 2.21 0.03 0.84 1.13 0.32 1.94 1.51 2.01 2.34 ns 8 ma std. 0.60 2.97 0.04 1.12 1.51 0.43 2.60 2.02 2.69 3.14 ns ?1 0.51 2.52 0.04 0.95 1.28 0.36 2.21 1.72 2.29 2.67 ns ?2 0.45 2.21 0.03 0.84 1.13 0.32 1.94 1.51 2.01 2.34 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-23 3.3 v lvcmos wide range table 2-33 ? minimum and maximum dc input and output levels for 3.3 v lv cmos wide range 3.3 v lvcmos wide range v il v ih v ol v oh i ol i oh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma a 4 a 4 any 3 ?0.3 0.8 2 3.6 0.2 v dd ? 0.2 100 100 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. all lvmcos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 4. currents are measured at 85c junction temperature.
proasic3 nano dc and switching characteristics 2-24 advance v0.2 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. it uses a 5 v?tolerant input buffer and push-pull output buffer. table 2-34 ? minimum and maximum dc input and output levels 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-35 ? 2.5 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.210 notes: 1. measuring point = v trip. see table 2-16 on page 2-16 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
proasic3 nano dc and switching characteristics advance v0.2 2-25 timing characteristics table 2-36 ? 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 11.40 0.04 1.39 t bd 0.43 9.71 9.33 2.37 2.25 ns ?1 0.51 9.70 0.04 1.19 tbd 0.36 8.26 7.94 2.02 1.91 ns ?2 0.45 8.51 0.03 1.04 tbd 0.32 7.25 6.97 1.77 1.68 ns 4 ma std. 0.60 11.40 0.04 1.39 t bd 0.43 9.71 9.33 2.37 2.25 ns ?1 0.51 9.70 0.04 1.19 tbd 0.36 8.26 7.94 2.02 1.91 ns ?2 0.45 8.51 0.03 1.04 tbd 0.32 7.25 6.97 1.77 1.68 ns 6 ma std. 0.60 8.24 0.04 1.39 tbd 0.43 7.20 6.77 2.70 2.87 ns ?1 0.51 7.01 0.04 1.19 tbd 0.36 6.13 5.76 2.30 2.44 ns ?2 0.45 6.15 0.03 1.04 tbd 0.32 5.38 5.05 2.01 2.14 ns 8 ma std. 0.60 8.24 0.04 1.39 tbd 0.43 7.20 6.77 2.70 2.87 ns ?1 0.51 7.01 0.04 1.19 tbd 0.36 6.13 5.76 2.30 2.44 ns ?2 0.45 6.15 0.03 1.04 tbd 0.32 5.38 5.05 2.01 2.14 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-37 ? 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 8.54 0.04 1.39 0.43 6.25 6.65 2.37 2.34 ns ?1 0.51 7.26 0.04 1.19 0. 36 5.31 5.66 2.01 1.99 ns ?2 0.45 6.38 0.03 1.04 0. 32 4.66 4.97 1.77 1.75 ns 4 ma std. 0.60 8.54 0.04 1.39 0.43 6.25 6.65 2.37 2.34 ns ?1 0.51 7.26 0.04 1.19 0. 36 5.31 5.66 2.01 1.99 ns ?2 0.45 6.38 0.03 1.04 0. 32 4.66 4.97 1.77 1.75 ns 6 ma std. 0.60 5.11 0.04 1.39 0.43 4.24 4.16 2.69 2.97 ns ?1 0.51 4.35 0.04 1.19 0. 36 3.61 3.54 2.29 2.53 ns ?2 0.45 3.82 0.03 1.04 0. 32 3.17 3.11 2.01 2.22 ns 8 ma std. 0.60 5.11 0.04 1.39 0.43 4.24 4.16 2.69 2.97 ns ?1 0.51 4.35 0.04 1.19 0.36 3.61 3.54 2.29 2.53 ns ?2 0.45 3.82 0.03 1.04 0.32 3.17 3.11 2.01 2.22 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-26 advance v0.2 table 2-38 ? 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 6.79 0.04 1.39 1. 61 0.43 5.87 5.37 2.37 2.25 ns ?1 0.51 5.77 0.04 1.19 1.37 0.36 5.00 4.56 2.02 1.91 ns ?2 0.45 5.07 0.03 1.04 1.20 0.32 4.39 4.01 1.77 1.68 ns 4 ma std. 0.60 6.79 0.04 1.39 1. 61 0.43 5.87 5.37 2.37 2.25 ns ?1 0.51 5.77 0.04 1.19 1.37 0.36 5.00 4.56 2.02 1.91 ns ?2 0.45 5.07 0.03 1.04 1.20 0.32 4.39 4.01 1.77 1.68 ns 6 ma std. 0.60 5.34 0.04 1.39 1. 61 0.43 4.79 4.55 2.70 2.87 ns ?1 0.51 4.55 0.04 1.19 1.37 0.36 4.08 3.87 2.30 2.44 ns ?2 0.45 3.99 0.03 1.04 1.20 0.32 3.58 3.40 2.01 2.14 ns 8 ma std. 0.60 5.34 0.04 1.39 1. 61 0.43 4.79 4.55 2.70 2.87 ns ?1 0.51 4.55 0.04 1.19 1.37 0.36 4.08 3.87 2.30 2.44 ns ?2 0.45 3.99 0.03 1.04 1.20 0.32 3.58 3.40 2.01 2.14 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-39 ? 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 3.93 0.04 1.39 1. 61 0.43 3.17 2.84 2.37 2.34 ns ?1 0.51 3.34 0.04 1.19 1.37 0.36 2.69 2.41 2.01 1.99 ns ?2 0.45 2.93 0.03 1.04 1.20 0.32 2.36 2.12 1.77 1.75 ns 4 ma std. 0.60 3.93 0.04 1.39 1. 61 0.43 3.17 2.84 2.37 2.34 ns ?1 0.51 3.34 0.04 1.19 1.37 0.36 2.69 2.41 2.01 1.99 ns ?2 0.45 2.93 0.03 1.04 1.20 0.32 2.36 2.12 1.77 1.75 ns 6 ma std. 0.60 3.01 0.04 1.39 1. 61 0.43 2.64 2.25 2.69 2.97 ns ?1 0.51 2.56 0.04 1.19 1.37 0.36 2.25 1.92 2.29 2.53 ns ?2 0.45 2.25 0.03 1.04 1.20 0.32 1.97 1.68 2.01 2.22 ns 8 ma std. 0.60 3.01 0.04 1.39 1.61 0.43 2.64 2.25 2.69 2.97 ns ?1 0.51 2.56 0.04 1.19 1.37 0.36 2.25 1.92 2.29 2.53 ns ?2 0.45 2.25 0.03 1.04 1.20 0.32 1.97 1.68 2.01 2.22 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-27 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-40 ? minimum and maximum dc input and output levels 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 17 22 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-41 ? 1.8 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.910 notes: 1. measuring point = v trip. see table 2-16 on page 2-16 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
proasic3 nano dc and switching characteristics 2-28 advance v0.2 timing characteristics table 2-42 ? 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 15.34 0.04 1.31 tbd 0.43 12.49 12.58 2.35 1.72 ns ?1 0.51 13.05 0.04 1.12 tbd 0.36 10.63 10.70 2.00 1.46 ns ?2 0.45 11.45 0.03 0.98 tbd 0.32 9.33 9.40 1.76 1.28 ns 4 ma std. 0.60 10.68 0.04 1.31 t bd 0.43 9.39 8.98 2.75 2.74 ns ?1 0.51 9.09 0.04 1.12 tbd 0.36 7.99 7.64 2.34 2.33 ns ?2 0.45 7.98 0.03 0.98 tbd 0.32 7.01 6.70 2.05 2.04 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-43 ? 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 11.61 0.04 1.31 0.43 7.36 8.94 2.35 1.78 ns ?1 0.51 9.88 0.04 1.12 0. 36 6.26 7.60 2.00 1.51 ns ?2 0.45 8.67 0.03 0.98 0. 32 5.49 6.67 1.75 1.33 ns 4 ma std. 0.60 6.75 0.04 1.31 0.43 4.96 5.40 2.74 2.84 ns ?1 0.51 5.74 0.04 1.12 0.36 4.22 4.60 2.33 2.42 ns ?2 0.45 5.04 0.03 0.98 0.32 3.70 4.04 2.05 2.12 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-29 table 2-44 ? 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 8.90 0.04 1.31 1. 89 0.43 7.80 7.02 2.35 1.72 ns ?1 0.51 7.57 0.04 1.12 1.60 0.36 6.64 5.97 2.00 1.46 ns ?2 0.45 6.65 0.03 0.98 1.41 0.32 5.82 5.24 1.76 1.28 ns 4 ma std. 0.60 7.08 0.04 1.31 1. 89 0.43 6.40 5.93 2.75 2.74 ns ?1 0.51 6.02 0.04 1.12 1.60 0.36 5.44 5.05 2.34 2.33 ns ?2 0.45 5.29 0.03 0.98 1.41 0.32 4.78 4.43 2.05 2.04 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-45 ? 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 4.99 0.04 1.31 1. 89 0.43 3.70 3.53 2.35 1.78 ns ?1 0.51 4.24 0.04 1.12 1.60 0.36 3.15 3.01 2.00 1.51 ns ?2 0.45 3.72 0.03 0.98 1.41 0.32 2.77 2.64 1.75 1.33 ns 4 ma std. 0.60 3.49 0.04 1.31 1.89 0.43 3.04 2.70 2.74 2.84 ns ?1 0.51 2.97 0.04 1.12 1.60 0.36 2.58 2.30 2.33 2.42 ns ?2 0.45 2.61 0.03 0.98 1.41 0.32 2.27 2.02 2.05 2.12 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-30 advance v0.2 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-46 ? minimum and maximum dc input and output levels 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 2 ma ? 0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 13 16 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation cond itions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended oper ating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-47 ? 1.5 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 1.5 0.75 10 notes: 1. measuring point = v trip. see table 2-16 on page 2-16 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
proasic3 nano dc and switching characteristics advance v0.2 2-31 timing characteristics table 2-48 ? 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 13.17 0.04 1.52 tbd 0.43 11.64 10.91 2.81 2.67 ns ?1 0.51 11.20 0.04 1.29 tbd 0.36 9.90 9.28 2.39 2.27 ns ?2 0.45 9.83 0.03 1.14 tbd 0.32 8.69 8.15 2.10 1.99 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-49 ? 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 8.10 0.04 1.52 tbd 0.43 5.78 6.45 2.80 2.79 ns ?1 0.51 6.89 0.04 1.29 tbd 0.36 4.92 5.48 2.39 2.37 ns ?2 0.45 6.05 0.03 1.14 tbd 0.32 4.32 4.81 2.09 2.08 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-50 ? 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 8.87 0.04 1.52 2. 14 0.43 8.06 7.19 2.81 2.67 ns ?1 0.51 7.54 0.04 1.29 1.82 0.36 6.86 6.12 2.39 2.27 ns ?2 0.45 6.62 0.03 1.14 1.60 0.32 6.02 5.37 2.10 1.99 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-51 ? 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 4.04 0.04 1.52 2.14 0.43 3.50 3.11 2.80 2.79 ns ?1 0.51 3.44 0.04 1.29 1.82 0.36 2.98 2.65 2.39 2.37 ns ?2 0.45 3.02 0.03 1.14 1.60 0.32 2.62 2.32 2.09 2.08 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-32 advance v0.2 i/o register specifications fully registered i/o buffers with s ynchronous enable an d asynchronous preset figure 2-10 ? timing model of registered i/ o buffers with synchronous en able and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive-edge triggered data output register and enable output register with: active high enable active high preset postive-edge triggered pad out clk enable preset data_out data eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
proasic3 nano dc and switching characteristics advance v0.2 2-33 table 2-52 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of th e output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the ou tput enable register j, h t oesue enable setup time for the ou tput enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of th e output enable register i, eout t oerempre asynchronous preset removal time fo r the output enable register i, h t oerecpre asynchronous preset recovery time for the output enab le register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of the input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a * see figure 2-10 on page 2-32 for more information.
proasic3 nano dc and switching characteristics 2-34 advance v0.2 fully registered i/o buffers with s ynchronous enable an d asynchronous clear figure 2-11 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear enable clk pad out clk enable clr data_out data y aa eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_e nable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf data input i/o register with active high enable active high clear positive-edge triggered data output register and enable output register with active high enable active high clear positive-edge triggered
proasic3 nano dc and switching characteristics advance v0.2 2-35 table 2-53 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time fo r the output data register ll, hh t orecclr asynchronous clear reco very time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the ou tput enable register kk, hh t oehe enable hold time for the ou tput enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enab le register ii, hh t oerecclr asynchronous clear recove ry time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear reco very time for the inpu t data register dd, aa * see figure 2-11 on page 2-34 for more information.
proasic3 nano dc and switching characteristics 2-36 advance v0.2 input register timing characteristics figure 2-12 ? input register timing diagram 50 % preset clear out_1 clk data enable t isue 50 % 50 % t isud t ihd 50 % 50 % t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-54 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t iclkq clock-to-q of the input da ta register 0.24 0.27 0.32 ns t isud data setup time for the inpu t data register 0.26 0.30 0.35 ns t ihd data hold time for the inpu t data register 0.00 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the in put data register 0.45 0.52 0.61 ns t ipre2q asynchronous preset-to-q of the in put data register 0.45 0.52 0.61 ns t iremclr asynchronous clear removal time for the input data regi ster 0.00 0.00 0.00 ns t irecclr asynchronous clear recove ry time for the input da ta register 0.22 0.25 0.30 ns t irempre asynchronous preset remo val time for the input data register 0.00 0.00 0.00 ns t irecpre asynchronous preset recovery time fo r the input data register 0.22 0.25 0.30 ns t iwclr asynchronous clear mi nimum pulse width for the input data register 0.22 0.25 0.30 ns t iwpre asynchronous preset minimu m pulse width for the input data register 0.22 0.25 0.30 ns t ickmpwh clock minimum pulse widt h high for the input data register 0.36 0.41 0.48 ns t ickmpwl clock minimum pulse widt h low for the input data register 0.32 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-37 output register timing characteristics figure 2-13 ? output register timing diagram preset clear dout clk data_out enable t osue 50 % 50 % t osud t ohd 50 % 50 % t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-55 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t oclkq clock-to-q of the output data register 0.59 0.67 0.79 ns t osud data setup time for the output data register 0.31 0.36 0.42 ns t ohd data hold time for the output data register 0.00 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the ou tput data register 0.80 0.91 1.07 ns t opre2q asynchronous preset-to-q of the output data register 0.80 0.91 1.07 ns t oremclr asynchronous clear removal time for th e output data register 0.00 0.00 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.22 0.25 0.30 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.22 0.25 0.30 ns t owclr asynchronous clear minimum pulse width fo r the output data register 0.22 0.25 0.30 ns t owpre asynchronous preset minimum pulse width for the output data register 0.22 0.25 0.30 ns t ockmpwh clock minimum pulse width high for the output data register 0.36 0.41 0.48 ns t ockmpwl clock minimum pulse width low for the output data register 0.32 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-38 advance v0.2 output enable register timing characteristics figure 2-14 ? output enable regist er timing diagram 50 % preset clear eout clk d_enable enable t oesue 50 % 50 % t oesud t oehd 50 % 50 % t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-56 ? output enable regist er propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t oeclkq clock-to-q of the output en able register 0.44 0.51 0.59 ns t oesud data setup time for the output enable register 0.31 0.36 0.42 ns t oehd data hold time for the output enable register 0.00 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the ou tput enable register 0.67 0.76 0.89 ns t oepre2q asynchronous preset-to-q of the output enable register 0.67 0.76 0.89 ns t oeremclr asynchronous clear removal time for th e output enable register 0.00 0.00 0.00 ns t oerecclr asynchronous clear recovery time for th e output enable register 0.22 0.25 0.30 ns t oerempre asynchronous preset removal time for th e output enable register 0.00 0.00 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.22 0.25 0.30 ns t oewclr asynchronous clear minimum pu lse width for the output enable register 0.22 0.25 0.30 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.22 0.25 0.30 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.36 0.41 0.48 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.32 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-39 ddr module specifications input ddr module figure 2-15 ? input ddr timing model table 2-57 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
proasic3 nano dc and switching characteristics 2-40 advance v0.2 timing characteristics figure 2-16 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-58 ? input ddr propagation delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ? 2 ? 1 std. units t ddriclkq1 clock-to-out out_qr fo r input ddr 0. 27 0.31 0.37 ns t ddriclkq2 clock-to-out out_qf fo r input ddr 0.39 0.44 0.52 ns t ddrisud data setup for input ddr (fall) 0.25 0.28 0.33 ns data setup for input ddr (rise) 0.25 0.28 0.33 ns t ddrihd data hold for input ddr (fall) 0.00 0.00 0.00 ns data hold for input ddr (rise) 0.00 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_ qr for input ddr 0.46 0.53 0.62 ns t ddriclr2q2 asynchronous clear-to-out out_ qf for input ddr 0.57 0.65 0.76 ns t ddriremclr asynchronous clear removal ti me for input ddr 0.00 0.00 0.00 ns t ddrirecclr asynchronous clear re covery time for input ddr 0.22 0.25 0.30 ns t ddriwclr asynchronous clear mini mum pulse width for input ddr 0.22 0.25 0.30 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.36 0.41 0.48 ns t ddrickmpwl clock minimum pulse width lo w for input ddr 0.32 0.37 0.43 ns f ddrimax maximum frequency for input ddr mhz note: for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-41 output ddr module figure 2-17 ? output ddr timing model table 2-59 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x x a b d e c c b outbuf data_r (from core)
proasic3 nano dc and switching characteristics 2-42 advance v0.2 timing characteristics figure 2-18 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-60 ? output ddr propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 0.70 0.80 0.94 ns t ddrosud1 data_f data setup for output ddr 0.38 0.43 0.51 ns t ddrosud2 data_r data setup for output ddr 0.38 0.43 0.51 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 0.80 0.91 1.07 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 0.00 ns t ddrorecclr asynchronous clear re covery time for output ddr 0.22 0.25 0.30 ns t ddrowclr1 asynchronous clear mini mum pulse width for output ddr 0.22 0.25 0.30 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.36 0.41 0.48 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.32 0.37 0.43 ns f ddomax maximum frequency for th e output ddr tbd tbd tbd mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-43 versatile characteristics versatile specifications as a combinatorial module the proasic3 library offers all combinations of lut-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the libr ary. for more details, refer to the fusion, igloo ? /e, and proasic3/e macro library guide . figure 2-19 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
proasic3 nano dc and switching characteristics 2-44 advance v0.2 figure 2-20 ? timing model and waveforms t pd a b t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell y nand2 or any combinatorial logic t pd t pd 50 % v cc v cc v cc 50 % gnd a, b, c 50 % 50 % 50 % (rr) (rf) gnd out out gnd 50 % (ff) (fr) t pd t pd
proasic3 nano dc and switching characteristics advance v0.2 2-45 timing characteristics versatile specifications as a sequential module the proasic3 library offers a wide variety of sequential cells, including flip-flops and latches. each has a data input and optional enable, clear, or pres et. in this section, ti ming characteristics are presented for a representative sample from the library. for more details, refer to the fusion, igloo/e, and proasic3/e macro library guide . table 2-61 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v combinatorial cell equation parameter ?2 ?1 std. units inv y = !a t pd 0.40 0.46 0.54 ns and2 y = a b t pd 0.47 0.54 0.63 ns nand2 y = !(a b) t pd 0.47 0.54 0.63 ns or2 y = a + b t pd 0.49 0.55 0.65 ns nor2 y = !(a + b) t pd 0.49 0.55 0.65 ns xor2 y = a bt pd 0.74 0.84 0.99 ns maj3 y = maj(a, b, c) t pd 0.70 0.79 0.93 ns xor3 y = a b ct pd 0.87 1.00 1.17 ns mux2 y = a !s + b s t pd 0.51 0.58 0.68 ns and3 y = a b c t pd 0.56 0.64 0.75 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. figure 2-21 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
proasic3 nano dc and switching characteristics 2-46 advance v0.2 timing characteristics figure 2-22 ? timing model and waveforms pre clr out clk data en t sue 50 % 50 % t sud t hd 50 % 50 % t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-62 ? register delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t clkq clock-to-q of the core register 0.55 0.63 0.74 ns t sud data setup time for the core register 0.43 0.49 0.57 ns t hd data hold time for the core register 0.00 0.00 0.00 ns t sue enable setup time for the core register 0.45 0.52 0.61 ns t he enable hold time for the core register 0.00 0.00 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.40 0.45 0.53 ns t pre2q asynchronous preset-to-q of the core register 0.40 0.45 0.53 ns t remclr asynchronous clear removal time fo r the core register 0.00 0.00 0.00 ns t recclr asynchronous clear reco very time for the core register 0.22 0.25 0.30 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.22 0.25 0.30 ns t wclr asynchronous clear minimu m pulse width for the core register 0.22 0.25 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.22 0.25 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.36 0.41 0.48 ns t ckmpwl clock minimum pulse width low for the core register 0.32 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-47 global resource characteristics a3pn250 clock tree topology clock delays are device-specific. figure 2-23 is an example of a global tree used for clock routing. the global tree presented in figure 2-23 is driven by a ccc located on the west side of the a3pn250 device. it is used to drive al l d-flip-flops in the device. figure 2-23 ? example of global tree use in an a3pn250 device for clock routing central global rib versatile rows global spine ccc
proasic3 nano dc and switching characteristics 2-48 advance v0.2 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-51 . table 2-63 to table 2-68 on page 2-50 present minimum and ma ximum global clock dela ys within each device. minimum and maximum delays are measur ed with minimum an d maximum loading. timing characteristics table 2-63 ? a3pn010 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.56 0.75 0.64 0.85 0.75 1.00 ns t rckh input high delay for global clock 0.57 0.79 0.65 0.90 0.76 1.05 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.22 0.25 0.29 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the fa rthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-64 ? a3pn015 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.61 0.86 0.70 0.98 0.82 1.15 ns t rckh input high delay for global clock 0.62 0.91 0.71 1.03 0.83 1.21 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.28 0.32 0.38 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the fa rthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-49 table 2-65 ? a3pn020 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.61 0.86 0.70 0.98 0.82 1.15 ns t rckh input high delay for global clock 0.62 0.91 0.71 1.03 0.83 1.21 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.28 0.32 0.38 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the fa rthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-66 ? a3pn060 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.72 0.95 0.82 1.08 0.96 1.26 ns t rckh input high delay for global clock 0.71 0.96 0.81 1.11 0.96 1.30 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.25 0.30 0.35 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the fa rthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-50 advance v0.2 table 2-67 ? a3pn125 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.76 0.99 0.87 1.12 1.02 1.32 ns t rckh input high delay for global clock 0.76 1.02 0.87 1.17 1.02 1.37 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.30 0.35 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the fa rthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-68 ? a3pn250 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.79 1.02 0.90 1.16 1.06 1.36 ns t rckh input high delay for global clock 0.78 1.04 0.88 1.18 1.04 1.39 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.30 0.35 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the fa rthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-51 clock conditioning circuits ccc electrical specifications timing characteristics table 2-69 ? proasic3 nano ccc/ pll specification parameter minimum typical maximum units clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz delay increments in programmable delay blocks 1,2 200 ps number of programmable values in each programmable delay block 32 serial clock (sclk) for dynamic pll 3 125 mhz input cycle-to-cycle jitte r (peak magnitude) 1.5 ns ccc output peak-to-p eak period jitter f ccc_out max peak-to-peak period jitter 1 global network used external fb used 3 global networks used 0.75 mhz to 24 mhz 0.50 % 0.70 % 24 mhz to 100 mhz 1.00 % 1.20 % 100 mhz to 250 mhz 1.75 % 2.00 % 250 mhz to 350 mhz 2.50 % 5.60 % acquisition time lockcontrol = 0 lockcontrol = 1 300 s 6.0 ms tracking jitter 5 lockcontrol = 0 lockcontrol = 1 1.6 ns 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1,2 1.25 15.65 ns delay range in block: programmable delay 2 1,2 0.025 15.65 ns delay range in block: fixed delay 1,2 2.2 ns notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-5 for deratings. 2. t j = 25c, v cc = 1.5 v 3. maximum value obtained fo r a ?2 speed-grade device in worst-ca se commercial conditions. for specific junction temperature and volt age supply levels, refer to table 2-6 on page 2-5 for derating values. 4. the a3pn010, a3pn015, and a3pn020 devices do not support plls. 5. tracking jitter is defined as the va riation in clock edge position of p ll outputs with reference to the pll input clock edge. tracking jitter does not measure th e variation in pll output period, which is covered by the period jitter parameter.
proasic3 nano dc and switching characteristics 2-52 advance v0.2 note: peak-to-peak jitter measurements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-24 ? peak-to-peak jitter definition t perio d _max t perio d _min output s i g nal
proasic3 nano dc and switching characteristics advance v0.2 2-53 embedded sram and fifo characteristics sram figure 2-25 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
proasic3 nano dc and switching characteristics 2-54 advance v0.2 timing waveforms figure 2-26 ? ram read for pass-through output figure 2-27 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
proasic3 nano dc and switching characteristics advance v0.2 2-55 figure 2-28 ? ram write, output retained (wmode = 0) figure 2-29 ? ram write, output as write data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (pass-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2
proasic3 nano dc and switching characteristics 2-56 advance v0.2 figure 2-30 ? ram reset clk reset_b do d n t cyc t ckh t ckl t rstbq d m
proasic3 nano dc and switching characteristics advance v0.2 2-57 timing characteristics table 2-70 ? ram4k9 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren_b, wen_b setup time 0.14 0.16 0.19 ns t enh ren_b, wen_b hold time 0.10 0.11 0.13 ns t bks blk_b setup time 0.23 0.27 0.31 ns t bkh blk_b hold time 0.02 0.02 0.02 ns t ds input data (di) setup time 0.18 0.21 0.25 ns t dh input data (di) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 1.79 2.03 2.39 ns clock high to new data valid on do (flow-through, wmode = 1) 2.36 2.68 3.15 ns t ckq2 clock high to new data valid on do (pipelined) 0.89 1.02 1.20 ns t c2cwwl address collision clk-to-clk delay fo r reliable write after write on same address; applicable to closing edge 0.33 0.28 0.25 ns t c2cwwh address collision clk-to-clk delay fo r reliable write after write on same address; applicab le to rising edge 0.30 0.26 0.23 ns t c2crwh address collision clk-to-clk delay fo r reliable read access after write on same address; applicable to opening edge 0.45 0.38 0.34 ns t c2cwrh address collision clk-to-clk delay fo r reliable write access after read on same address; applicable to opening edge 0.49 0.42 0.37 ns t rstbq reset_b low to data out low on do (flow through) 0.92 1.05 1.23 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 ns t remrstb reset_b removal 0.29 0.33 0.38 ns t recrstb reset_b recovery 1.50 1.71 2.01 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 nano dc and switching characteristics 2-58 advance v0.2 table 2-71 ? ram512x18 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren_b, wen_b setup time 0.09 0.10 0.12 ns t enh ren_b, wen_b hold time 0.06 0.07 0.08 ns t ds input data (di) setup time 0.18 0.21 0.25 ns t dh input data (di) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do ( output retained, wmode = 0) 2.16 2.46 2.89 ns t ckq2 clock high to new data valid on do (pipelined) 0.90 1.02 1.20 ns t c2crwh address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.50 0.43 0.38 ns t c2cwrh address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 0.59 0.50 0.44 ns t rstbq reset_b low to data out low on do (flow-through) 0.92 1.05 1.23 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 ns t remrstb reset_b removal 0.29 0.33 0.38 ns t recrstb reset_b recovery 1.50 1.71 2.01 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-59 fifo figure 2-31 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
proasic3 nano dc and switching characteristics 2-60 advance v0.2 timing waveforms figure 2-32 ? fifo reset figure 2-33 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
proasic3 nano dc and switching characteristics advance v0.2 2-61 figure 2-34 ? fifo full flag and afull flag assertion figure 2-35 ? fifo empty flag and ae mpty flag deassertion figure 2-36 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
proasic3 nano dc and switching characteristics 2-62 advance v0.2 timing characteristics table 2-72 ? fifo worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. units t ens ren_b, wen_b setup time 1.38 1.57 1.84 ns t enh ren_b, wen_b hold time 0.02 0.02 0.02 ns t bks blk_b setup time 0.22 0.25 0.30 ns t bkh blk_b hold time 0.00 0.00 0.00 ns t ds input data (di) setup time 0.18 0.21 0.25 ns t dh input data (di) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.36 2.68 3.15 ns t ckq2 clock high to new data valid on do (pipelined) 0.89 1.02 1.20 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 ns t ckaf clock high to almost empty/ full flag valid 6.19 7.05 8.29 ns t rstfg reset_b low to empty/full flag valid 1.69 1.93 2.27 ns t rstaf reset_b low to almost empty/fu ll flag valid 6.13 6.98 8.20 ns t rstbq reset_b low to data out low on do (flow-through) 0.92 1.05 1.23 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 ns t remrstb reset_b removal 0.29 0.33 0.38 ns t recrstb reset_b recovery 1.50 1.71 2.01 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency fo r fifo 310 272 231 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-63 embedded flashrom characteristics timing characteristics figure 2-37 ? timing diagram a 0 a 1 t s u t hold t s u t hold t s u t hold t c kq2 t c kq2 t c kq2 c lk a dd ress data d 0 d 0 d 1 table 2-73 ? embedded flashrom access time commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t su address setup time 0.53 0.61 0.71 ns t hold address hold time 0.00 0.00 0.00 ns t ck2q clock to out 16.23 18.48 21.73 ns f max maximum clock frequenc y 15.00 15.00 15.00 mhz
proasic3 nano dc and switching characteristics 2-64 advance v0.2 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtain complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing ch aracteristics in the "user i/o characteristics" section on page 2-11 for more details. timing characteristics table 2-74 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time 0.53 0.60 0.71 ns t dihd test data input hold time 1.07 1.21 1.42 ns t tmssu test mode select setup time 0.53 0.60 0.71 ns t tmdhd test mode select hold time 1.07 1.21 1.42 ns t tck2q clock to q (data out) 6.39 7.24 8.52 ns t rstb2q reset to q (data out) 21.31 24.15 28.41 ns f tckmax tck maximum frequenc y 23.00 20.00 17.00 mhz t trstrem resetb removal time 0.00 0.00 0.00 ns t trstrec resetb recovery time 0.21 0.24 0.28 ns t trstmpw resetb minimum pulse tbd tbd tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics advance v0.2 2-65 part number and revision date part number 51700111-002-1 revised november 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance st atus datasheet may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information. previous version changes in current version (advance v0.2) page advance v0.1 (october 2008) table 2-2 recommended operating conditions 1, 2 was revised to add vmv to the v cci row. the following table note was added: "vmv pins must be connected to the corresponding v cci pins." 2-2 the values in table 2-7 quiescent supply current characteristics were revised for a3pn010, a3pn015, and a3pn020. 2-6 a table note, "all lvcmos 3.3 v softw are macros support lvcmos 3.3 v wide range, as specified in the jesd 8-b specification," was added to table 2-14 summary of maximum and mi nimum dc input and output levels , table 2-18 summary of i/o timing char acteristics?softwar e default settings (at 35 pf) , and table 2-19 summary of i/o timi ng characteri stics?software default settings (at 10 pf) . 2-15 , 2-17 3.3 v lvcmos wide range was added to table 2-21 i/o output buffer maximum resistances 1 and table 2-23 i/o short currents iosh/iosl . 2-18 , 2-19

advance v0.2 3-1 proasic ? 3 nano packaging 3 ? package pin assignments 48-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx. notes: 1. this is the bottom view of the package. 2. the die attach paddle of the pa ckage is tied to ground (gnd). 48 1 pin 1
package pin assignments 3-2 advance v0.2 48-pin qfn pin number a3pn010 function 1 gec0/io37rsb1 2 io36rsb1 3 gea0/io34rsb1 4 io22rsb1 5 gnd 6v cci b1 7 io24rsb1 8 io33rsb1 9 io26rsb1 10 io32rsb1 11 io27rsb1 12 io29rsb1 13 io30rsb1 14 io31rsb1 15 io28rsb1 16 io25rsb1 17 io23rsb1 18 v cc 19 v cci b1 20 io17rsb1 21 io14rsb1 22 tck 23 tdi 24 tms 25 v pump 26 tdo 27 trst 28 v jtag 29 io11rsb0 30 io10rsb0 31 io09rsb0 32 io08rsb0 33 v cci b0 34 gnd 35 v cc 36 io07rsb0 37 io06rsb0 38 gda0/io05rsb0 39 io03rsb0 40 gdc0/io01rsb0 41 io12rsb1 42 io13rsb1 43 io15rsb1 44 io16rsb1 45 io18rsb1 46 io19rsb1 47 io20rsb1 48 io21rsb1 48-pin qfn pin number a3pn010 function
proasic3 nano packaging advance v0.2 3-3 68-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . notes: 1. this is the bottom view of the package. 2. the die attach paddle of the pa ckage is tied to ground (gnd). pin a1 mark 1 6 8
package pin assignments 3-4 advance v0.2 68-pin qfn pin number a3pn015 function 1 io60rsb2 2 io54rsb2 3 io52rsb2 4 io50rsb2 5 io49rsb2 6 gec0/io48rsb2 7 gea0/io47rsb2 8v cc 9gnd 10 v cci b2 11 io46rsb2 12 io45rsb2 13 io44rsb2 14 io43rsb2 15 io42rsb2 16 io41rsb2 17 io40rsb2 18 io39rsb1 19 io37rsb1 20 io35rsb1 21 io33rsb1 22 io31rsb1 23 io30rsb1 24 v cc 25 gnd 26 v cci b1 27 io27rsb1 28 io25rsb1 29 io23rsb1 30 io21rsb1 31 io19rsb1 32 tck 33 tdi 34 tms 35 v pump 36 tdo 37 trst 38 v jtag 39 io17rsb0 40 io16rsb0 41 gda0/io15rsb0 42 gdc0/io14rsb0 43 io13rsb0 44 v cci b0 45 gnd 46 v cc 47 io12rsb0 48 io11rsb0 49 io09rsb0 50 io05rsb0 51 io00rsb0 52 io07rsb0 53 io03rsb0 54 io18rsb1 55 io20rsb1 56 io22rsb1 57 io24rsb1 58 io28rsb1 59 nc 60 gnd 61 nc 62 io32rsb1 63 io34rsb1 64 io36rsb1 65 io61rsb2 66 io58rsb2 67 io56rsb2 68 io63rsb2 68-pin qfn pin number a3pn015 function
proasic3 nano packaging advance v0.2 3-5 68-pin qfn pin number a3pn020 function 1 io60rsb2 2 io54rsb2 3 io52rsb2 4 io50rsb2 5 io49rsb2 6 gec0/io48rsb2 7 gea0/io47rsb2 8v cc 9 gnd 10 v cci b2 11 io46rsb2 12 io45rsb2 13 io44rsb2 14 io43rsb2 15 io42rsb2 16 io41rsb2 17 io40rsb2 18 io39rsb1 19 io37rsb1 20 io35rsb1 21 io33rsb1 22 io31rsb1 23 io30rsb1 24 v cc 25 gnd 26 v cci b1 27 io27rsb1 28 io25rsb1 29 io23rsb1 30 io21rsb1 31 io19rsb1 32 tck 33 tdi 34 tms 35 v pump 36 tdo 37 trst 38 v jtag 39 io17rsb0 40 io16rsb0 41 gda0/io15rsb0 42 gdc0/io14rsb0 43 io13rsb0 44 v cci b0 45 gnd 46 v cc 47 io12rsb0 48 io11rsb0 49 io09rsb0 50 io05rsb0 51 io00rsb0 52 io07rsb0 53 io03rsb0 54 io18rsb1 55 io20rsb1 56 io22rsb1 57 io24rsb1 58 io28rsb1 59 nc 60 gnd 61 nc 62 io32rsb1 63 io34rsb1 64 io36rsb1 65 io61rsb2 66 io58rsb2 67 io56rsb2 68 io63rsb2 68-pin qfn pin number a3pn020 function
package pin assignments 3-6 advance v0.2 100-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . pin assignments pin assignments for the 100-pin qfn package will be publi shed in a future version of this document. notes: 1. this is the bottom view of the package. 2. the die attach paddle of the pa ckage is tied to ground (gnd). a43 a42 pin #1 b34 b33 b1 a56 a1 b44 a28 b23 b22 a29 b12 b11 a15 a14 100-pin qfn
proasic3 nano packaging advance v0.2 3-7 100-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the top view of the package. 1 100
package pin assignments 3-8 advance v0.2 100-pin vqfp pin number a3pn060 function 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 v complf 13 gfa0/io85rsb1 14 v ccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 v cc 18 v cci b1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 v cc 38 gnd 39 v cci b1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 io57rsb1 44 gdc2/io56rsb1 45 gdb2/io55rsb1 46 gda2/io54rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 gcc2/io43rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 v cci b0 67 gnd 68 v cc 69 io31rsb0 70 gbc2/io29rsb0 71 gbb2/io27rsb0 72 io26rsb0 100-pin vqfp pin number a3pn060 function 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 v cci b0 88 gnd 89 v cc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number a3pn060 function
proasic3 nano packaging advance v0.2 3-9 100-pin vqfp pin number a3pn125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7 io130rsb1 8 io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 v complf 13 gfa0/io122rsb1 14 v ccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 v cc 18 v cci b1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 v cc 38 gnd 39 v cci b1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 v cci b0 67 gnd 68 v cc 69 io47rsb0 70 gbc2/io45rsb0 71 gbb2/io43rsb0 72 io42rsb0 100-pin vqfp pin number a3pn125 function 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 v cci b0 88 gnd 89 v cc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 100-pin vqfp pin number a3pn125 function
package pin assignments 3-10 advance v0.2 100-pin vqfp pin number a3pn250 function 1gnd 2 gaa2/io67rsb3 3 io66rsb3 4 gab2/io65rsb3 5 io64rsb3 6 gac2/io63rsb3 7 io62rsb3 8 io61rsb3 9gnd 10 gfb1/io60rsb3 11 gfb0/io59rsb3 12 v complf 13 gfa0/io57rsb3 14 v ccplf 15 gfa1/io58rsb3 16 gfa2/io56rsb3 17 v cc 18 v cci b3 19 gfc2/io55rsb3 20 gec1/io54rsb3 21 gec0/io53rsb3 22 gea1/io52rsb3 23 gea0/io51rsb3 24 vmv3 25 gndq 26 gea2/io50rsb2 27 geb2/io49rsb2 28 gec2/io48rsb2 29 io47rsb2 30 io46rsb2 31 io45rsb2 32 io44rsb2 33 io43rsb2 34 io42rsb2 35 io41rsb2 36 io40rsb2 37 v cc 38 gnd 39 v cci b2 40 io39rsb2 41 io38rsb2 42 io37rsb2 43 gdc2/io36rsb2 44 gdb2/io35rsb2 45 gda2/io34rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io33rsb1 58 gdc0/io32rsb1 59 gdc1/io31rsb1 60 io30rsb1 61 gcb2/io29rsb1 62 gca1/io27rsb1 63 gca0/io28rsb1 64 gcc0/io26rsb1 65 gcc1/io25rsb1 66 v cci b1 67 gnd 68 v cc 69 io24rsb1 70 gbc2/io23rsb1 71 gbb2/io22rsb1 72 io21rsb1 100-pin vqfp pin number a3pn250 function 73 gba2/io20rsb1 74 vmv1 75 gndq 76 gba1/io19rsb0 77 gba0/io18rsb0 78 gbb1/io17rsb0 79 gbb0/io16rsb0 80 gbc1/io15rsb0 81 gbc0/io14rsb0 82 io13rsb0 83 io12rsb0 84 io11rsb0 85 io10rsb0 86 io09rsb0 87 v cci b0 88 gnd 89 v cc 90 io08rsb0 91 io07rsb0 92 io06rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 100-pin vqfp pin number a3pn250 function
proasic3 nano packaging advance v0.2 3-11 part number and revision date part number 51700111-003-1 revised november 2008 list of changes the following table lists critical changes that were made in the current version of the chapter. previous version changes in current version (advance v0.2) page advance v0.1 (october 2008) the "48-pin qfn" pin diagram was revised. 3-1 note 2 for the "48-pin qfn" , "68-pin qfn" , and "100-pin vqfp" pin diagrams was added/changed to "the die attach paddle of the package is tied to ground (gnd)." 3-1 , 3-3 , 3-7 the "100-pin vqfp" pin diagram was revised to mo ve the pin ids to the upper left corner instead of the upper right corner. 3-7
51700111-005-1/ actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court,meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu buillding 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. 11.08

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