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december 2010 doc id 18323 rev 1 1/12 12 STL65DN3LLH5 dual n-channel 30 v, 0.0059 , 19 a powerflat?(5x6) double island, stripfet? v power mosfet features r ds(on) * q g industry benchmark extremely low on-resistance r ds(on) very low switching gate charge high avalanche ruggedness low gate drive power losses application switching applications description this product utilizes the 5 th generation of design rules of st?s proprietary stripfet? technology. the lowest available r ds(on) *q g , in this chip scale package, makes this device suitable for the most demanding dc-dc converter applications, where high power density is to be achieved. figure 1. internal schematic diagram type v dss r ds(on) max i d STL65DN3LLH5 30 v <0.0065 19 a (1) 1. the value is rated according r thj-pcb powerflat? (5x6) double island table 1. device summary order code marking package packaging STL65DN3LLH5 65dn3llh5 powerflat?(5x6) double island tape and reel www.st.com
contents STL65DN3LLH5 2/12 doc id 18323 rev 1 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STL65DN3LLH5 electrical ratings doc id 18323 rev 1 3/12 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v gs gate-source voltage 22 v i d (1) 1. the value is rated according r thj-c drain current (continuous) at t c = 25 c 65 a i d (1) drain current (continuous) at t c = 100 c 41 a i d (2) 2. the value is rated according r thj-pcb drain current (continuous) at t c = 25 c 19 a i d (2) drain current (continuous) at t c =100c 11.8 a i dm (3) 3. pulse width limited by safe operating area drain current (pulsed) 76 a p tot (1) total dissipation at t c = 25c 60 w p tot (2) total dissipation at t c = 25c 4 w derating factor 0.03 w/c t j t stg operating junction temperature storage temperature -55 to 150 c table 3. thermal resistance symbol parameter value unit r thj-case thermal resistance junction-case (drain) (steady state) 2.08 c/w r thj-pcb (1) 1. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec thermal resistance junction-ambient 32 c/w table 4. avalanche data symbol parameter value unit i av not-repetitive avalanche current, (pulse width limited by t j max) 18.5 a e as single pulse avalanche energy (starting t j = 25 c, i d = i av , v dd = 24 v) 270 mj electrical characteristics STL65DN3LLH5 4/12 doc id 18323 rev 1 2 electrical characteristics (t case =25c unless otherwise specified) table 5. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating, v ds = max rating @125 c 1 10 a a i gss gate body leakage current (v ds = 0) v gs = 22 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 11.5 v r ds(on) static drain-source on resistance v gs = 10 v, i d = 9.5 a v gs = 4.5 v, i d = 9.5 a 0.0059 0.0071 0.0065 0.0079 table 6. dynamic symbol parameter test conditions min. typ. max. unit c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25 v, f=1 mhz, v gs =0 - 1500 230 23 - pf pf pf q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =15 v, i d = 19 a v gs =4.5 v (see figure 14 ) - 12 5 4.4 - nc nc nc r g intrinsic gate resistance f = 1 mhz open drain, bias=0 test signal level = 20 mv, open drain -1.6 - STL65DN3LLH5 electrical characteristics doc id 18323 rev 1 5/12 table 7. switching times symbol parameter test conditions min. typ. max. unit t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd =15 v, i d = 9.5 a, r g =4.7 , v gs =10 v (see figure 13 ) - 8.8 18 26 4 - ns ns ns ns table 8. source drain diode symbol parameter test conditions min. typ. max. unit i sd source-drain current - 19 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) - 76 a v sd (2) 2. pulsed: pulse duration=300s, duty cycle 1.5% forward on voltage i sd = 19 a, v gs =0 -1.1v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 19 a, di/dt = 100 a/s, v dd =25 v, tj=150 c - 24 12 1.8 ns nc a electrical characteristics STL65DN3LLH5 6/12 doc id 18323 rev 1 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. normalized b vdss vs temperature figure 7. static drain-source on resistance ) $ 6 $ 3 6 ! / p e r a t i o n i n t h i s a r e a i s , i m i t e d b y m a x 2 $ 3 o n m s m s s 4 j ? # 4 c ? # 3 i n g l e p u l s e ! - v ) $ 6 $ 3 6 ! 6 6 6 6 ' 3 6 ! - v ) $ 6 ' 3 6 ! $ $ 3 2 ) 6 a $ 3 o n m a x ! - v " 6 $ 3 3 4 * ? # n o r m ! - v 2 $ 3 o n ) $ ! m / h m 6 ' 3 6 ! - v STL65DN3LLH5 electrical characteristics doc id 18323 rev 1 7/12 figure 8. gate charge vs gate-source voltage figure 9. capacitance variations figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on resistance vs temperature figure 12. source-drain diode forward characteristics 6 ' 3 1 g n # 6 6 $ $ 6 ) $ ! ! - v # 6 $ 3 6 p & |